Voltage regulator for switch control

Abstract

In the described example, the R2R digital-to-analog converter includes a plurality of arms and a voltage regulator (110). Each arm includes an arm switch (130) having a p-channel MOSFET (PFET) switch (132) and an NFET switch (134). The voltage regulator includes a differential amplifier (314), a p-ladder (308) including N cascode-coupled PFETs (306) and having first and second ends, an n-ladder (318) including γ×N cascode-coupled NFETs (316) and having first and second ends, a first resistor (310), and a second resistor (resistor γ×R) (312). The first p-ladder end is coupled to a first terminal of the first resistor. The second terminal of the first resistor is coupled to the input of the differential amplifier and the first terminal of the second resistor, the second terminal of the second resistor is coupled to the first n-ladder end, and the output of the differential amplifier is coupled to the second n-ladder end to provide the gate voltage of the NFET switch.

Description

[Technical Field]

[0001] TECHNICAL FIELD This application relates generally to voltage regulation, and more particularly to regulating the voltage of a switch control terminal. [Background technology]

[0002] A digital-to-analog converter ("DAC") is a device that accepts a digital input value or code and provides an analog output voltage that is proportional to or representative of the value of the digital input. The digital input value may, for example, follow a standard binary representation. There are a variety of DAC architectures currently used in available devices. The selection of a particular architecture may depend on the application and performance and design metrics, such as power consumption, speed, glitch magnitude and energy, and area required for device implementation. An R2R or R-2R resistor ladder is an example structure used to implement a high-bit precision DAC. Summary of the Invention

[0003] In the described example, an R2R digital-to-analog converter includes multiple arms and a voltage regulator. Each arm includes an arm switch having a p-channel MOSFET (PFET) switch and an n-channel MOSFET (NFET) switch. The voltage regulator includes a differential amplifier, a p-ladder including N cascaded PFETs and having first and second ends, an n-ladder including γ×N cascaded NFETs and having first and second ends, a first resistor (resistance R), and a second resistor (resistance γ×R). The first p-ladder end is coupled to a first terminal of the first resistor. The second terminal of the first resistor is coupled to an input of the differential amplifier and a first terminal of the second resistor. The second terminal of the second resistor is coupled to the first n-ladder end. The output of the differential amplifier is coupled to the second n-ladder end and provides a gate voltage for the NFET switch. [Brief explanation of the drawings]

[0004] [Figure 1] FIG. 1 is a functional block and circuit diagram of an example R2R DAC.

[0005] [Figure 2] FIG. 1 is a functional block and circuit diagram of an example model of an R2R DAC.

[0006] [Figure 3] FIG. 10 is a functional block and circuit diagram of an example arm switch drive circuit, including example voltage regulators for the gate voltages of the NMOS switches of the thermometer arm and binary arm of the R2R DAC.

[0007] [Figure 4] FIG. 1 is a circuit diagram of another example R2R DAC.

[0008] [Figure 5A] 2 is an example graph of DNL error versus code for the R2R DAC of FIG. 1;

[0009] [Figure 5B] 5 is an example graph of DNL versus code for the R2R DAC of FIG. 4.

[0010] [Figure 6] 10 is an example process for determining where to place an offset resistor to allow stop scaling for the arm switch of the least significant bit binary arm of an R2R resistor ladder.

[0011] [Figure 7] FIG. 10 is a functional block and circuit diagram of an alternative example arm switch drive circuit, including example voltage regulators for the gate voltages of the NMOS switches of the thermometer arm and binary arm of the R2R DAC. DETAILED DESCRIPTION OF THE INVENTION

[0012] In some instances, the difference between the intended DAC output for a code and the actual DAC output for that code is classified as differential nonlinearity (DNL) or integral nonlinearity (INL). The ideal output voltage step should correspond to the least significant bit change in the code. DNL error is the difference between the ideal output voltage step magnitude between successive codes and the measured voltage step magnitude between successive codes. INL error is the difference between the ideal output voltage for a particular code and the measured output voltage for that code.

[0013] In an R2R resistor ladder, the on-resistance (R ON ) can result in nonlinearity. In some instances, the on-voltage at the switch control terminal is adjusted to adjust the on-resistance of the switch. Metal-oxide-semiconductor field-effect transistors (MOSFETs) can be used to implement such switches. Using high-side p-channel MOSFETs (PFETs) and low-side n-channel MOSFETs (NFETs) for the switches used to pass the high-side and low-side voltage references to the ladder arms reduces R ON The larger the size of the high-side and low-side switches, the easier it is to match the high-side and low-side switch on-resistances. Using a voltage regulator to adjust the gate voltages of the PFET and NFET switches also allows the high-side and low-side switch on-resistances to be better matched, thus allowing the use of smaller high-side and low-side switches.

[0014] In some examples, an R2R resistor ladder includes a temperature measurement arm (also called a thermometer arm) and a binary arm. Activating successive thermometer arms produces a voltage equal to the DAC output. The binary arms are referred to as having a most significant bit (MSB) arm and a least significant bit (LSB) arm. Activating successive binary arms from the MSB arm to the LSB arm (arms of successively decreasing weight) produces a voltage, then half that voltage, a quarter of that voltage, and so on.

[0015] Therefore, in the switches connecting successive binary arms to their respective voltage references, R ON By halving the switch size in successive binary arms, R ON The value doubles. In some examples, a high-resolution DAC (a DAC with a relatively large number of bits of resolution, such as 18 bits) reaches the minimum switch size allowed by the manufacturing process before the least weight arm. In some examples, an offset resistor added to the series resistor of the R2R ladder can be used to reduce the maximum magnitude of DNL caused by not scaling one or more LSB arms.

[0016] 1 is a functional block and circuit diagram of an example R2R DAC 100. The R2R DAC 100 is an N-bit precision DAC. The R2R DAC 100 includes a voltage source 102, an R2R resistor ladder 104, and a control circuit 106. The control circuit 106 includes a switch control 108, a voltage regulator 110, and a gate driver 112. The voltage source 102 couples a relatively high voltage reference V to a high voltage rail or terminal 116 of the R2R resistor ladder 104. REFP and a first output providing a relatively low voltage reference V REFM and a second output providing a second output. In some examples, some or all components of resistor ladder 104 and / or control circuit 106 are included on a single integrated circuit (IC).

[0017] In some examples, voltage source 102 generates V using an off-chip reference generator, such as a bandgap reference. REFP The resulting voltage is buffered internally on the chip using a reference buffer before voltage source 102 provides the voltage to high voltage rail 116. Alternatively, voltage source 102 may generate V using an on-chip reference generator. REFP , buffers the resulting voltage using a reference buffer, and provides the buffered voltage to the high voltage rail 116. In some examples, the voltage source 102 uses an internal chip ground buffer to provide a reference voltage to the high voltage rail 116. REFM and provides the resulting voltage to the low-voltage rail 118. The input of the ground buffer is connected to the REFGND pin. The REFGND pin is connected to the REFGND plane on the printed circuit board (PCB). Alternatively, the low-voltage rail 118 is connected directly to the REFGND pin. In some examples, the high-voltage rail 116 has a voltage of 5 volts and the low-voltage rail 118 has a voltage of 0 volts.

[0018] The R2R DAC 100 has a total of N bits of precision and has two types of structures called arms. A first set of (thermometer) arms roughly resolves the most significant bits of the N bits, and a second set of (binary) arms refines the least significant bits of the N bits. In this regard, these arms have inputs that receive signals from the control circuit 106. The R2R resistor ladder 104 is connected to a voltage V OUT The R2R resistor ladder 104 has an output voltage terminal 114 of 2 T - One thermometer arm 120 and B binary arms 122, where T and B are integers and T+B=N. The R2R resistor ladder 104, in its entirety, has 2 T -1+B arms. Therefore, the R2R resistor ladder 104 has M=2 T It has a number of arms M equal to the sum of the number of thermometer arms 120 and the number of binary arms 122, such as -1+B.

[0019] Activating the thermometer arm 120 or the binary arm 122 refers to coupling the output voltage terminal 114 to the high voltage rail 116 via the activated thermometer arm 120 or the binary arm 122. Deactivating the thermometer arm 120 or the binary arm 122 refers to coupling the output voltage terminal 114 to the low voltage rail 118 via the deactivated thermometer arm 120 or the binary arm 122. The R2R resistor ladder 104 also includes a termination resistor 128 having a resistance 2R and M arm switches 130 that selectively connect the thermometer arm 120 and the binary arm 122 to the high voltage rail 116 or the low voltage rail 118.

[0020] The control circuit 106 includes a code input for receiving a code, such as a digital code. The control circuit 106 also includes a first set of M outputs coupled to the first set of M inputs of the R2R resistor ladder 104 to control the low-side switches of all arms of the R2R resistor ladder 104. The control circuit 106 further includes a second set of M outputs coupled to the second set of M inputs of the R2R resistor ladder 104 to control the high-side switches of all arms of the R2R resistor ladder 104. In some examples, the first and second sets of outputs of the control circuit 106 are respective buses that are each M control lines wide.

[0021] The code is a control input signal of the DAC 100 and is used to determine the control signal of the R2R resistor ladder 104. The control signal of the R2R resistor ladder 104 is used to activate and deactivate the thermometer arm 120 and the binary arm 122. Thus, in response to the code, the switch control 108 determines which combination of the thermometer arm 120 and the binary arm 122 to couple to the high voltage rail 116 or the low voltage rail 118, and in response, the R2R resistor ladder 104 outputs a voltage representing the code to the V OUT114. The switch control 108 provides a control signal to the gate driver 112 to drive the PFET switch 132 or the NFET switch 134 to couple the temperature measurement arm 120 and the binary arm 122 to the high voltage rail 116 or the low voltage rail 118, respectively. The voltage regulator 110 is used to set the voltage used by the gate driver 112 to drive the NFET switch 134. In some examples, the switch control 108, the voltage regulator 110, or the gate driver 112 are implemented as digital circuits, analog circuits, or mixed digital / analog circuits.

[0022] For purposes of explanation, we will assume an ideal DAC 100 output voltage response to an input code. In some instances, in response to non-ideal behavior of the DAC 100, the thermometer arms 120 and binary arms 122 activated or deactivated by the control signals of the R2R resistor ladder 104 will differ from the thermometer arms 120 and binary arms 122 that correspond to the code. Ideally, for an N-bit code corresponding to a DAC 100 with N-bit resolution, the T most significant bits correspond to the thermometer arms 120 and the B least significant bits correspond to the binary arms 122. Each thermometer arm 120 corresponds to a code value of 2 B The jth binary arm 122 corresponds to the code value 2 B-j where the 1st binary arm 122 is the MSB binary arm 122 and the Bth binary arm 122 is the LSB binary arm 122.

[0023] The thermometer arms 120 include arm resistors 124 having a resistance 2R. The arm resistors 124 of the thermometer arms 120 are individually labeled with subscripts (1-2) depending on the ordinal position of the respective thermometer arm 120 within the set of thermometer arms 120. T The arm resistors 124 of the thermometer arms 120 are numbered in subscripts in the order in which the thermometer arms 120 are activated as the code increases. For example, the first arm resistor is 1241, the second is 1242, and so on. T-1) (the last arm resistor 124 of the thermometer arm 120) is 124 2^T-1 A first terminal of the arm resistor 124 of the thermometer arm 120 is connected to the output voltage terminal 114.

[0024] The binary arm 122 includes an arm resistor 124 having a resistance 2R and a connector resistor 126 having a resistance R. M=2 T Recall that the value is -1+B. The individual resistors of the arm resistors 124 of the binary arms 122 are labeled with a subscript (2 T The individual resistors in the connector resistors 126 of the binary arms 122 are numbered with subscripts (1 to B) from the MSB binary arm 122 to the LSB binary arm 122. For example, the most significant bit (1st) arm resistor 124 2^T and connector resistor 1261, next most significant bit (second) arm resistor 124 2^T+1 and connector resistor 1262, and least significant bit (Bth) arm resistor 124 M and connector resistor 126 B is.

[0025] The connector resistors 126 of the binary arm 122 are connected in series between the voltage output terminal 114 and a first terminal of the termination resistor 128. More specifically, a first terminal of a first connector resistor 1261 is connected to the voltage output terminal 114. A second terminal of the first connector resistor 1261 is connected to a first terminal of a second connector resistor 1262, and so on. Finally, the Bth connector resistor 126 B A second terminal of the resistor 128 is connected to a first terminal of the termination resistor 128. A second terminal of the termination resistor 128 is connected to the low voltage rail 118.

[0026] The arm switch 130 includes a PFET switch 132 (high-side switch) and an NFET switch 134 (low-side switch). The arm switches 130 and the corresponding PFET switches 132 and NFET switches 134 are numbered with the same subscript as the subscript of the corresponding connected arm resistor 124. The jth arm resistor 124 of the thermometer arm 122 j (1≦j≦2 T The first terminal of the j-th arm resistor 124 of the thermometer arm 122 is connected to the output voltage terminal 114. j The second terminal of the j-th PFET switch 132 j and the jth NFET switch 134 j The j-th arm resistor 124 of the binary arm 122 is connected to the drain of the 2^T-1+j The first terminal of (1≦j≦B−1) is the jth connector resistor 126 j and j+1th connector resistor 126 j+1 The B-th arm resistor 124 of the binary arm 122 is connected between B The first terminal of the B-th connector resistor 126 B and the termination resistor 128. The j-th arm resistor 124 of the binary arm 122 2^T-1+j The second terminal of (2 T (-1+j)th PFET switch 132 2^T-1+j Source and (2 T (-1+j)th NFET switch 134 2^T-1+j The drain of the transistor is connected to the drain of the transistor.

[0027] jth PFET switch 132 j (1≦j≦M) drains are connected to the high voltage rail 116, and the j-th NFET switch 134 j The source of the jth PFET switch 132 is connected to the low voltage rail 118. j The gate of the jth NFET switch 134 is connected to a corresponding one of M high-side control lines 134. j The drains of the transistors 132 and 133 are connected to corresponding ones of the M low-side control lines 136.

[0028] The thermometer arm 120 or the binary arm 122 controls V by turning on the corresponding PFET switch 132 and turning off the corresponding NFET switch 134. REFP The thermometer arm 120 or the binary arm 122 can be coupled to V by turning off the corresponding PFET switch 132 and turning on the corresponding NFET switch 134. REFM By selectively activating or deactivating the thermometer arm 120, an analog output voltage V responsive to the code can be generated. OUT By selectively activating or deactivating the binary arm 122, an analog output voltage V responsive to the code is provided. OUT Activating h thermometer arms 120 provides a relatively fine selection of V OUT becomes. TIFF2026507183000002.tif557 formula 1

[0029] Activating up to B j-th binary arms 122 specified by a code generates a voltage V as given by Equation 2. OUT becomes. TIFF2026507183000003.tif654 formula 2

[0030] Activating and deactivating the thermometer arm 120 and the binary arm 122 is controlled by the switch control 108 in response to codes received by the control circuit 106 .

[0031] 2 is a functional block and circuit diagram of an example resistance and voltage model 200 of the thermometer arm 120 and binary arm 122 of the R2R DAC 100 of FIG. 1 in intermediate code. In the drawings, the same reference numerals or other reference designators are used to indicate the same or similar features (structurally and / or functionally).

[0032] The model 200 is a graph showing the R of the PFET switch 132 in the thermometer arm 120 and the binary arm 122. ON and R of the NFET switch 134 ON How is the difference between the R2R and V of the DAC100? OUT The term "intermediate code" is used to describe how the nonlinearity of a code can contribute to the nonlinearity of a code. An intermediate code or "mid-code" is midway between the first value of the code (zero code) and the last value of the code (full code). In some examples, the first value of the code is 0 or 000...000 (N zeros), and the last value of the code is 2 N -1 or 111...111 (N 1s), and the intermediate code is 2 N-1 -1 or 011...111 (a zero followed by N-1 ones). In the intermediate code, the value of the thermometer arm 120 is rounded down by half (2 T-1 -1) is activated and the thermometer arm 120 is rounded up to half the value (2 T-1 ) are deactivated, and all binary arms 122 are activated, providing a voltage equal to the other active thermometer arm 120 (minus one LSB, which for the purposes of this model can be ignored for the precision R2R DAC 100).

[0033] The model 200 calculates the equivalent on-resistance (R) of the PFET switch 132 that is turned on to activate the thermometer arm 120 and the binary arm 122. ON )R SWITCH-P 202(V REFP ), the equivalent resistance R of the activated thermometer arm 120 and binary arm 122 ARM-ON 204 and the equivalent R of the NFET switch 134 that is turned on to deactivate the thermometer arm 120 that is deactivated. ON R SWITCH-M 206(V REFM ) and the equivalent resistance R of the deactivated thermometer arm 120 ARM-OFF Includes 204. R SWITCH-P Parallel 2, corresponding to 202 T-1The resistance of the PFET switches 132 in one turned-on thermometer arm 120 and B turned-on binary arms 122 is R ON (PFET) / 2 T-1 R SWITCH-M 206, parallel 2 T-1 The resistance of the turned-on NFET switches 134 is R ON (NFET) / 2 T-1 2 T-1 - the look-in resistance of one thermometer arm resistor 124 and the various resistors of the B binary arms 122 is R ARM-ON Corresponding to 204. Parallel 2 T-1 The resistance of the thermometer arm resistor 124 is R TH-OFF Corresponds to 208. R ARM-ON 204 and R TH-OFF 208 is 2R / 2 T-1 is equal to.

[0034] All thermometer arms 120 and binary arms 122 are deactivated, so V OUT is true at zero code, so V OUT is zero (or V REFM ) Since all thermometer arms 120 and binary arms 122 are activated, V OUT is also correct in the full code, so V OUT is V REFP ×(2 N -1) / 2 N (V REFP As illustrated by model 200, in the intermediate code, the voltage from high voltage rail 116 through activated thermometer arm 120 and binary arm 122 to V OUT 114 is connected to the low voltage rail 118 via the deactivated thermometer arm 120 to V OUT If these resistances are equal in the intermediate code, the thermometer arm 120 and the binary arm 122 will both have a voltage of V, which is half the voltage that the thermometer arm 120 and the binary arm 122 can contribute. OUT(See Equations 1 and 2). If these resistances are different at intermediate codes, INL errors will occur.

[0035] FIG. 3 is a functional block and circuit diagram of a circuit 300, which includes a gate driver 112 for providing gate voltages for the NMOS switches 134 of the thermometer arm 120 and the binary arm 122. N The circuit 300 also includes an exemplary voltage regulator 110 coupled to the arm switch 130 and a gate driver 112 (gate driver 112) for the PFET switch 132. P ), and a gate driver for the NFET switch 112 (gate driver 112 N ) and switch control 108. In one example, the voltage regulator 110, gate driver 112 of FIG. P , gate driver 112 N , and switch control 108 is one implementation of control circuit 106 of FIG. 1. In this example, gate driver 112 of FIG. P and gate driver 112 N 1. The gate driver 112 is controlled by the switch control 108. P and 112 N The control signal provided to (see description of FIG. 1) determines which PMOS switch 132 or NMOS switch 134 the gate driver 112 drives to activate or deactivate the respective temperature measurement arm 120 or binary arm 122.

[0036] The switch control 108 is connected to a gate driver 112 P a first output connected to the input of the gate driver 112; N and a second output connected to the input of the gate driver 112. P is connected to the ground terminal 306, which is an electrical ground, and the gate driver 112 P The output of the gate driver 112 is connected to the gate of the PFET switch 132. N The voltage input is V SN receives the voltage V SNis used to drive the NFET switch 134 from the output of the voltage regulator 110, as described further below. In some examples, a single gate driver 112 N voltage V to enable driving the various NFET switches 134 of the R2R resistor ladder 104. SN A single voltage regulator 110 is sufficient to provide

[0037] Gate Driver 112 N The output of the NFET switch 134 is connected to the gate of the NFET switch 134. In response to the code, the switch control 108 adjusts the voltage at the ground terminal 306 (V SS ) to drive the PFET switch 132. P to activate the corresponding thermometer arm 120 or binary arm 122. Alternatively, the switch control 108 may control V SN gate driver 112 to drive NFET switch 134 using N to deactivate the corresponding thermometer arm 120 or binary arm 122. Therefore, V REFP and V REFM In response to receiving SN The switch control 108 receives the digital code and applies V to selected ones of the NFET switches 134. SN (e.g., using a set of switches) to provide N Also, in response to the digital code, the switch control 108 controls the gate driver 112 to provide Vss to selected ones of the PFET switches 132. P Control.

[0038] The voltage regulator 110 includes n ladder PFETs, a ground terminal 306, and a resistor R C A first resistor (R C )310 and resistance y×R C A second resistor (yR C) 312, a first differential amplifier 314, y×n ladder NFETs 316, and y×n−1 third resistors (R B resistor 320, a current source 322, and a resistor R A A fourth resistor (R A ) 388 and resistance y × R A A fifth resistor (yR A ) 340, where n and y are integers. In some examples, n is greater than or equal to 1. In some examples, y is greater than or equal to 1. In some examples, y is greater than 1. Current source 322 includes a first regulator PFET 326 and a resistor n×R B A fourth resistor (nR B ) 328, a second differential amplifier 330, n second regulator PFETs 332, and regulator resistors 334. B The use of current source 322 in conjunction with resistor 320 avoids introducing nonlinearities associated with the stacked drain-source voltages of ladder NFET 316, as further explained below.

[0039] As shown, the high voltage rail 116 is connected to the sources of the first ladder PFETs 3041. When turned on, the first ladder PFETs 3041 each have an equivalent resistance R P where n is greater than or equal to 1. By cascaded, the ladder PFET 304 has a drain-to-source (high voltage rail 116 and R C 310) and have their gates connected together to a ground terminal 306 to form a p-ladder 308 that includes n ladder PFETs 304. The ladder PFETs 304 are therefore turned on in response to the R2R DAC 100 being powered up and providing power to the high voltage rail 116. Each of the ladder PFETs 304 is numbered with a subscript (1 through n) starting with the ladder PFET 304 closest to the high voltage rail 116.

[0040] As mentioned above, the gate of the PFET switch 132 in the thermometer arm 120 is connected to the voltage at the ground terminal 306 (V SS ) to the gate driver 112 P The gate of the NFET switch 134 in the thermometer arm 120 is turned on by the voltage V at node A 324. SN Using the gate driver 112 N , and node A 324 is coupled to or forms the output of voltage regulator 110. Therefore, node 324 is also referred to as output 324 of voltage regulator 110. Voltage V SN is determined such that when the NFET switch 134 of the thermometer arm 120 or binary arm 122 is turned on, its equivalent resistance is close to the equivalent resistance of the PFET switch 132 of the turned on thermometer arm 120 or binary arm 122 (further explained with respect to Equation 6).

[0041] nth ladder PFET304 n The drain of R C 310. R C The second terminal of 310 is connected to yR C 312 and the non-inverting input of the first differential amplifier 314. Here, the first end of the ladder PFET 304 (of the p-ladder 308) corresponds to the first ladder PFET 3041, and the second end of the ladder PFET 304 corresponds to the nth ladder PFET 304 n Corresponds to.

[0042] yR C The second terminal of 312 is connected to the drain of first ladder NFET 3161. First ladder NFET 3161 is one of y×n cascaded ladder NFETs 316, each of which has an equivalent resistance R N Therefore, ladder NFET 316 has a drain-to-source (yR C 312 and the low voltage rail 118) to form an n-ladder 318 including y×n ladder NFETs 316. Each of the ladder PFETs 304 has a y×n CThe PFETs 304 are numbered with subscripts (1 to y×n) starting with the ladder PFET 304 connected to the second terminal of 312.

[0043] (y×n)th ladder NFET316 y×n The sources of the first ladder NFETs 3161 are connected to the low voltage rail 118. The gates of the first ladder NFETs 3161 are connected to the low voltage rail 118. B y×n−1 third resistors (R B A first terminal of a first resistor of the resistors 320 is connected to the output terminal of the current source 322. B Each of the resistors 320 has an R connected to the gate of the first ladder NFET 3161. B The resistors 3201 are numbered with subscripts (1 to y×n−1) starting with the ladder NFET 316 (of the n ladders 318), where the first end of the ladder NFET 316 corresponds to the first ladder NFET 3161, the second end of the ladder NFET 316 corresponds to the nth ladder PFET 316, and so on. n Corresponds to.

[0044] The first R B The second terminal of resistor 3201 is connected to the gate of the second ladder NFET 3162 and the second R B The gates of adjacent ones of the n ladder NFETs 316 are connected to the first terminal of the y×n−1 R B The (y×n)th ladder FET 316 is connected together through a resistor 320. y×n The gate is the (y×n-1)th R B resistor 320 y×n-1 the second terminal of the first differential amplifier 314, and the output of the gate driver 112 (via the output of the voltage regulator 110). N This connection (e.g., with the output of the first differential amplifier 314) is connected to the voltage input of the voltage V SN As mentioned above, the gate driver 112 N applies V to the gate of NFET switch 134 to turn on NFET switch 134. SNThis is done when controlled to do so by switch control 108.

[0045] The drain-source voltage V of each ladder PFET 304 DS are ideally equal, the same, or substantially the same, depending on manufacturing process variations. Similarly, the drain-source voltage V of each ladder NFET 304 DS are ideally equal, the same, or substantially the same, except that, as will be explained below, the V DS The error accumulated in R B This is avoided in ladder NFET 316 as a result of resistor 320 .

[0046] The description of current source 322 is as follows: The drain of first regulator PFET 326 is connected to the output terminal of current source 322. The source of first regulator PFET 326 is connected to the output terminal of resistor n×R B A fourth resistor (nR B ) 328 and the inverting input of a second differential amplifier 330. When the current through the first regulator PFET 326 is DS / R B , and this current is set as follows: The gate of the first regulator PFET 326 is connected to the output of the second differential amplifier 330. nR B The second terminal of 328 is connected to the high voltage rail 116 .

[0047] The source of a first of the n second regulator PFETs 3221 is connected to the high voltage rail 116. The second regulator PFETs 322 are cascoded. Thus, the second regulator PFETs 322 are connected in series from drain to source (between the high voltage rail 116 and node B 336) with their gates connected together to ground 306. Each of the second regulator PFETs 322 is numbered with a subscript (1 to n) starting with the second regulator PFET 3321 closest to the high voltage rail 116. The second regulator PFETs 322 are matched with the ladder PFET 304. In some examples, matched MOSFETs include MOSFETs that are the same size or substantially the same size. In some examples, matched MOSFETs include matching orientation and / or the use of matched dummy fingers and / or the use of matched interleaving, meaning that these parameters are the same or substantially the same throughout the matched MOSFETs.

[0048] As previously mentioned, the drain-source voltage of each second regulator PFET 322 is V DS and is subject to errors as described above and further below. n The drain of the resistor 334 is connected to the non-inverting input of the second differential amplifier 330 and to the first terminal of the regulator resistor 334. This connection (to the non-inverting input of the second differential amplifier 330, etc.) provides a voltage V REFP -n×V DS A second terminal of regulator resistor 334 is connected to low voltage rail 118. The resistance of regulator resistor 334 is selected so that the source-drain current flowing through second regulator PFET 322 is equal to the source-drain current flowing through ladder PFET 304. This, in conjunction with the matching described above, determines the V DS is the V of the ladder PFET304 DSwhere the first end of the second regulator PFET 332 corresponds to the second regulator PFET 3321 closest to the high voltage rail 116, and the second end of the second regulator PFET 332 corresponds to the nth second regulator PFET 332 n Corresponds to.

[0049] The second differential amplifier 330 operates such that the voltage at its inverting input is equal to the voltage V at node B 336. REFP -n×V DS Set the voltage at the output to be equal to V REFP and V REFP -n×V DS nR is the difference between B The voltage across 328 is n × V DS This is equal to the current provided by current source 322 (I RB ) is expressed as nR B The voltage across 328 is nR B This means it is equal to 328 divided by the resistance. I RB =(n×V DS ) / (n×R B )=V DS / R B formula 3

[0050] Resistance R A A fourth resistor (R A ) 338 is connected to the high voltage rail 116. A The second terminal of 338 is connected to the inverting terminal of the first differential amplifier 314 and the resistor y×R A A fifth resistor (yR A ) 340 and the first terminal of yR A The second terminal of 340 is connected to the low voltage rail 118. This part of the voltage regulator (R A 338 and yR A 340 ) sets the target voltage for the inverting input of the differential amplifier 314 .

[0051] Negative feedback forces the voltage at the non-inverting input of differential amplifier 314 to equal (or substantially equal) this target voltage. This reduces the on-resistance (R N ) is the on-resistance of the ladder PFET 304 (R P ) of the individual NFET switches 134 in the thermometer arm 120 and binary arm 122. NLADDER ) also corresponds to the on-resistance (R PLADDER ) to account for non-ideal circuit behavior. P and R N The difference between PLADDER and R NLADDER The difference between is determined by Equations 4 to 8 (described below).

[0052] current I RB is the gate-source voltage of the ladder NFET316 (V GS ) is used to equalize the (y×n)th ladder NFET316 y×n is the gate voltage V SN and source voltage V REFM R B If resistor 320 is not present, then the (y×n−1)th ladder NFET 316 y×n-1 is the gate voltage V SN and source voltage V REFM +V DS The (y×n-2)th ladder NFET316 y×n-2 is the gate voltage V SN and source voltage V REFM +2×V DS and so on, with V for each successive ladder NFET 316. DS This results in a successively increasing error, except that the V of each successive ladder NFET 316 will be slightly different. GS will be slightly different.

[0053] R BThe current I across resistor 320 B addresses this cumulative error. Each R B There is a voltage drop R across resistor 320. B ×I B =R B ×V DS / R B Therefore, the (y×n-1)th ladder NFET316 y×n-1 is the gate voltage V SN +V DS and source voltage V REFM +V DS (y×n-2)th ladder NFET316 y×n-2 is the gate voltage V SN +V DS and source voltage V REFM +2×V DS , and so on, so that each (matched) ladder NFET 316 has the same gate-source voltage, and therefore the same V DS It has.

[0054] R PLADDER and R NLADDER The difference between is given by Equation 4. TIFF2026507183000004.tif13133 formula 4

[0055] V OS is the offset voltage of the first differential amplifier 314 (caused by non-ideal characteristics of the first differential amplifier 314). The scaling factor k is N R NLADDER Therefore, k is given by Equation 5. k=R N / R NLADDER formula 5

[0056] If the drain-source voltages of the stacked ladder NFETs 316 are equal, the accuracy of Equation 4 is improved. PLADDER -R NLADDER can be determined from the INL target (INL design budget) as described in Equation 6. Max INL=(R PLADDER -R NLADDER)×2 N / (8×R) Equation 6

[0057] In Equation 6, Max INL is the INL target value, R is the R resistance unit used in FIG. 1, and N is the bit resolution of the R2R DAC 100. NLADDER is the difference R as shown in Equation 7. PLADDER -R NLADDER It can be written in units of TIFF2026507183000005.tif13135 formula 7

[0058] As y increases, the corresponding term in Equation 4 approaches 1 from 2 (when y is 1). Equation 4 also shows that as y and / or n increase, R PLADDER and R NLADDER This shows that the difference between R and R decreases. In some instances, as the size of a transistor decreases, its on-resistance increases, and as the size of a transistor increases, its on-resistance decreases. Thus, Equation 4, Equation 5, and Equation 7 show that with the offset factor y, the on-resistance is 2y / (1+y) times higher than without the offset factor y. NLADDER where y is greater than 1 (equivalently, if y is equal to 1). Therefore, the offset factor y allows the size of NFET switch 134 to be (1+y) / 2y times larger than it would otherwise be. In some examples, if y is equal to 5, the size of NFET switch 134 may be 3 / 5 of the size it would be if y was equal to 1.

[0059] In some instances, V due to the ladder PFET 306 and regulator PFET 332 being stacked GS The errors are not corrected, so n is relatively small to avoid the accumulation of corresponding nonlinearities. BUsing resistors 320 to equalize the gate-source voltages of ladder NFETs 316 allows a relatively large number of ladder NFETs 316 to be stacked, i.e., y can be relatively large. Therefore, using a resistive offset y can reduce the nonlinearity, thereby allowing for a larger number of stacked ladder NFETs 316, and reduce R as described in Equation 7. NLADDER increases (and the size of NFET switch 134 decreases). Therefore, smaller PFET switch 132 and NFET switch 134 can be used without increasing the nonlinearity due to the unequal resistance of PFET switch 132 and NFET switch 134. In one example, y is equal to 5, n is equal to 2, and R PLADDERR -N LADDER is equal to 0.4 ohms (Ω), and V DS is equal to 20 millivolts (mV), and V OS is equal to 2mV, so (using Equation 7) R NLADDER is equal to 6.7 ohms.

[0060] As mentioned above, R NLADDER , which can be used to determine the size or width / length (W / L) ratio of the NFET switch 134. R, which can be used to determine the size or W / L ratio of the PFET switch 132. PLADDER is given by Equation 8. R PLADDER / R NLADDER= R P / R N formula 8

[0061] In some examples, the PFET switch 132, the NFET switch 134, and the transistors in the p-ladder 308 and the n-ladder 318 are operated deep in the triode region. For transistors in the triode region, V DS =I DS ×R ONTherefore, Equation 5 can be rewritten as shown in Equation 9, which relates certain currents and voltages of the arm switches 130 of the thermometer arm 120 and the binary arm 122 to certain currents and voltages of the voltage regulator 110. TIFF2026507183000006.tif1684 formula 9

[0062] V DS_LADDER is the drain-source voltage across the turned-on PFET switch 132 or NFET switch 134 in each thermometer arm 120 and binary arm 122, and I LADDER is the current flowing through it. I LADDER is V REF / (4 × R), where V REF is V REFP -V REFM where R is the resistance unit used in Figure 1. DS_REGULATOR is the drain-source voltage across the turned-on ladder PFET 304 in the p-ladder 308 or the ladder NFET 316 in the n-ladder 318, and I REGULATOR is the current flowing through it. In one example, I REGULATOR teeth ILADDER is equal to V REF is equal to 5V, R is equal to 128kΩ, so I(ladder) is equal to 10 microamperes, and V DS (ladder) is equal to 67 microvolts (μV), and V DS_REGULATOR is equal to 20mV, k is equal to approximately 300 (20mV / 67µV), so R N is approximately 2 kΩ. Therefore, in the described example, ladder PFET 304 and ladder NFET 316 can be fabricated with an equivalent resistance of 2 kΩ using available process nodes. In some examples, the characteristics of the various transistors are further adjusted to address second-order effects.

[0063] Therefore, the V of the ladder NFET316 GS Value and V DSBy matching the values, the voltage regulator 110 can more precisely regulate the gate voltages of the NFET switches 134 in the thermometer arm 120 and the binary arm 122 to reduce R PLADDER and R NLADDER The resistance offset y also allows a greater number of stack ladder NFETs 316 to be used, allowing the voltage regulator 110 to more precisely regulate the temperature 120 and the gate voltages of the NFET switches 134 in the binary arms 122 to reduce the difference between R PLADDER and R NLADDER This can reduce the difference between R PLADDER and R NLADDER By reducing the difference between R2R resistor ladder 104 and NFET switches 120 and 122, the R2R resistor ladder 104 can reduce the size of the NFET switches in the thermometer arm 120 and the binary arm 122 while meeting the same nonlinearity budget.

[0064] 4 is a circuit diagram of an example R2R resistor ladder 400. In one example, R2R resistor ladder 400 is an implementation of R2R resistor ladder 104 of FIG. 1. R2R resistor ladder 400 includes a structure corresponding to R2R resistor ladder 104 of FIG. 1, and includes resistors R OS An additional offset resistor (R OS ) 402. Resistor R OS 402 is the P-th connector resistor 126 P The resistor R has a first terminal coupled to a second terminal of the resistor R. OS 402 is the (P+1)th connector resistor 126 P+1 The first terminal of (2 T -1+P)th arm switch 130 2^T-1+P Arm resistor 124 connected to 2^T-1+P In the illustrated example, P is equal to B-2, and the (B-2)th connector resistor 126 B-2 and the (M-2)th arm switch 130 M-2 In some examples, R OS 402 is the P-th connector resistor 126 P It is implemented as an additional resistor that is part of the

[0065] In some instances, due to the characteristics of the R2R resistor ladder 104, the (j+1)th binary arm 122 j+1 The PFET switch 132 in the arm switch 130 of the jth binary arm 122 j The (j+1)th binary arm 122 has twice the total resistance of the PFET switch 132 in the (j+1)th binary arm 122, and therefore the former has half the size of the latter. j+1 The NFET switch 134 in the arm switch 130 of the jth binary arm 122 j The temperature measurement arm 120 has twice the total resistance and half the size of the NFET switch 134 in the binary arm switch 130. The temperature measurement arm 120 can be considered the zeroth binary arm 122 in terms of this scaling. The scaling of the PFET switch 132 and NFET switch 134 in the binary arm is done to balance the R2R resistor ladder 104.

[0066] In some examples, doubling the resistance by halving the size of each successive PFET switch 132 / NFET switch 134 pair means that for the smallest PFET switch 132 and NFET switch 134 (the switches on the LSB binary arm 122) that can be fabricated by an available process, the largest PFET switch 132 and NFET switch 134 (the switches on the thermometer arm 120) occupy a relatively large device area. In some examples, the device area limits the maximum size (and therefore the minimum resistance) of the PFET switch 132 and NFET switch 134.

[0067] Conversely, LSB arm switch 130 N (Bth binary arm 122 B In some instances, a series stack of MOSFETs in arm switch 130 is used to compensate for the unavailability of smaller switch sizes. In some instances, the switch stack allows for the VGS and V DS There are additional DNL contributions due to issues such as the problem of . Compensating for such DNL generation issues can incur significant additional area costs, and such compensation structures can incur switching speed costs.

[0068] Also, as noted, the resistance of PFET switch 132 and NFET switch 134 increases (towards LSB binary arm 122) as the subscript number of arm switch 130 increases. DS also increases as the subscript number of the switch 130 in the binary arm 122 increases. DS As θ increases, the precision of the resistance of the PFET switch 132 and the NFET switch 134 decreases, i.e., process errors increase. In some instances, the precision of the switch resistance deteriorates to the point that the PFET switch 132 and the NFET switch 134 operate in saturation mode rather than triode mode.

[0069] In some examples, to mitigate or prevent these problems, the arm switch 130 of the (P-1)th binary arm 122 P-1 (P-th binary arm 122 arm switch 130 P , (P+1)th, etc.) the size of the PFET switch 132 and NFET switch 134 of the arm switch 130 of the (P-1)th binary arm 122 P-1 This is called "stop scaling" and is maintained equal to the size of the arm switch 130 of the (P-1)th binary arm 122. P-1 Following this, the continuous scaling down of the arm switch 130 is stopped.

[0070] In the R2R resistor ladder 400, the switch sizes are indicated by labels such as "Size A," "Size 2A," "Size 4A," etc. As noted above, in the example R2R resistor ladder 400 of FIG. 4, P is equal to B-2. Therefore, the arm switch 130 of the (P-1)th binary arm 122 P-1 , as well as the lower bit arm switch 130 (arm switch 130 P , 130 P+1 , etc.) have respective sizes corresponding to size A. In some examples, the PFET switch 132 and the NFET switch 134 have the same size corresponding to size A. In some examples, size A indicates a size of the PFET switch 132 that is different from the size of the NFET switch 134. P-2 The PFET switch 132 and the NFET switch 134 of the (P-3)th binary arm 122 have respective sizes corresponding to size 2A. P-3 The PFET switch 132 and NFET switch 134 have respective sizes corresponding to size 4A, and so on.

[0071] Due to stop scaling, the Pth and subsequent (lower-order bit) arm switches 130 contribute additional DNL. In some examples, the Pth binary arm 122 contributes additional DNL due to stop scaling, and each successive arm after the Pth binary arm 122 contributes half the DNL due to stop scaling. The DNL contribution arises from a mismatch in look-in impedance between the binary arm 122 where the binary scaling of switch size is stopped and the more significant bit binary arms 122.

[0072] The look-in impedance (R eq ) is multiplied by 2R by the equivalent resistance component (R SWIn a balanced R2R resistor ladder 104 where the unit resistance R is the same and the arm switches 130 follow the binary scaling rule, R of the binary arms 122 is equal to eq The value is the same. The stop scaling is performed by the binary arm 122 to which the stop scaling is applied (the P-th binary arm 122 M )R SW Reduces R SW By the difference of Pth binary arm 122 M R eq is the R of the more significant binary arm 122 eq R eq The difference between the offset resistance (R OS ) 402.

[0073] Figure 5A is an example graph 500 of DNL error versus code for the R2R DAC 100 of Figure 1. In the illustrated example, stop scaling has been applied, so the DNL error plot 502 shows a relatively large maximum DNL error peak 504 at the code corresponding to the arm switch 130 where no scaling was applied.

[0074] 5B is an example graph 506 of DNL versus code for an R2R DAC using the R2R resistor ladder 400 of FIG. 4. The graph 506 includes a DNL error plot 508. In the example shown, stop scaling has been applied. However, R OS 402 produces a DNL error 510 in the code corresponding to the shifted arm switch 130 without scaling applied. This spreads the DNL error range for the arm switch 130 without scaling applied from a positive range to a negative range. Thus, the maximum magnitude of the DNL error 510 is reduced. In some examples, the sum of the existing maximum DNL magnitude and the maximum DNL magnitude resulting from the stop scaling is halved.

[0075] FIG. 6 illustrates the addition of an offset resistor R to the arm switch 130 of the least significant bit binary arm 122 of the R2R resistor ladder 104 to allow for stop scaling. OS 6 is an exemplary process for determining where to place the V 402 of the R2R resistor ladder 104. OUT A DNL budget is determined for the DNL added by stop scaling to the R2R DAC 100. In some examples, a DNL budget of 0.2 LSB, or another amount less than 1 LSB (or significantly less), is used as the DNL budget for the R2R DAC 100. In step 604, the Pth binary arm switch 130 P and the lower-order binary arm switch (130 P+1 etc.), while applying stop scaling to the P-th connector resistor 126 P offset resistor R OS By adding 402, the P-th binary arm switch 130 is configured to add a DNL amount that is less than the DNL budget. M is determined. In some examples, the DNL may be expressed as a function of P, and P may be determined in response to a DNL budget. In some examples, P is determined empirically.

[0076] 7 is a functional block and circuit diagram of an alternative example circuit 700 including an alternative example voltage regulator 110 for the gate voltages of the NMOS switches 134 of the thermometer arm 120 and the binary arm 122. The voltage regulator 110 of FIG. 7 is similar to the voltage regulator 110 of FIG. 3, except that the voltage regulator 110 of FIG. 7 does not include the third resistor (R B ) 318 and current source 322. The voltage regulator 110 of FIG. C A second resistor (yR C ) 312 and n-ladder 318. Thus, the voltage regulator 110 of FIG. 7 includes R PLADDER and R NLADDERIn some examples, the V of ladder NFET 316, as described with respect to FIG. GS Uncorrected mismatch between the

[0077] Variations in the described examples are possible, and other examples are possible, within the scope of the claims.

[0078] In some examples, an R2R resistor ladder includes zero or more thermometer arms and two or more binary arms.

[0079] In some instances, the minimum MOSFET size referred to herein refers to a MOSFET having the smallest width or length (or other) dimension available within a corresponding manufacturing process.

[0080] In some examples, resistor ladders other than R2R resistor ladders are used. In some examples, the resistance of the connector resistors 124 or arm resistors 126 is intentionally modified, such as to induce an intentional DNL value or sign of the value to facilitate trimming.

[0081] In some cases, the V of the ladder NFET GS A current source and resistor arrangement similar to that used for the V GS . In some instances, this is not done because there is insufficient voltage range (headroom) to do this. In some instances, there is insufficient headroom to do this because the R2R resistor ladder 104 is designed to swing from the low (minimum) rail to the high (maximum) rail of the corresponding IC.

[0082] In some examples, ladder PFET 306 and PFET switch 132 are matched (or corresponding design techniques are applied) and / or ladder NFET 316 and NFET switch 134 are matched (or corresponding design techniques are applied). For example, matching can be applied using the same placement orientation, the same use of dummy devices, and the same use of equal-sized fingers. For example, for equal-sized features, if ladder NFET 306 is designed as a single-finger PFET having a unit width and unit length, the NFET switch is designed as a multi-finger PFET with X fingers, one of which has a unit width and unit length. In some examples, X is much greater than 1.

[0083] In some examples, to further reduce the maximum magnitude of DNL caused by stop scaling, one or more offset resistors are added between one or more pairs of connector resistors having subscripts (lower bits) of numbers higher than the Mth and (M+1)th connector resistors.

[0084] The term "coupled" is used throughout this specification. This term may encompass a connection, communication, or signal path that enables a functional relationship consistent with this description. For example, in a first example, device A is coupled to device B when device A provides a signal to control device B to perform a certain operation, or in a second example, device A is coupled to device B through an intervening component C such that device B is controlled by device A through a control signal provided by device A, without substantially changing the functional relationship between device A and device B.

[0085] In this description, the term "and / or" (when used in the form A, B, and / or C, etc.) refers to any combination or subset of A, B, and C, such as, for example, (a) A only, (b) B only, (c) C only, (d) A with B, (e) A with C, (f) B with C, (g) A with B and C, etc. Also, as used herein, the phrase "at least one of A or B" (or "at least one of A and B") refers to implementations that include any of: (a) at least one A, (b) at least one B, and (c) at least one A and at least one B.

[0086] A device that is "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform that function by a manufacturer at the time of manufacture, and / or may be configurable (or reconfigurable) by a user after manufacture to perform that function and / or other additional or alternative functions. Such configuring may be achieved through firmware and / or software programming of the device, through the construction and / or layout of the hardware components and interconnections of the device, or a combination thereof.

[0087] As used herein, the terms "terminal," "node," "interconnect," "pin," "ball," and "lead" are used interchangeably and, unless otherwise noted, are used generally to refer to an interconnection between or termination of a device element, circuit element, integrated circuit, device or other electronic device or semiconductor component.

[0088] Circuits or devices described herein as including certain components may instead be coupled to those components and adapted to form the described circuit element or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage and / or current sources) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure, either during or after manufacture, e.g., by an end user and / or a third party.

[0089] Although the use of particular transistors is described herein, other transistors (or equivalent devices) may be used instead with little or no modification to the remaining circuit elements. For example, MOSFETs (e.g., n-channel MOSFETs, nMOSFETs, or p-channel MOSFETs, pMOSFETs), bipolar junction transistors (e.g., BJTs, NPN or PNP), insulated gate bipolar transistors (IGBTs), junction field-effect transistors (JFETs), and / or other field-effect transistors (e.g., FETs, n-channel FETs, or p-channel FETs) may be used in place of or in combination with the devices disclosed herein. The transistors may be depletion-mode devices, drain-extension devices, enhancement-mode devices, natural transistors, or other types of device structures. Additionally, the devices may be implemented in or on silicon (Si), silicon carbide (SiC), gallium nitride (GaN), or gallium arsenide (GaAs) substrates. Additionally, the control terminal of a FET may correspond to the base on a BJT or the gate or other corresponding structure of another type of transistor.

[0090] Circuits described herein are reconfigurable to include replaced components to provide functionality at least partially similar to that available prior to the replacement of the components. Components depicted as resistors, unless otherwise noted, generally represent any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the depicted resistor. For example, a resistor or capacitor depicted and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in parallel between the same nodes. For example, a resistor or capacitor depicted and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series between the same two nodes as a single resistor or capacitor.

[0091] While some elements of the illustrated examples may be included in an integrated circuit and other elements may be external to the integrated circuit, in other exemplary embodiments, additional or fewer features may be incorporated into the integrated circuit. Also, some or all of the features illustrated as being external to the integrated circuit may be included within the integrated circuit, and / or some of the features illustrated as being internal to the integrated circuit may be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" refers to one or more circuits that are (1) incorporated within / on a semiconductor substrate, (2) incorporated within a single semiconductor package, (3) incorporated within the same module, and / or (4) incorporated within / on the same printed circuit board.

[0092] Use of the term "ground" in the above description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable or appropriate to the teachings of the present application. Unless otherwise specified, "about," "approximately," or "substantially" in front of a value means within ±10 percent of the stated value, or, if the value is zero, a reasonable range of values ​​around zero.

Claims

1. 1. An integrated circuit (IC), comprising: a first resistor having a first terminal and a second terminal, the first resistor having a resistance R1; N p-channel field effect transistors (ladder PFETs) coupled together as a p-ladder, each ladder PFET having a source, a drain, and a gate, where N is an integer greater than or equal to 1, and when N is greater than 1, the ladder PFETs are coupled together as a p-ladder such that the gates of the ladder PFETs are coupled together, the drains and sources of the ladder PFETs are cascode-coupled between a first end and a second end of the p-ladder, and the second end of the p-ladder is coupled to the first terminal of the first resistor; a differential amplifier including a first input, a second input, and an output; a second resistor including a first terminal and a second terminal, the second resistor having a resistance y×R1, where y is an integer greater than 1, the first terminal of the second resistor being coupled to the second terminal of the first resistor and to the first input of the differential amplifier; y×N n-channel field effect transistors (ladder NFETs) coupled together as an n-ladder, each ladder NFET having a source, a drain, and a gate, the gates of the ladder NFETs coupled together, the drain and the source of the ladder NFETs cascode-coupled between a first end and a second end of the n-ladder, the first end of the n-ladder coupled to the second terminal of the second resistor, and the second end of the n-ladder coupled to the output of the differential amplifier; Including, IC.

2. 10. The IC of claim 1, a third resistor having a first terminal, a second terminal, and a resistance R2; a fourth resistor having a first terminal, a second terminal, and a resistance y×R2; further comprising the first terminal of the fourth resistor is coupled to the second terminal of the third resistor and to the second input of the differential amplifier.

3. 10. The IC of claim 1, a gate driver including an input and a plurality of outputs, the input of the gate driver being coupled to the output of the differential amplifier; an R2R resistor ladder including a plurality of arms coupled together; further comprising at least some of the arms each include a p-channel field effect transistor (PFET switch) and an n-channel field effect transistor (NFET switch), the source of the NFET switch coupled to the source of the PFET switch and the gate of the NFET switch coupled to one of the outputs of the gate driver that is different from the gate of the NFET switch of another arm; IC.

4. 10. The IC of claim 1, further comprising y×N−1 third resistors each having a resistance R2; an IC, wherein different pairs of the ladder NFETs having adjacently coupled drains and sources in the n-ladder have their respective gates coupled together via different ones of the third resistors.

5. 5. The IC of claim 4, each of the third resistors having a first terminal and a second terminal; the IC further includes a current source having a first terminal and a second terminal, the second terminal of the current source coupled to the gate of the ladder NFET at the first end of the n-ladder and to the first terminal of one of the third resistors.

6. 6. The IC of claim 5, Each of the ladder NFETs has a drain-source voltage V ＤＳ configured to have The current source is V ＤＳ an IC configured to provide a current equal to the value of the resistor R1 divided by R2.

7. 6. The IC of claim 5, wherein the ladder PFET is a first PFET, the p-ladder is a first p-ladder, and the differential amplifier is a first differential amplifier; The current source a second differential amplifier including a first input, a second input, and an output; a second PFET having a source, a drain, and a gate, the gate of the second PFET coupled to the output of the second differential amplifier and the drain of the second PFET coupled to the second terminal of the current source; a fourth resistor having a first terminal, a second terminal, and a resistance N×R2, the first terminal of the fourth resistor being coupled to the first input of the second differential amplifier and the source of the second PFET; a fifth resistor having a first terminal and a second terminal; N third PFETs, each having a source, a drain, and a gate; and when N is greater than 1, the third PFETs are coupled together as a second p-ladder so that the gates of the third PFETs are coupled together, the drains and sources of the third PFETs are cascode-coupled between a first end and a second end of the second p-ladder, and the second end of the second p-ladder is coupled to the first terminal of the fifth resistor and the second input of the second differential amplifier.

8. 1. An integrated circuit (IC), comprising: a first resistor having a first terminal, a second terminal, and a resistance R1; N p-channel field effect transistors (ladder PFETs), each ladder PFET having a source, a drain, and a gate, where N is greater than or equal to 1, and when N is greater than 1, the ladder PFETs are coupled together as a p-ladder such that the gates of the ladder PFETs are coupled together, the drains and sources of the ladder PFETs are cascode-coupled between a first end and a second end of the p-ladder, and the second end of the p-ladder is coupled to the first terminal of the first resistor; a differential amplifier including a first input, a second input, and an output; a second resistor having a first terminal, a second terminal, and having a resistance y×R1, where y is an integer greater than or equal to 1, so that y×N is greater than 1, and the first terminal of the second resistor is coupled to the second terminal of the first resistor and to the first input of the differential amplifier; y×N−1 third resistors, each having a resistance R2; a number y×N of n-channel field effect transistors (ladder NFETs) coupled together as an n-ladder, each ladder NFET having a source, a drain, and a gate, the drain and the source of the ladder NFETs being cascode-coupled between a first end and a second end of the n-ladder, the first end of the n-ladder being coupled to the second terminal of the second resistor, and the second end of the n-ladder being coupled to the output of the differential amplifier; Including, an IC, wherein different pairs of the ladder NFETs having adjacently coupled drains and sources in the n-ladder have their respective gates coupled together via different ones of the third resistors.

9. 9. The IC of claim 8, wherein y is greater than 1.

10. 9. The IC of claim 8, a fourth resistor having a first terminal, a second terminal, and a resistance R3; a fifth resistor having a first terminal, a second terminal, and a resistance y×R2; further comprising the first terminal of the fifth resistor is coupled to the second terminal of the fourth resistor and to the second input of the differential amplifier.

11. 9. The IC of claim 8, a gate driver including an input and a plurality of outputs, the input of the gate driver being coupled to the output of the differential amplifier; an R2R resistor ladder including a plurality of arms coupled together, at least some of the arms each including a p-channel field effect transistor (PFET switch) and an n-channel field effect transistor (NFET switch), the sources of the NFET switches coupled to the sources of the PFET switches and the gates of the NFET switches coupled to one of the outputs of the gate driver that is different from the gates of the NFET switches in other arms; The IC further includes:

12. 9. The IC of claim 8, each of the third resistors having a first terminal and a second terminal; the IC further includes a current source having a first terminal and a second terminal, the second terminal of the current source coupled to the gate of the ladder NFET at the first end of the n-ladder and to the first terminal of one of the third resistors.

13. 13. The IC of claim 12, Each of the ladder NFETs has a drain-source voltage V ＤＳ configured to have The current source is V ＤＳ an IC configured to provide a current equal to the value of the resistor R1 divided by R2.

14. 13. The IC of claim 12, wherein the ladder PFET is a first PFET, the p-ladder is a first p-ladder, and the differential amplifier is a first differential amplifier; The current source a second differential amplifier including a first input, a second input, and an output; a second PFET having a source, a drain, and a gate, the gate of the second PFET coupled to the output of the second differential amplifier and the drain of the second PFET coupled to the second terminal of the current source; a fourth resistor having a first terminal, a second terminal, and a resistance N×R2, the first terminal of the fourth resistor being coupled to the first input of the second differential amplifier and the source of the second PFET; a fifth resistor having a first terminal and a second terminal; N third PFETs, each including a source, a drain, and a gate; Including, when N is greater than 1, the third PFETs are coupled together as a second p-ladder such that the gates of the third PFETs are coupled together, the drains and sources of the third PFETs are cascode-coupled between a first end and a second end of the second p-ladder, and the second end of the second p-ladder is coupled to the first terminal of the fifth resistor and the second input of the second differential amplifier.

15. 1. A digital-to-analog converter system comprising: a gate driver including a first input, a second input, and a plurality of outputs; a control circuit including an input and an output, the output of the control circuit being coupled to the first input of the gate driver; an R2R resistor ladder including a plurality of arms coupled together, at least some of the arms each including a p-channel field effect transistor (PFET) switch and an n-channel field effect transistor (NFET) switch, the sources of the NFET switches being coupled to sources of the PFET switches and the gates of the NFET switches being coupled to different ones of the outputs of the gate driver than the gates of the NFET switches in other arms; A voltage regulator; Including, The voltage regulator a first resistor having a first terminal, a second terminal, and a resistance R1; N ladder PFETs, each having a source, a drain, and a gate, where N is an integer greater than or equal to 1, and when N is greater than 1, the ladder PFETs are coupled together as a p-ladder such that the gates of the ladder PFETs are coupled together, the drains and sources of the ladder PFETs are cascode-coupled between a first end and a second end of the p-ladder, and the second end of the p-ladder is coupled to the first terminal of the first resistor; a differential amplifier including a first input, a second input, and an output, the output of the differential amplifier being coupled to the second input of the gate driver; a second resistor having a first terminal, a second terminal, and a resistance y×R1, where y is an integer greater than 1, and the first terminal of the second resistor is coupled to the second terminal of the first resistor and to the first input of the differential amplifier; y×N ladder NFETs coupled together as an n-ladder, each ladder NFET having a source, a drain, and a gate, the gates of the ladder NFETs coupled together, the drains and sources of the ladder NFETs cascaded between a first end and a second end of the n-ladder, the first end of the n-ladder coupled to the second terminal of the second resistor, and the second end of the n-ladder coupled to the output of the differential amplifier; Including, Digital-to-analog converter system.

16. 16. A digital-to-analog converter system according to claim 15, comprising: a third resistor having a first terminal, a second terminal, and a resistance R2; a fourth resistor having a first terminal, a second terminal, and a resistance y×R2; further comprising The digital-to-analog converter system, wherein the first terminal of the fourth resistor is coupled to the second terminal of the third resistor and to the second input of the differential amplifier.

17. 16. A digital-to-analog converter system according to claim 15, comprising: further comprising y×N−1 third resistors each having a resistance R2; a first pair of the ladder NFETs, each having a drain and a source adjacently coupled within the n-ladder, each having a gate coupled together via a different one of the third resistors;

18. 18. A digital-to-analog converter system according to claim 17, comprising: each of the third resistors having a first terminal and a second terminal; the digital-to-analog converter system further includes a current source having a first terminal and a second terminal, the second terminal of the current source coupled to the gate of the ladder NFET at the first end of the n-ladder and to the first terminal of one of the third resistors.

19. 20. The digital-to-analog converter system of claim 18, comprising: Each of the ladder NFETs has a drain-source voltage V ＤＳ configured to have The current source is V ＤＳ a digital-to-analog converter system configured to provide a current equal to a value obtained by dividing by R2.

20. 20. The digital-to-analog converter system of claim 18, wherein the ladder PFET is a first PFET, the p-ladder is a first p-ladder, and the differential amplifier is a first differential amplifier; The current source a second differential amplifier including a first input, a second input, and an output; a second PFET having a source, a drain, and a gate, the gate of the second PFET coupled to the output of the second differential amplifier and the drain of the second PFET coupled to the second terminal of the current source; a fourth resistor having a first terminal, a second terminal, and a resistance N×R2, the first terminal of the fourth resistor being coupled to the first input of the second differential amplifier and the source of the second PFET; a fifth resistor having a first terminal and a second terminal; N third PFETs, each including a source, a drain, and a gate; Including, When N is greater than 1, the third PFETs are coupled together as a second p-ladder, such that the gates of the third PFETs are coupled together, the drains and sources of the third PFETs are cascode-coupled between a first end and a second end of the second p-ladder, and the second end of the second p-ladder is coupled to the first terminal of the fifth resistor and the second input of the second differential amplifier.

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