Method and semiconductor device

Abstract

Method and semiconductor device In at least one embodiment, the method is for manufacturing a semiconductor device (1), A) Providing a semiconductor body (2) based on a group IV semiconductor material; B) doping a first region (21) in the semiconductor body (2), the first region (21) being of a first conductivity type, starting from the surface (20) of the semiconductor body (2); C) forming a recess (3) in the semiconductor body (2) by selective wet chemical etching of the first region (21).

Description

[Technical Field]

[0001] A method for manufacturing a semiconductor device is provided, as well as a corresponding semiconductor device. [Background technology]

[0002] EP 1 011 130 A1 relates to a method for manufacturing silicon-based acceleration sensors using electrochemical etching.

[0003] US Patent Application Publication No. 2022 / 0399442 discloses a power semiconductor device having a recess in a semiconductor body.

[0004] The document H. Mikami et al., "Analysis of Photoelectrochemical Processes in α-SiC Substrates with Atomically Flat Surfaces" in Japanese Journal of Applied Physics, Volume 44, 8329 (2005), DOF 10.1143 / JJAP.44.8329, relates to etching of SiC.

[0005] The literature, K. Kawahara et al., “Deep levels induced by reactive ion etching in n- and p-type 4H-SiC,” in Journal of Applied Physics, Volume 108, 023706 (2010), DOI: 10.1063 / 1.3460636, relates to energy levels in SiC.

[0006] The document T. Nakamura et al., “High performance SiC trench devices with ultra-low ron”, 2011 International Electron Devices Meeting, December 2011, DOI: 10.1109 / IEDM.2011.6131619, relates to MOSFETs based on SiC.

[0007] The literature M. Rashid et al., “Optical properties of mesoporous 4H-SiC prepared by anodic electrochemical etching”, Journal of Applied Physics, Volume 120, 194303 (2016), DOI: 10.1063 / 1.4968172 and the literature M.D.Pirnaci et al., “Systematic Characterization of Plasma-Etched Trenches on 4H-SiC Wafers” in ACS Omega, Volume 6, 20667 (2021), DOI: 10.1021 / acsomega.1c02905, relate to the properties of SiC related to SiC handling.

[0008] The literature H.K. Sung et al., “Vertical and bevel-structured SiC etching techniques incorporating different gas mixture plasmas for various microelectronic applications”, Scientific Reports, Volume 7, 3915 (2017), DOI: 10.1038 / s41598-017-04389-y and Y.Ke et al., “Surface polishing by electrochemical etching of p-type 4H SiC”, Journal of Applied Physics, Volume 106, 064901 (2009), DOI: 10.1063 / 1.3212541 discusses the roughness resulting from etching of SiC. Summary of the Invention [Problem to be solved by the invention]

[0009] The object to be achieved is to provide a method for efficiently manufacturing semiconductor devices. [Means for solving the problem]

[0010] This object is achieved, inter alia, by a method and a semiconductor device as defined in the independent claims. Exemplary further developments form the subject matter of the dependent claims.

[0011] For example, in this method, the trenches of a SiC trench MOSFET are created by ion implantation and selective wet etching of the areas affected by the ion implantation.

[0012] In at least one embodiment, the method is for manufacturing a semiconductor device and comprises the following steps: A) providing a semiconductor body based on a group IV semiconductor material; B) doping one or more first regions in the semiconductor body, at least one first region being of a first conductivity type, e.g. starting from the surface of the semiconductor body; C) forming a recess in the semiconductor body by selective wet chemical etching of at least one first region; for example, in the order stated. Optionally, the completed semiconductor device is one of a metal-insulator-semiconductor field-effect transistor (MISFET), a metal-oxide-semiconductor field-effect transistor (MOSFET), an insulated-gate bipolar transistor (IGBT), or a reverse-conducting insulated-gate bipolar transistor (RC-IGBT). Further optionally, the method includes: D) doping a second region of the second conductivity type in the semiconductor body directly on the surface-remote side of the first region, wherein the etching in step C) automatically stops in the second region such that after step C) the second region is directly on the bottom of the recess remote from the surface (20) of the semiconductor body, the bottom surface having a root mean square (RMS) roughness of 15 nm or less, and the second region is configured as a shielding region in the finished semiconductor device.

[0013] Inductively coupled plasma reactive ion etching (ICP-RIE) is a selective dry-etching manufacturing process used to form trenches, mesas, and other features. It relies on mask deposition and has good accuracy and reproducibility, making it suitable for processing SiC devices. For example, due to the chemical inertness of SiC, different types of plasmas can be used, typically chlorides or fluorides, but mixtures with oxygen and inert gases can also be used. Etch rates range from 500 nm / min to 800 nm / min, depending on the plasma and the power used. One undesirable consequence of using ICP-RIE can be unevenness at the bottom of SiC trenches, due to reflection of plasma ions from the sidewalls. These unevenness can appear on the sidewalls themselves, resulting in microtrenches. These undesirable results can be avoided by additional processing steps, such as a sidewall passivation layer, or by adding an oxide to Cl-based plasmas. Another undesirable consequence is the possible formation of carbon vacancies in the etched epilayer, i.e., the epitaxially grown semiconductor layer. Furthermore, RIE can produce two electrically active levels, labeled IN6 and EN, at 1.0 eV and 1.6 eV below the conduction band edge, respectively (compare K. Kawahara et al., cited above).

[0014] Therefore, to improve semiconductor devices, the method described herein fabricates SiC trench devices without the use of RIE.

[0015] Instead of RIE, the method described herein uses ion implantation and electrochemical etching (ECE) to form trenches. ECE is a selective wet chemical etching method. For example, ECE involves immersing the area to be etched in an HF-based solution. A SiC wafer can be used as the anode in the solution. The current density can be varied to control the etching rate. Etching occurs only in areas of the correct conductivity type, i.e., conductive areas with a specific electrical resistivity of, for example, about 0.03 Ω cm, depending on the applied potential, while areas with a higher specific electrical resistivity are left untouched. By reversing the polarity of the applied potential, etching of materials with the opposite conductivity type is also possible. Etching rates can be as high as 200 μm / h.

[0016] In the method described herein, unlike the use of RIE, an etch end-point detection system is not required because ECE stops when a region of different doping is reached. Furthermore, unlike RIE, ECE of the trench does not detect carbon vacancies V. C Furthermore, ECE results in a smaller surface roughness after etching; for example, Cl-based RIE results in a surface roughness of about 60 nm to 70 nm, while ECE can result in a surface roughness, root mean square (RMS), of about 2 nm to 7 nm.

[0017] Trenches of any depth and shape can be defined by implantation and then formed more quickly by ECE than by RIE.

[0018] For example, plasma immersion ion implantation, or PIII, after ECE of the trench can form a field-limiting layer, and V that may have been formed by ion implantation. C Remove.

[0019] In the methods described herein, V-shaped trenches and the like can be produced by tilted ion implantation at an angle of, for example, 54.7° with respect to the 0-33-8 plane.

[0020] Reverse engineering of the final product is possible by x-ray photoelectron spectroscopy, or XPS. In the energy range of 280 eV to 290 eV, there are clearly distinguishable features for 4H-SiC etched by ECE compared to 4H-SiC etched by RIE (see the references M. Rashid et al. and MDPirnaci et al. cited above).

[0021] Reverse engineering of the final product is also possible by deep level transient spectroscopy, or DLTS. After implantation in n-type SiC, the presence of ON1, ON2, and IN2 levels indicates that an ECE-based method was used (see T. Nakamura et al., cited above). After implantation in p-type SiC, the presence of HK0, IP5, IP7, and IP8 levels indicates that an ECE-based method was used (see also T. Nakamura et al., cited above).

[0022] According to at least one embodiment, the Group IV semiconductor material, also referred to as Group 14 semiconductor material, is C, Si, Ge, such as diamond, or any mixture thereof, such as SiC. In particular, the semiconductor material is SiC, such as stoichiometric SiC.

[0023] According to at least one embodiment, the first regions are defined by doping. That is, all regions starting from the surface and doped in step B) can be referred to as first regions. That is, the doping in step B) defines the first regions. However, although multiple first regions are defined by the doping in step B), one or some of these first regions may not be to be etched, and such first regions may be covered with another material before step C). In the following, such regions that are covered with another material and are not configured for etching will not be referred to as first regions, since they do not start from the surface as meant in this context.

[0024] According to at least one embodiment, the recess in the semiconductor body is formed exclusively by wet-chemical etching of the first region, so that all material removal resulting in the recess comes from wet-chemical etching.

[0025] According to at least one embodiment, the wet chemical etch is selective, meaning that the etching rate of the first region during wet chemical etching is at least 10 times, at least 100 times, at least 10 times, or at least 10 times, greater than the etching rate of other regions of the semiconductor body exposed to the etchant used in the wet chemical etch. 3 times at least 10 4 times at least 10 5 Thus, "selectively" may mean that substantially only the at least one first region is etched without significant material removal in other regions of the semiconductor body.

[0026] According to at least one embodiment, the at least one first region exposed to the etching solution is completely removed by etching, so that nothing of the respective at least one first region may remain in the completed semiconductor device.

[0027] According to at least one embodiment, the etching solution is an acid or a solution containing at least one acid. For example, the etching solution is an HF-based solution. For example, the HF-based solution is a 5% to 10% aqueous HF solution mixed with ethanol in a 1:1 or 2:1 ratio. Alternatively, HF (50%): acetic acid: HO can be used in a ratio of, for example, 4:6:2 or 1:1:5.

[0028] According to at least one embodiment, in the ECE, the applied voltage is such that the current density is at least 10 mA / cm 2 and / or up to 80mA / cm 2 is selected to be maintained at

[0029] According to at least one embodiment, method step B) comprises: B1) applying an electric potential to the semiconductor body such that at least a portion of the semiconductor body acts as an etching electrode; B2) removing the first region by electrochemical etching as wet chemical etching, i.e. ECE; Includes:

[0030] Thus, the ECE is used to selectively remove at least one first region.

[0031] According to at least one embodiment, if the first conductivity type is p-conductivity, the etching electrode is a cathode, or if the first conductivity type is n-conductivity, the etching electrode is an anode, i.e., if the first region is p-conductivity, a negative voltage is applied to the semiconductor body, and correspondingly, if the first region is n-conductivity, a positive voltage is applied to the semiconductor body.

[0032] According to at least one embodiment, the etching electrode is formed by at least a portion of a semiconductor substrate of the semiconductor body, for example, said portion being located away from a surface of the semiconductor body, for example, the surface being a top surface of the semiconductor body opposite the substrate, the top surface being oriented perpendicular to the growth direction of an epilayer of the semiconductor body.

[0033] According to at least one embodiment, the first region has a first doping concentration that is at least 10 times or at least 10 times greater than a second doping concentration of a material of the semiconductor body adjacent the first region and also of the first conductivity type. 2 100 times higher. Thus, the first region is embedded in a semiconductor material that is also of the first conductivity type but with a lower doping concentration. Alternatively, or in addition, adjacent to the first region, the semiconductor body is of a second conductivity type different from the first conductivity type. For example, in the latter case, the first region may be n-doped and embedded in a p-doped region, or vice versa. A mixture of both of the above cases may also exist.

[0034] According to at least one embodiment, the first region has a resistivity of at most 10 Ωcm, or at most 1 Ωcm, or at most 0.1 Ωcm; the same may be true for the etching electrode. Therefore, the first region can be considered conductive, and the same is true for the etching electrode. When the semiconductor material of the semiconductor body adjacent to the first region is of the same first conductivity type, the resistivity of the adjacent semiconductor material is, for example, greater than 10 Ωcm, or at least 0.1 kΩcm, or at least 1 kΩcm. The aforementioned values ​​may apply at room temperature, i.e., 293 K.

[0035] According to at least one embodiment, the etching electrode and the at least one first region are separated from each other, i.e., the etching electrode and the at least one first region are not in contact. For example, a semiconducting material may be present between the etching electrode and the at least one first region, i.e., a material having a resistivity of more than 10 Ωcm, or at least 0.1 kΩcm, or at least 1 kΩcm. The distance between the etching electrode and the at least one first region may be at least 1 μm, or at least 5 μm, or at least 40 μm.

[0036] According to at least one embodiment, when viewed in a cross section perpendicular to the top surface of the semiconductor body, the recess narrows monotonically or strictly monotonically in a direction away from the top surface. "Monotonically" means that the thickness t at a position x is the same as or greater than the thickness t' at a position x+d further away from the top surface: i.e., t(x)≧t'(x+d), where d is a distance greater than zero (d>0). Thus, when "strictly monotonic," t(x)>t'(x+d) applies. This can apply to the actual sidewall of the recess, or to a virtual sidewall of the recess that is a straight line of best fit through the roughness of the actual sidewall, when viewed in a cross section perpendicular to the top surface and / or perpendicular to the main extension direction of the recess as determined in a top view of the top surface.

[0037] According to at least one embodiment, the recesses are formed without reactive ion etching, or RIE.

[0038] According to at least one embodiment, in step B) the first region is doped by ion implantation. Alternatively or additionally, in step B) the doping is performed by epitaxial growth.

[0039] According to at least one embodiment, the recess is a trench. For example, the aspect ratio of the maximum depth of the trench to the maximum width of the trench is at least 0.8, or at least 1, or at least 1.0, or at least 2. Alternatively, or additionally, the aspect ratio is at most 20, or at most 10, or at most 5.

[0040] According to at least one embodiment, the method comprises: D) doping exclusively or at least at least one second region of the second conductivity type in the semiconductor body located directly on the surface-remote side of the recess or on the surface-remote side of the first region; The at least one second region may be separate from the first region or recess, or may be located directly within the first region or recess. Thus, the second region may be formed by doping before etching the recess, or may be formed by doping after etching the recess.

[0041] According to at least one embodiment, the second region is configured as a shielding region, i.e., the second region may be heavily doped and electrically conductive (see the definition of "electrically conductive" above in the context of the first region).

[0042] According to at least one embodiment, the maximum depth of the recesses is at least 1 μm, or at least 5 μm, or at least 15 μm. Alternatively, or in addition, the maximum depth is at most 0.1 mm, or at most 50 μm, or at most 30 μm.

[0043] According to at least one embodiment, the maximum doping concentration of the first region is at least 10 18 cm -3 or at least 5×10 18 cm -3 or at least 1×10 19 cm -3 Alternatively or additionally, the doping concentration is at most 10 21 cm -3 or up to 5×10 20 cm -3 is.

[0044] According to at least one embodiment, the recess is formed in epitaxially grown layers of the semiconductor body. When grown, all of the layers may be of the first conductivity type. For example, when grown, the layers may be up to 10 16 cm -3 or up to 5×10 15 cm -3 Alternatively or additionally, the doping concentration is at least 5×10 14 cm -3or at least 1×10 15 cm -3 is.

[0045] According to at least one embodiment, after the recesses are formed, the method further comprises: E1) applying an electrically insulating film to the walls of the recess; and E2) Providing a gate electrode in the recess Further includes:

[0046] Thus, the completed semiconductor device may include a gate electrode housed in a trench or recess.

[0047] Further provided is a semiconductor device, which can be produced by the method as set forth in relation to at least one of the above-described embodiments. Accordingly, features of the semiconductor device are also disclosed for the method, and vice versa.

[0048] In at least one embodiment, the semiconductor device comprises a semiconductor body based on a Group IV semiconductor material such as Si or SiC, and the semiconductor device is one of a metal-insulator-semiconductor field effect transistor (MISFET), a metal-oxide-semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), or a reverse-conducting insulated gate bipolar transistor (RC-IGBT). At least one recess is formed in the semiconductor body, and the root-mean-square (RMS) roughness of a bottom surface of the recess is 15 nm or less, or 10 nm or less, or 7 nm or less, and / or 1 nm or more, or 2 nm or more. A gate electrode is located in the at least one recess.

[0049] According to at least one embodiment, the semiconductor device is one of a metal-insulator-semiconductor field effect transistor, or MISFET, a metal-oxide-semiconductor field effect transistor, or MOSFET, an insulated gate bipolar transistor, or IGBT, or a reverse conducting insulated gate bipolar transistor, or RC-IGBT.

[0050] The methods and semiconductor devices described herein are described in further detail below by way of exemplary embodiments with reference to the drawings. Elements that are the same in the individual figures are designated by the same reference numerals. However, the relationships between the elements are not shown to scale, and rather individual elements may be exaggerated to facilitate understanding.

[0051] In the drawings. [Brief explanation of the drawings]

[0052] [Figure 1] FIG. 1 is a schematic block diagram of an exemplary embodiment of a method for manufacturing a semiconductor device as described herein. [Figure 2] 1A-1D are schematic cross-sectional views of method steps of an exemplary embodiment of a method for manufacturing a semiconductor device as described herein. [Figure 3] 1A-1D are schematic cross-sectional views of method steps of an exemplary embodiment of a method for manufacturing a semiconductor device as described herein. [Figure 4] 1A-1D are schematic cross-sectional views of method steps of an exemplary embodiment of a method for manufacturing a semiconductor device as described herein. [Figure 5] 1A-1D are schematic cross-sectional views of method steps of an exemplary embodiment of a method for manufacturing a semiconductor device as described herein. [Figure 6] 1A-1D are schematic cross-sectional views of method steps of an exemplary embodiment of a method for manufacturing a semiconductor device as described herein. [Figure 7] 2 is a schematic cross-sectional view of the bottom of a trench of an exemplary embodiment of a semiconductor device described herein. [Figure 8] 10A-10C are schematic cross-sectional views of method steps of an exemplary embodiment of a further method for manufacturing a semiconductor device as described herein. [Figure 9] 10A-10C are schematic cross-sectional views of method steps of an exemplary embodiment of a further method for manufacturing a semiconductor device as described herein. [Figure 10] 10A-10C are schematic cross-sectional views of method steps of an exemplary embodiment of a further method for manufacturing a semiconductor device as described herein. [Figure 11] 10A-10C are schematic cross-sectional views of method steps of an exemplary embodiment of a further method for manufacturing a semiconductor device as described herein. [Figure 12] 10A-10C are schematic cross-sectional views of method steps of an exemplary embodiment of a further method for manufacturing a semiconductor device as described herein. [Figure 13] 10A-10C are schematic cross-sectional views of method steps of an exemplary embodiment of a further method for manufacturing a semiconductor device as described herein. [Figure 14] 10A-10C are schematic cross-sectional views of method steps of an exemplary embodiment of a further method for manufacturing a semiconductor device as described herein. [Figure 15] 10A-10C are schematic cross-sectional views of method steps of an exemplary embodiment of a further method for manufacturing a semiconductor device as described herein. [Figure 16] 10A-10C are schematic cross-sectional views of method steps of an exemplary embodiment of a further method for manufacturing a semiconductor device as described herein. [Figure 17] 10A-10C are schematic cross-sectional views of method steps of an exemplary embodiment of a further method for manufacturing a semiconductor device as described herein. [Figure 18] 10A-10C are schematic cross-sectional views of method steps of an exemplary embodiment of a further method for manufacturing a semiconductor device as described herein. [Figure 19] 10A-10C are schematic cross-sectional views of method steps of an exemplary embodiment of a further method for manufacturing a semiconductor device as described herein. [Figure 20]10A-10C are schematic cross-sectional views of method steps of an exemplary embodiment of a further method for manufacturing a semiconductor device as described herein. [Figure 21] 1 is a schematic cross-sectional view of an exemplary embodiment of a semiconductor device described herein. [Figure 22] 2A-2C are schematic top views of various recesses for exemplary embodiments of semiconductor devices described herein. [Figure 23] 2A-2C are schematic cross-sectional views of various recesses for exemplary embodiments of semiconductor devices described herein. DETAILED DESCRIPTION OF THE INVENTION

[0053] In Figure 1 a block diagram of a method for manufacturing a semiconductor device 1 is shown. In a first method step S1 a semiconductor body 2 is provided (see also Figure 2 below). The semiconductor body 2 is based on a group IV semiconductor material such as SiC or Si.

[0054] In a next method step S2, a first region 21 is defined by doping a portion of the semiconductor body 2 (see also FIG. 3 below). The first region 21 is of a first conductivity type and starts from the surface 20 of the semiconductor body 2.

[0055] Next, in method step S3, recesses 3 are formed in the semiconductor body 2 by selective wet-chemical etching of the first regions 21 (see also FIG. 4 below). Optionally, method step S3 may comprise or consist of two steps S31 and S32. In step S31, an electric potential is applied to the semiconductor body 2 so that the semiconductor body 2 or a part of the semiconductor body 2 acts as an etching electrode 41, as shown in FIG. 4 below. In step S32, the first regions 21 are removed by electrochemical etching, i.e. ECE. Steps S31 and S32 may be performed simultaneously. ECE may be a continuous etch or a pulse etch.

[0056] As a further option, there is a subsequent method step S5 in which the gate electrode 44 is produced (compare FIG. 11 below). Step S5 may comprise steps S51 and S52. In step S51, an electrically insulating film 5 is applied to the walls and bottom of the recess 3. Thereafter, in step S52, a gate electrode material, such as poly-Si, is applied to the recess 3 to form the gate electrode.

[0057] As a further option, in step S4, second regions 22 of the second conductivity type are formed in the semiconductor body 2, for example by direct doping of the recesses 3 or the sides of the first regions 21 remote from the surface 20 (compare, for example, Figures 6 and 9 below). Step S4 can be performed, for example, between steps S2 and S3, or after step S3, such as between steps S3 and S5.

[0058] An example of a method is explained in more detail in Figures 2 to 6. In Figure 2, a semiconductor body 2 is provided. For example, the semiconductor body 2 comprises a semiconductor substrate 23, for example made of heavily n-doped SiC. On the semiconductor substrate 23, a layer 29 is formed by epitaxial growth. For example, the layer 29 is made of moderately n-doped SiC. The main surface of the layer 29 remote from the substrate 23 is the top surface 20, which corresponds to the surface 20 mentioned in Figure 1.

[0059] 3, a first region 21 is then applied in the epitaxially grown layer 29. In cross section, the first region 21 may be rectangular in shape. Perpendicular to the plane of the drawing of FIG. 3, the first region 21 may extend linearly. The first region 21 terminates away from the substrate 23.

[0060] For example, first region 21 is formed by ion implantation with a box profile. The term "box profile" is sometimes referred to as a multi-energy implant profile. Thus, the doping concentration within first region 21 may be approximately constant, for example, within a range of 0.5 to 2 times the average doping concentration, or within a range of 0.75 to 1.3 times the average doping concentration. Therefore, first region 21 is conductive, but the remainder of epilayer 29, which has the same conductivity type as first region 21 and has an exposed surface, is merely semiconducting, so that only conductive material of the correct conductivity type is etched by ECE with high selectivity.

[0061] The performance of selective etching is shown in Figure 4. The first region 21 is therefore placed in and exposed to an etching solution 62 in an etching tube 61. An external etching electrode 63 is applied to the substrate 23, which serves as the etching electrode 41 for the semiconductor body 2, and a voltage is applied between the etching solution 62 and the etching electrode 41. In the case of a first region of n-type conductivity, the etching electrode 41 is an anode, as shown schematically in Figure 4.

[0062] 4, the first regions 21 are shown as only partially removed as the etching is still in progress, but after the etching is completed, the first regions 21 are completely removed (see FIG. 5). The shape of the resulting recesses 3 is therefore determined by the shape of the regions doped in the step of FIG.

[0063] According to Fig. 6, after the recess 3 has been formed, a second region 22 of the second conductivity type is optionally created, for example by ion implantation through the recess 3. The recess 3 can be referred to as a trench extending perpendicular to the plane of the drawing of Fig. 6.

[0064] So, for example, 1 x 10 15 cm -3 ~1×10 16 cm -3Starting with a 10 μm-100 μm thick n-type 4H—SiC epilayer 29 having a doping concentration of about 1×10 for the first region, implantation with N, P, B, and / or Al is performed. 18 cm -3 ~1×10 20 cm -3 The implantation energy for forming the first region 21 is selected to be between 100 keV and 100 MeV, for example, to form a trench having a depth of 0.2 μm to 90 μm. After the implantation, activation can be performed at, for example, about 1600° C. or about 1700° C. for 30 minutes. n + or p + Once the first region 21 is formed, ECE is performed to form the trench 3 by ECE.

[0065] The field limiting layer, i.e. the second region 22, can then be formed, for example by ion beam techniques: thus, starting from the n-type epilayer 29, + or n + Implantation and activation of n is performed to create the first region 21. Referring to FIGS. 2 to 6, for example, + implantation is used for the first region 21. The field limiting layer 22 is formed so that the first region 21 is n + If it is of type p + After activation of the dopants, n + The first region 21 of the silicon nitride film is etched by ECE, thereby forming p + This results in a trench 3 having a region 22. The second region 22 can therefore be formed after the ECE, as shown in Figure 6, or it can be formed before the ECE.

[0066] Optionally, after ECE of the trenches in n-type epilayer 29, plasma immersion ion implantation of C is performed, e.g., at an energy of 5 keV to 10 keV and a voltage of 10 15 cm -2 ~10 16 cm-2 This can be performed at room temperature using a dose between 0.1 and 1.0, which implants carbon atoms into epilayer 29 and removes all carbon vacancies in this layer 29.

[0067] 2 to 6, for the sake of simplicity, only one trench 3 is shown. In contrast to this, of course, several trenches 3 can be present and several semiconductor devices 1 can be manufactured simultaneously. Since etching automatically terminates once the assigned first region 21 has been completely removed in each trench 3, trenches 3 of different shapes, for example different depths, can be produced simultaneously. The same applies to all other examples.

[0068] Otherwise, what is the same as for FIG. 1 is also applicable to FIGS. 2-6, and vice versa.

[0069] It should be noted that Cl-based RIE, used for etching SiC, results in surface roughness ranging between 60 nm and 70 nm, while ECE can achieve surface roughness of only 2 nm to 7 nm (see, for example, H.K. Sung et al. and Y.Ke et al., cited above). Thus, ECE provides much better surface roughness and therefore improved electrical behavior. This is shown in Figure 7, where the roughness 7 of the bottom surface 71 of the recess 3 has an RMS value of less than 10 nm.

[0070] Otherwise, the same as with respect to Figures 1-6 is applicable to Figure 7, and vice versa.

[0071] 8 to 12, another example of the method is illustrated. In FIG. 8, a semiconductor body 2 is provided, similar to FIG. 2. Then, both a first region 21 and a second region 22 are formed by ion implantation, with the first region 21 being n + The second region 22 is p + type (see Figure 9).

[0072] According to Figure 10, n +The first region 21 of the type is completely removed. The ECE is p + It stops automatically in the second region 22 of the mold, n - The mold epi layer 29 is not etched because it is not sufficiently conductive.

[0073] 11, an electrically insulating film 5 is then applied to the walls of the trench 3 and also to the bottom surface 71. Subsequently, the gate electrode 44 is applied to the remainder of the trench 3.

[0074] Finally, with reference to FIG. 12, the semiconductor body 2 is provided with p-type well regions 25, p + Type plug region 27, and n + This is completed by forming the source region 26.

[0075] Subsequently, although not shown, further electrodes, passivation and protective layers, bond pads, etc. may be formed.

[0076] Therefore, the above method can be used to fabricate a SiC trench MOSFET. For example, first, + A SiC epitaxial layer 29 is provided grown on a mold substrate 29. High dose P and Al implants are performed, in any order, at temperatures between 200°C and 600°C, for example, followed by activation above 1600°C to form first and second regions 21, 22. + type and p + Once the first and second regions 21, 22 of the type are formed, the ECE is + This is done using polarity to remove only the implanted region of type p. + The p-type region is used as the field limiting layer 22. + Mold injection, n + It is also possible to carry out this after the ECE of the first region 21 of the mold. + Following the formation of the second region of the mold, plasma ion implantation of C, e.g., PIII, is performed at 5 keV to 30 keV, 10 12 cm -2~10 16 cm -2 This can be done with a dose of 0.15g / cm 2 . In this way, any carbon vacancies that may have formed previously are removed. Afterwards, the trench is filled with SiO2 and then poly-Si for the gate electrode 44. Finally, regions 25, 26, and 27 are formed.

[0077] Otherwise, the same as with respect to Figures 1-7 is also applicable to Figures 8-12, and vice versa.

[0078] It is also possible to fabricate V-trench MOSFETs by the method described herein using implantation followed by ECE (compare Figures 13 and 14). Starting with an epilayer 29 of 4H-SiC, p + Type plug area 27, p + a p-type second region 22, a p-type well region 25, and an n + A first region 21 of the mold is formed by implantation. + The first region 21 of the mold is formed by oblique implantation of N or P at an angle of, for example, 54.7° along the 0-33-8 plane of the SiC (see FIG. 13).

[0079] Then, the ECE calculates n + The first region 21 of the mold is removed by etching, and PIII of C can be performed. Finally, n + The source regions 26 of the type are formed by implantation and activation. The trenches 3 can then be coated with SiO2 as in Figure 11 and the gate electrode can be applied.

[0080] In other respects, the same content as in FIGS. 1 to 12 is also applicable to FIGS. 13 and 14, and vice versa.

[0081] Further examples of this method are shown in Figures 15 to 20. Another possibility is therefore the use of PIII of Al or B to form the channel without using ion implantation. +type and p + A type implant is performed in the epi layer 29 (see FIG. 15). The region 21a adjacent to the top surface 20 is p + The deeper region 21b is of the n type. + It is a type.

[0082] Next, p adjacent to the upper surface 20 + ECE is performed to remove the mold region 21a (see FIG. 16). When this is done, as shown in FIG. 17, PIII of Al is generated at 5 keV to 30 keV and 10 12 cm -2 ~10 14 cm -2 (see arrows pointing to the wall of trench 3). + To remove region 21b of the mold, ECE is performed (see Figure 18).

[0083] Then, a second region 22 for electric field confinement is formed, located at the bottom surface 71 of the trench 3 (see FIG. 19). Furthermore, the trench 3 is filled with oxide and poly-Si for the electrical insulating film 5 and the gate electrode 44, respectively.

[0084] Finally, as shown in Figure 20, p + a p-type plug region 27, a p-type well region 25, and an n + A source region 26 of the same type is formed.

[0085] Otherwise, the same as with respect to Figures 1-14 is also applicable to Figures 15-20, and vice versa.

[0086] 21 shows a schematic representation of the completed semiconductor device 1, with only one trench 3. As is possible in all other examples, regions 25, 26, 27, 28 may be located on either side of trench 3.

[0087] 20, the semiconductor device 1 is an insulated gate bipolar transistor, or IGBT, or a metal-insulator-semiconductor field effect transistor, or MISFET, or a metal-oxide-semiconductor field effect transistor, or MOSFET. In the case of an IGBT, the region 25 is a well region. In the well region 25, a first electrode 42, for example an emitter electrode, is connected to a first electrode 42, for example a p + There is a plug region 27. In addition, the well region 25 has an n + Therefore, the region 24 is n - The doping concentration of the drift layer 24 is, for example, 2×10 14 cm -3 is.

[0088] Optionally, there is a further layer 284 of semiconductor body 2 below drift region 24, which may be a buffer region. For example, buffer region 284 may have a thickness of about 1×10 18 cm -3 The buffer region 284 is doped n-type with a maximum doping concentration of 10 μm or more. The thickness of the buffer region 284 may be, for example, 2 μm or more and 10 μm or less.

[0089] A further region 28 of the semiconductor body 2 is located on the side of the drift region 24 remote from the top surface 20 or on the side of the buffer region 284 remote from the top surface 20. The further region 28 is a collector region of the same conductivity type as the plug region 27. The collector region 28 has a conductivity of, for example, about 1×10 19 cm -3 The second electrode 43 located in the collector region 28 is the collector electrode.

[0090] Similarly, the semiconductor device 1 may be a MISFET or a MOSFET. In this case, the region 284 may be omitted and the region 28 may be, for example, 1×10 18 cm -3 or more than 5×10 18 cm -3 or more than 1×10 19 cm -3or greater and / or 5x10 20 cm -3 or less or 2×10 20 cm -3 or less or 1×10 20 cm -3 1. In this case, region 26 is the source region, and first and second electrodes 42, 43 are the source and drain electrodes, respectively.

[0091] In other respects, the same content as in Figures 1 to 20 is also applicable to Figure 21, and vice versa.

[0092] FIG. 22 shows that various geometric shapes of the recess 3 can be realized in a top view by doping the first region 21. For example, in a top view, the recess 3 can be in the shape of a square, rectangle, triangle, trapezoid, pentagon, hexagon, octagon, or polygon, or even shaped as a cross. While FIG. 22 shows equilateral triangle, regular pentagon, regular hexagon, regular octagon, and regular polygon shapes, irregular shapes with different angles at the corners can also be used. For example, any combination of the shapes shown in FIG. 22 can be realized.

[0093] Thus, comparing Figure 23, depending on the doping of the first region 21 and the subsequent ECE, the resulting recesses can have a variety of cross-sectional shapes. Again, similar to Figure 22, any combination of shapes is possible in the same semiconductor device 1.

[0094] For example, in cross section, the recess may be a symmetrical or asymmetrical trapezoidal shape widening or narrowing toward the top surface 20, a triangular shape, a square shape, a rectangular shape, or even a pentagonal shape with its apex pointing away from the top surface. Furthermore, sharp and rounded corners are possible. Furthermore, a U-shaped trench 3 having a curved bottom surface 71 is also possible.

[0095] In other respects, the same content as in Figures 1 to 21 is also applicable to Figures 22 and 23, and vice versa.

[0096] Components shown in the figures illustratively directly overlap one another in the designated order, unless otherwise indicated. Components that are not touching in the figures are illustratively spaced apart from one another. Where lines are drawn parallel to one another, corresponding surfaces may be oriented parallel to one another. Similarly, unless otherwise indicated, the positions of the drawn components relative to one another are accurately reproduced in the figures.

[0097] The invention described herein is not limited by the description based on the embodiments, but rather the invention encompasses any novel feature and any combination of features, including in particular any combination of features in the claims, even if that feature or combination itself is not explicitly set forth in the claims or in the exemplary embodiments.

[0098] This patent application claims priority from European Patent Application No. 23164334.7, the disclosure of which is incorporated herein by reference. [Explanation of symbols]

[0099] Reference symbol enumeration 1. Semiconductor devices 2. Semiconductor body 20 Surface (Top surface) 21 First region (etching defined region) 22 Second Area (Shielding Area) 23 Semiconductor substrate 24 Drift Region 25 well area 26 Source region / emitter region 27 Plug Area 28 Drain region / Collector region 284 buffer space 29 Epitaxial growth layer 3. Trench 41 Etching electrode 42 First electrode (source electrode, emitter electrode) 43 Second electrode (drain electrode, collector electrode) 44 gate electrode 5 Electrical insulating film 61 Etching tube 62 Etching solution 62 External electrode for etching 7 Roughness 71 Bottom of recess S Method Step

Claims

1. 1. A method for fabricating a semiconductor device (1) that is one of a metal-insulator-semiconductor field effect transistor (MISFET), a metal-oxide-semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), or a reverse conducting insulated gate bipolar transistor (RC-IGBT), comprising: A) Providing a semiconductor body (2) based on a group IV semiconductor material; B) doping a first region (21) in the semiconductor body (2), the first region (21) being of a first conductivity type, starting from the surface (20) of the semiconductor body (2); C) forming a recess (3) in said semiconductor body (2) by selective wet chemical etching of said first region (21); A method comprising:

2. D) doping a second region (22) of a second conductivity type in the semiconductor body (2) located directly on the side of the first region (21) remote from the surface (20). further comprising the etching in step C) automatically stops at the second region (22) so that after step C) the second region (22) is located directly on a bottom surface (71) of the recess (3) remote from the surface (20) of the semiconductor body (2), the bottom surface (31) having a root-mean-square (RMS) roughness of 15 nm or less; 10. The method of claim 9, wherein the second region (22) is configured as a shielding region in the finished semiconductor device (1).

3. Process B) B1) applying an electric potential to the semiconductor body (2) so that the semiconductor body (2) acts as an etching electrode (41); B2) removing said first region (21) by electrochemical etching (ECE); Including, If the first conductivity type is p-conductivity, the etching electrode (41) is a cathode, or if the first conductivity type is n-conductivity, the etching electrode (41) is an anode; 10. The method of any one of the preceding claims, wherein the group IV semiconductor material is SiC.

4. 10. The method according to the preceding claim, wherein the etching electrode (41) is formed by a part of the semiconductor substrate (23) of the semiconductor body (2) located remote from the surface (20) of the semiconductor body (2).

5. The following, i.e. the first region (21) has a first doping concentration that is at least 10 times greater than a second doping concentration of a material of the semiconductor body (2) adjacent to the first region (21) and also of the first conductivity type; ２ times higher, or Adjacent to the first region (21), the semiconductor body (2) is of a second conductivity type different from the first conductivity type; 10. The method of any one of the preceding claims, wherein one or both of the following apply:

6. 10. The method according to any one of the preceding claims, wherein, viewed in a cross section perpendicular to the top surface (20) of the semiconductor body (2), the recess (3) narrows monotonically or strictly monotonically in a direction moving away from the top surface (20).

7. 10. A method according to any one of the preceding claims, wherein the recess (3) is formed without reactive ion etching (RIE).

8. 10. A method according to any one of the preceding claims, wherein in step B) said first region (21) is doped by at least one of ion implantation and epitaxial growth.

9. The recess (3) is a trench, 10. The method of claim 1, wherein an aspect ratio of a maximum depth of the trench to a maximum width of the trench is 1 to 10, inclusive.

10. The maximum depth of the recess (3) is 5 μm or more and 50 μm or less, The maximum doping concentration of the first region (21) is 10 １８ cm －３ 10 above ２１ cm －３ 10. The method of any one of the preceding claims, wherein:

11. The recess (3) is of the first conductivity type and has a doping concentration of 10 １６ cm －３ 10. The method according to any one of the preceding claims, wherein in an epitaxially grown layer (29) of the semiconductor body (2) there is formed:

12. After the recess (3) is formed, E1) applying an electrical insulating film (5) to the walls of said recess (3); E2) Providing a gate electrode (44) in the recess (3).

10. The method of any one of the preceding claims, further comprising:

13. 1. A semiconductor device (1) comprising a semiconductor body (2) based on a Group IV semiconductor material, the semiconductor body being one of a metal-insulator-semiconductor field-effect transistor (MISFET), a metal-oxide-semiconductor field-effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), or a reverse-conducting insulated gate bipolar transistor (RC-IGBT), a recess (3) is formed in the semiconductor body (2), and the root mean square (RMS) roughness of the bottom surface (71) of the recess (3) is 15 nm or less; A semiconductor device (1), wherein a gate electrode (44) is located within said recess (3).

14. Produced by the method of any one of claims 1 to 12, 10. The semiconductor device (1) according to the preceding claim, wherein the group IV semiconductor material is SiC.

15. 10. The semiconductor device (1) according to claim 9, wherein a second region (22) of a second conductivity type different from the first conductivity type is present in the semiconductor body (2) directly on the side of the recess (3) remote from the surface (20) of the semiconductor body (2), the second region (22) being configured as a shielding region.

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