NOR memory cell with floating gate

Abstract

An electrically erasable programmable nonvolatile memory cell includes a semiconductor substrate having a bit line region, a surface region laterally spaced from the bit line region, and a trench region having a bottom and sidewall portions adjacent to the trench in the semiconductor substrate; a conductive control gate laterally offset from a sidewall of the trench by a first distance; a conductive word line laterally offset from a second portion of the control gate by a second distance greater than the first distance; and a floating gate insulated from the substrate and the word line, having a first end closest to the control gate and laterally separated from the control gate by a third distance greater than the first distance and less than the second distance.

Description

[Technical Field]

[0001] Related Applications This application is a continuation of U.S. Patent Application No. 18 / 429,938, filed February 1, 2024, and claims priority to U.S. Provisional Patent Application No. 63 / 626,450, filed January 29, 2024, and U.S. Provisional Patent Application No. 63 / 443,343, filed February 3, 2023.

[0002] The present invention relates generally to semiconductor memory devices, including, but not limited to, electrically programmable and erasable non-volatile memory cells, sometimes referred to as NOR memory cells, having floating gates. [Background technology]

[0003] During programming of a nonvolatile semiconductor memory cell array, e.g., a conventional stacked-gate memory cell, each memory cell having a floating gate and a control gate, to "inject" electrons onto the floating gate, accelerated electrons moving at least partially away from the floating gate in the depletion region must collide with impurities or lattice defects in the substrate to generate momentum toward the floating gate. Furthermore, only electrons with sufficient energy toward the floating gate to overcome the energy barrier at the silicon-oxide interface (i.e., the substrate-gate oxide interface) plus the potential change across the floating gate oxide will be injected onto the floating gate. As a result, the efficiency of the programming operation is highly dependent on the direction and energy of the programming electrons.

[0004] Electric fields within a memory cell can interfere with the direction of electron movement during programming operations. Such fields can pull electrons in a direction that is not optimal for injection onto the floating gate. The memory cell structure can be adjusted to overcome competing electric fields and maintain the optimal electron movement direction during programming operations. However, such adjustments can affect the threshold voltage of certain gates in ways that adversely affect other operations of the memory cell. For example, read current is sensitive to the voltage threshold of the control gate. Therefore, optimizing a memory cell for programming efficiency can make the memory cell less efficient during other operations, thereby resulting in design tradeoffs. Summary of the Invention

[0005] Therefore, there is a need to improve the programming efficiency of non-volatile memory cells in a manner that minimizes the impact on other operations. The present disclosure describes devices and methods configured to increase programming efficiency while maintaining a sufficiently high read current when the cell is erased. The memory cell structures described herein include multiple indium implants strategically placed throughout the substrate of the memory cell. These implants, combined with the specific architecture of the memory cell, advantageously resolve the trade-off between programming efficiency and threshold voltage, which affects read current.

[0006] According to some embodiments, an electrically erasable programmable nonvolatile memory cell, sometimes referred to as a NOR memory cell, includes: a semiconductor substrate having a bit line region, a surface region laterally spaced from the bit line region, and a trench region laterally spaced from the surface region, the trench region having a bottom and sidewalls adjacent the trench in the semiconductor substrate; a conductive control gate disposed within the trench, the control gate being insulated from the bottom and sidewalls of the trench region of the substrate and having a first portion laterally spaced a first distance from the sidewalls of the trench region, and a second portion disposed above the trench and extending away from the trench; a conductive word line insulated from the control gate and laterally offset from the second portion of the control gate by a second distance greater than the first distance; and a tantalum nitride floating gate insulated from the substrate and the word line, the first end substantially aligned with the sidewalls of the trench region of the substrate and a second end self-aligned with an edge of the word line furthest from the second portion of the control gate.

[0007] In some embodiments, the electrically erasable programmable non-volatile memory cell includes two or more of a first indium implant disposed in a region of the substrate below a bottom of the trench region, a second indium implant disposed in a region of the substrate adjacent a sidewall and surface region of the substrate, and a third indium implant disposed in a region of the substrate adjacent a bottom of a source or drain node of the memory cell. [Brief explanation of the drawings]

[0008] For a better understanding of the various embodiments described, please refer to the following detailed description in conjunction with the following drawings, in which like reference numerals refer to corresponding parts throughout the drawings, in which: [Figure 1] 1A-1C illustrate cross-sectional views of a pair of electrically erasable programmable non-volatile memory cells according to some embodiments. [Figure 2]FIG. 1 illustrates the effect of competing electric fields on electron flow during a programming operation, according to some embodiments. [Figure 3] 1A-1C illustrate indium implantation with post-implant annealing and redistribution in a substrate of a memory cell according to some embodiments. [Figure 4] 1A-1C illustrate indium implantation with post-implant annealing and redistribution in a substrate of a memory cell according to some embodiments. [Figure 5] 1A-1C illustrate indium implantation with post-implant annealing and redistribution in a substrate of a memory cell according to some embodiments. [Figure 6] 1A-1C illustrate halo implants in the substrate of a memory cell according to some embodiments. [Figure 7] 1A-1C illustrate halo implants in the substrate of a memory cell according to some embodiments. [Figure 8] 1A-1C illustrate alternative plan views of memory cell arrays according to some embodiments. [Figure 9] 1A-1C illustrate alternative plan views of memory cell arrays according to some embodiments. [Figure 10A] 1 illustrates a process for fabricating an array of electrically erasable programmable non-volatile memory cells according to some embodiments. [Figure 10B] 1 illustrates a process for fabricating an array of electrically erasable programmable non-volatile memory cells according to some embodiments. [Figure 10C] 1 illustrates a process for fabricating an array of electrically erasable programmable non-volatile memory cells according to some embodiments. [Figure 10D] 1 illustrates a process for fabricating an array of electrically erasable programmable non-volatile memory cells according to some embodiments. [Figure 10E] 1 illustrates a process for fabricating an array of electrically erasable programmable non-volatile memory cells according to some embodiments. [Figure 10F]1 illustrates a process for fabricating an array of electrically erasable programmable non-volatile memory cells according to some embodiments. [Figure 11A] 1 illustrates a process for fabricating an array of electrically erasable programmable non-volatile memory cells according to some embodiments. [Figure 11B] 1 illustrates a process for fabricating an array of electrically erasable programmable non-volatile memory cells according to some embodiments. [Figure 11C] 1 illustrates a process for fabricating an array of electrically erasable programmable non-volatile memory cells according to some embodiments. [Figure 11D] 1 illustrates a process for fabricating an array of electrically erasable programmable non-volatile memory cells according to some embodiments. [Figure 11E] 1 illustrates a process for fabricating an array of electrically erasable programmable non-volatile memory cells according to some embodiments. [Figure 11F] 1 illustrates a process for fabricating an array of electrically erasable programmable non-volatile memory cells according to some embodiments. [Figure 11G] 1 illustrates a process for fabricating an array of electrically erasable programmable non-volatile memory cells according to some embodiments. [Figure 11H] 1 illustrates a process for fabricating an array of electrically erasable programmable non-volatile memory cells according to some embodiments. [Figure 11I] 1 illustrates a process for fabricating an array of electrically erasable programmable non-volatile memory cells according to some embodiments. [Figure 11J] 1 illustrates a process for fabricating an array of electrically erasable programmable non-volatile memory cells according to some embodiments. [Figure 11K] 1 illustrates a process for fabricating an array of electrically erasable programmable non-volatile memory cells according to some embodiments. [Figure 11L]1 illustrates a process for fabricating an array of electrically erasable programmable non-volatile memory cells according to some embodiments. [Figure 11M] 1 illustrates a process for fabricating an array of electrically erasable programmable non-volatile memory cells according to some embodiments. [Figure 12A] 1A-1C illustrate block diagrams of a process for fabricating an array of electrically erasable programmable non-volatile memory cells, each having a polysilicon floating gate, and the resulting memory cell pairs, according to some embodiments. [Figure 12B] 1A-1C illustrate block diagrams of a process for fabricating an array of electrically erasable programmable non-volatile memory cells, each having a polysilicon floating gate, and the resulting memory cell pairs, according to some embodiments. [Figure 12C] 1A-1C illustrate block diagrams of a process for fabricating an array of electrically erasable programmable non-volatile memory cells, each having a polysilicon floating gate, and the resulting memory cell pairs, according to some embodiments. [Figure 12D] 1A-1C illustrate block diagrams of a process for fabricating an array of electrically erasable programmable non-volatile memory cells, each having a polysilicon floating gate, and the resulting memory cell pairs, according to some embodiments. [Figure 12E] 1A-1C illustrate block diagrams of a process for fabricating an array of electrically erasable programmable non-volatile memory cells, each having a polysilicon floating gate, and the resulting memory cell pairs, according to some embodiments. [Figure 12F] 1A-1C illustrate block diagrams of a process for fabricating an array of electrically erasable programmable non-volatile memory cells, each having a polysilicon floating gate, and the resulting memory cell pairs, according to some embodiments. [Figure 12G]1A-1C illustrate block diagrams of a process for fabricating an array of electrically erasable programmable non-volatile memory cells, each having a polysilicon floating gate, and the resulting memory cell pairs, according to some embodiments. [Figure 12H] 1A-1C illustrate block diagrams of a process for fabricating an array of electrically erasable programmable non-volatile memory cells, each having a polysilicon floating gate, and the resulting memory cell pairs, according to some embodiments. [Figure 12I] 1A-1C illustrate block diagrams of a process for fabricating an array of electrically erasable programmable non-volatile memory cells, each having a polysilicon floating gate, and the resulting memory cell pairs, according to some embodiments. [Figure 12J] 1A-1C illustrate block diagrams of a process for fabricating an array of electrically erasable programmable non-volatile memory cells, each having a polysilicon floating gate, and the resulting memory cell pairs, according to some embodiments. [Figure 12K] 1A-1C illustrate block diagrams of a process for fabricating an array of electrically erasable programmable non-volatile memory cells, each having a polysilicon floating gate, and the resulting memory cell pairs, according to some embodiments. [Figure 12L] 1A-1C illustrate block diagrams of a process for fabricating an array of electrically erasable programmable non-volatile memory cells, each having a polysilicon floating gate, and the resulting memory cell pairs, according to some embodiments. [Figure 12M] 1A-1C illustrate block diagrams of a process for fabricating an array of electrically erasable programmable non-volatile memory cells, each having a polysilicon floating gate, and the resulting memory cell pairs, according to some embodiments. [Figure 12N]1A-1C illustrate block diagrams of a process for fabricating an array of electrically erasable programmable non-volatile memory cells, each having a polysilicon floating gate, and the resulting memory cell pairs, according to some embodiments. [Figure 12O] 1A-1C illustrate block diagrams of a process for fabricating an array of electrically erasable programmable non-volatile memory cells, each having a polysilicon floating gate, and the resulting memory cell pairs, according to some embodiments. [Figure 12P] 1A-1C illustrate block diagrams of a process for fabricating an array of electrically erasable programmable non-volatile memory cells, each having a polysilicon floating gate, and the resulting memory cell pairs, according to some embodiments. [Figure 12Q] 1A-1C illustrate block diagrams of a process for fabricating an array of electrically erasable programmable non-volatile memory cells, each having a polysilicon floating gate, and the resulting memory cell pairs, according to some embodiments. [Figure 12R] 1A-1C illustrate block diagrams of a process for fabricating an array of electrically erasable programmable non-volatile memory cells, each having a polysilicon floating gate, and the resulting memory cell pairs, according to some embodiments. [Figure 12S] 1A-1C illustrate block diagrams of a process for fabricating an array of electrically erasable programmable non-volatile memory cells, each having a polysilicon floating gate, and the resulting memory cell pairs, according to some embodiments. [Figure 12T] 1A-1C illustrate block diagrams of a process for fabricating an array of electrically erasable programmable non-volatile memory cells, each having a polysilicon floating gate, and the resulting memory cell pairs, according to some embodiments. [Figure 12U]1A-1C illustrate block diagrams of a process for fabricating an array of electrically erasable programmable non-volatile memory cells, each having a polysilicon floating gate, and the resulting memory cell pairs, according to some embodiments. [Figure 12V] 1A-1C illustrate block diagrams of a process for fabricating an array of electrically erasable programmable non-volatile memory cells, each having a polysilicon floating gate, and the resulting memory cell pairs, according to some embodiments. [Figure 12W] 1A-1C illustrate block diagrams of a process for fabricating an array of electrically erasable programmable non-volatile memory cells, each having a polysilicon floating gate, and the resulting memory cell pairs, according to some embodiments. [Figure 13A] 1A-1C illustrate block diagrams of a process for fabricating an array of electrically erasable programmable non-volatile memory cells, each having a tantalum nitride floating gate, and the resulting memory cell pairs, according to some embodiments. [Figure 13B] 1A-1C illustrate block diagrams of a process for fabricating an array of electrically erasable programmable non-volatile memory cells, each having a tantalum nitride floating gate, and the resulting memory cell pairs, according to some embodiments. [Figure 13C] 1A-1C illustrate block diagrams of a process for fabricating an array of electrically erasable programmable non-volatile memory cells, each having a tantalum nitride floating gate, and the resulting memory cell pairs, according to some embodiments. [Figure 13D] 1A-1C illustrate block diagrams of a process for fabricating an array of electrically erasable programmable non-volatile memory cells, each having a tantalum nitride floating gate, and the resulting memory cell pairs, according to some embodiments. [Figure 13E]1A-1C illustrate block diagrams of a process for fabricating an array of electrically erasable programmable non-volatile memory cells, each having a tantalum nitride floating gate, and the resulting memory cell pairs, according to some embodiments. [Figure 13F] 1A-1C illustrate block diagrams of a process for fabricating an array of electrically erasable programmable non-volatile memory cells, each having a tantalum nitride floating gate, and the resulting memory cell pairs, according to some embodiments. [Figure 13G] 1A-1C illustrate block diagrams of a process for fabricating an array of electrically erasable programmable non-volatile memory cells, each having a tantalum nitride floating gate, and the resulting memory cell pairs, according to some embodiments. [Figure 13H] 1A-1C illustrate block diagrams of a process for fabricating an array of electrically erasable programmable non-volatile memory cells, each having a tantalum nitride floating gate, and the resulting memory cell pairs, according to some embodiments. [Figure 13I] 1A-1C illustrate block diagrams of a process for fabricating an array of electrically erasable programmable non-volatile memory cells, each having a tantalum nitride floating gate, and the resulting memory cell pairs, according to some embodiments. [Figure 13J] 1A-1C illustrate block diagrams of a process for fabricating an array of electrically erasable programmable non-volatile memory cells, each having a tantalum nitride floating gate, and the resulting memory cell pairs, according to some embodiments. [Figure 13K] 1A-1C illustrate block diagrams of a process for fabricating an array of electrically erasable programmable non-volatile memory cells, each having a tantalum nitride floating gate, and the resulting memory cell pairs, according to some embodiments. [Figure 13L]1A-1C illustrate block diagrams of a process for fabricating an array of electrically erasable programmable non-volatile memory cells, each having a tantalum nitride floating gate, and the resulting memory cell pairs, according to some embodiments. [Figure 13M] 1A-1C illustrate block diagrams of a process for fabricating an array of electrically erasable programmable non-volatile memory cells, each having a tantalum nitride floating gate, and the resulting memory cell pairs, according to some embodiments. [Figure 13N] 1A-1C illustrate block diagrams of a process for fabricating an array of electrically erasable programmable non-volatile memory cells, each having a tantalum nitride floating gate, and the resulting memory cell pairs, according to some embodiments. [Figure 13O] 1A-1C illustrate block diagrams of a process for fabricating an array of electrically erasable programmable non-volatile memory cells, each having a tantalum nitride floating gate, and the resulting memory cell pairs, according to some embodiments. [Figure 13P] 1A-1C illustrate block diagrams of a process for fabricating an array of electrically erasable programmable non-volatile memory cells, each having a tantalum nitride floating gate, and the resulting memory cell pairs, according to some embodiments. [Figure 13Q] 1A-1C illustrate block diagrams of a process for fabricating an array of electrically erasable programmable non-volatile memory cells, each having a tantalum nitride floating gate, and the resulting memory cell pairs, according to some embodiments. [Figure 13R] 1A-1C illustrate block diagrams of a process for fabricating an array of electrically erasable programmable non-volatile memory cells, each having a tantalum nitride floating gate, and the resulting memory cell pairs, according to some embodiments. [Figure 13S]1A-1C illustrate block diagrams of a process for fabricating an array of electrically erasable programmable non-volatile memory cells, each having a tantalum nitride floating gate, and the resulting memory cell pairs, according to some embodiments. [Figure 13T] 1A-1C illustrate block diagrams of a process for fabricating an array of electrically erasable programmable non-volatile memory cells, each having a tantalum nitride floating gate, and the resulting memory cell pairs, according to some embodiments. [Figure 13U] 1A-1C illustrate block diagrams of a process for fabricating an array of electrically erasable programmable non-volatile memory cells, each having a tantalum nitride floating gate, and the resulting memory cell pairs, according to some embodiments. [Figure 13V] 1A-1C illustrate block diagrams of a process for fabricating an array of electrically erasable programmable non-volatile memory cells, each having a tantalum nitride floating gate, and the resulting memory cell pairs, according to some embodiments. [Figure 13W] 1A-1C illustrate block diagrams of a process for fabricating an array of electrically erasable programmable non-volatile memory cells, each having a tantalum nitride floating gate, and the resulting memory cell pairs, according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0009] Reference will now be made in detail to the embodiments, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the various described embodiments. However, it will be apparent to those skilled in the art that the various described embodiments may be practiced without these specific details. In other instances, well-known methods, procedures, components, circuits, and networks have not been described in detail so as not to unnecessarily obscure aspects of the embodiments.

[0010] It will also be understood that, although terms such as first, second, etc. are used herein in some instances to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first contact can be referred to as a second contact, and similarly, a second contact can be referred to as a first contact, without departing from the scope of various described embodiments. Although a first contact and a second contact are both contacts, they are not the same contact unless the context clearly dictates otherwise.

[0011] The terminology used in the description of various embodiments herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in the various described embodiments and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. Terms such as "first," "second," etc. are used only to distinguish one element from another and do not limit the elements themselves. It will also be understood that the term "and / or," as used herein, refers to and encompasses any and all possible combinations of one or more of the associated listed items. It will also be understood that the terms "includes," "including," "comprises," and / or "comprising," as used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0012] As used herein, the term "if" is optionally interpreted to mean "if" or "when," or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "when determined" or "when detected (a stated condition or event)" is optionally interpreted to mean "when determining," or "in accordance with a determination that," or "in response to determining," or "when detecting (a stated condition or event)," or "in response to detecting (a stated condition or event)," depending on the context.

[0013] Unless otherwise specified, all distances, material thicknesses, voltages, and currents included in the following description are examples and should be assumed to be specified within a 10 percent tolerance. For example, unless otherwise specified, a stated distance or thickness of 200 Å includes a 10% tolerance and therefore ranges from 180 Å to 220 Å.

[0014] Attention now turns to embodiments of electrically erasable programmable nonvolatile memory cells, sometimes referred to as NOR memory cells or split-gate NOR memory cells, according to some embodiments. FIG. 1 shows a cross-sectional view of a pair of memory cells 100, 101, which are mirror images of each other, with the memory cells formed on either side of and including a shared control / erase gate 120. For simplicity, the remainder of this disclosure will refer to only one memory cell, namely memory cell 100. However, it will be understood that the mirrored memory cell 101 (the adjacent memory cell) has corresponding characteristics and behaves similarly under similar circumstances.

[0015] In some embodiments, memory cell 100 includes a semiconductor substrate 102 having bit line regions 104 (sometimes referred to as drain or source regions), surface regions 106 laterally spaced from the bit line regions, and trench regions 108 a / 108 b laterally spaced from the surface regions, the trench regions including a bottom portion 108 a adjacent a bottom surface of a trench 109 in substrate 102 and a sidewall portion 108 b adjacent a sidewall of trench 109. In some embodiments, sidewall portion 108 b of trench region is substantially perpendicular to surface 111 of the substrate. In some embodiments, bit line region 104 functions as a drain or a source. It is understood that the drain and source of a transistor may be switched during operation. Furthermore, in some embodiments, bit line region 104 includes substrate region 105, which is a shallower doped region than bit line region 104 (e.g., a moderately N-doped region in a P-doped substrate). In some embodiments, region 105, sometimes referred to as the LDD region, is not moderately N-doped, thereby increasing the threshold voltage required to conduct current through the channel (along the surface of the substrate) between bit line region 104 and the bit line regions of other memory cells.

[0016] The substrate 102 further includes a surface region 106. The surface region 106 is disposed between the bit line region 104 and the trench sidewall 108b. The substrate 102 further includes a horizontal surface 111 disposed over the bit line region 104 and extending laterally toward the trench sidewall 108b. The surface region 106 includes a portion of the surface 111 between the bit line region 104 and the trench sidewall 108b. In some embodiments, at least a portion of the surface 111 is a silicon-oxide interface (e.g., between a silicon substrate and an oxide-based insulating region). For purposes of this disclosure, the term "trench" describes the region (109) from which substrate material (102) has been removed, and thus the absence of substrate material, while the terms "trench region" (108a / 108b), "bottom" (108a), and "sidewall" (108b) describe the regions of the substrate 102 adjacent to the trench 109.

[0017] In some embodiments, memory cell 100 further includes a conductive control / erase gate 120 (alternatively referred to as a control gate or an erase gate). Control / erase gate 120 functions as either a control gate or an erase gate depending on the operating mode of memory cell 100. For example, when memory cell 100 (specifically, floating gate 150) is being written or read, gate 120 functions as a control gate, and when memory cell 100 (specifically, floating gate 150) is being erased, gate 120 functions as an erase gate.

[0018] Control / erase gate 120 is disposed within trench 109 and is insulated from bottom 108a and sidewalls 108b of the trench region of substrate 102 and includes a first portion 122 laterally spaced a first distance A from trench sidewalls 108b. Control / erase gate 120 further includes a second portion 124 disposed above first portion 122 and extending away from trench 109. In some embodiments, first control / erase gate portion 122 and second control / erase gate portion 124 are heavily doped (e.g., n+) polysilicon or alternatively are (or include) a metal (e.g., tungsten). In some embodiments, second control / erase gate portion 124 includes a laterally extending region 124a at the end of memory cell 100 farthest from substrate 102. Because region 124a is substantially perpendicular (e.g., at an angle of 45° to 135°) to the lower regions of first portion 122 and second portion 124 of control / erase gate 120, control / erase gate 120 is sometimes referred to as a T-shaped gate. In some embodiments, region 124a includes a self-aligned metal silicide (sometimes called salicide), which increases the conductivity of the control / erase gate. In other words, a metal contact (silicide) is added on top of region 124a both to provide a signal or reference voltage to control / erase gate 120 and to increase the conductivity of the control / erase line.

[0019] In some embodiments, memory cell 100 further includes a conductive word line 130 (optionally referred to as a gate) insulated from control / erase gate 124 and laterally offset from the second portion of control / erase gate 120 by a second distance B that is greater than first distance A. Word line 130 is further disposed above and insulated from floating gate 150.

[0020] In some embodiments, memory cell 100 further includes a conductive floating gate 150 insulated from substrate 102 and word line 130. Floating gate 150 includes a first end 152 substantially aligned with a sidewall 108b of the trench region of substrate 102 (more specifically, substantially aligned with the sidewall of the trench) and a second end 154 self-aligned with an edge 132 of word line 130 farthest from control / erase gate second portion 124. In some embodiments, floating gate first end 152 includes a pointed tip, a portion of which has a cross-section smaller than the cross-section of floating gate second end 154. In some embodiments, floating gate 150 is substantially parallel to substrate surface 111. In some embodiments, capacitive coupling between floating gate 150 and control / erase gate 120 is very small because the thickness of the floating gate is very thin, e.g., 20 Å or less. Thus, the cross-sectional area of ​​the floating gate edge 152 facing the control / erase gate 120 is much smaller than the cross-sectional area of ​​the word line 130 disposed above the floating gate 120. This small capacitive coupling, combined with the wider spacing B (between the control / erase gate 120 and the word line 130) relative to spacing A (between the control / erase gate 120 and the floating gate 150), allows the thin floating gate edge 152 to function as an efficient tunneling injector. As a result, a relatively low voltage is required for the erase operation, as will be described in more detail below with reference to FIG. 2.

[0021] In some embodiments, memory cell 100 further includes a dielectric layer 140 between floating gate 150 and word line 130. Dielectric layer 140 is a "thin" dielectric layer so as to provide strong capacitive coupling between floating gate 150 and word line 130. In some embodiments, dielectric layer 140 includes oxide, nitride, a combination of oxide and nitride, or other high-k material. In some embodiments, dielectric layer 140 has a total combined thickness of 8 nm to 10 nm. In some embodiments, as a result of the fabrication process, dielectric layer 140 includes a first portion 142 substantially aligned with first end 152 of the floating gate and sidewall 108 b of the trench region in the substrate, and a second portion 144 substantially aligned with second end 154 of the floating gate and edge 132 of the word line furthest from second portion 124 of the control gate.

[0022] In some embodiments, memory cell 100 further includes insulating material 160 between control / erase gate 120 and word line 130, between control / erase gate 120 and floating gate 150, between control / erase gate 120 and substrate 102, and between control / erase gate 120 and dielectric layer 140. In some embodiments, insulating material 160 includes an oxide, a nitride, a combination of an oxide and a nitride, or other dielectric material. In some embodiments, insulating material 160 provides lower capacitive coupling between control / erase gate 120 and word line 130 compared to a conventional silicon oxide layer.

[0023] In some embodiments, memory cell 100 further includes an erase gate insulating region 162 disposed between first end 152 of floating gate 150 and second portion 124 of control / erase gate 120, with erase gate insulating region 162 having a thickness that enables tunneling of electrons from first end 152 of floating gate to second portion 124 of control / erase gate during an erase operation. In some embodiments, the erase gate insulating region thickness is greater than 120 Å, enabling tunneling of electrons upon application of 7 V or less between the control gate and floating gate.

[0024] In some embodiments, memory cell 100 further includes a floating gate insulating region 164 (e.g., sometimes referred to herein as floating gate oxide 164) disposed between substrate surface portion 111 and floating gate 150. Floating gate insulating region 164 has a thickness that allows for frontal injection of electrons traveling an upward path to the floating gate during program operations. In some embodiments, floating gate insulating region 164 has a thickness of at least 100 Å, which prevents floating gate charge loss even in high temperature environments, thereby increasing charge retention of the memory cell, which increases the product life of the memory cell.

[0025] In some embodiments, the conductive elements of memory cell 100 (e.g., control / erase gate 120, floating gate 150, and / or wordline 130) are constructed of appropriately doped polysilicon. It should be understood that "polysilicon" refers to any suitable conductive material formed at least in part from silicon or a metallic material that can be used to form the conductive elements of a non-volatile memory cell. In some embodiments, floating gate 150 is constructed of tantalum nitride, which can be very thermally stable up to 1000°C. In some embodiments, floating gate 150 can have a thickness on the order of 10 Å.

[0026] In some embodiments, the insulating elements of memory cell 100 (e.g., insulating material 160) are constructed of silicon dioxide, silicon nitride, and / or any suitable insulator that can be used to form insulating elements of non-volatile memory cells.

[0027] Attention is now directed to the channel portions of memory cell 100, as shown in FIG. 2 . These channel portions are operative during a program operation of memory cell 100 (described in more detail below). In some embodiments, surface portion 106 of mirror memory cell 101, sidewall portion 108b of the trench region of mirror memory cell 101, bottom portion 108a of the trench region, and sidewall portion 108b of the trench region of memory cell 100 form a continuous channel 190 that extends from bit line region 104 of mirror memory cell 101 to the portion of the substrate closest to sidewall region 108b of memory cell 100. In some embodiments, adjacent portions of channel 190 are adjacent to or overlap one another, and in some embodiments, surface region 106 of mirror memory cell 101 overlaps bit line region 104 of mirror memory cell 101. In other words, portions 106, 108a, and 108b form a continuous channel 190. In some embodiments, the continuous channel region formed by portions 106 (of cell 101), 108b (of cell 101), and 108a and 108b (of cell 100) is non-coplanar because sidewalls 108b of channel 190 extend substantially perpendicular to the lateral direction in which surface portion 106 extends, and bottom 108a of channel 190 extends substantially perpendicular to the direction of sidewalls 108b of channel 190. In some embodiments, "substantially perpendicular" means an angle in the range of 75 to 105 degrees.

[0028] The operation of memory cell 100 according to some embodiments is described below with reference to Figure 2. The following description discloses erase, program, and read operations of memory cell 100. All items described with reference to Figure 2 refer to items included in memory cell 100 unless explicitly stated as referring to mirror memory cell 101.

[0029] To erase the memory cell 100 (in an erase operation), a negative high voltage (e.g., about −7 V (or alternatively, −7 V to −8 V)) is applied to the word line 130, and a positive high voltage (e.g., about 6 V) is applied to the erase gate 120, keeping the source / drain (bit line region 104) and substrate 102 at ground. The floating gate 150 is coupled to a negative voltage by capacitive coupling to the word line 130, which causes Fowler-Nordheim (FN) tunneling of electrons injected from the floating gate tip (first end 152) due to an enhanced electric field at the floating gate tip (first end 152, the end pointing toward the erase gate 120). As electrons are extracted, the floating gate 150 becomes positively charged until the voltage drop between the floating gate 150 and the erase gate 120 is no longer strong enough to support a significant FN tunneling current. As mentioned above, the capacitive coupling between the floating gate 150 and the erase gate 120 is very small compared to the capacitive coupling between the floating gate 150 and the word line 130. Therefore, a relatively low high voltage is required for the erase operation, thereby enabling efficient erasing (also called erasure) of the memory cell 100.

[0030] In some embodiments, during an erase operation, the word lines 130 of both adjacent memory cells 100 and 101 are biased at the same voltage (e.g., about −7V (or alternatively, −7V to −8V)). When both word lines are set to the same voltage, both memory cells 100 and 101 are erased simultaneously because the memory cells along the word line pair are treated as the smallest erase sector.

[0031] To program memory cell 100 (in a program operation), electrons are injected into floating gate 150 of memory cell 100 to neutralize a positive charge from an erase operation on the same memory cell or to negatively charge floating gate 150 of memory cell 100. Exemplary voltage bias values ​​for a program operation include approximately 4V to 4.5V on the source / drain (bit line region 104) of memory cell 100, 0V on the source / drain (bit line region 104) of mirror memory cell 101, a high positive voltage (e.g., approximately 6V to 8V) on word lines 130 of both memory cell 100 and mirror memory cell 101, and 1.6V to 1.8V on control / erase gate 120. These voltage bias values ​​cause a sub-threshold current of electrons (e.g., less than 100 nA) to flow along channel 190 from bit line region 104 of mirror memory cell 101 to bit line region 104 of memory cell 100. In some embodiments, a fixed potential (i.e., a fixed voltage) is applied to the control / erase gate 120 (e.g., 1.8V) and the source / drain (bit line region 104) of the memory cell 100 (e.g., 4V), and the source / drain (bit line region 104 of the mirror cell 101) is controlled with a signal pulse from 1.8V to ground and then back to 1.8V to perform a program operation.

[0032] As electrons flow through the bottom trench portion 108a beneath the control / erase gate 120 and turn upward at the transition from the bottom trench portion 108a to the sidewall trench portion (the trench corner labeled X in FIG. 2), they experience a strong vertical electric field component that accelerates them upward toward the substrate surface 111 beneath the floating gate 150. If the electrons gain enough energy (e.g., 3.2 eV) to overcome the energy barrier at the substrate and SiO2 interface at the substrate surface 111 beneath the floating gate 150, they cross the surface 111 and are pulled toward the floating gate 150 by Coulomb attraction. This programming mechanism improves programming speed. The potential of the floating gate 150 drops as the floating gate acquires electrons. This process continues until the floating gate potential is low enough to reduce the vertical electric field below surface portion 106, preventing electrons in the channel from gaining enough energy vertically to overcome the energy barrier at the interface (surface 111 below floating gate 150).

[0033] Thus, during a program operation, the word line potential (as described above), the control gate potential (as described above), and the bit line potential (as described above) are configured to allow electrons to move under the bottom 108a of the trench region, over the sidewalls 108b (of the memory cell 100) of the trench region, and toward the floating gate 150. In some embodiments, the floating gate 150 may reach its programmed state in 20 ns or less during such a program operation. Stated differently, in some embodiments, the memory cell 100 is configured such that the floating gate 150 reaches its programmed state in 20 ns or less during a program operation. Further details regarding the programming process are described below.

[0034] To read memory cell 100 (in a read operation), 0V is applied to the source / drain (bit line region 104) and word line 130 of memory cell 100, Vdd (e.g., 1.8V) is applied to the source / drain (bit line region 104) of mirror memory cell 101, 3V-4V (or alternatively, 2.5V-5V) is applied to control gate 120, and 0V or Vdd (e.g., 1.8V) (i.e., no charge pump is required) is applied to word line 130 of mirror memory cell 101. These voltage bias values ​​fully turn on trench bottom 108a and trench sidewall portions 108b of channel 190, and the fully depleted substrate region under the floating gate of mirror cell 101 allows electrons to flow freely from any portion of trench sidewall 108b toward bit line region 104 of mirror cell 101 without significant resistance (e.g., in the opposite direction of path 206 in FIG. 2 ). In other words, during a read operation, the portion of the substrate on the side of the mirror cell 101 is fully depleted due to the 1.8V applied to the source / drain 104 of the mirror cell 101 and the deep halo implant 306 (see FIG. 3 and the description of FIG. 3 below) in the region adjacent to the source / drain (bit line region 104) of the mirror cell 101. The mirror cell's channel region 190 is fully depleted regardless of the mirror cell's floating gate voltage. When the mirror cell's floating gate voltage is positively charged, the mirror cell's channel region has an inversion layer, but when the mirror cell's floating gate voltage is negatively charged, it does not have an inversion layer. In either case, the resistance to electron flow in the mirror cell channel region is substantially the same, affecting the read current flow by less than 3%. In other words, the read current is insensitive to the program / erase state of the mirror cell within a 3% tolerance.

[0035] Thus, in some embodiments, during a read operation of memory cell 100 as described above, the only node that requires a charge pump (e.g., to maintain the node at a voltage different from the fixed potential provided to the integrated circuit in which memory cell 100 resides) is control / erase gate 120, keeping power consumption caused by charge pumping to a minimum.

[0036] In embodiments including trench and deep halo implants but not corner implants (see implantation discussion below), if the floating gate 150 is sufficiently positively charged (e.g., +1.0 V in the erased state, or alternatively, +1.0 V to +2.0 V), the electric field generated by the floating gate 150 fully turns on the remaining portion of the channel 190 (e.g., the surface portion 106 of the memory cell 100), a high read current is generated and detected, and the floating gate channel threshold voltage is adjusted to be approximately −1.0 V to −1.2 V. On the other hand, if the floating gate 150 is negatively charged (e.g., having a potential of approximately −1.0 V to −1.5 V in the programmed state), the electric field generated by the floating gate 150 is not sufficient to turn on the portion of the channel 190 between the trench sidewall 108 b of the channel 190 and the bit line region 104 of the memory cell 100 (e.g., the surface portion 106 of the memory cell 100), and the read current is at a sub-threshold level.

[0037] The following description describes embodiments that include features for high-efficiency programming. As described above, to program the floating gate 150 of the memory cell 100, electrons flow from the source node (bit line region 104) along the portion of the channel 190 located in the mirror memory cell 101 (surface portion 106, trench sidewall 108b, and trench bottom 108a). At the transition from the trench bottom 108a to the trench sidewall 108b (of the memory cell 100), i.e., the trench corner indicated by X in FIG. 2, the electrons are no longer confined to the inversion layer and are freed to face a stronger electric field. This field is in a fully depleted space-charge region that pulls the electrons leftward and upward (e.g., toward paths 204 and 206).

[0038] To increase programming efficiency, electrons need to be pulled primarily upward (toward path 202) toward floating gate 150. These programming electrons gain kinetic energy while being accelerated, and if their energy is higher than the energy barrier height at the silicon / oxide interface at surface 111, the electrons are injected into floating gate insulating region 164 ( FIG. 1 ) and then attracted to floating gate 150. At trench angle X, the electrons are affected by pulling forces (e.g., attractive Coulomb forces or electrostatic forces induced by electric fields) from floating gate 150 of upper memory cell 100 (toward paths 202 and 204), from the drain node (bit line region 104) of memory cell 100 (toward path 206), and from control / erase gate 120 (toward control / erase gate 120).

[0039] Thus, if the pulling force from the drain (bit line region 104) is approximately the same as the pulling force from the control gate, electrons will flow primarily along path 202. However, if the pulling force from the drain (bit line region 104) is stronger than the pulling force from the control gate, electrons will flow primarily along path 204 or 206 (depending on how strong the pulling force from the drain is compared to the pulling force from the control gate). While FIG. 2 shows three electron paths 202, 204, and 206, these paths are shown as three discrete lines to illustrate the examples described herein. However, in practice, those skilled in the art will understand that the paths an electron can take when pulled from position X resemble a spectrum, and the paths themselves may vary based on the amount of pulling force described above, as well as the pulling force from above due to the floating gate potential. The pulling force from the floating gate decreases as the programming mechanism progresses.

[0040] If the pulling force from the drain node (bit line region 104) is stronger than the pulling force from the control / erase gate 230, the electrons will flow primarily toward path 204 or 206 while moving upward, which is undesirable because the horizontal direction of electron movement is less favorable for obtaining the vertical energy required for injection into floating gate 150. In other words, the electrons after passing through corner X must have a sufficient vertical component in their flow direction to obtain sufficient energy to be injected into floating gate 150. Therefore, in some embodiments, it is desirable to increase the control gate voltage during a program operation to counteract the pulling force from the drain (bit line region 104), thereby counteracting the horizontal component in the electron flow direction after the electrons pass through corner X and ensuring a sufficient vertical component in their flow direction to obtain sufficient energy to be injected into floating gate 150.

[0041] However, increasing the control gate voltage during a program operation while maintaining a low programming current requires a high control gate threshold, which adversely affects the read current. To address this tradeoff, in some embodiments, memory cells 100 and 101 include (e.g., consist of) multiple implants to optimize the threshold voltage of different portions of channel 190 to achieve high programming efficiency while maintaining a sufficiently high read current for erased cells.

[0042] In embodiments in which the word lines 130 from both memory cells in a memory cell pair 100 / 101 are biased at the same voltage for read operations (e.g., 0V), program operations (e.g., 7V), and erase operations (e.g., −7V), such a mirror cell structure may be implemented as described above with reference to Figures 1 and 2, but with the additional feature of each word line 130 of the memory cell pair electrically connected to each other. In these embodiments, the mirror cell structure including the two memory cells 100 / 101 may be implemented as a four-node device with nodes consisting of: (i) the source (e.g., 104 in cell 100 / 101), (ii) the drain (e.g., 104 in cell 101 / 100), (iii) the word line (both word lines 130 are electrically connected together), and (iv) the control / erase gate 120.

[0043] 3 illustrates multiple implants in substrate 102 of memory cell 100 / 101, according to some embodiments. In some embodiments, the implants include indium (atomic number 49), which is similar to boron and is a p-type dopant, but is much heavier and diffuses much slower in high temperature environments than boron in silicon substrates. In some embodiments, the dopant in the implants described herein is gallium.

[0044] Referring to FIG. 3, the substrate 102 includes (i) a first indium implant, referred to as a "trench implant" 302, disposed in a region of the substrate below the bottom of the trench; (ii) a second indium implant, referred to as a "corner implant" 304, disposed in a region of the substrate adjacent to the sidewalls of the trench and the surface region of the substrate of each memory cell 100 / 101; and (iii) a third indium implant, referred to as a "deep halo implant" 306, disposed in a region of the substrate adjacent to the lower portion (e.g., bottom) of the source / drain (bit line region 104) of each memory cell 100 / 101.

[0045] In some embodiments, the trench implant 302 increases the threshold voltage of the trench bottom channel (the portion of the channel 190 located within the trench bottom 108a in FIG. 2) so that the channel current is controlled to about 100 nA with a control gate 120 voltage Vcg of about 1.6 V to 2.0 V during a program operation to program the memory cell in 10 ns to 20 ns (or less).

[0046] In some embodiments including the corner implant 304, the corner implant 304 of each memory cell 100 / 101 controls the threshold voltage of the floating gate channel (portion of channel 190 located in surface region 106 of FIG. 2) to be approximately 0.2 V, such that the read current is less than 1 μA for a programmed cell and greater than 10 μA for an erased cell. Thus, the substrate 102 includes a second indium implant (corner implant 304) that controls the threshold voltage of the channel (region 106, FIG. 2) of the floating gate 150 to be approximately 0.2 V, and the read current is less than 1 μA (i) when the floating gate 150 is programmed (e.g., negatively or neutrally charged) and greater than 10 μA (ii) when the floating gate 150 is erased (e.g., positively charged to +2.0 V).

[0047] In some embodiments, the deep halo implant 306, in combination with the trench implant 302, controls the punch-through current of unselected rows (control gate 120 voltage Vcg, word line 130 voltage Vwl) to be 10 pA or less. The deep halo implant 306 (preferably does not include a lateral p-type halo between the deep halo implant and the surface of the substrate) provides the additional advantage that during a read operation of one memory cell 100 or 101, the read current is insensitive to the programmed or erased state of the mirror memory cell 101 or 100, within a 3% tolerance. Thus, the substrate 102 includes a third indium implant (deep halo implant 306) that, in combination with the trench implant 302, causes the punch-through current of unselected rows to be 10 pA or less, and further, the difference in read current between the mirror cell 101 in its erased or programmed state and the erased cell 100 is less than 3%. More generally, in some embodiments, the state of mirror cell 101 affects the read current by less than 3% when reading memory cell 100, and in some other embodiments, the state of mirror cell 101 affects the read current by less than 10% or 15% when reading memory cell 100.

[0048] In some embodiments, the substrate 102 for adjacent memory cells 100 / 101 includes only two of the three types of implants described above, as shown in FIGS.

[0049] 4, in some embodiments, substrate 102 includes trench implant 302 and halo implant 306, or a halo implant similar to implant 602 shown in FIG. 6, but without the corner implant. In some such embodiments, during a read operation on memory cell 100, a voltage of 3V to 4V is applied to the word line of mirror cell 101 to reduce or minimize the read current sensitivity to the programmed / erased state of mirror cell 101.

[0050] As another example, in some embodiments, the substrate 102 includes the corner implants 304 and the deep halo implants 306, but does not include the trench implant, as shown in FIG.

[0051] 6 and 7 are diagrams illustrating halo implants in the substrate of memory cells 100 / 101 according to some embodiments.

[0052] A conventional halo implant 602 (FIG. 6) is disposed around bit line region 104 (source / drain node), from beneath region 104 all the way down to surface 111 of substrate 102. With such an implant, during a read operation, when the source / drain node (region 104) of mirror cell 101 is at 1.8V, channel region 106 of mirror cell 101 is partially depleted by the source / drain voltage, and the read current when reading memory cell 100 is more sensitive to the program / erase state of mirror cell 101 than the memory cells described above with reference to FIGS. 1-5 (e.g., the read current when reading cell 100 can vary by more than 25% depending on the state of mirror cell 101).

[0053] The deep halo implant 306 (FIG. 7) is disposed only around the lower portion of the bit line region 104 (the source / drain node), and not between the bottom of the substrate 102 and the surface 111 (not in region 702 of the substrate). With such an implant, during a read operation, when the source / drain node (region 104 of the mirror memory cell 101) is at 1.8V, the channel region 106 of the mirror memory cell 101 is fully depleted, regardless of the floating gate voltage of the floating gate of the mirror memory cell 101. The deep halo implant 306 does not significantly affect the doping profile of the channel region 106 (i.e., at the interface between the substrate and the source / drain), where "does not significantly affect" is defined in this context as not preventing the depletion region in the mirror cell 101 from reaching the trench sidewalls 108b of the channel 190, thereby allowing electrons to flow with little resistance from the trench sidewalls 108b in the mirror cell 101 toward the source / drain (bit line regions 104) of the mirror cell 101 when a read voltage is applied to the source / drain (bit line regions 104) of the mirror cell 101.

[0054] Memory array plan view Attention is now directed to Figures 8 and 9, which illustrate alternative plan views of memory cell arrays 800 and 900, respectively, according to some embodiments. In some embodiments, bit lines interconnect the drain / source regions of paired memory cells.

[0055] Manufacturing Process Attention is now directed to Figures 10A-10F, which illustrate a process for fabricating memory cells 100 / 101 according to some embodiments.

[0056] A process according to some embodiments begins in FIG. 10A, which shows a cross-sectional view of a silicon substrate 1002, a dielectric layer 1004 (e.g., thermal silicon dioxide or low-trap silicon nitride), a tantalum nitride floating gate material 1006, an oxide layer 1008, and a silicon nitride layer 1010. Including removal of all oxide, a number of N-wells or P-wells are formed. A floating gate dielectric layer 1004 is formed on the substrate 1002 (e.g., thermal SiO or low-trap SiN) (e.g., about 100 Å, or alternatively, greater than 100 Å). Next, a floating gate material 1006, TaN (tantalum nitride) (e.g., 20 Å or less), is deposited. Next, an oxide layer 1008 (e.g., about 20 Å or less) and a silicon nitride layer 1010 (e.g., 100 Å) are deposited. Next, an STI (shallow trench insulation) mask is laid down for STI formation (including CMP, stopping on the silicon nitride layer).

[0057] As shown in Figure 10B, the nitride layer 1010 is stripped and a high-quality Si3N4 thin film 1012 (approximately 80 Å) is redeposited as a coupling dielectric between the word lines and the TaN floating gates. A cell array protection mask is applied to protect the memory cell array area and remove the nitride / oxide / TaN / oxide stack from other areas (e.g., non-cell area 1014). Next, HV gate oxide and LV thin gate oxide 1016 are grown in the non-cell areas using masking operations to define the thin oxide areas.

[0058] 10C, polysilicon gate material 1018 is deposited with appropriate doping. Next, a gate mask 1020 is applied in a masking operation to define word lines 1022 and peripheral transistor gates 1024.

[0059] As shown in Figure 10D, a layer 1026 of Si3N4 (e.g., about 20 Å to 30 Å) is deposited, followed by a layer 1028 of SiO2 (e.g., 80 Å). A trench mask operation is performed to form trenches 1030 in the control / erase gate region.

[0060] In some embodiments, before the trench etch, a corner implant is performed to dope the trench corners with p-type dopants.

[0061] As shown in FIG. 10E, a photoresist strip operation is performed. Next, a high-temperature oxide (HTO) layer 1032 (e.g., 120 Å to 150 Å) is added, or a low-trap Si3N4 layer is added as a tunnel dielectric. Next, doped polysilicon 1034 is deposited to fill the trench regions between the word lines, and the doped polysilicon is partially etched back. Next, to protect the trench and peripheral regions, a source / drain TaN removal mask is placed at location 1036 to remove the remaining polysilicon, tunnel dielectric, and TaN in the memory cell array source / drain regions. Next, to protect the memory cell array region, a non-cell region oxide removal mask is placed to remove the remaining polysilicon, tunnel dielectric, and oxide in the non-cell regions.

[0062] As shown in FIG. 10F, source / drain regions 1038 are formed using a typical back-end source / drain formation process.

[0063] Manufacturing Process Attention is now directed to Figures 11A-11M, which illustrate a process for fabricating memory cells 100 / 101 according to some embodiments.

[0064] A process according to some embodiments begins in FIG. 11A, which shows a cross-sectional view of a silicon substrate 1102, a dielectric layer 1104 (e.g., thermal silicon dioxide or low-trap silicon nitride), a floating gate material 1106, an oxide layer 1108, and a silicon nitride layer 1110. A number of wells are formed, including N-wells, deep N-wells, and P-wells (for the peripheral region), which includes stripping of all oxide. A floating gate dielectric layer 1104 is formed (e.g., thermal SiO or low-trap SiN) (e.g., about 100 Å or thicker) on the substrate 1102. Next, a peripheral HV oxide (e.g., 135 Å to 160 Å) and a thin oxide (e.g., 32 Å or thinner) region are formed (not shown). Then, a polysilicon floating gate material 1106 (about 300 Å, N-type doped (Poly 1)) is formed, and an oxide layer 1108 (e.g., about 20 Å) and a sacrificial silicon nitride layer 1110 (e.g., Si3N4, 100 Å) are deposited. Next, an STI mask is placed for STI formation (including CMP, stopping on the silicon nitride layer).

[0065] As shown in FIG. 11B, the portion of the oxide in the STI (above the substrate) is removed by anisotropic etching.

[0066] As shown in Figure 11C, the remaining silicon nitride is removed, and a high-quality 100 Å layer of silicon nitride or a combination of oxide and silicon nitride 1114 is redeposited as the coupling dielectric material between the word lines and the floating gates. A cell array protection mask is then placed to protect the memory cell array area and remove the nitride / oxide from other areas (non-cell areas). Next, N-type doped polysilicon (poly 2) 1116 is deposited, which will become the word line material for the cell array and the gate material for the peripheral transistors (poly 2 and poly 1 are connected). Next, oxide 1118 is deposited.

[0067] As shown in Figure 11D, a gate mask 1120 is laid down to define the word lines and word line pick-up areas in the cell array and the gates of the peripheral transistors (not shown).

[0068] As shown in Figure 11E, an anisotropic etch is performed to partially remove the oxide / poly2 / nitride stack and poly1, leaving about 100 Å (region 1122), after which the photoresist is stripped.

[0069] As shown in Figure 11F, a high quality 130 Å HTO layer 1124 is deposited, followed by an anisotropic etch to remove the 130 Å HTO over the remaining 100 Å Poly 1.

[0070] As shown in Figure 11G, polysilicon (Poly 1) 1106 is isotropically etched with appropriate overetching to form a sharp Poly 1 edge 1126 (also called a tip, sharp point, or pointed tip) that functions as a tunnel injector. While the tantalum floating gates described above with reference to Figures 10A-10F may have a thickness of 10 Å to 20 Å, Poly 1 floating gate 1106 may have a thickness of 300 Å to 400 Å, with tip 1126 having a thickness of less than 30 Å, typically 10 Å to 20 Å.

[0071] As shown in Figure 11H, a trench mask 1128 is placed and a corner implant 1130 is applied to define the threshold voltage of the floating gate channel (e.g., an indium implant at a 7 degree angle along the wordline direction, with a narrow portion of the implanted indium impurities doping the trench corners). Corner implant 1130 corresponds to corner implant 304 of Figure 3.

[0072] As shown in Figure 11I, a portion of the substrate silicon 1102 is anisotropically etched to create an approximately 400 Å trench 1132. Next, a trench implant 1134 (e.g., indium 80 Kev, tilted 7 degrees along the wordline direction) is applied. Trench implant 1134 corresponds to trench implant 302 in Figure 3.

[0073] The photoresist is stripped from area 1136, as shown in FIG. 11J.

[0074] As shown in FIG. 11K, a layer of HTO 1138 (eg, 120 Å) is deposited as a tunnel dielectric material between the floating gate and the control / erase gate.

[0075] As shown in FIG. 11L, doped polysilicon (poly 3) 1140 is deposited as the control / erase gate material using a control / erase gate mask to define the erase gate.

[0076] As shown in Figure 11M, source / drain regions 1142 are formed. In some embodiments, the process of forming source / drain regions 1142 does not involve a conventional halo implant with a lateral halo in the memory cell array region. Instead, an indium punch-through suppression (deep halo) implant 1144 is applied. Deep halo implant 1144 corresponds to deep halo implant 306 of Figure 3.

[0077] In some embodiments, the steps for applying implants 1130 (FIG. 11H), 1134 (FIG. 11I), and 1144 (FIG. 11M) are applied in a similar manner to the process flows of FIGS. 10A-10F.

[0078] As shown in FIG. 11M, the shape of the floating gate 150 is defined on one side by shallow trench isolation (STI) and on the other side by the word line 130, and therefore no separate mask is involved in forming the floating gate 150.

[0079] Second manufacturing process Attention is now directed to Figures 12A-12V, which illustrate a process for fabricating a pair of electrically erasable, programmable, non-volatile memory cells, including electrically erasable, programmable, non-volatile memory cells 1200 / 1201, according to some embodiments. Figures 12A-12V show cross-sectional views of the pair of memory cells 1200, 1201 as the fabrication process progresses. Note that the structures shown in Figures 12A-12V, as well as Figures 12W, 13A-13V, and 13W, are not drawn to scale, and some features are shown at a disproportionately large size in order for those features to be visible in these figures.

[0080] As shown in FIG. 12A, the process for fabricating an electrically erasable programmable nonvolatile memory cell begins with a substrate 1202 having an insulator layer 1204 and a floating gate layer 1206 (e.g., polysilicon) disposed thereon. FIG. 12A illustrates a cross-sectional view of a silicon substrate 1202, a dielectric layer 1204 (e.g., thermal silicon dioxide or low-trap silicon nitride), and a floating gate layer 1206 (e.g., polysilicon). In some embodiments, the polysilicon floating gate layer 1206 has a thickness between two hundred angstroms and four hundred angstroms (200 Å and 400 Å), e.g., 300 Å, within a ten percent (10%) tolerance. Because the dielectric layer 1204 is positioned between the floating gate layer 1206 and the substrate 1202, it is sometimes referred to as a floating gate oxide layer.

[0081] 12B, a series of additional layers 1208-1216 of the structure shown in FIG. 12A are then deposited, including a dielectric (e.g., oxide) layer 1208 (sometimes referred to as a bond oxide / dielectric or word line gate oxide / dielectric), a polysilicon layer 1210 (sometimes referred to as a Poly 2 layer or word line layer), a stacked dielectric (e.g., oxide) layer 1212, a silicon nitride (e.g., SiN) layer 1214, and another dielectric (e.g., oxide) layer 1216 on top. In some embodiments, the dielectric layer 1216 serves to protect memory structural elements underneath the dielectric layer 1216 during subsequent processing.

[0082] As shown in FIG. 12C , using a mask 1220 and an appropriate etchant and process (e.g., an anisotropic etch), a trench 1222 is opened in the structure shown in FIG. 12B to remove portions of dielectric layer 1216, silicon nitride layer 1214, and overlying dielectric layer 1212 that are not protected by mask 1220. The etching operation shown in FIG. 12C stops at silicon nitride layer 1210. Note that reference numeral 1222 is used herein to identify a trench even though the shape (e.g., width and depth) of the trench may change during subsequent processing steps. At this early stage, "trench" 1222 is not yet truly a trench, as it has not yet extended into substrate 1202.

[0083] Next, as shown in Figure 12D, word line (WL) spacer (e.g., dielectric) material is deposited and etched back to form word line (WL) spacers 1224 on the outer vertical edges of trench 1222. As a result, trench 1222 is substantially narrowed.

[0084] Next, as shown in FIG. 12E, using the WL spacers 1224 as a mask, an anisotropic etch 1226 is used to etch the polysilicon word line layer 1210 and the bonding oxide / dielectric layer 1208 and partially etch the polysilicon floating gate layer 1206, so that the trench 1222 is separated from the substrate 1202 by a portion of the polysilicon floating gate layer 1206 and the floating gate oxide / dielectric 1204.

[0085] Next, as shown in Figures 12F and 12G, offset spacers 1228 (e.g., a dielectric material) are deposited and etched back to create narrower trenches 1222 (for ease of reference, the label 1222 continues to apply to "trench" even though the dimensions, including width and depth, of the trenches change as processing continues), and the offset spacers 1228 separate the word line layer 1210 from the trenches. The boundary between the WL spacers 1224 and the offset spacers 1228 is shown with a dashed line. In some embodiments, the WL spacers 1224 and the offset spacers 1228 are formed from the same dielectric, e.g., silicon oxide.

[0086] Next, as shown in FIG. 12H, an etching operation, e.g., an isotropic etch, is performed to remove the remainder of the polysilicon layer 1206 at the bottom of the trench 1222 and also to etch a portion of the polysilicon layer 1206 positioned under the offset spacer 1228 adjacent to the bottom of the trench 1222, thereby forming a polysilicon tip 1232 facing the trench 1222 (e.g., the tip 1232 is the narrowest part of the polysilicon layer and also the part of the polysilicon floating gate 150 (see FIG. 12W) formed from the polysilicon layer 1206 that is closest to the trench 1222).

[0087] Next, as shown in Figure 12I, a first tunnel oxide 1234 (e.g., a dielectric layer) is deposited in the trench 1222. At this point, the polysilicon tip 1232 is separated from the trench 1222 only by the first tunnel oxide 1234, while the polysilicon layer 1206 (floating gate 150) and other portions of the word line layer 1210 are separated from the trench 1222 by the offset spacers 1228 and the first tunnel oxide 1234.

[0088] Next, as shown in Figure 12J, an oxide etch (e.g., an anisotropic etch) operation is performed to extend trench 1222 into the substrate while minimizing etching of first tunnel oxide 1234. In some embodiments, the lateral thickness of first tunnel oxide 1234 after completion of the etch operation of Figure 12J is approximately 70 Å (e.g., less than 100 Å) within a 10-15 percent tolerance, and in some embodiments, has a thickness between 50 Å and 100 Å. As shown in Figure 12J, floating gate 150 covers the entire portion of floating gate oxide 164 except for the portion nearest trench 1222, sometimes referred to herein as offset gap 1238. The presence of the offset gap 1238 in the memory cell increases the floating gate threshold voltage (e.g., the voltage of the floating gate 150 relative to the voltage of the substrate 102) required to allow the flow of at least a predetermined amount of current (e.g., the amount of current required to determine the state of the memory cell 1200 during a read operation) through the channel 190 under the floating gate oxide 1204 / 164 (see FIG. 12W).

[0089] Next, as shown in FIG. 12K, a trench implant operation is performed during which trench implant 1240 is introduced into the substrate below trench 1222 (e.g., into the region of substrate 102 below the bottom of trench 1222). In some embodiments, trench implant 1240 comprises an indium implant. The characteristics of trench implant 1240 are described above with respect to trench implant 302 (e.g., to determine or increase the threshold voltage at the trench bottom of channel 190).

[0090] Next, typically after trench implantation, a second tunnel oxide 1242 (e.g., a dielectric layer) is deposited in the trench 1222, as shown in FIG. 12L. At this point, the polysilicon tip 1232 is separated from the trench by both the first tunnel oxide 1234 and the second tunnel oxide 1242, while the polysilicon layer 1206 (floating gate 150) and other portions of the word line layer 1210 are separated from the trench 1222 by the offset spacer 1228, the first tunnel oxide 1234, and the second tunnel oxide 1242. The dashed lines in FIG. 12L indicate the boundaries between the WL spacer 1224, the offset spacer 1228, the first tunnel oxide 1234, and the second tunnel oxide 1242. In some embodiments, the lateral thickness of the second tunnel oxide 1242 is approximately 80 Å within a 10-20 percent tolerance, and in some embodiments, has a thickness between 50 Å and 110 Å.

[0091] Next, as shown in Figure 12M, one or more conductive materials are deposited in trench 1222 to form the control gate. In some embodiments, the conductive material forming the control gate comprises polysilicon, and in some embodiments, comprises a metal such as titanium nitride and / or tungsten. Further, as shown in Figure 12M, an etching operation 1244 is performed to remove excess upper portions of the insulator layer and conductive material forming the control gate. Note that electrical connections to the control gate, for example to control gates of other memory cell pairs within the same row or column or memory cell, are made using conductors that extend in directions not visible in the cross-sectional view of Figure 12M.

[0092] Next, as shown in Figure 12N, a dielectric material (e.g., oxide) is formed on top of the memory cell pairs and then planarized using, for example, chemical mechanical planarization (CMP). Thereafter, as shown in Figure 12O, the silicon nitride structure formed from silicon nitride layer 1214 is removed by etching 1248, resulting in the structure shown in Figure 12O. As shown in Figure 12P, a further etching operation 1250 removes portions of the word line, floating gate, and word line gate layers 1206, 1208, 1210 farthest from the control gate to form the structure shown in Figure 12P.

[0093] In Figure 12P, portions of polysilicon layers 1206, 1210 are exposed, and then these portions are covered with a dielectric layer to form a protective dielectric layer over the outer portions of the word lines and floating gates, as shown in Figure 12Q.

[0094] Next, as shown in FIG. 12R, a first silicon nitride spacer 1254 is added (e.g., deposited and then anisotropically etched) to the outer portion of the memory pair structure, followed by an oxide etching operation as shown in FIG. 12S, then a silicon oxide layer is deposited, and then a second silicon nitride spacer is added to the outer portion of the memory pair structure as shown in FIG. 12T.

[0095] Next, as shown in Figure 12U, a deep halo implant operation 1260 is performed to add a dopant, such as indium, to the region of the substrate beneath the drain / source regions (bit line regions 104) of the two memory cells 1200, 1201. The characteristics of the deep halo implant 1260 are described above with respect to the deep halo implant 306.

[0096] Finally, bitline (e.g., N+) and LDD implant operations are performed to form the bitline and LDD regions of each memory cell 1200, 1201. The LDD implant is optional depending on the desired threshold level of the floating gate 150 (see FIG. 12W). Furthermore, as shown in FIG. 12W, the floating gate 150 (e.g., the remaining portion of the floating gate region 1206 after the etching operation shown in FIG. 12P) does not overlap the LDD region 105 of each memory cell 1200, 1201 (whether the “LDD region” 105 is implanted with N+ dopants or not), thereby forming an offset region in the substrate 102 between the source / drain (bitline) region 104 and the portion of the channel 190 covered by the floating gate 150. The LDD region 105 is sometimes referred to herein as the distal portion of the channel in an electrically erasable programmable nonvolatile memory cell that is furthest from the trench region and not covered by the floating gate 150.

[0097] Second Memory Cell Structure FIG. 12W shows a block diagram of a memory cell pair structure including electrically erasable programmable nonvolatile memory cells 1200 and 1201 resulting from the fabrication process described above. An example of a plan view of a memory cell array according to an embodiment using the memory cell pair structure of FIG. 12W is shown in FIG. 9. In some embodiments, memory cell 1200 includes: a semiconductor substrate (102) having bit line regions (104), a surface region (106) laterally spaced from the bit line regions (e.g., horizontally in FIG. 12W) and a trench region laterally spaced from the surface region (106), the trench region having a bottom (108a) and sidewalls (108b) adjacent to a trench (109) in the semiconductor substrate; A conductive control gate (120), a first portion (122) disposed within the trench and insulated from a bottom and sidewalls of the trench region of the substrate and laterally spaced a first distance (A) from the sidewalls of the trench region; a conductive control gate (120) disposed over the trench (109) and having a second portion (124) extending away from the trench; a conductive word line (130) insulated from the control gate (120) and laterally offset from the second portion (124) of the control gate by a second distance (B) greater than the first distance (A); a floating gate (150) (e.g., a polysilicon floating gate) insulated from the substrate (102) and the word line (130); a first end (152) comprising a portion of the floating gate closest to the control gate and separated laterally from a second portion of the control gate by a third distance (C) that is greater than the first distance (A) and less than the second distance (B); a floating gate (150) having a second end (154) self-aligned with the edge (132) of the word line furthest from the second portion of the control gate.

[0098] In some embodiments, the second memory cell 1201 of the memory cell pair has the same structural components as the first memory cell 1200, except that both memory cells share the same control gate 120, and the components of the second memory cell 1201 are arranged as a mirror image of the components of the first memory cell 1200.

[0099] In some embodiments, as shown in Figure 12W (and Figure 12L), the conductive word line is insulated from the control gate and offset from the second portion of the control gate by an insulator sequence comprising an offset spacer, a first tunnel oxide, and a second tunnel oxide, the insulator sequence laterally separating the word line from the control gate by a second distance (B) greater than the first distance (A). Furthermore, in such embodiments, the first end (152) of the floating gate is separated from the second portion (124) of the control gate (120) by the first tunnel oxide and the second tunnel oxide, but not by the offset spacer.

[0100] In some embodiments, the second tunnel oxide extends into the trench, rather than the first tunnel oxide.

[0101] In some embodiments, memory cell 1200 further includes a first indium implant (1240) disposed in a region of the substrate below the bottom of the trench region and a second indium implant (1260) disposed in a region of the substrate adjacent to a source or drain region of the memory cell. Furthermore, in some embodiments, the first indium implant is configured to induce a threshold voltage of the channel at the bottom of the trench region during a program operation to control a programming current of 100 nA with a control gate voltage of 1.6 V to 2.0 V, and the floating gate reaches its programmed state in 20 ns or less upon application of the programming current. In some embodiments, the second indium implant, in combination with the first indium implant, (i) reduces the punch-through current of unselected rows of memory cells to 10 pA or less, and (ii) insensitive the read current to the program / erase state of a mirror cell (e.g., memory cell 1201) within a 10% tolerance.

[0102] In some embodiments, the lateral extent of the first tunnel oxide corresponds to the portion of the channel (190, FIG. 12W) in the substrate (102) that extends from the bitline region (104) to the sidewall of the trench region (109) and is not covered by the floating gate (150). See FIG. 12W. In other words, the width (or lateral extent) of the first tunnel oxide corresponds to the offset gap 1238 shown in FIG. 12J. See the above discussion of FIG. 12J.

[0103] In some embodiments, an erase gate insulation region (162, FIG. 12W) is disposed between the first end (152) of the floating gate (150) and the second portion (124) of the control gate (120), the erase gate insulation region corresponding to portions of the first tunnel oxide and second tunnel oxide disposed between the first end of the floating gate and the second portion of the control gate, the erase gate insulation region having a thickness that enables tunneling of electrons from the first end of the floating gate to the second portion of the control gate during an erase operation. In some embodiments, the erase gate insulation region thickness is greater than 120 Å (e.g., 150 Å within a 10% or 15% tolerance) and enables tunneling of electrons when 7 V or less is applied between the control gate and the floating gate.

[0104] In some embodiments, the floating gate comprises polysilicon having a thickness between 200 Å and 400 Å and a tip at the first end having a thickness of less than 20 Å.

[0105] In some embodiments, the control gate is configured to function as an erase gate during an erase operation.

[0106] In some embodiments, the memory cell 1200 includes a floating gate insulating region (164) disposed between a surface region of the substrate and the floating gate, the floating gate insulating region having a thickness that allows for frontal injection of electrons traveling an upward path to the floating gate during a program operation.

[0107] In some embodiments, the word line potential of the word lines, the control gate potential of the control gate, and the bit line potential of the bit line regions are configured to allow electrons to move down the bottom of the trench region and then up towards the floating gate during a program operation.

[0108] In some embodiments, the floating gate 150 is configured to reach a programmed state in 20 ns or less during a program operation.

[0109] In some embodiments, the word line (130) is electrically connected to the word line (130) of the mirror memory cell. The electrically erasable programmable nonvolatile memory cell (1200) and the mirror memory cell (1201) form a four-node memory cell pair, the four nodes consisting of a source node, a drain node, a word line node, and a control / erase node, the word line node comprising the electrically connected word line, the control / erase node comprising a control gate shared by the electrically erasable programmable nonvolatile memory cell (1200) and the mirror memory cell (1201), and the source node or the drain node comprising or electrically connected to the bit line region (104) of the electrically erasable programmable nonvolatile memory cell (1200). Alternatively, the word line (130) is not electrically connected to the word line (130) of the mirror memory cell. The electrically erasable programmable nonvolatile memory cell (1200) and the mirror memory cell (1201) form a five-node memory cell pair, the five nodes consisting of a source node, a drain node, a first word line node (in the case of the first memory cell 1200) and a second word line node (in the case of the mirror memory cell 1201), and a control / erase node, the first word line node comprising the word line of the first memory cell, the second word line node comprising the word line of the mirror memory cell, the control / erase node comprising a control gate shared by the electrically erasable programmable nonvolatile memory cell (1200) and the mirror memory cell (1201), the source node comprising or electrically connected to the bit line region (104) of the electrically erasable programmable nonvolatile memory cell (1200), and the drain node comprising or electrically connected to the bit line region (104) of the electrically erasable programmable nonvolatile mirror memory cell (1201).

[0110] 4 and 5 node configurations of memory cell pairs The memory cell pair shown in FIG. 12W, which includes two memory cells 1200 and 1201 that share a control gate, can be used as a four-node device, where the word lines of both memory cells are electrically connected to the same node and controlled together, or as a five-node device, where the word lines of the two memory cells are controlled separately. The following tables show example control voltages applied to the nodes of a four-node device and a five-node device to perform read (first and second memory cells), program (first and second memory cells), and erase operations. Unless otherwise indicated, all example voltages for operating the memory cell pair are considered to be within voltage ranges that vary by up to 10% of the example control voltages provided in the tables herein.

[0111] [Table 1]

[0112] [Table 2]

[0113] The third manufacturing process Figures 13A-13V illustrate a process for fabricating a pair of electrically erasable, programmable, non-volatile memory cells, including electrically erasable, programmable, non-volatile memory cells 1300 / 1301 having tantalum nitride floating gates, as opposed to the polysilicon floating gates of the pair of memory cells fabricated using the process of Figures 12A-12V. As will be shown below in the description of this third fabrication process, many portions of the fabrication process of Figures 13A-13V are the same as the fabrication process of Figures 12A-12V.

[0114] Figures 13A-13V show cross-sectional views of a pair of memory cells 1300, 1301 as the fabrication process progresses. Note that the structures shown in Figures 13A-13V, as well as Figure 13W, are not drawn to scale, and some features are shown at a disproportionately large size in order for those features to be visible in these figures.

[0115] As shown in FIG. 13A, the process for fabricating an electrically erasable programmable nonvolatile memory cell begins with a substrate 1302 having an insulator layer 1304 and a floating gate layer 1306 (e.g., tantalum nitride (TaN)) disposed thereon. FIG. 13A illustrates a cross-sectional view of a silicon substrate 1302, a dielectric layer 1304 (e.g., thermal silicon dioxide or low-trap silicon nitride), a floating gate layer 1306 (e.g., TaN), and a dielectric (e.g., oxide) layer 1308 (which may be referred to as a bond oxide / dielectric or a word line gate oxide / dielectric). In some embodiments, the TaN floating gate layer 1306 has a thickness of between eight angstroms and twenty angstroms (8 Å and 20 Å), e.g., 10 Å, within a ten percent (10%) tolerance. Because the dielectric layer 1304 is positioned between the floating gate layer 1306 and the substrate 1302, it is sometimes referred to as a floating gate oxide layer.

[0116] 13B, a series of additional layers 1310-1316 of the structure shown in FIG. 13A are then deposited, including a polysilicon layer 1310 (sometimes referred to as a poly2 layer or wordline layer), a stacked dielectric (e.g., oxide) layer 1312, a silicon nitride (e.g., SiN) layer 1314, and another dielectric (e.g., oxide) layer 1316 on top. In some embodiments, the dielectric layer 1316 serves to protect memory structural elements underneath the dielectric layer 1316 during subsequent processing.

[0117] As shown in FIG. 13C , using a mask 1320 and an appropriate etchant and process (e.g., an anisotropic etch), a trench 1322 is opened in the structure shown in FIG. 13B to remove portions of dielectric layer 1316, silicon nitride layer 1314, and stacked dielectric layer 1312 that are not protected by mask 1320. The etching operation shown in FIG. 13C stops at silicon nitride layer 1314. Note that reference numeral 1322 is used herein to identify a trench even though the shape (e.g., width and depth) of the trench may change during subsequent processing steps. At this early stage, "trench" 1322 is not yet truly a trench, as it has not yet extended into substrate 1302.

[0118] Next, as shown in Figure 13D, word line (WL) spacer (e.g., dielectric) material is deposited and etched back to form word line (WL) spacers 1324 on the outer vertical edges of trench 1322. As a result, trench 1322 becomes substantially narrower.

[0119] Next, as shown in FIG. 13E, using the WL spacers 1324 as a mask, an anisotropic etch 1326 (e.g., a polysilicon etch) is used to etch the polysilicon word line layer 1310, resulting in trenches 1322 separated from the substrate 1302 by the TaN floating gate layer 1306 and the floating gate oxide / dielectric 1304.

[0120] Next, as shown in Figures 13F and 13G, offset spacers 1328 (e.g., a dielectric material) are deposited and etched back (1330) to create narrower trenches 1322 (for ease of reference, the label 1322 continues to apply to "trench" even though the dimensions, including width and depth, of the trench may change as processing continues), and the offset spacers 1328 separate the word line layer 1310 from the trench. The boundary between the WL spacers 1324 and the offset spacers 1328 is shown with a dashed line. In some embodiments, the WL spacers 1324 and the offset spacers 1328 are formed from the same dielectric, e.g., silicon oxide.

[0121] Next, as shown in FIG. 13H, an etching operation 1332, e.g., an isotropic etch, removes the TaN layer 1306 at the bottom of the trench 1322, thereby forming an end (TaN tip) of the TaN layer 1306 facing the trench 1322 (e.g., the TaN tip 1333 is the portion of the TaN floating gate 150 (see FIG. 13W) formed from the TaN layer 1306 that is closest to the trench 1322).

[0122] Next, as shown in Figure 13I, a first tunnel oxide 1334 (e.g., a dielectric layer) is deposited in the trench 1322. Then, as shown in Figure 13J, an oxide etch (e.g., an anisotropic etch) operation is performed to extend the trench 1322 into the substrate while minimizing etching of the first tunnel oxide 1334. At this point, the TaN tip 1333 is separated from the trench 1322 by the first tunnel oxide 1334, while the word line layer 1310 is separated from the trench 1322 by the offset spacer 1328 and the first tunnel oxide 1334.

[0123] In some embodiments, the lateral thickness of the first tunnel oxide 1334 after completion of the etching operation of FIG. 13J is approximately 70 Å, within a 10-15 percent tolerance, and in some embodiments, has a thickness of 50 Å to 100 Å. As shown in FIG. 13W, the floating gate 150 (corresponding to the TaN layer 1306) covers the entire portion of the floating gate oxide 164 except for the portion nearest the trench 1322, sometimes referred to herein as the offset gap 1338. The presence of the offset gap 1338 in the memory cell increases the floating gate threshold voltage (e.g., the voltage of the floating gate 150 relative to the voltage of the substrate 102) required to allow the flow of at least a predetermined amount of current through the channel 190 beneath the floating gate oxide 1304 / 164 (e.g., the amount of current required to determine the state of the memory cell 1300 during a read operation) (see FIG. 13W).

[0124] Next, as shown in FIG. 13K, a trench implant operation is performed during which trench implant 1340 is introduced into the substrate below trench 1322 (e.g., into the region of substrate 102 below the bottom of trench 1322). In some embodiments, trench implant 1340 comprises an indium implant. The characteristics of trench implant 1340 are described above with respect to trench implant 302 (e.g., to determine or increase the threshold voltage at the trench bottom of channel 190).

[0125] Next, typically after trench implantation, a second tunnel oxide 1342 (e.g., a dielectric layer) is deposited in the trench 1322, as shown in FIG. 13L. At this point, the TaN tip 1333 is separated from the trench by both the first tunnel oxide 1334 and the second tunnel oxide 1342, while the word line layer 1310 is separated from the trench 1322 by the offset spacer 1328, the first tunnel oxide 1334, and the second tunnel oxide 1342. The dashed lines in FIG. 13L indicate the boundaries between the WL spacer 1324, the offset spacer 1328, the first tunnel oxide 1334, and the second tunnel oxide 1342. In some embodiments, the lateral thickness of the second tunnel oxide 1342 is approximately 80 Å within a 10-20 percent tolerance, and in some embodiments, has a thickness of 50 Å to 110 Å.

[0126] Next, as shown in Figure 13M, one or more conductive materials are deposited in trench 1322 to form the control gate. In some embodiments, the conductive material forming the control gate comprises polysilicon, and in some embodiments, comprises a metal such as titanium nitride and / or tungsten. Further, as shown in Figure 13M, an etching operation 1344 is performed to remove excess upper portions of the insulator layer and conductive material forming the control gate. Note that electrical connections to the control gate, for example to the control gates of other memory cell pairs in the same row of memory cells, are made using conductors that extend in directions not visible in the cross-sectional view of Figure 13M.

[0127] Next, as shown in Figure 13N, a dielectric material (e.g., oxide) is formed on top of the memory cell pairs and then planarized using, for example, chemical mechanical planarization (CMP). Thereafter, as shown in Figure 13O, the silicon nitride structure formed from silicon nitride layer 1314 is removed by etching 1348, resulting in the structure shown in Figure 13O. As shown in Figure 13P, a further etching operation 1350 removes portions of the word line, floating gate, and word line gate layers 1306, 1308, 1310 farthest from the control gate to form the structure shown in Figure 13P.

[0128] In Figure 13P, portions of the TaN layer 1306 and polysilicon layer 1310 are exposed, and these portions are covered with a dielectric layer 1352 deposited in a subsequent step to form a protective dielectric layer over the outer portions of the word lines and floating gates, as shown in Figure 13Q.

[0129] Next, as shown in FIG. 13R, a first spacer 1354 is added (e.g., deposited and then anisotropically etched) to the outer portion of the memory pair structure, followed by an oxide etching operation as shown in FIG. 13S, and then a second spacer is added (e.g., deposited and then anisotropically etched) to the outer portion of the memory pair structure as shown in FIG. 13T.

[0130] Next, as shown in Figure 13U, a deep halo implant operation 1360 is performed to add a dopant, such as indium, to the region of the substrate beneath the drain / source regions (bit line regions 104) of the two memory cells 1300, 1301. The characteristics of the deep halo implant 1360 are described above with respect to the deep halo implant 306.

[0131] Finally, bitline (e.g., N+) and LDD implant operations are performed to form the bitline and LDD regions of each memory cell 1300, 1301. The LDD implant is optional depending on the desired threshold level of the floating gate 150 (see FIG. 13W). Furthermore, as shown in FIG. 13W, the floating gate 150 (e.g., the remaining portion of the floating gate region 1306 after the etching operation shown in FIG. 13P) does not overlap the LDD region 105 of each memory cell 1300, 1301 (whether the “LDD region” 105 is implanted with N+ dopants or not), thereby forming an offset region in the substrate 102 between the source / drain (bitline) region 104 and the portion of the channel 190 covered by the floating gate 150. The LDD region 105 is sometimes referred to herein as the distal portion of the channel in an electrically erasable programmable nonvolatile memory cell that is furthest from the trench region and not covered by the floating gate 150.

[0132] In some embodiments, a method of fabricating an electrically erasable programmable non-volatile memory cell, such as the fabrication method illustrated by the sequence of FIGS. 12A-12V or the fabrication method illustrated by FIGS. 13A-13V, includes forming a base structure including a sequence of layers on a substrate, the sequence of layers including a floating gate layer separated from the substrate by a floating gate insulating layer, a word line layer separated from the floating gate layer by a dielectric layer, and one or more protection layers over the word line layer; 1) forming trenches through a sequence of layers to form electrically isolated portions of floating gate and word line layers, the portions including a first floating gate region and a first word line region for a first memory cell of a pair of memory cells, a second floating gate region and a second word line region for a second memory cell, and first and second protection regions positioned above the first and second word line regions for the first and second memory cells, respectively; 2) forming an offset spacer, a first tunnel oxide, and a second tunnel oxide, in that order, in the trench, such that portions of the first and second floating gate regions nearest the trench are separated from control gates formed in the trench by the first and second tunnel oxides, but not by the offset spacer, and such that the first and second word lines are separated from the trench by the offset spacer, the first and second tunnel oxides; 3) forming a control gate in the trench.

[0133] In some embodiments, in the aforementioned manufacturing methods, a portion of the trench extends into the substrate, and the second tunnel oxide, rather than the first tunnel oxide, extends into the portion of the trench that extends into the substrate.

[0134] In some embodiments, the aforementioned manufacturing method includes forming a conductive control gate in the trench, the conductive control gate being the control gate for both the first memory cell and the second memory cell of the pair of memory cells.

[0135] In some embodiments, in the aforementioned method of fabrication, the first tunnel oxide has a lateral thickness of less than 100 Å. Similarly, in some embodiments, in the aforementioned method of fabrication, the second tunnel oxide has a lateral thickness of less than 100 Å.

[0136] In some embodiments, the aforementioned manufacturing method includes forming a first indium implant in a region of the substrate below the bottom of the trench and forming a second indium implant in a region of the substrate adjacent to the source / drain region of the first memory cell and the source / drain region of the second memory cell.

[0137] Third Memory Cell Structure FIG. 13W illustrates a block diagram of a memory cell pair structure including electrically erasable programmable nonvolatile memory cells 1300 and 1301 resulting from the fabrication process described above. An example plan view of a memory cell array according to an embodiment using the memory cell pair structure of FIG. 13W is shown in FIG. 9. In some embodiments, memory cell 1300 includes the same elements as those described above for memory cell 1200, except that the floating gate (150) is formed from or comprises tantalum nitride (TaN) instead of polysilicon. The TaN floating gate typically has a thickness of between eight angstroms and twenty angstroms (8 Å and 20 Å), e.g., 10 Å, within a ten percent (10%) tolerance. Tip 1333 of the TaN floating gate (see FIG. 13H) comprises the portion of the TaN floating gate closest to the control gate and typically has the same thickness as the TaN floating gate, e.g., between 8 Å and 20 Å.

[0138] The above descriptions of the four-node and five-node implementations of memory cell pair 1200 / 1201 are equally applicable to memory cell pair 1300 / 1301, and the control voltages shown in Tables 1 and 2 above are equally applicable to memory cells 1300 and 1301, optionally with adjustments to account for the floating gate threshold voltage difference between tantalum nitride floating gates and polysilicon floating gates.

[0139] The foregoing description has been described with reference to specific implementations. However, the exemplary discussion above is not intended to be exhaustive or to limit the scope of the claims to the precise form disclosed. Many variations are possible in light of the above teachings, including memory device structures other than floating gates, such as charge trap memory device structures, or mask programmable read-only memories (mask ROMs). The embodiments were chosen and described to best explain the operating principles and practical applications, thereby enabling others skilled in the art.

[0140] The various figures show some elements in a particular order. However, elements that are not order-dependent may be rearranged, and other elements may be combined or separated. While some rearrangements or other groupings are specifically mentioned, other rearrangements or groupings will be apparent to those skilled in the art, and thus the rearrangements and groupings presented herein are not an exhaustive list of alternatives.

Claims

1. 1. An electrically erasable programmable non-volatile memory cell comprising: a semiconductor substrate having a bit line region, a surface region laterally spaced from the bit line region, and a trench region laterally spaced from the surface region, the trench region having a bottom and sidewalls adjacent to a trench in the semiconductor substrate; a conductive control gate, a first portion disposed within the trench, insulated from the bottom and sidewalls of the trench region of the substrate, and spaced a first distance (A) in the lateral direction from the sidewalls of the sidewalls of the trench region; a conductive control gate disposed over the trench and having a second portion extending away from the trench; a conductive word line insulated from the control gate and offset laterally from the second portion of the control gate by a second distance (B) greater than the first distance; a floating gate insulated from the substrate and the word line, the floating gate comprising: a first end including a portion of the floating gate closest to the control gate, the first end separated in the laterally direction from the second portion of the control gate by a third distance greater than the first distance and less than the second distance; An electrically erasable programmable nonvolatile memory cell having a second end self-aligned with an edge of the word line furthest from the second portion of the control gate.

2. the conductive word line is insulated from the control gate and offset from the second portion of the control gate by an insulator sequence comprising an offset spacer, a first tunnel oxide, and a second tunnel oxide, the insulator sequence separating the word line from the control gate in the lateral direction by the second distance greater than the first distance; 2. The electrically erasable programmable nonvolatile memory cell of claim 1, wherein the first end of the floating gate is separated from the second portion of the control gate by the first tunnel oxide and the second tunnel oxide, but not by the offset spacer.

3. 3. The electrically erasable programmable nonvolatile memory cell of claim 2, wherein said second tunnel oxide extends into said trench, but said first tunnel oxide does not extend into said trench.

4. a first indium implant disposed in a region of the substrate below the bottom of the trench region; 4. The electrically erasable programmable nonvolatile memory cell of claim 1, further comprising: a second indium implant disposed in a region of the substrate adjacent to a source or drain region of the memory cell.

5. the first indium implant produces a threshold voltage of a channel at the bottom of the trench region during a program operation to control a programming current of 100 nA at a control gate voltage between 1.6 V and 2.0 V; 5. The electrically erasable programmable nonvolatile memory cell of claim 4, wherein said floating gate is configured to reach a programmed state upon application of said programming current in 20 ns or less.

6. 6. The electrically erasable programmable nonvolatile memory cell of claim 4, wherein the first and second indium implants (i) reduce the punch-through current of unselected rows of memory cells to 10 pA or less, and (ii) make the read current insensitive to the program / erase state of mirror cells within a 10% tolerance.

7. 7. The electrically erasable programmable nonvolatile memory cell of claim 2, wherein the lateral extent of the first tunnel oxide corresponds to a portion of a channel in the substrate that is not covered by the floating gate and that extends from the bit line region of the substrate to the sidewall of the trench region.

8. 8. The electrically erasable programmable nonvolatile memory cell of claim 2, wherein a distal portion of the channel in the substrate, including a portion of the channel extending from the bit line region of the substrate to the sidewall portion of the trench region that is within the electrically erasable programmable nonvolatile memory cell and furthest from the trench region, is not covered by the floating gate.

9. 7. The electrically erasable programmable nonvolatile memory cell of claim 2, wherein an erase gate insulating region is disposed between the first end of the floating gate and the second portion of the control gate, the erase gate insulating region corresponding to portions of the first tunnel oxide and the second tunnel oxide disposed between the first end of the floating gate and the second portion of the control gate, and the erase gate insulating region has a thickness that enables tunneling of electrons from the first end of the floating gate to the second portion of the control gate during an erase operation.

10. 10. The electrically erasable programmable nonvolatile memory cell of claim 9, wherein an erase gate insulating region thickness is greater than 120 Å, allowing electron tunneling when 7V or less is applied between said control gate and said floating gate.

11. The electrically erasable programmable non-volatile memory cell of any one of claims 1 to 10, wherein the floating gate comprises tantalum nitride having a thickness of 10 Å to 20 Å.

12. 11. The electrically erasable programmable nonvolatile memory cell of claim 1, wherein the floating gate comprises polysilicon having a thickness of 200 Å to 400 Å, and the tip at the first end has a thickness of less than 20 Å.

13. The electrically erasable programmable non-volatile memory cell of any one of claims 1 to 12, wherein the control gate is configured to function as an erase gate during an erase operation.

14. 14. The electrically erasable programmable nonvolatile memory cell of claim 1, further comprising a floating gate insulating region disposed between the surface region of the substrate and the floating gate, the floating gate insulating region having a thickness that allows frontal injection of electrons traveling an upward path to the floating gate during a programming operation.

15. 15. The electrically erasable programmable nonvolatile memory cell of claim 1, wherein a word line potential of the word line, a control gate potential of the control gate, and a bit line potential of the bit line region are configured to allow electrons to move below the bottom of the trench region and then upward toward the floating gate during a program operation.

16. The electrically erasable programmable non-volatile memory cell of any one of claims 1 to 15, wherein the floating gate is configured to reach a programmed state in 20 ns or less during a programming operation.

17. the word line is electrically connected to a word line of a mirror memory cell; the electrically erasable programmable nonvolatile memory cell and the mirror memory cell form a four-node memory cell pair, the four nodes consisting of a source node, a drain node, a word line node, and a control / erase node; 6. The electrically erasable programmable nonvolatile memory cell of claim 1, wherein the word line node comprises an electrically connected word line, the control / erase node comprises the control gate shared by the electrically erasable programmable nonvolatile memory cell and the mirror memory cell, and the source or drain node comprises or is electrically connected to the bit line region of the electrically erasable programmable nonvolatile memory cell.

18. 1. An electrically erasable programmable non-volatile memory cell comprising: a semiconductor substrate having a bit line region, a surface region laterally spaced from the bit line region, and a trench region laterally spaced from the surface region, the trench region having a bottom and sidewalls adjacent to a trench in the semiconductor substrate; a conductive control gate, a first portion disposed within the trench, insulated from the bottom and sidewalls of the trench region of the substrate, and spaced a first distance (A) laterally from the sidewalls of the trench region; a conductive control gate disposed over the trench and having a second portion extending away from the trench; a conductive word line insulated from the control gate and offset laterally from the second portion of the control gate by a second distance (B) greater than the first distance; a conductive floating gate insulated from the substrate and the word line, the conductive floating gate comprising: a first end comprising a portion of the floating gate closest to the control gate; a second end self-aligned with an edge 132 of the word line furthest from the second portion of the control gate; a first indium implant disposed in a region of the substrate below the bottom of the trench region; a second indium implant disposed in a region of the substrate adjacent a bottom of a source or drain region of the memory cell.

19. 20. The electrically erasable programmable nonvolatile memory cell of claim 18, wherein the first end of the conductive floating gate includes a top and a bottom adjacent the top, the bottom of the floating gate extending in the lateral direction closer to the control gate than the top of the floating gate.

20. 20. The electrically erasable programmable nonvolatile memory cell of claim 18 or 19, wherein the second indium implant makes the read current insensitive to the programmed / erase state of the mirror cell within a 10% tolerance.

21. the word line is electrically connected to a word line of a mirror memory cell; the electrically erasable programmable nonvolatile memory cell and the mirror memory cell form a four-node memory cell pair, the four nodes consisting of a source node comprising or electrically connected to the bit line region of the electrically erasable programmable nonvolatile memory cell, a drain node connected to the bit line region of the mirror memory cell, a word line node, and a control / erase node comprising or electrically connected to the conductive control gate; 21. The electrically erasable programmable non-volatile memory cell of any one of claims 18 to 20, wherein the word line node comprises the electrically connected word line or is electrically connected to the electrically connected word line.

22. 1. A memory cell structure comprising: A mirrored pair of electrically erasable programmable non-volatile memory cells, each memory cell of the mirror pair includes a word line, a source / drain region, and a portion of a shared control / erase gate; the word lines of each memory cell of the mirror pair are electrically connected; and The mirror pair is a four-node memory cell pair, and the four nodes are: a source node including the source / drain region of a first memory cell of the mirror pair; a drain node including the source / drain region of a second memory cell of the mirror pair; a word line node including the electrically connected word line of each memory cell of the mirror pair; a control / erase node including the shared control / erase gate.

23. The memory cell structure of claim 22, wherein each memory cell of the mirror pair further comprises one or more of the features of any one of claims 1-21.

24. 1. A memory cell structure comprising: A mirrored pair of programmable non-volatile memory cells, each memory cell of the mirror pair includes a word line, a source / drain region, and a portion of a shared control gate; the word lines of each memory cell of the mirror pair are electrically connected; and The mirror pair is a four-node memory cell pair, and the four nodes are: a source node including the source / drain region of a first memory cell of the mirror pair; a drain node including the source / drain region of a second memory cell of the mirror pair; a word line node including the electrically connected word line of each memory cell of the mirror pair; a control node including the shared control gate.

25. 25. The memory cell structure of claim 24, wherein each memory cell of said mirror pair is a charge trapping type electrically erasable programmable memory cell.

26. 25. The memory cell structure of claim 24, wherein each memory cell of the mirror pair is a mask-programmable read-only memory cell.

27. 1. A method for fabricating an electrically erasable programmable non-volatile memory cell, comprising: after forming a base structure including a sequence of layers on a substrate, the sequence of layers including a floating gate layer separated from the substrate by a floating gate insulating layer, a word line layer separated from the floating gate layer by a dielectric layer, and one or more protection layers over the word line layer; forming trenches through the sequence of layers to form electrically isolated portions of the floating gate layer and the word line layer, the portions including a first floating gate region and a first word line region for a first memory cell of a pair of memory cells, a second floating gate region and a second word line region for a second memory cell, and first and second protection regions positioned above the first and second word line regions for the first and second memory cells, respectively; forming an offset spacer, a first tunnel oxide, and a second tunnel oxide, in that order, in the trench, such that portions of the first and second floating gate regions nearest the trench are separated from a control gate formed in the trench by the first and second tunnel oxides, rather than the offset spacer, and such that the first and second word lines are separated from the control gates by the offset spacer, the first and second tunnel oxides; forming the control gate in the trench.

28. 28. The method of claim 27, wherein a portion of the trench extends into the substrate, and the second tunnel oxide but not the first tunnel oxide extends into the portion of the trench that extends into the substrate.

29. 29. The method of claim 27 or 28, comprising forming a conductive control gate in the trench, the conductive control gate being a control gate for both the first memory cell and the second memory cell of the pair of memory cells.

30. The method of any one of claims 27 to 29, wherein the first tunnel oxide has a lateral thickness of less than 100 Å.

31. The method of any one of claims 27 to 30, wherein the second tunnel oxide has a lateral thickness of less than 100 Å.

32. forming a first indium implant in a region of the substrate below a bottom of the trench; forming a second indium implant in a region of the substrate adjacent to the source / drain region of the first memory cell and the source / drain region of the second memory cell; The method of any one of claims 27 to 30, comprising:

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