Output block for vector multiplication array with matrix of non-volatile memory cells

Abstract

The system comprises a vector × matrix multiplication array of nonvolatile memory cells arranged in rows and columns, the array comprising a first bit line coupled to a first column of nonvolatile memory cells and a second bit line coupled to a second column of nonvolatile memory cells; and an output block coupled to the array, the output block comprising a current-voltage converter for converting a first current on the first bit line to a first voltage and a second current on the second bit line to a second voltage, and an analog-to-digital converter for converting one or more of the first voltage and the second voltage into a set of output bits.

Description

[Technical Field]

[0001] (Claiming priority) This application claims priority to U.S. Provisional Patent Application No. 63 / 446,210, “Output Block for Neural Network Array,” filed on 16 February 2023, and U.S. Patent Application No. 18 / 195,322, “Output Block for Array of Non-Volatile Memory Cells,” filed on 9 May 2023.

[0002] (Field of Invention) Numerous examples of output blocks for arrays of non-volatile memory cells are disclosed. [Background technology]

[0003] Artificial neural networks mimic biological neural networks (such as the central nervous system of animals, particularly the brain), can depend on a large number of inputs, and are generally used to estimate or approximate unknown functions. Artificial neural networks typically consist of layers of interconnected "neurons" that exchange messages with one another.

[0004] Figure 1 shows an artificial neural network, where circles represent the inputs or layers of neurons. Connections (called synapses) are represented by arrows and have numerical weights that can be tuned based on experience. This allows the neural network to adapt to inputs and learn. Typically, a neural network contains multiple input layers. Typically, there are one or more hidden layers of neurons and output layers of neurons that provide the output of the neural network. Neurons at each level make decisions individually or collectively based on the data they receive from synapses.

[0005] One of the major challenges in developing artificial neural networks for high-performance information processing is the lack of suitable hardware technology. In fact, practical neural networks rely on a very large number of synapses, which enables high connectivity between neurons and thus very high levels of parallel processing. In principle, such complexity can be achieved with digital supercomputers or dedicated graphics processing unit clusters. However, in addition to their high cost, these approaches also suffer from poor energy efficiency compared to biological networks, which consume far less energy because they primarily perform low-precision analog calculations. While CMOS analog circuits have been used in artificial neural networks, the synapses in most CMOS implementations are too large considering the large number of neurons and synapses.

[0006] The applicant previously disclosed, in U.S. Patent Application Publication No. 2017 / 0337466(A1), incorporated by reference, an artificial (analog) neural network utilizing one or more non-volatile memory arrays as synapses. The non-volatile memory arrays operate as analog neural memory and comprise non-volatile memory cells arranged in rows and columns. The neural network device includes a first plurality of synapses configured to receive a first plurality of inputs and therefrom produce a first plurality of outputs, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses comprises a plurality of memory cells, each of which includes spaced source and drain regions formed in a semiconductor substrate, with a channel region extending between them, a floating gate insulated and disposed above a first portion of the channel region, and a non-floating gate insulated and disposed above a second portion of the channel region. Each of the plurality of memory cells stores weight values ​​corresponding to the number of electrons on the floating gate. The plurality of memory cells generate a first plurality of outputs by multiplying the first plurality of inputs by the stored weight values. <Non-volatile membrane>

[0007] Non-volatile memory is well known. For example, U.S. Patent No. 5,029,130 ​​("Patent No. 130"), incorporated herein by reference, discloses an array of split-gate non-volatile memory cells, a type of flash memory cell. Such a memory cell 210 is shown in Figure 2. Each memory cell 210 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 between the source region 14 and the drain region 16. A floating gate 20 is formed insulated above a first portion of the channel region 18 (and controlling the conductivity of the first portion of the channel region 18) and extends above a portion of the source region 14. A word line terminal 22 (typically coupled to a word line) has a first portion positioned above a second portion of the channel region 18 and insulated from (and controlling the conductivity of) the second portion, and a second portion extending above the floating gate 20. The floating gate 20 and the word line terminal 22 are insulated from the substrate 12 by a gate oxide. Bit line 24 is connected to drain region 16.

[0008] By applying a positive high voltage to the word line terminal 22, the memory cell 210 is erased (electrons are removed from the floating gate), causing the electrons on the floating gate 20 to pass through the intermediate insulator from the floating gate 20 to the word line terminal 22 via a Fowler-Nordheim (FN) tunnel.

[0009] The memory cell 210 is programmed by source-side injection (SSI) with hot electrons by applying a positive voltage to the word line terminal 22 and a positive voltage to the source region 14 (electrons are added to the floating gate). The electron flow flows from the drain region 16 towards the source region 14. The electrons are accelerated and generate heat when they reach the gap between the word line terminal 22 and the floating gate 20. Some of the heated electrons are injected into the floating gate 20 via the gate oxide due to the electrostatic attraction from the floating gate 20.

[0010] The memory cell 210 is read by applying a positive read voltage to the drain region 16 and the word line terminal 22 (turning on the portion of the channel region 18 below the word line terminal). When the floating gate 20 is positively charged (i.e., electrons are erased), the portion of the channel region 18 below the floating gate 20 is also turned on, and current flows through the channel region 18, which is detected as the erased state, i.e., the "1" state. When the floating gate 20 is negatively charged (i.e., programmed with electrons), the portion of the channel region below the floating gate 20 becomes almost or completely off, and current does not flow (or hardly flows) through the channel region 18, which is detected as the programmed state, i.e., the "0" state.

[0011] Table 1 shows the typical voltage / current ranges that can be applied to the terminals of the memory cell 210 to perform read, erase, and program operations. Table 1: Operation of the flash memory cell 210 in FIG. 2 [Table 1]

[0012] Other split-gate type memory cell configurations, which are other types of flash memory cells, are also known. For example, FIG. 3 shows a four-gate memory cell 310 including a source region 14, a drain region 16, a floating gate 20 above a first portion of a channel region 18, a select gate 22 (typically coupled to a word line WL) above a second portion of the channel region 18, a control gate 28 above the floating gate 20, and an erase gate 30 above the source region 14. This configuration is described in U.S. Patent No. 6,747,310, which is hereby incorporated by reference for all purposes. Here, all gates except the floating gate 20 are non-floating gates, that is, they are electrically connected or connectable to a voltage source. Programming is performed by injecting the electrons themselves from the channel region 18 into the floating gate 20 by the heated electrons. Erasing is performed by tunneling of electrons from the floating gate 20 to the erase gate 30.

[0013] Table 2 shows typical voltage / current ranges that can be applied to the terminals of the memory cell 310 to perform read, erase, and program operations. Table 2: Operation of the Flash Memory Cell 310 of FIG. 3 [Table 2]

[0014] FIG. 4 shows a three-gate memory cell 410, which is another type of flash memory cell. The memory cell 410 is identical to the memory cell 310 of FIG. 3 except that the memory cell 410 does not have a separate control gate. (Erasing occurs through the use of the erase gate) The erase operation and the read operation are the same as those of FIG. 3 except that no control gate bias is applied. The programming operation is also performed without a control gate bias. As a result, during the programming operation, a higher voltage is applied to the source line to compensate for the lack of control gate bias.

[0015] Table 3 shows typical voltage / current ranges that may be applied to the terminals of the memory cell 410 to perform read, erase, and program operations. Table 3: Operation of flash memory cell 410 in Figure 4 [Table 3]

[0016] Figure 5 shows another type of flash memory cell, a stacked gate memory cell 510. Memory cell 510 is similar to memory cell 210 in Figure 2, except that the floating gate 20 extends above the entire channel region 18, and the control gate 22 (coupled here to the word line) extends above the floating gate 20, separated by an insulating layer (not shown). Erase is performed by FN tunneling of electrons from the FG to the substrate, programming is performed by channel hot electron (CHE) injection in the region between the channel 18 and the drain region 16, and read operation is performed by electrons flowing from the source region 14 to the drain region 16, similar to the read operation of memory cell 210, which has a higher control gate voltage.

[0017] Table 4 shows typical voltage ranges that can be applied to the terminals of the memory cell 510 and the circuit board 12 for performing read, erase, and program operations. Table 4: Operation of flash memory cell 510 in Figure 5 [Table 4]

[0018] The methods and means described herein may be applied to other non-volatile memory technologies, including but not limited to FINFET split-gate flash or stack-gate flash memory, NAND flash, SONOS (silicon-oxide-nitride-oxide-silicon, charge trap in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge trap in nitride), ReRAM (resistive random-access memory), PCM (phase change memory), MRAM (magnetic random-access memory), FeRAM (ferroelectric random-access memory), CT (charge trap) memory, CN (carbon-tube) memory, OTP (one-time programmable, bi-level or multi-level), and CeRAM (correlated electron random-access memory).

[0019] Two modifications are made to utilize a memory array containing one of the non-volatile memory cell types in the artificial neural network described above. First, lines are configured to allow each memory cell to be programmed, erased, and read individually without adversely affecting the memory state of other memory cells in the array, as will be further described below. Second, sequential (analog) programming of the memory cells is provided.

[0020] Specifically, the memory state of each memory cell in the array (i.e., the charge on the floating gate) can be changed independently and continuously, with minimal disturbance to other memory cells, from a completely erased state to a fully programmed state, and vice versa. This means that cell memory is essentially analog, or can store at least one of a large number of discontinuous values ​​(such as 16 or 64 different values), making every memory cell in the memory array highly precise and individually tunable, and the memory array becomes ideal for memory and fine-tuning of synaptic weights in neural networks. <Neural networks using non-volatile memory cell arrays>

[0021] Figure 6 conceptually illustrates an unrestricted example of a neural network utilizing a non-volatile memory array in this example. While this example uses a non-volatile memory array neural network for a facial recognition application, it is also possible to implement other suitable applications using a non-volatile memory array-based neural network.

[0022] S0 is the input layer, which in this example is a 32x32 pixel RGB image with 5-bit precision (i.e., three 32x32 pixel arrays, one for each color R, G, and B, with each pixel having 5-bit precision). The synapse CB1, going from input layer S0 to layer C1, scans the input image with a 3x3 pixel overlapping filter (kernel), applying different weight sets to some instances and shared weights to others, and shifts the filter by one pixel (or more than one pixel depending on the model). Specifically, the values ​​of nine pixels in the 3x3 portion of the image (i.e., referred to as the filter or kernel) are provided to synapse CB1, where these nine input values ​​are multiplied by appropriate weights, and after adding the outputs of the multiplications, a single output value is determined, which is then given by the first synapse of CB1 to generate one of the pixels in the feature map of layer C1. The 3x3 filter is then shifted one pixel to the right within the input layer S0 (i.e., a column of 3 pixels is added to the right and a column of 3 pixels is dropped to the left), thereby providing the 9 pixel values ​​of this newly positioned filter to synapse CB1, where they are multiplied by the same weights as above, determining a second single output value by the associated synapse. This process continues until the 3x3 filter scans the entire 32x32 pixel image of the input layer S0 for all three colors and all bits (precision values). The process is then repeated with different weight sets to generate different feature maps of layer C1 until all feature maps of layer C1 have been computed.

[0023] In this example, layer C1 contains 16 feature maps, each having 30x30 pixels. Each pixel is a new feature pixel extracted from the multiplication of the input and the kernel; therefore, each feature map is a two-dimensional array, and thus in this example, layer C1 constitutes 16 layers of two-dimensional arrays (note that the layers and arrays referred to herein are logical relationships, not necessarily physical relationships; i.e., arrays are not necessarily oriented to physical two-dimensional arrays). Each of the 16 feature maps in layer C1 is generated by one of 16 different synaptic weight sets applied to the filtered scan. All C1 feature maps can target different aspects of the same image feature, such as boundary identification. For example, a first map (generated using a first weight set shared across all scans used to generate this first map) can identify circular edges, a second map (generated using a second weight set different from the first) can identify rectangular edges or the aspect ratio of a particular feature, and so on.

[0024] Before moving from layer C1 to layer S1, an activation function P1 (pooling) is applied that pools values ​​from non-overlapping, consecutive 2x2 regions within each feature map. The purpose of the pooling function P1 is to average neighbor positions (or use the max function), for example, to reduce dependence on edge positions, and to reduce the data size before moving to the next stage. In layer S1, there are 16 15x15 feature maps (i.e., 16 different arrays, each 15x15 pixels). Synapse CB2, moving from layer S1 to layer C2, scans the maps in layer S1 with a 4x4 filter, shifting by 1 pixel. In layer C2, there are 22 12x12 feature maps. Before moving from layer C2 to layer S2, an activation function P2 (pooling) is applied that pools values ​​from non-overlapping, consecutive 2x2 regions within each feature map. In layer S2, there are 22 6x6 feature maps. At synapse CB3, which goes from layer S2 to layer C3, an activation function (pooling) is applied, where all neurons in layer C3 are connected to all maps in layer S2 via each synapse of CB3. There are 64 neurons in layer C3. Synapse CB4, which goes from layer C3 to output layer S3, completely connects C3 to S3; that is, all neurons in layer C3 are connected to all neurons in layer S3. The output in S3 contains 10 neurons, where the neuron with the highest output determines the class. This output can, for example, indicate the identification or classification (classification) of the content of the original image.

[0025] Each layer of a synapse is implemented using an array or a portion of an array of non-volatile memory cells.

[0026] Figure 7 is a block diagram of an array that can be used for that purpose. The vector-by-matrix multiplication (VMM) array 32 contains non-volatile memory cells and is used as synapses between one layer and the next (e.g., CB1, CB2, CB3, and CB4 in Figure 6). Specifically, the VMM array 32 includes an array of non-volatile memory cells 33, erase gate and word line gate decoders 34, a control gate decoder 35, a bit line decoder 36, and a source line decoder 37, each of which decoders decodes its respective input to the non-volatile memory cell array 33. Input to the VMM array 32 can be from the erase gate and word line gate decoder 34 or from the control gate decoder 35. In this example, the source line decoder 37 also decodes the output of the non-volatile memory cell array 33. Alternatively, the bit line decoder 36 can decode the output of the non-volatile memory cell array 33.

[0027] The non-volatile memory cell array 33 serves two purposes. First, it stores the weights used by the VMM array 32. Second, the non-volatile memory cell array 33 effectively multiplies the weights stored in the non-volatile memory cell array 33 by the inputs and adds them together for each output line (source line or bit line) to generate an output, which becomes the input to the next layer or the last layer. By having the non-volatile memory cell array 33 perform the multiplication and addition functions, the need for separate multiplication and addition logic circuits is eliminated, and the calculations are more power-efficient due to being performed in memory.

[0028] The output of the non-volatile memory cell array 33 is fed to a differential adder (such as an adding operational amplifier or adding current mirror) 38, which adds the outputs of the non-volatile memory cell array 33 to create a single value for its convolution. The differential adder 38 is configured to perform the summation of positive and negative weights.

[0029] The summed output values ​​of the differential adder 38 are then fed to an activation function block 39, which normalizes the output. The activation function block 39 may provide a sigmoid, tanh, or ReLU function. The normalized output values ​​of the activation function block 39 become elements of a feature map as the next layer (e.g., C1 in Figure 6), and are then applied to the next synapse to generate the next feature map layer or the final layer. Thus, in this example, the non-volatile memory cell array 33 constitutes multiple synapses (receiving input from the previous layer of the neuron or from an input layer such as an image database), and the summation amplifier 38 and activation function block 39 constitute multiple neurons.

[0030] The inputs to the VMM array 32 in Figure 7 (WLx, EGx, CGx, and optionally BLx and SLx) can be analog level, binary level, or digital bits (in which case a DAC is provided to convert the digital bits to the appropriate input analog level), and the outputs can be analog level, binary level, or digital bits (in which case an output ADC is provided to convert the output analog level to the digital bits).

[0031] Figure 8 is a block diagram showing the use of multiple layers of the VMM array 32, labeled in the figure as VMM arrays 32a, 32b, 32c, 32d, and 32e. As shown in Figure 8, the input (indicated as Inputx) is converted from digital to analog by the digital-to-analog converter 31 and provided to the input VMM array 32a. The converted analog input can be voltage or current. Input D / A conversion of the first layer can be performed by using a function or LUT (look-up table) that maps the input Inputx to the appropriate analog level of the matrix multiplier of the input VMM array 32a. Input conversion can also be performed by an analog-to-analog (A / A) converter to convert an external analog input to the mapped analog input to the input VMM array 32a.

[0032] The output generated by input VMM array 32a is provided as input to the next VMM array (hidden level 1) 32b, the next VMM array (hidden level 1) 32b generates an output that is provided as input to the next input VMM array (hidden level 2) 32c, and so on. The various layers of VMM array 32 function as the synapses and neurons of a convolutional neural network (CNN). Each VMM array 32a, 32b, 32c, 32d, and 32e can be a standalone physical non-volatile memory array, or multiple VMM arrays can utilize different parts of the same physical non-volatile memory array, or multiple VMM arrays can utilize overlapping parts of the same physical non-volatile memory array. The example shown in Figure 8 includes five layers (32a, 32b, 32c, 32d, 32e), namely one input layer (32a), two hidden layers (32b, 32c), and two fully connected layers (32d, 32e). Those skilled in the art will understand that this is merely an example, and that a system could instead include more than two hidden layers and more than two fully connected layers. <Vector × Matrix Multiplication (VMM) Array>

[0033] Figure 9 shows a neuron VMM array 900, which is particularly suitable for the memory cell 310 shown in Figure 3 and is used as part of a synapse and neuron between the input layer and the next layer. The VMM array 900 includes a memory array 901 of non-volatile memory cells and a reference array 902 of non-volatile reference memory cells (located at the top of the array). Alternatively, another reference array may be located at the bottom.

[0034] In the VMM array 900, control gate lines such as control gate line 903 extend vertically (thus the row-direction reference array 902 is perpendicular to the control gate line 903), and erase gate lines such as erase gate line 904 extend horizontally. Here, inputs to the VMM array 900 are provided to the control gate lines (CG0, CG1, CG2, CG3), and outputs of the VMM array 900 appear on the source lines (SL0, SL1). In one example, only even rows are used, and in another example, only odd rows are used. The current on each source line (SL0, SL1, respectively) performs the function of summing all currents from memory cells connected to that particular source line.

[0035] As described herein with respect to neural networks, the non-volatile memory cells of the VMM array 900, i.e., the memory cells 310 of the VMM array 900, may be configured to operate selectively in a region below a threshold.

[0036] The non-volatile reference memory cells and non-volatile memory cells described herein are biased with weak inversion (in the region below the threshold) as follows: Ids = Io × e (Vg-Vth) / nVt =w × Io × e (Vg) / nVt , In the formula, w=e (-Vth) / nVt And, Ids is the drain-source current, Vg is the gate voltage on the memory cell, Vth is the threshold voltage of the memory cell, Vt is the thermal voltage = k × T / q, where k is Boltzmann's constant, T is the Kelvin temperature, q is the electron charge, n is the gradient coefficient = 1 + (Cdep / Cox), where Cdep is the capacitance of the depletion layer, and Cox is the capacitance of the gate oxide layer, Io is the memory cell current at a gate voltage equal to the threshold voltage, and Io is (Wt / L) × u ​​× Cox × (n-1) × Vt 2 It is proportional to , where u is the carrier mobility, and Wt and L are the width and length of the memory cell, respectively.

[0037] When using an IV logarithmic converter that converts input current to input voltage using a memory cell (such as a reference memory cell or peripheral memory cell) or transistor: Vg = n × Vt × log[Ids / wp × Io] In the formula, wp is the w of the reference or peripheral memory cell.

[0038] For a memory array used as a vector × matrix multiplier VMM array with current input, the output current is as follows: Iout=wa×Io×e (Vg) / nVt That is to say Iout = (wa / wp) × Iin = W × Iin W=e (Vthp-Vtha) / nVt Here, wa = w of each memory cell in the memory array. Vthp is the effective threshold voltage of the peripheral memory cell, and Vtha is the effective threshold voltage of the main (data) memory cell. Note that the threshold voltage of a transistor is a function of the substrate bias voltage, and the substrate bias voltage, denoted as Vsb, can be modulated to compensate for various conditions at such temperatures. The threshold voltage Vth can be expressed as follows:

number

number

[0039] Word lines or control gates can be used as inputs to memory cells for input voltage.

[0040] Alternatively, the flash memory cells of the VMM array described herein can be configured to operate in a linear region. Ids=beta×(Vgs-Vth)×Vds, beta=u×Cox×Wt / L W = α(Vgs - Vth) That is, the weight W in the linear region is proportional to (Vgs - Vth).

[0041] The word line or control gate or bit line or source line can be used as an input to a memory cell operating within the linear region. The bit line or source line can be used as an output of the memory cell.

[0042] For an I-V linear converter, an input-output current can be linearly converted to an input-output voltage using a memory cell (such as a reference memory cell or a peripheral memory cell) or a transistor operating in the linear region.

[0043] Alternatively, the memory cells of the VMM array described herein can be configured to operate in the saturation region. Ids = 1 / 2 × beta × (Vgs - Vth) 2 , beta = u × Cox × Wt / L W α(Vgs - Vth) 2 , that is, the weight W is 2 proportional to (Vgs - Vth).

[0044] The word line, control gate, or erase gate can be used as an input to a memory cell operating within the saturation region. The bit line or source line can be used as an output of the output neuron.

[0045] Alternatively, the memory cells of the VMM array described herein can be used in all regions or combinations thereof (below threshold, linear, or saturation) for each layer or multiple layers of a neural network.

[0046] Another example for the VMM array 32 of FIG. 7 is described in U.S. Patent No. 10,748,630, which is incorporated herein by reference. As described in the above application, the source line or bit line can be used as a neuron output (current sum output).

[0047] Figure 10 shows a neuron VMM array 1000, particularly suited to the memory cell 210 shown in Figure 2 and used as a synapse between the input layer and the next layer. The VMM array 1000 includes a memory array 1003 of non-volatile memory cells, a reference array 1001 of a first non-volatile reference memory cell, and a reference array 1002 of a second non-volatile reference memory cell. The reference arrays 1001 and 1002, arranged in the column direction of the array, function to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs WL0, WL1, WL2, and WL3. In practice, the first and second non-volatile reference memory cells are diode-connected through a multiplexer 1014 (partially shown) with current inputs flowing in. The reference cells are tuned (e.g., programmed) to a target reference level. The target reference level is provided by a reference miniarray matrix (not shown).

[0048] The memory array 1003 serves two purposes. First, it stores the weights used by the VMM array 1000 in each memory cell. Second, the memory array 1003 effectively multiplies the weights stored in it by the inputs (i.e., the current inputs supplied to terminals BLR0, BLR1, BLR2, and BLR3, which are converted into input voltages by the reference arrays 1001 and 1002 and supplied to word lines WL0, WL1, WL2, and WL3), then adds all the results (memory cell currents) to generate outputs on each bit line (BL0~BLN), which become inputs to the next layer or the last layer. By performing multiplication and addition functions, the memory array 1003 eliminates the need for separate multiplication and addition logic circuits and is also power efficient. Here, voltage inputs are supplied to word lines WL0, WL1, WL2, and WL3, and outputs appear on the respective bit lines BL0 to BLN during the read (inference) operation. Each current in bit lines BL0 to BLN performs the function of summing the currents from all non-volatile memory cells connected to that particular bit line.

[0049] Table 5 shows the operating voltages and currents of the VMM array 1000. The columns in the table show the voltages applied to the word lines of selected cells, word lines of unselected cells, bit lines of selected cells, bit lines of unselected cells, source lines of selected cells, and source lines of unselected cells. The rows show the read, erase, and program operations. Table 5: Operation of VMM Array 1000 in Figure 10 [Table 5]

[0050] Figure 11 shows a neuron VMM array 1100, which is particularly suitable for the memory cell 210 shown in Figure 2 and is used as part of a synapse and neuron between the input layer and the next layer. The VMM array 1100 includes a memory array 1103 of non-volatile memory cells, a reference array 1101 of a first non-volatile reference memory cell, and a reference array 1102 of a second non-volatile reference memory cell. The reference arrays 1101 and 1102 extend in the row direction of the VMM array 1100. The VMM array is similar to the VMM 1000, except that the word lines in the VMM array 1100 extend vertically. Here, inputs are provided to the word lines (WLA0, WLB0, WLA1, WLB2, WLA2, WLB2, WLA3, WLB3), and outputs appear on the source lines (SL0, SL1) during read operations. The current on each source line performs the function of summing all the currents from the memory cells connected to that particular source line.

[0051] Table 6 shows the operating voltages and currents of the VMM array 1100. The columns in the table show the voltages applied to the word lines of selected cells, word lines of unselected cells, bit lines of selected cells, bit lines of unselected cells, source lines of selected cells, and source lines of unselected cells. The rows show the read, erase, and program operations. Table 6: Operation of VMM Array 1100 in Figure 11 [Table 6]

[0052] Figure 12 shows a neuron VMM array 1200, which is particularly suitable for the memory cell 310 shown in Figure 3 and is used as part of a synapse and neuron between the input layer and the next layer. The VMM array 1200 includes a memory array 1203 of non-volatile memory cells, a reference array 1201 of a first non-volatile reference memory cell, and a reference array 1202 of a second non-volatile reference memory cell. The reference arrays 1201 and 1202 function to convert the current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs CG0, CG1, CG2, and CG3. In practice, the first and second non-volatile reference memory cells are diode-connected through a multiplexer 1212 (partially shown) with current inputs flowing through BLR0, BLR1, BLR2, and BLR3. Each multiplexer 1212 includes a separate multiplexer 1205 and a cascoding transistor 1204 to ensure that the respective bit lines (such as BLR0) of the first and second non-volatile reference memory cells maintain a constant voltage during read operations. The reference cells are tuned to a target reference level.

[0053] The memory array 1203 serves two purposes. First, it stores the weights used by the VMM array 1200. Second, the memory array 1203 effectively multiplies the weights stored in the memory array by the inputs (current inputs supplied to terminals BLR0, BLR1, BLR2, and BLR3, which the reference arrays 1201 and 1202 convert into input voltages and supply to the control gates (CG0, CG1, CG2, and CG3)), then adds all the results (cell currents) to produce an output, which appears in BL0~BLN and becomes the input to the next layer or the last layer. By having the memory array perform the multiplication and addition functions, the need for separate multiplication and addition logic circuits is eliminated, and power efficiency is also improved. Here, the inputs are provided to the control gate lines (CG0, CG1, CG2, and CG3), and the output appears in the bit lines (BL0~BLN) during read operations. The current in each bit line performs the function of adding up all the currents from the memory cells connected to that particular bit line.

[0054] The VMM array 1200 implements one-way tuning of non-volatile memory cells within the memory array 1203. That is, each non-volatile memory cell is erased and then partially programmed until the desired charge on the floating gate is reached. If too much charge is applied to the floating gate (resulting in an incorrect value being stored in the cell), the cell is erased and the series of partial programming operations is restarted from the beginning. As shown, two rows sharing the same erase gate (such as EG0 or EG1) are erased together (also referred to as page erase), and then each cell is partially programmed until the desired charge on the floating gate is reached.

[0055] Table 7 shows the operating voltages and currents of the VMM array 1200. The columns in the table show the voltages applied to the word lines of selected cells, word lines of unselected cells, bit lines of selected cells, bit lines of unselected cells, control gates of selected cells, control gates of unselected cells in the same sector as the selected cell, control gates of unselected cells in a different sector than the selected cell, erase gates of selected cells, erase gates of unselected cells, source lines of selected cells, and source lines of unselected cells. The rows show the read, erase, and program operations. Table 7: Operation of VMM Array 1200 in Figure 12 [Table 7]

[0056] Figure 13 shows a neuron VMM array 1300, which is particularly suitable for the memory cell 310 shown in Figure 3 and is used as part of a synapse and neuron between the input layer and the next layer. The VMM array 1300 comprises a memory array 1303 of nonvolatile memory cells, a reference array 1301 or a first nonvolatile reference memory cell, and a reference array 1302 of a second nonvolatile reference memory cell. The EG lines EGR0, EG0, EG1, and EGR1 extend vertically, and the CG lines CG0, CG1, CG2, and CG3 and the SL lines WL0, WL1, WL2, and WL3 extend horizontally. The VMM array 1300 is similar to the VMM array 1400 except that the VMM array 1300 implements bidirectional tuning, and each individual cell can be completely erased, partially programmed, and partially erased as needed to reach a desired amount of charge on the floating gate by using individual EG lines. As shown, reference arrays 1301 and 1302 convert the input currents at terminals BLR0, BLR1, BLR2, and BLR3 into control gate voltages CG0, CG1, CG2, and CG3 (through the action of diode-connected reference cells via multiplexer 1314), and these voltages are applied to memory cells in the row direction. Current outputs (neurons) are located in the bit lines BL0~BLN, and each bit line sums all the currents from the non-volatile memory cells connected to that particular bit line.

[0057] Table 8 shows the operating voltages and currents of the VMM array 1300. The columns in the table show the voltages applied to the word lines of selected cells, word lines of unselected cells, bit lines of selected cells, bit lines of unselected cells, control gates of selected cells, control gates of unselected cells in the same sector as the selected cell, control gates of unselected cells in a different sector than the selected cell, erase gates of selected cells, erase gates of unselected cells, source lines of selected cells, and source lines of unselected cells. The rows show the read, erase, and program operations. Table 8: Operation of VMM Array 1300 in Figure 13 [Table 8]

[0058] Figure 14 shows a VMM array 1400 that is particularly suitable for the memory cell 210 shown in Figure 2 and is used as part of the synapses and neurons between the input layer and the next layer. In the VMM array 1400, inputs INPUT0...., INPUT N These are bit lines BL0, ...BL, respectively. N The signal is received, and outputs OUTPUT1, OUTPUT2, OUTPUT3, and OUTPUT4 are generated on source lines SL0, SL1, SL2, and SL3, respectively.

[0059] Figure 15 shows a VMM array 1500 that is particularly suitable for the memory cell 210 shown in Figure 2 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, INPUT1, INPUT2, and INPUT3 are received by source lines SL0, SL1, SL2, and SL3, respectively, and outputs OUTPUT0, .....OUTPUT N These are bit lines BL0, ..., BL N It is generated by [this method].

[0060] Figure 16 shows a VMM array 1600 that is particularly suitable for the memory cell 210 shown in Figure 2 and is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M These are the word lines WL0, ..., WL, respectively. M Received by, output OUTPUT0, ...OUTPUT N These are bit lines BL0, ..., BL N It is generated by [this method].

[0061] Figure 17 shows a VMM array 1700 that is particularly suitable for the memory cell 310 shown in Figure 3 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M These are the word lines WL0, ..., WL, respectively. M Received by, output OUTPUT0, ...OUTPUT N These are bit lines BL0, ..., BL N It is generated by [this method].

[0062] Figure 18 shows a VMM array 1800 that is particularly suitable for the memory cell 410 shown in Figure 4 and is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT n However, each of them is a vertical control gate line CG0, ..., CG N The signal is received, and outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0063] Figure 19 shows a VMM array 1900 that is particularly suitable for the memory cell 410 shown in Figure 4 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, the inputs are INPUT0, ..., INPUT N These are bit lines BL0, ..., BL, respectively. NThe bit line control gates 1901-1, 1901-2, ..., 1901-(N-1) and 1901-N, which are coupled to the bit line control gates, are received by the gates. Exemplary outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0064] Figure 20 shows a VMM array 2000 that is particularly suitable for the memory cell 310 shown in Figure 3, the memory cell 510 shown in Figure 5, and the memory cell 710 shown in Figure 7, and is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M These are the word lines WL0, ..., WL, respectively. M Received by, output OUTPUT0, ..., OUTPUT N These are bit lines BL0, ..., BL N It is generated in [location].

[0065] Figure 21 shows a VMM array 2100 that is particularly suitable for the memory cell 310 shown in Figure 3, the memory cell 510 shown in Figure 5, and the memory cell 710 shown in Figure 7, and is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M These are control gate lines CG0, ..., CG M It is received as follows. Output OUTPUT0, ..., OUTPUT N These are the vertical source lines SL0, ..., SL, respectively. N It is generated in each source line SL i It is coupled to the source lines of all memory cells in column i.

[0066] Figure 22 shows a VMM array 2200 that is particularly suitable for the memory cell 310 shown in Figure 3, the memory cell 510 shown in Figure 5, and the memory cell 710 shown in Figure 7, and is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M These are control gate lines CG0, ..., CG MIt is received as follows. Output OUTPUT0, ..., OUTPUT N These are the vertical bit lines BL0, ..., BL N Generated in each bit line BL i It is coupled to the bit lines of all memory cells in column i.

[0067] The input to the VMM array may be analog level, binary level, pulse, time-modulated pulse, or digital bit (in which case a DAC is used to convert the digital bit to an appropriate input analog level), and the output may be analog level, binary level, timing pulse, pulse, or digital bit (in which case an output ADC is used to convert the output analog level to a digital bit).

[0068] Typically, for each memory cell in a VMM array, each weight W can be implemented by a single memory cell, a differential cell, or two blended memory cells (the average of two cells). In the case of a differential cell, two memory cells are used to implement the weight W as a differential weight (W = W+-W-). In the case of two blended memory cells, two memory cells are used to implement the weight W as the average of two cells.

[0069] Figure 23 shows the VMM system 2300 (which comprises a VMM array 2301, as well as adders 2301 and 2302). In some examples, the weights W stored in the VMM array are stored as differential pairs, W+ (positive weight) and W- (negative weight), where W = (W+) - (W-). In the VMM system 2300, half of a plurality of bit lines are designated as W+ lines, i.e., bit lines that will connect to memory cells that will store the positive weights W+, and the other half of the plurality of bit lines are designated as W- lines, i.e., bit lines that will connect to memory cells that will implement the negative weights W-. The W- lines are interspersed alternately between the W+ lines. Subtraction operations are performed by adders, such as adders 2301 and 2302, which receive current from the W+ and W- lines. The outputs of the W+ and W- lines are combined to effectively give W=W+-W- for each pair of (W+, W-) cells in all pairs of (W+, W-) lines. We have so far described W- lines that are alternately scattered between W+ lines, but in other examples, the W+ and W- lines can be arbitrarily placed anywhere in the array.

[0070] Figure 24 shows another example. In the VMM system 2410, positive weights W+ are implemented in the first array 2411, and negative weights W- are implemented in the second array 2412, which is separate from the first array, and the resulting weights are appropriately combined by the adder circuit 2413.

[0071] Figure 25 shows the VMM system 2500. The weights W stored in the VMM array are stored as differential pairs, W+ (positive weight) and W- (negative weight), where W = (W+) - (W-). The VMM system 2500 comprises arrays 2501 and 2502. Half of the multiple bit lines in each of arrays 2501 and 2502 are designated as W+ lines, i.e., bit lines connected to memory cells that store the positive weights W+, and the other half of the multiple bit lines in each of arrays 2501 and 2502 are designated as W- lines, i.e., bit lines connected to memory cells that implement the negative weights W-. The W- lines are interspersed alternately between the W+ lines. Subtraction operations are performed by adders, such as adders 2503, 2504, 2505 and 2506, which receive current from the W+ and W- lines. The outputs of the W+ line and the W- line from each array 2501 and 2502 are combined together to effectively give W=W+-W- for each pair of (W+, W-) cells in all pairs of (W+, W-) lines. In addition, the W values ​​from each array 2501 and 2502 can be further combined through adders 2507 and 2508, such that each W value is the result of subtracting the W value from array 2502 from the W value from array 2501, meaning that the final result from adders 2507 and 2508 is the difference of one of the two difference values.

[0072] Each non-volatile memory cell used in an analog neural memory system is erased and programmed to hold a very specific and precise amount of charge, i.e., the number of electrons, within a floating gate. For example, each floating gate can hold one of N different values, where N is the number of different weights that can be represented in each cell. Examples of N include 16, 32, 64, 128, and 256.

[0073] Since each cell can hold one of N distinct values, it is desirable that the output block perform verification and read operations accurately and consistently. In the prior art, the input to the output block has a voltage that fluctuates depending on the current drawn by the memory array, as shown below with reference to Figure 26, which illustrates the relationship between changes in bit line voltage and changes in current drawn by the bit line through the memory cells coupled to that bit line. As can be seen from the figure, the bit line voltage fluctuates significantly as the bit line current fluctuates. This results in inaccuracy and also an asymmetry between the verification operation when one or a few cells are read and the neural read operation when all cells are read. [Overview of the project]

[0074] In one example, the system comprises an array of non-volatile memory cells arranged in rows and columns, the array having a first bit line coupled to a first column of non-volatile memory cells and a second bit line coupled to a second column of non-volatile memory cells; and an output block coupled to the array, the output block comprising a current-voltage converter for converting a first current on the first bit line to a first voltage and a second current on the second bit line to a second voltage, and an analog-to-digital converter for converting one or more of the first voltage and the second voltage into a set of output bits.

[0075]

[0076]

[0077]

[0078]

[0079]

[0080] [Brief explanation of the drawing]

[0081] [Figure 1]This is a diagram of an artificial neural network. [Figure 2] This shows a prior art split-gate flash memory cell. [Figure 3] This shows another prior art split-gate flash memory cell. [Figure 4] This shows another prior art split-gate flash memory cell. [Figure 5] This shows another prior art split-gate flash memory cell. [Figure 6] This figure shows various levels of artificial neural networks that utilize one or more non-volatile memory arrays. [Figure 7] This is a block of VMM systems. [Figure 8] This block diagram shows an exemplary artificial neural network utilizing one or more VMM systems. [Figure 9] Here is another example of a VMM system. [Figure 10] Here is another example of a VMM system. [Figure 11] Here is another example of a VMM system. [Figure 12] Here is another example of a VMM system. [Figure 13] Here is another example of a VMM system. [Figure 14] Here is another example of a VMM array. [Figure 15] Here is another example of a VMM array. [Figure 16] Here is another example of a VMM array. [Figure 17] Here is another example of a VMM array. [Figure 18] Here is another example of a VMM array. [Figure 19] Here is another example of a VMM system. [Figure 20] Here is another example of a VMM array. [Figure 21] Here is another example of a VMM array. [Figure 22] Here is another example of a VMM array. [Figure 23] Here is another example of a VMM system. [Figure 24] Here is another example of a VMM system. [Figure 25] Here is another example of a VMM system. [Figure 26] This shows the change in bit line voltage in prior art when the bit line current changes. [Figure 27] This shows the VMM system. [Figure 28] This shows the output block within the VMM system. [Figure 29] This shows a current-voltage converter. [Figure 30] This shows a current-voltage converter. [Figure 31] This shows a current-voltage converter. [Figure 32] A common-mode circuit for a current-voltage converter is shown. [Figure 33] A common-mode circuit for a current-voltage converter is shown. [Figure 34] A common-mode circuit for a current-voltage converter is shown. [Figure 35] A common-mode circuit for a current-voltage converter is shown. [Figure 36] A common-mode circuit for a current-voltage converter is shown. [Figure 37] This shows a current-voltage converter. [Figure 38] This shows the bit line adjustment circuit. [Figure 39] This shows the bit line adjustment circuit. [Figure 40] This shows a bit wire metal layer coupled to a current-voltage converter. [Figure 41] This shows a bit wire metal layer coupled to a current-voltage converter. [Figure 42] This shows an operational amplifier. [Figure 43] This shows a portion of a current-voltage converter equipped with an operational amplifier. [Figure 44] The output block is shown. [Figure 45] The output block is shown. [Figure 46] Shows the output block. [Figure 47] Shows the output block. [Figure 48] Shows the output block. [Figure 49] Shows the output block. [Figure 50] Shows the output block. [Figure 51] Shows the output block. [Figure 52] Shows the verification circuit. [Figure 53] Shows the read circuit. [Figure 54] Shows the read circuit. [Figure 55] Shows the read circuit. [Figure 56] Shows the read circuit. [Figure 57A] Shows the level shifter. [Figure 57B] Shows the level shifter. [Figure 58] Shows the output block. [Figure 59] Shows the output block. [Figure 60] Shows the output block. [Figure 61] Shows the output block. [Figure 62] Shows the VMM system. [Figure 63] Shows an example of load.

Best Mode for Carrying Out the Invention

[0082] <Structure of the VMM System> Figure 27 shows a block diagram of the VMM system 2700. The VMM system 2700 comprises a VMM array 2701, redundant arrays 2719A (row redundant array) and 2719B (column redundant array), a row decoder 2702, a high-voltage decoder 2703, a column decoder 2704, a bit line driver 2705 (including a bit line control circuit for programming), an input circuit 2706, an output circuit 2707, a control logic 2708, and a bias generator 2709. The VMM system 2700 further comprises a high-voltage generation block 2710, which includes a charge pump 2711, a charge pump regulator 2712, and a high-voltage level generator 2713. The VMM system 2700 further comprises an algorithm controller 2714 (for program / erase or weight tuning), analog circuits 2715, a control engine 2716 (which may include, but is not limited to, functions such as arithmetic functions, activation functions, and embedded microcontroller logic), test control logic 2717, and a static random access memory (SRAM) block 2718 for storing intermediate data such as input circuits (e.g., activation data) or output circuits (neuron output data, partial sum output neuron data), or programming data (such as data inputs for all or multiple rows).

[0083] The VMM array 2701 includes non-volatile memory cells arranged in rows and columns (for example, non-volatile memory cells of the type shown as memory cells 210, 310, 410, and 510 in Figures 2, 3, 4, and 5, respectively). Here, redundant arrays 2719A and 2719B are shown as part of the same physical array as the VMM array 2701, but those skilled in the art will understand that redundant arrays 2719A and 2719B, as well as the VMM array 2701, could instead be located in separate physical arrays.

[0084] The input circuit 2706 may include circuits such as a DAC (digital-to-analog converter), DPC (digital-to-pulses converter, digital-to-time modulated pulse converter), AAC (analog-to-analog converter, such as a current-to-voltage converter or logarithmic converter), PAC (pulse-to-analog level converter), or any other type of converter. The input circuit 2706 may implement one or more of the following: normalization, linear or nonlinear up / downscaling functions, or arithmetic functions. The input circuit 2706 may implement a temperature compensation function for the input level. The input circuit 2706 may implement an activation function such as ReLU or sigmoid. The input circuit 2706 can store digital activation data that is applied as an input signal during program or read operation, or combined with an input signal. The digital activation data can be stored in a register. The input circuit 2706 may include a sample-and-hold circuit and a buffer, and may also include a circuit for driving array terminals such as CG lines, WL lines, EG lines, and SL lines. A DAC can be used to convert digital activation data into analog input voltages applied to the array.

[0085] The output circuit 2707 may include circuits such as an ITV (current-to-voltage circuit), an ADC (analog-to-digital converter for converting the analog output of a neuron into digital bits), an AAC (analog-to-analog converter, such as a logarithmic converter), an APC (analog-to-pulse converter, such as an analog-to-time modulated pulse converter), or any other type of converter. The output circuit 2707 can convert the array output into activation data. The output circuit 2707 may implement an activation function such as a rectified linear activation function (ReLU) or a sigmoid. The output circuit 2707 may implement one or more of the following functions of the neuron output: statistical normalization, regularization, up / down scaling / gain function, statistical rounding, or arithmetic function (e.g., addition, subtraction, division, multiplication, shift, logarithm). The output circuit 2707 may implement a temperature compensation function for the neuron output or array output (such as a bit line output) in order to keep the power consumption of the array nearly constant, or to improve the accuracy of the array (neuron) output by keeping the IV gradient nearly the same with respect to temperature changes. The output circuit 2707 may also include a register for storing the output data.

[0086] Figure 28 shows output block 2800, which receives analog signals from the VMM array and generates digital outputs. The columns in the VMM array are paired together, with one column providing current BLW+ from bit line W+ (which may be referred to herein as the first bit line) and the other column providing current BLW- from bit line W- (which may be referred to herein as the second bit line). There are i column pairs, labeled column pairs 2801-1, ..., 2801-i, and each pair includes the W+ bit line and the W- bit line. Current-voltage converters 2802-1, ..., 2802-i convert the currents received from each column pair 2801-1, ..., 2801-i into pairs of voltages V+ and V-. The analog-to-digital converters 2803-1, ..., 2803-i each receive pairs of voltages V+ and V- from the current-to-voltage converters 2802-1, ..., 2802-i, respectively, and generate their respective digital outputs DOUT1, ..., DOUTi. The use of differential cells (one storing a W+ value and the other storing a W- value, and together they store the value W according to the formula W=W+-W-) is disclosed in U.S. Patent Application No. 17 / 875,281, filed on 27 July 2022 and published as U.S. Patent Application Publication No. 2022 / 0374699(A1), entitled “Precise Data Tuning Method and Apparatus for Analog Neural Memory in an Artificial Neural Network,” which is incorporated herein by reference.

[0087] Figures 29, 30, and 31 disclose three examples of a current-voltage converter that can be used as the current-voltage converter 2802 in the output block 2800 of Figure 28. The inputs are the currents BLW+ and BLW- from the bit lines W+ and W-, respectively, and the outputs are the voltages V+ and V-. V+ and V- are complementary, i.e., the output common-mode voltage V CMCentered around (which may be ground or another voltage), one side is positive and the other is negative. The inverting and non-inverting inputs to operational amplifiers 2904, 3004, and 3106 are maintained at a common reference voltage determined by common-mode circuits 2903, 3003, and 3105, respectively.

[0088] Figure 29 shows a current-voltage converter 2900 comprising a variable resistor 2901, a variable resistor 2902, a common-mode circuit 2903, and an operational amplifier 2904. The first output of the common-mode circuit 2903 is coupled to node 2905, which is coupled to the non-inverting input of the operational amplifier 2904, and the second output of the common-mode circuit 2903 is coupled to node 2906, which is coupled to the inverting input of the operational amplifier 2904. The common-mode circuit 2903 maintains the same voltage at nodes 2905 and 2906, i.e., the voltages at the non-inverting and inverting inputs of the operational amplifier 2904 are equal. The common-mode circuit 2903 receives a reference voltage VCIMREF and outputs current Iout+ to node 2905 and current Iout- to node 2906, where Iout+ and Iout- are equal. Equal voltages and equal currents Iout+ and Iout- at nodes 2905 and 2906 are the common-mode components V in the output voltage centered on V+ and V-. CM This leads to the generation of the following. The current-voltage converter 2900 converts the currents BLW+ and BLW- into voltages V+ and V-. The output voltages minus the common-mode component, dV+=V+-VCIMREF and dV-=V--VCIMREF, are proportional to half the difference between BLW+ and BLW- multiplied by the resistance of each feedback resistor (2901 / 2902), specifically as follows. dV+={(BLW+-BLW-) / 2}×R_2901, and dV-={(BLW--BLW+) / 2}×R_2902

[0089] Figure 30 shows a current-voltage converter 3000 comprising a variable capacitor 3001, a variable capacitor 3002, a common-mode circuit 3003, and an operational amplifier 3004. The first output of the common-mode circuit 3003 is coupled to node 3005, which is coupled to the non-inverting input of the operational amplifier 3004. The second output of the common-mode circuit 3003 is coupled to node 3006, which is coupled to the inverting input of the operational amplifier 2904. The common-mode circuit 3003 maintains the same voltage at nodes 3005 and 3006, that is, the voltages at the non-inverting and inverting inputs of the operational amplifier 3004 are equal. The common-mode circuit 3003 receives a reference voltage VCIMREF and outputs a current Iout+ to node 3005 and a current Iout- to node 3006, where Iout+ = Iout-. Equal voltages and equal currents Iout+ and Iout- at nodes 3005 and 3006 are the common mode components in the output voltage around V+ and V, which are centered. CM This results in the generation of the current-voltage converter 3000, which converts currents BLW+ and BLW- into voltages V+ and V-. The output voltages minus the common-mode component, dV+ = V+ - VCIMREF and dV- = V- - VCIMREF, are proportional to half the difference between BLW+ and BLW- multiplied by the capacitance values ​​of the respective feedback capacitors (3001 / 3002), specifically as follows. dV+={(BLW+-BLW-) / 2} * C_3001, and dV-={(BLW--BLW+) / 2} * C_3003

[0090] Figure 31 shows a current-voltage converter 3100 comprising a variable capacitor 3101, a variable capacitor 3102, a variable resistor 3103, a variable resistor 3104, a common-mode circuit 3105, and an operational amplifier 3106. The first output of the common-mode circuit 3105 is coupled to node 3107, which is coupled to the non-inverting input of the operational amplifier 3106, and the second output of the common-mode circuit 3105 is coupled to node 3108, which is coupled to the inverting input of the operational amplifier 3106. The common-mode circuit 3105 maintains the same voltage at nodes 3107 and 3108, that is, the voltages at the non-inverting and inverting inputs of the operational amplifier 3106 are equal. The common-mode circuit 3105 receives a reference voltage VCIMREF and outputs a current Iout+ to node 3107 and a current Iout- to node 3108, where Iout+ = Iout-. Equal voltages and equal currents Iout+ and Iout- at nodes 3107 and 3108 are the common mode components in the output voltage around V+ and V, which are centered. CM This results in the generation of the current-voltage converter 3100, which converts the currents on BLW+ and BLW- into voltages V+ and V-. The output voltages minus the common-mode component, dV+ = V+ - VCIMREF and dV- = V- - VCIMREF, are proportional to half the difference between BLW+ and BLW- multiplied by the resistance value of the feedback resistors (3103 / 3104), specifically as follows. dV+={(BLW+-BLW-) / 2}×R_3101, and dV-={(BLW--BLW+) / 2}×R_3102

[0091] Therefore, resistors 3103 and 3104 convert current to voltage. After the conversion is complete, resistors 3103 and 3104 are disconnected by a switch (not shown), and capacitors 3101 and 3102 are used to hold the converted voltage.

[0092] Figures 32 to 36 show examples of common-mode circuits that can be used as common-mode circuits 2903, 3003, and 3105 in the current-voltage converters 2900, 3000, and 3100 in Figures 29 to 31, respectively.

[0093] Figure 32 shows a common-mode circuit 3200 comprising an operational amplifier 3201 (an example of a regulating circuit), a current source 3202, a current source 3203, a node 3204 (corresponding to nodes 2905, 3005, and 3107 in Figures 29, 30, and 31), and a node 3205 (corresponding to nodes 2906, 3006, and 3108 in Figures 29, 30, and 31). The operational amplifier 3201 receives the voltage VCIMREF as input at its non-inverting input and the voltage of node 3205 at its inverting input. Due to the high input impedance of the operational amplifier 3201, no current flows from BLw- to the operational amplifier 3201. The operational amplifier 3201 generates a voltage output Vbias (voltage bias), which is applied as a bias signal to the current sources 3202 and 3203 to control their current amounts Iout+ and Iout-, respectively. The operational amplifier 3201 corrects Vbias until the voltage on bit line W-, which is the voltage at node 3205, is equal to VCIMREF.

[0094] Figure 33 shows a common-mode circuit 3300 comprising an operational amplifier 3301 (an example of a tuning circuit), a variable resistor 3302, a variable resistor 3303, node 3304 (corresponding to nodes 2905, 3005, and 3107 in Figures 29, 30, and 31), and node 3305 (corresponding to nodes 2906, 3006, and 3108 in Figures 29, 30, and 31). Vbias (voltage bias) is applied to the node between variable resistors 3302 and 3303. The currents through variable resistors 3302 and 3303 are Iout+ and Iout-, respectively, where Iout+ = Iout-. The variable resistors are set during configuration mode to ensure that the voltages at nodes 3304 and 3305 are equal, which in turn equals Iout+ and Iout-. The operational amplifier 3301 receives the voltage VCIMREF as input at its non-inverting input and the voltage at node 3305 at its inverting input. Due to the high input impedance of the operational amplifier 3301, no current flows from node 3305 (or bit line W-) to the operational amplifier 3301. The operational amplifier 3301 generates a voltage output Vbias and modifies Vbias until the voltage at node 3305, which is the voltage at bit line W-, equals VCIMREF.

[0095] Figure 34 shows a common-mode circuit 3400 comprising an operational amplifier 3401 (an example of a regulating circuit), PMOS transistors 3402 and 3403, node 3404 (corresponding to nodes 2905, 3005, and 3107 in Figures 29, 30, and 31), and node 3405 (corresponding to nodes 2906, 3006, and 3108 in Figures 29, 30, and 31). Vbias (voltage bias) is applied to nodes coupled to the gates of PMOS transistors 3402 and 3403, yielding currents Iout+ and Iout-, where Iout+=Iout-. The voltages at nodes 3404 and 3405 are equal. The operational amplifier 3401 receives the voltage VCIMREF as input at its non-inverting input and the voltage at node 3405 at its inverting input. Due to the high input impedance of the operational amplifier 3401, no current flows from node 3405 (or bit line W-) to the operational amplifier 3401. The operational amplifier 3401 generates a voltage output Vbias and modifies Vbias until the voltage on bit line W-, which is the voltage at node 3405, becomes equal to VCIMREF.

[0096] Figure 35 shows a common-mode circuit 3500 comprising an operational amplifier 3501 (an example of a regulating circuit), an NMOS transistor 3502, an NMOS transistor 3503, node 3504 (corresponding to nodes 2905, 3005, and 3107 in Figures 29, 30, and 31), and node 3505 (corresponding to nodes 2906, 3006, and 3108 in Figures 29, 30, and 31). Vbias (voltage bias) is applied to the node between NMOS transistors 3502 and 3503, and VB is the bias voltage applied to turn on NMOS transistors 3502 and 3503 during operation, resulting in currents Iout+ and Iout-, where Iout+=Iout-. The voltages at nodes 3504 and 3505 are equal. The operational amplifier 3501 receives the voltage VCIMREF as input at its non-inverting input and the voltage at node 3505 at its inverting input. Due to the high input impedance of the operational amplifier 3501, no current flows from node 3505 (or bit line W-) to the operational amplifier 3501. The operational amplifier 3501 generates a voltage output Vbias and modifies Vbias until the voltage on bit line W-, which is the voltage at node 3505, becomes equal to VREF.

[0097] Figure 36 shows a common-mode circuit 3600 comprising an operational amplifier 3601 (an example of a tuned circuit), a variable capacitor 3602, a variable capacitor 3603, node 3604 (corresponding to nodes 2905, 3005, and 3107 in Figures 29, 30, and 31), and node 3605 (corresponding to nodes 2906, 3006, and 3108 in Figures 29, 30, and 31). Vbias (voltage bias) is applied to the node between variable capacitors 3602 and 3603. The currents from variable capacitors 3602 and 3603 are Iout+ and Iout-, respectively, where Iout+ = Iout-. The variable capacitors are set during configuration mode to ensure that the voltages at nodes 3604 and 3605 are equal, thereby also equaling Iout+ and Iout-. The operational amplifier 3601 receives the voltage VCIMREF as input at its non-inverting input and the voltage at node 3605 at its inverting input. Due to the high input impedance of the operational amplifier 3601, no current flows from node 3605 (or bit line W-) to the operational amplifier 3601. The operational amplifier 3601 generates a voltage output Vbias and modifies Vbias until the voltage at node 3605, which is the voltage at bit line W-, equals VCIMREF.

[0098] Figure 37 shows an exemplary output block 3700 for a column pair. Although only one output block 3700 for a column pair is shown, it should be understood that instantiations of the output block 3700 for a column pair are used for each pair of columns in the VMM array 2701. The output block of the column pair 3700 receives the current BLW+ (first current) from one column and the current BLW- (second current) from the other column in the VMM array 2701 and generates DOUTx, which is a digital output with a set of output bits.

[0099] The output block 3700 for the row pair comprises a current-to-voltage (ITV) converter 3701 and an analog-to-digital converter (ADC) 3702. The current-to-voltage converter 3701 comprises a regulator 3703 (first regulator), a regulator 3704 (second regulator), a common-mode circuit 3713, a switch 3709, a switch 3710, an NMOS transistor 3711, an NMOS transistor 3712, an operational amplifier (which may be referred to as an operational amplifier) ​​(which is an example of a regulating circuit) 3714, a switched capacitor 3715 (first capacitor), a switched resistor 3716 (first resistor), a switched resistor 3717 (second resistor), and a switched capacitor 3718 (second capacitor). The operational amplifier 3714 includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal, the first output terminal and the second output terminal providing a differential voltage.

[0100] Switched capacitors 3715 and 3718 may be variable or fixed capacitors. Switched resistors 3716 and 3717 may be variable or fixed resistors. Optionally, switched capacitors 3715 and 3718 can be removed. Optionally, switched resistors 3716 and 3717 can be removed. Regulator 3703 comprises switch 3706 and operational amplifier 3705 (an example of a regulating circuit). Regulator 3704 comprises switch 3708 and operational amplifier 3707 (an example of a regulating circuit). BL+ regulating circuit 3720A comprises regulator 3703, switch 3709, and NMOS transistor 3711. BL- regulating circuit 3720B comprises regulator 3704, switch 3710, and NMOS transistor 3712.

[0101] In the case of a circuit path connecting bit line BL+ (the first bit line), switches 3709 and 3706 are part of a column multiplexer that multiplexes the bit line from the VMM array 2701 to the current-voltage converter 3701. Specifically, the column multiplexer selects bit line BL+ by closing switches 3706 and 3709. Conventional column multiplexers use only an equivalent of switch 3709 to conduct bit line current from the VMM array 2701 to the current-voltage converter 3701 (which may also be known as the output circuit or sense circuit). The example shown here adds switch 3706, which is part of a sense multiplexer (YMUX-S) that does not carry current due to the high impedance of the operational amplifier 3705. Under this configuration, switches 3706 and 3709 have the same voltage, but switch 3709 carries current and switch 3706 does not. When switches 3706 and 3709 are closed, the bit line voltage is initially lower than VBLRD, which increases the output of operational amplifier 3705 and turns on NMOS transistor 3711. As the voltage at the gate of NMOS transistor 3711 increases, the voltage at the source of NMOS transistor 3711 also increases until the bit line voltage becomes equal to VBLRD.

[0102] In the case of a circuit path connecting bit line BL- (second bit line), switches 3710 and 3708 are part of a column multiplexer that multiplexes bit lines from the VMM array 2701 to the current-voltage converter 3701. Specifically, the column multiplexer selects bit line BL- by closing switches 3708 and 3710. Conventional column multiplexers use only an equivalent of switch 3710 to conduct bit line current from the VMM array 2701 to the current-voltage converter 3701 (which may also be known as the output circuit or sense circuit). The example shown here adds switch 3708, which is part of a sense multiplexer (YMUX-S) that does not carry current due to the high impedance of the operational amplifier 3707. Under this configuration, switches 3708 and 3710 have the same voltage, but switch 3710 carries current and switch 3708 does not. When switches 3708 and 3710 are closed, the bit line voltage is initially lower than VBLRD, which increases the output of operational amplifier 3707 and turns on NMOS transistor 3712. As the voltage at the gate of NMOS transistor 3712 increases, the voltage at the source of NMOS transistor 3712 also increases until the bit line voltage becomes equal to VBLRD.

[0103] Alternatively, transistors 3711 and 3712 may be PMOS transistors instead of NMOS transistors.

[0104] The common-mode circuit 3713 is specifically isolated from the bit lines BL+ and BL- by NMOS transistors 3711 and 3712 (which may be called bit-line tuner transistors or bit-line decoupler transistors). The common-mode circuit 3713 equalizes the voltages supplied to the inverting and non-inverting inputs of the operational amplifier 3714. In contrast, without the BL+ tuner circuit 3720A, the BL- tuner circuit 3720B, and the common-mode circuit 3713, the voltages on the lines carrying BL+ and BL- change as the current through each line changes based on the value in the attached memory cell, as shown in the characterization shown in Figure 26. The use of the BL+ tuner circuit 3720A, the BL- tuner circuit 3720B, and the common-mode circuit 3713 results in greater precision in generating the voltages V+ and V from the currents BL+ and BL-. It also reduces the asymmetry that otherwise exists between verification operation (one or a few memory cells draw current) and neural readout operation (many or all memory cells may draw current).

[0105] Figure 38 shows a BL adjustment circuit 3800, which can be used as an alternative to one or more of the BL+ adjustment circuits 3720A and BL- adjustment circuits 3720B in Figure 37. The BL adjustment circuit 3800 comprises a regulator 3801, a switch 3804, a native NMOS transistor 3805, an enhancement-mode NMOS transistor 3806, and a switch 3807. The regulator 3801 comprises a switch 3803 and an operational amplifier 3802 (an example of an adjustment circuit). Switches 3804 and 3803 are parts of a column multiplexer that select this particular bit line. Specifically, the column multiplexer selects this bit line by closing switches 3804 and 3803. The native NMOS transistor 3805 and the enhancement-mode NMOS transistor 3806 are activated by the output of the operational amplifier 3802 and used for different current ranges on the bit line. For example, the enhancement-mode NMOS transistor 3806 can be used for low current levels in the nA range, such as during verification operations, to limit leakage, while the native NMOS transistor 3805 can be used for high current levels in the μA range, such as during neural readout operations (enabling many rows within the VMM).

[0106] Figure 39 shows a BL adjustment circuit 3900, which can be used as an alternative to one or more of the BL+ adjustment circuit 3970A and BL- adjustment circuit 3720B in Figure 37. The BL adjustment circuit 3900 comprises a regulator 3901, a switch 3904, a native NMOS transistor 3905, an enhancement-mode NMOS transistor 3906, and a switch 3907. The regulator 3901 comprises a switch 3903 and an operational amplifier 3902 (an example of an adjustment circuit). Switches 3904 and 3903 are parts of a column multiplexer that select this particular bit line. Specifically, the column multiplexer selects this bit line by closing switches 3904 and 3903. The native NMOS transistor 3905 and the enhancement-mode NMOS transistor 3906 are activated by the output of the operational amplifier 3902 and used for different current ranges on the bit line. For example, the enhancement-mode NMOS transistor 3906 can be used for low current levels in the nA range, such as during verification operations, to limit leakage, while the native NMOS transistor 3905 can be used for high current levels in the μA range, such as during neural readout operations (enabling many rows within the VMM).

[0107] Figure 40 shows details of how the aforementioned example is connected to the bit lines in the VMM array 2701. Here, the bit line metal layer 4010 in the VMM array 2701 provides BL+ or BL-, as shown in Figure 37, to the regulator 3703, switch 3709, and NMOS transistor 3711.

[0108] Figure 41 shows details of a modification to the method by which the VMM array 2701 can be connected to the previously described example. Here, the bit line sensing metal wire 4111 is provided to enable precise bit line adjustment without carrying current due to the high input impedance of the operational amplifier 4103 (an example of a tuning circuit). The lower bit line metal layer 4110 (coupled to the upper bit line metal layer) provides the current BL+ or BL- of the selected cell to the NMOS transistor 4105 through the switch 4104. The BL+ regulator 4121 comprises the regulator 4101, the switch 4104, and the NMOS transistor 4105. The regulator 4101 comprises the operational amplifier 4103 and the switch 4102. The BL+ regulator 4121 can be used in place of the BL+ regulator 3720A in Figure 37. A similar regulator, the BL- regulator (not shown), is connected to BL-.

[0109] Figure 42 discloses operational amplifier 4201 (an example of a regulating circuit), which is an example of an operational amplifier that can be used in operational amplifiers 3705, 3707, and 3714 in Figure 37, operational amplifiers 3802 and 3902 in Figures 38 and 39, and operational amplifier 4103 in Figure 41. Operational amplifier 4201 comprises PMOS transistors 4202 and 4203, and NMOS transistors 4204, 4205, and 4206. The non-inverting input of operational amplifier 4201 is INP, the inverting input is INN, and the output is OUT.

[0110] Figure 43 discloses an example of how the operational amplifier 4201 (example of a regulating circuit) can be used in Figure 37, where it is shown to be connected to switches 3706 (sensing multiplexer) and 3709 (current carrier multiplexer) and transistor 3711 (BL regulating transistor) from Figure 37.

[0111] Figure 44 shows an exemplary output block 4400 for a column pair that can be used during a verification or readout neural operation. Although only one output block 4400 for a column pair is shown, it should be understood that instantiations of the output block 4400 for a column pair are used for each pair of columns in the VMM array 2701. The output block 4400 for a column pair comprises a current-voltage converter 3701 and an analog-to-digital converter (ADC) 4410. The ADC 4410 comprises the ADC 3702, which has already been described with reference to Figure 37 and will not be described again here, and the ADC 4402 comprises a comparator 4401 and switches 4403, 4404, and 4405. The ADC 3702 is used to perform a readout neural operation on both V+ and V- during the first mode, and the ADC 4402 is used to perform a verification operation on only one of V+ or V- during the second mode. Optionally, the ADC3702 and ADC4402 can share common components such as the comparator 4401, saving die space.

[0112] During readout neural operation in the first mode, the output block of column pair 4400 receives current from the first bit line BL+ coupled to the first column of nonvolatile memory cells in the VMM array 2701 and from the second bit line BL- coupled to the second column of nonvolatile memory cells in the VMM array 2701, generating DOUTx, a digital output containing a set of output bits, from the ADC 3702. Regulator 3703 (first regulator) provides a first input to the adjustment circuit 3714, and regulator 3704 (second regulator) provides a second input to the adjustment circuit 3714.

[0113] During the verification operation of one or more cells coupled to BL+ in second mode, regulator 3703 (first regulator) provides a first input to the adjustment circuit 3714, and switch 4403 is closed and switch 4404 is opened, so comparator 4401 compares V+ against VREF_VFY, which is the reference voltage on which the verification is performed, and the output VER_OUT from ADC 4402 indicates whether the verification operation was successful. During the verification operation of one or more cells coupled to BL- in second mode, regulator 3704 (second regulator) provides a second input to the adjustment circuit 3714, and switch 4403 is opened and switch 4404 is closed, so comparator 4401 compares V- against VREF_VFY, and VER_OUT indicates whether the verification operation was successful.

[0114] In this way, any offset of regulator 3703 or 3704 is replicated during the verification operation to be the same as the neural readout operation of BL+ and BL-, respectively. Various systems and methods for verification are disclosed in U.S. Patent Application No. 18 / 080,545, filed on 13 December 2022, entitled "Verification Method and System in Artificial Neural Network Array," which is incorporated herein by reference.

[0115] Figure 45 shows an exemplary output block 4500 for a row pair used during verification operation. Although only one output block 4500 for a row pair is shown, it should be understood that instantiations of output block 4500 for a row pair are used for each pair of rows in the VMM array 2701. The output block of row pair 4500 receives current BL+ (first current) from one row of nonvolatile memory cells in the VMM array 2701 and current BL- (second current) from another row of nonvolatile memory cells in the VMM array 2701, and generates DOUTx, which is a digital output containing a set of output bits. The output block of row pair 4500 comprises a current-voltage converter 4501 and an ADC 4520. The ADC 4520 comprises ADC 3702 (as described with reference to Figure 37) and ADC 4502. The current-voltage converter 4501 comprises many of the same components as the current-voltage converter 3701. These components have the same function as the current-voltage converter 3701 and will not be described again for efficiency. The current-voltage converter 4501 further comprises switches 4507, 4508, 4509, 4510, 4511, and 4512. The ADC 3702 is used during readout neural operation, and the ADC 4502 is used during verification operation. The ADC 4502 comprises comparator 4503 and switch 4504. Optionally, the ADC 3702 and ADC 4502 can share common components, such as comparator 4503, to save die space. Optionally, the ADC 3702 in Figure 44 or Figure 45 can be used for verification operation. In this case, the output bit set DOUTx of the ADC 3702 is used as the verification target.

[0116] During readout neural operation, the output block of the first mode column pair 4500 receives current BL+ from one column in the VMM array 2701 and current BL- from another column, generating DOUTx, a digital output containing a set of output bits from the ADC 3702. Regulator 4521 (first regulator) provides a first input to the tune circuit 3714, and regulator 4522 (second regulator) provides a second input to the tune circuit 3714.

[0117] During the verification operation of one or more cells coupled to BL+ in the second mode, regulator 4521 (first regulator) provides a first input to the adjustment circuit 3714, switches 4504, 4505, 4507, 4508, 4511, and 4512 are closed, and switches 4506, 4509, and 4510 are opened, so that comparator 4503 compares V+ to VREF_VFY, which is the reference voltage on which the verification is performed, and the output VER_OUT from ADC 4502 indicates whether the verification operation was successful.

[0118] During the verification operation of one or more cells coupled to BL- in second mode, regulator 4522 (second regulator) provides a second input to the adjustment circuit 3714, switches 4504, 4506, 4508, 4509, 4510, and 4512 are closed and switches 4505, 4507, and 4511 are opened, so that comparator 4503 compares V- with VREF_VFY and VER_OUT indicates whether the verification operation was successful.

[0119] Figure 46 shows a column pair verification circuit 4600. Although only one column pair verification circuit 4600 is shown, it should be understood that instantiations of the column pair verification circuit 4600 are used for each column pair in the VMM array 2701. The column pair verification circuit 4600 receives a current BL+ (first current) from a first bit line coupled to a first column of nonvolatile memory cells in the VMM array 2701, and a current BL- (second current) from a second bit line coupled to a second column of nonvolatile memory cells in the VMM array 2701, and generates DOUTx, which is a digital output containing a set of output bits.

[0120] The row-pair verification circuit 4600 comprises a current-voltage (ITV) converter 4601 and a comparator 4602 (in this example, a 1-bit analog-to-digital converter). The current-voltage converter 4601 includes a first switch set 4603 (containing one or more switches), a second switch set 4604 (containing one or more switches), an operational amplifier 4605, an operational amplifier 4606, a switched capacitor 4607, a switched resistor 4608, a switched resistor 4609, and a switched capacitor 4610.

[0121] Switch sets 4603 and 4604 are part of a column multiplexer that multiplexes bit lines from the VMM array 2701 to the current-voltage converter 4601. Specifically, the column multiplexer selects the bit lines that provide BL+ by closing each switch set 4603, and the column multiplexer selects the bit lines that provide BL- by closing each switch set 4604. Switched capacitors 4607 and 4610 can be variable or fixed capacitors. Switched resistors 4608 and 4609 can be variable or fixed resistors. Optionally, switched capacitors 4607 and 4610 can be removed. Optionally, switched resistors 4608 and 4609 can be removed. Switched capacitors 4607 and 4610 are enabled (by pulse width) to convert current to voltages Vinp and Vinn, such as at low current levels (in which case switched resistors 4608 and 4609 are turned off). Resistors 4608 and 4609 are enabled to convert current to voltages Vinp and Vinn, such as at high current levels (in which case switched capacitors 4607 and 4610 may be on or off).

[0122] The current-voltage converter 4601 converts current BL+ to voltage Vinp and current BL- to voltage Vinn. VBLRD is a read voltage bias applied to the bit lines BL+ and BL-, for example, 0.6 V. Initially, the voltages on the bit lines BL+ and BL- are lower or higher than VBLRD, which increases or decreases the output voltages of operational amplifiers 4905 and 4907, thereby turning on the stronger or weaker NMOS transistors 4911 and 4912, respectively, to maintain the voltage at BL+ or BL- equal to VBLRD. Switches 4611 and 4612 are closed to apply voltages Vinp and Vinn to the inverting input (first input) of comparator 4602, respectively. The non-inverting input (second input or reference input) of comparator 4602 receives a reference voltage VREF_VFY, which is the voltage to be verified when voltage Vinp or Vinn is closed. The output of comparator 4602 is a digital output DOUTx containing a set of output bits, which, during a verification operation, is a first value (e.g., "1") when the verification operation is successful and a second value (e.g., "0") when the verification operation is unsuccessful (meaning that one or more cells coupled to BL+ or BL- may need to be tuned, depending on whether switch 4611 or 4612 is closed).

[0123] Figure 47 shows a column pair output block 4700. Although only one column pair output block 4700 is shown, it should be understood that instantiations of column pair output block 4700 are used for each column pair in the VMM array 2701. The column pair output block 4700 receives current BL+ from a first bit line coupled to a first column of nonvolatile memory cells in the VMM array 2701, and current BL- from a second bit line coupled to a second column of nonvolatile memory cells in the VMM array 2701, and generates DOUTx, which is a digital output containing a set of output bits.

[0124] The output block 4700 for the row pair comprises a current-to-voltage (ITV) converter 4601 and an analog-to-digital converter (ADC) 4702. The current-to-voltage converter 4601 is the same as the current-to-voltage converter 4601 in Figure 46 and includes the same components. The current-to-voltage converter 4601 converts current BL+ to voltage Vinp (first voltage) and current BL- to voltage Vinn (second voltage). Switches 4611 and 4612 are closed to apply Vinp and Vinn to the analog-to-digital converter (ADC) 4702, respectively, and the ADC converts the analog voltage to a digital signal DOUT[n:0]. The ADC 4702 may be, but is not limited to, a SAR ADC (successive approximation register ADC), a sigma-delta ADC, a slope ADC, or an algorithm (also known as cyclic) ADC.

[0125] Figure 48 shows a column pair output block 4800. Although only one column pair output block 4800 is shown, it should be understood that an instantiation of the column pair output block 4800 is used for each column pair in the VMM array 2701. The column pair output block 4800 receives current BL+ from a first bit line coupled to one column of nonvolatile memory cells in the VMM array 2701, and current BL- from a second bit line coupled to another column of memory cells in the VMM array 2701, and generates a digital output DOUTx containing a set of output bits.

[0126] The output block 4800 for the row pair comprises a current-to-voltage (ITV) converter 4601 and an analog-to-digital converter (ADC) 4802. The current-to-voltage converter 4601 is the same as the current-to-voltage converter 4601 in Figure 46 and includes the same components. The current-to-voltage converter 4601 converts current BL+ to voltage Vinp (first voltage) and current BL- to voltage Vinn (second voltage). Switches 4811 and 4812 are closed to apply Vinp and Vinn to the inverting and non-inverting inputs of the differential analog-to-digital converter (ADC) 4802, respectively, and the ADC converts the analog voltage to the digital signal DOUT[n:0]. The ADC 4802 may be, but is not limited to, a SAR ADC (successive approximate register ADC), a slope ADC, a sigma-delta ADC, or an algorithm (also known as cyclic) ADC.

[0127] Figure 49 shows a column pair output block 4900. Although only one column pair output block 4900 is shown, it should be understood that an instantiation of the column pair output block 4900 is used for each column pair in the VMM array 2701. The column pair output block 4900 receives current BL+ from a first bit line coupled to the first column of nonvolatile memory cells in the VMM array 2701 and current BL- from a second bit line coupled to the second column of nonvolatile memory cells in the VMM array 2701, generating a digital output DOUT[n:0].

[0128] The output block 4900 for the row pair comprises a current-to-voltage (ITV) converter 4901 and an analog-to-digital converter (ADC) 4902. The ADC 4902 may be, but is not limited to, a SAR ADC (successive registration ADC), a slope ADC, a sigma-delta ADC, or an algorithm (also known as a cyclic) ADC.

[0129] The current-voltage converter 4901 comprises a BL+ adjustment circuit 4919 and a BL- adjustment circuit 4920. The current-voltage converter 4901 converts current BL+ to voltage Vinp (first voltage) and current BL- to voltage Vinn (second voltage). The BL+ adjustment circuit 4919 comprises a regulator 4903 (sometimes called a forcing regulator or current-carrying regulator), a first switch set 4909 (equipped with one or more switches), an adjustment (cascode) NMOS transistor 4911, a switched capacitor 4915, and a switched resistor 4916. The BL- adjustment circuit 4920 comprises a regulator 4904 (which can be called a forcing regulator or current-carrying regulator), a second switch set 4910 (equipped with one or more switches), an adjustment (cascode) NMOS transistor 4912, a switched resistor 4917, and a switched capacitor 4918.

[0130] Regulator 4903 includes a third switch set 4906 (including one or more switches) and an operational amplifier 4905. Regulator 4904 includes a fourth switch set 4908 (including one or more switches) and an operational amplifier 4907.

[0131] In the case of a circuit path connecting bit line BL+ (the first bit line), switches 4909 and 4906 are part of a column multiplexer that multiplexes each bit line from the VMM array 2701 to the current-voltage converter 4901. Specifically, the column multiplexer selects each bit line BL+ by closing switch sets 4906 and 4909. Conventional column multiplexers use only the equivalent of switch set 4909, which conducts bit line current from the VMM array 2701 to the current-voltage converter 4901 (which may also be called the output circuit or sensing circuit). In the example shown here, a switch set 4906 is added, which is part of a sensing multiplexer (YMUX-S) that does not carry current due to the high impedance of the operational amplifier 4905. Under this configuration, the lines coupled to switch sets 4906 and 4909, namely the inverting input of operational amplifier 4905 and the source of NMOS transistor 4911 (the terminal of NMOS transistor 4911 coupled to bit line BL+), have substantially the same voltage, but switch set 4909 carries current, while switch set 4906 does not carry substantially current. VBLRD is a readout voltage bias applied to bit lines BL+ and BL-, for example, 0.6 V. When switch sets 4906 and 4909 are closed, the voltage on the bit lines is initially lower or higher than VBLRD, which increases or decreases the output voltage of operational amplifier 4905, thereby turning on a stronger or weaker NMOS transistor 4911, maintaining the voltage at BL+ or BL- the same as VBLRD.

[0132] In the case of a circuit path connecting bit line BL- (the first bit line), switch sets 4910 and 4908 are part of a column multiplexer that multiplexes each bit line from the VMM array 2701 to the current-voltage converter 4901. Specifically, the column multiplexer selects each bit line BL- by closing switch sets 4908 and 4910. Conventional column multiplexers use only the equivalent of switch set 4910, which conducts bit line current from the VMM array 2701 to the current-voltage converter 4901 (which may also be called the output circuit or sense circuit). The example shown here adds switch set 4908, which is part of a sense multiplexer (YMUX-S) that does not carry current due to the high impedance of the operational amplifier 4907. Under this configuration, the lines coupled to switch sets 4908 and 4910, namely the inverting input of operational amplifier 4907 and the source of NMOS transistor 4912, have substantially the same voltage, but switch set 4910 carries current and switch set 4908 does not carry substantially current. When switch sets 4908 and 4910 are closed, the bit line voltage is initially lower or higher than VBLRD, which increases or decreases the output voltage of operational amplifier 4907, thereby turning on NMOS transistor 4912 more strongly or weakly, maintaining the voltage at BL- the same as VBLRD. As the gate voltage of NMOS transistor 4912 increases, the current flowing through NMOS transistor 4912 increases, and the source voltage of NMOS transistor 4912 also increases until the bit line voltage becomes equal to VBLRD.

[0133] Switched capacitors 4915 and 4918 can be variable or fixed capacitors and couple the drain voltages of NMOS transistors 4911 and 4912, respectively, to VDD or VSUPP, indicated as Vinp and Vinn. Switched resistors 4916 and 4917 can be variable or fixed resistors and are arranged in parallel with switched capacitors 4915 and 4918, respectively. Optionally, switched capacitors 4915 and 4918 can be removed. Optionally, switched resistors 4916 and 4917 can be removed. Switched capacitors 4915 and 4918 and switched resistors 4916 and 4917 are loads that generate voltages Vinp and Vinn, respectively, in response to the current received. Since the ADC 4902 has a relatively high impedance, current flows substantially into the switched capacitors 4915 and 4918 and the switched resistors 4916 and 4917, each with corresponding voltage drops relative to the supply voltage VDD or VSUPP and VINP and Vinn.

[0134] Regulator 4903 comprises a switch set 4906 and an operational amplifier 4905. Regulator 4904 comprises a switch set 4908 and an operational amplifier 4907.

[0135] Figure 50 shows a column pair output block 5000. Although only one column pair output block 5000 is shown, it should be understood that an instantiation of the column pair output block 5000 is used for each column pair in the VMM array 2701. The column pair output block 5000 receives current BL+ from each column of one of the memory cells in the VMM array 2701 and current BL- from another column of memory cells in the VMM array 2701, and generates DOUT[n:0], which is a digital output containing a set of output bits.

[0136] The output block 5000 for the row pair comprises a current-voltage (ITV) converter 5001, an analog-to-digital converter (ADC) 5002, and switches 5011 and 5012. The current-voltage converter 5001 comprises a BL+ adjustment circuit 5019 and a BL- adjustment circuit 5020. The current-voltage converter 5001 converts the current BL+ to a voltage Vinp (first voltage) and the current BL- to a voltage Vinn (second voltage).

[0137] The BL+ adjustment circuit 5019 includes a regulator 4903, a first switch set 4909 (including one or more switches), an adjustment (cascode) NMOS transistor 4911, and a switched capacitor 5015 that couples voltage Vinp to voltage source VDD or VSUP. The regulator 4903 includes a third switch set 4906 (including one or more switches) and an operational amplifier 4905. The BL- adjustment circuit 5020 includes a regulator 4904, a second switch set 4910 (including one or more switches), an adjustment (cascode) NMOS transistor 4912, and a switched capacitor 5017 that couples voltage Vinn to voltage source VDD or VSUP. The regulator 4904 includes a fourth switch set 4908 (including one or more switches) and an operational amplifier 4907.

[0138] Alternatively, NMOS transistors 4911 and 4912 can be replaced with PMOS transistors.

[0139] Switched capacitors 5015 and 5017 are loads that generate voltages Vinp and Vinn, respectively, in response to the current they receive. Because the ADC 5002 has a relatively high impedance, the current flows substantially into switched capacitors 5015 and 5017, resulting in corresponding voltage drops referenced to the supply voltage VDD or VSUPP and VINP and Vinn, respectively.

[0140] The current-voltage converter 5001 converts current BL+ to voltage Vinp and current BL- to voltage Vinn. Switches 5011 and 5012 are closed to apply Vinp and Vinn as inputs to the analog-to-digital converter (ADC) 5002, which converts the analog voltage to the digital signal DOUT[n:0].

[0141] Figure 51 shows an output block 5100 for a column pair. Although only one output block 5100 for a column pair is shown, it should be understood that instantiations of output blocks 5100 for column pairs are used for each pair of columns in the VMM array 2701. The output block 5100 for a column pair receives current BL+ from a first bit line coupled to one column of memory cells in the VMM array 2701 and current BL- from a second bit line coupled to a memory cell in another column of the VMM array 2701, generating a digital output DOUT[n:0].

[0142] The row-pair output block 5100 comprises the current-voltage (ITV) converter 5001 and the SAR ADC 5102 described above with respect to Figure 50. The current-voltage converter 5001 converts the current BL+ to the voltage Vinp (first voltage) and the current BL- to the voltage Vinn (second voltage). The SAR ADC 5102 converts Vinp and Vinn to a digital signal DOUT[n:0] with a set of output bits. The S / H capacitors 5015 and 5017 in Figure 50 (which are loads that convert current from the bit lines to voltage) can be implemented using capacitor arrays 5115 and 5117 within the SAR 5102. This sharing of circuits for different functions reduces the area of ​​space used within the semiconductor die. As shown in Figure 51, the output voltages of the ITVs connected to BL+ and BL- are connected to the negative and positive terminals of the SAR ADC 5102, respectively.

[0143] The outputs of the ADC 4802 in FIG. 48, the ADC 4902 in FIG. 49, the ADC 5002 in FIG. 50, the SAR ADC 5102 in FIG. 51, the ADC 5307 in FIGS. 53 and 54, and the ADC 5503 in FIG. 55 effectively implement differential weights as W = W+ - W-, where W+ is the positive weight stored in the cell coupled to the bit line BL+, and W- is the negative weight stored in the cell coupled to the bit line BL-. For example, in the case of an 8-bit ADC, when IBL+ = Imax and IBL- = Imin, the ADC output = 255. When IBL+ = Imin and IBL- = Imax, the ADC output = 0. Exemplary values are Imax = 20 μA and Imin = 0 μA.

[0144] FIG. 52 shows a verification circuit 5200 used to verify the values stored in one or more memory cells coupled to bit lines. The current source 5201 represents the current IBL2 drawn by the bit line. The verification circuit includes a multiplexer 5202 (only one of its switches is shown), an operational amplifier 5203, a capacitor 5204, and a comparator 5205 (a 1-bit ADC in this example). The non-inverting input of the operational amplifier 5203 is coupled to a reference voltage VREFL (e.g., 0.6 V, the voltage applied to the bit line of the read cell), and the inverting input of the operational amplifier 5203 is coupled to receive IBL2 when the multiplexer 5202 passes IBL2. The capacitor 5204 is disposed between the output of the operational amplifier 5203 and the inverting input of the operational amplifier 5203. The capacitor 5204 is used to convert the cell current IBL2 to a voltage VBL2. The comparator 5205 compares the received voltage VBL2 with a target value, the reference voltage VREF_VFY. The verification circuit 5200 receives the current IBL2 and, during the verification operation, generates a digital signal DOUT that is a first value (e.g., "1") when the verification operation is successful (i.e., when VBL2 is ≧ VREF_VFY) and a second value (e.g., "0") when the verification operation is unsuccessful (i.e., when VBL2 < VREF_VFY), which means that one or more cells coupled to the bit line can receive tuning.

[0145] Figure 53 shows a read circuit 5300 used to read values ​​stored in differential memory cells coupled to a first bit line and a second bit line in an array of memory cells, where IBL1 is the current drawn in by the first bit line coupled to the first column of cells in the array, and IBL2 is the current drawn in by the second bit line coupled to the second column of cells in the array, and the read circuit 5300 is used to generate differential digital output bits by a differential ADC.

[0146] The readout circuit 5300 includes a current-voltage converter 5310 (first current-voltage converter), a current-voltage converter 5311 (second current-voltage converter), and a differential ADC 5307 (which may be a SAR ADC or another type of ADC).

[0147] The current-voltage converter 5310 comprises an operational amplifier 5301 (first operational amplifier) ​​(or an equivalent adjustment circuit), a load 5302 (a first load which may comprise one or more resistors, capacitors, or transistors), and an NMOS transistor 5303 (first transistor). The load 5302 comprises a first terminal coupled to a voltage source VDD and a second terminal. The NMOS transistor 5303 comprises a first terminal coupled to the second terminal of the load 5302, a gate, and a second terminal coupled to a first bit line. The operational amplifier 5301 comprises an inverting input coupled to a first bit line, an inverting input coupled to VREF1 (first reference voltage), and an output coupled to the gate of the NMOS transistor 5303.

[0148] The current-voltage converter 5311 comprises an operational amplifier 5304 (a second operational amplifier) ​​(or an equivalent adjustment circuit), a load 5305 (a second load which may comprise one or more resistors, capacitors, or transistors), and an NMOS transistor 5306 (a second transistor). The load 5305 comprises a first terminal coupled to the voltage source VDD and a second terminal. The NMOS transistor 5306 comprises a first terminal coupled to the second terminal of the load 5305, a gate, and a second terminal coupled to the second bit line. The operational amplifier 5304 comprises an inverting input coupled to the second bit line, an inverting input coupled to VREF2 (a second reference voltage which may be the same as or different from VREF1), and an output coupled to the gate of the NMOS transistor 5303.

[0149] The ADC 5307 comprises a first input coupled to a second terminal of a first load, a second input coupled to a second terminal of a second load, and an output for generating a set of output bits.

[0150] Therefore, the non-inverting inputs of operational amplifiers 5303 and 5304 are coupled to the reference voltage Vref, respectively, and the sources of regulating transistors 5306 and 5303 are connected to the inverting inputs of operational amplifiers 5304 and 5301, respectively. Thus, the source voltages of transistors 5306 and 5303 are driven to be equal to VREF, which means that the voltages of BL1 and BL2 coupled to the selected cells are driven to the VREF voltage. Here, the voltages supplied to the inverting and non-inverting terminals of ADC 5307 are referenced to the supply voltage VDD and are the result of a voltage drop from the supply voltage equal to the currents IBL2 and IBL1 passing through loads 5305 and 5302, respectively. The output of the ADC effectively implements W = W+-W-.

[0151] Figure 54 shows a readout circuit 5400 used to read values ​​stored in a differential memory cell coupled to a first bit line and a second bit line, where IBL1 is the current drawn by the first bit line and IBL2 is the current drawn by the second bit line. The readout circuit 5400 includes operational amplifiers 5401 and 5402 (or equivalent adjustment circuits), loads 5403 and 5404 (which may include one or more resistors, capacitors, or transistors), NMOS transistors 5405 and 5406, PMOS transistors 5407, 5408, 5409, and 5410, and a differential ADC 5411 (which may be a SAR ADC or another type of ADC). PMOS transistors 5407 and 5408 form a current mirror that mirrors the bit line current IBL2 to the load 5403. PMOS transistors 5409 and 5410 form a current mirror that mirrors the bit line current IBL1 to the load 5404. Here, the voltages supplied to the inverting and non-inverting terminals of the ADC 5411 are referenced to ground and are the result of a voltage gain relative to ground equal to the currents IBL2 and IBL1 passing through loads 5403 and 5404, respectively. The output of the ADC 5411 effectively implements W = W+-W-.

[0152] Figures 55 and 56 show examples of readout circuits equipped with level shifters.

[0153] In Figure 55, the readout circuit 5500 comprises a current-voltage converter 5501, a level shifter 5502, and an analog-to-digital converter 5503, which convert the currents received from the VMM array 2701 as BL+ and BL- into a digital output DOUT[n:0] containing a set of output bits. The current-voltage converter 5501 converts BL+ (first current) to V1 (first voltage) and BL- (second current) to V2 (second voltage), where BL+ and BL- are differential currents. The level shifter 5502 converts V1 to Vinp (third voltage) and V2 to Vinn (fourth voltage), where the third voltage is different from the first voltage and the fourth voltage is different from the second voltage. The analog-to-digital converter 5503 converts Vinp and Vinn into DOUT[n:0].

[0154] In Figure 56, the readout circuit 5600 includes a current-voltage converter 5601, a level shifter 5602, and an analog-to-digital converter 5603, which convert the current received as BL from the VMM array 2701 into a digital output DOUT[n:0] containing a set of output bits. The current-voltage converter 5601 converts BL (first current) to V1 (first voltage). The level shifter 5602 converts V1 to Vinp (second voltage), which is different from the first voltage. The analog-to-digital converter 5603 converts Vinp and Vinn into DOUT[n:0].

[0155] The use of level shifters 5502 and 5602 in Figures 55 and 56 may be advantageous, for example, when current-voltage converters 5501 and 5502 are operating in a first voltage range (e.g., supply voltage Vdd = 1.8V) and a second voltage range (e.g., supply voltage Vdd = 1.0V) is provided to ADC 5503 or 5603 to increase speed and utilize less area within the semiconductor die.

[0156] Figure 57A shows a level shifter 5700 that can be used as the level shifter 5502 in Figure 55. The level shifter 5700 comprises a source follower configuration NMOS transistor 5701 (first transistor) and current source 5702 (first current source), and a source follower configuration NMOS transistor 5703 (second transistor) and current source 5704 (second current source). The NMOS transistor 5701 comprises a first terminal coupled to VDD2 (supply voltage), a gate for receiving an input voltage V1 (first voltage), and a second terminal for supplying an output voltage Vinp (third voltage). The current source 5702 comprises a first terminal coupled to the second terminal of the NMOS transistor 5701 and a second terminal coupled to a common node 5705 which may be ground or another voltage. The NMOS transistor 5703 includes a first terminal connected to VDD2 (supply voltage), a gate that receives the input voltage V2 (second voltage), and a second terminal that supplies the output voltage Vinn (fourth voltage). The current source 5704 includes a first terminal connected to the second terminal of the NMOS transistor 5703 and a second terminal connected to the common node 5705.

[0157] The level shifter 5700 receives differential input voltages V1 and V2 and generates differential output voltages Vinp and Vinn. Vinp = V1 - dV1, where dV1 is determined by the threshold voltage and current bias 5702 of the NMOS transistor 5701. Vinn = V2 - dV2, where dV2 is determined by the threshold voltage and current bias 5704 of the NMOS transistor 5703. V1 and V2 are in a first voltage region, while Vinp and Vinn are in a second voltage region different from the first voltage region. For example, V1 and V2 may be in the 1.8V voltage region, and Vinp and Vinn may be in the 1V voltage region.

[0158] Figure 57B shows a level shifter 5710 that can be used as the level shifter 5710 in Figure 56. The level shifter 5710 comprises a source follower configuration NMOS transistor 5711 (first transistor) and a current source 5712 (first current source). The NMOS transistor 5711 comprises a first terminal coupled to VDD2 (supply voltage), a gate that receives an input voltage V1 (first voltage), and a second terminal that provides an output voltage Vinp (second voltage). The current source 5712 comprises a first terminal coupled to the second terminal of the NMOS transistor 5711 and a second terminal coupled to a common node 5705 which may be ground or another voltage. The NMOS transistor 5703 comprises a first terminal coupled to VDD2 (supply voltage), a gate that receives an input voltage V2 (second voltage), and a second terminal that provides an output voltage Vinn (fourth voltage). The current source 5704 includes a first terminal connected to the second terminal of the NMOS transistor 5703 and a second terminal connected to node 5713, which may be ground or another voltage.

[0159] The level shifter 5710 receives an input voltage V1 and generates an output voltage Vinp. Vinp = V1 - dV1, where dV1 is determined by the threshold voltage and current bias 5712 of the NMOS transistor 5711. V1 is in a first voltage region, and Vinp is in a second voltage region different from the first voltage region. For example, V1 may be in the 1.8V voltage region, and Vinp may be in the 1V voltage region.

[0160] Figure 58 shows a column pair output block 5800. Although only one column pair output block 5800 is shown, it should be understood that an instantiation of the column pair output block 5800 is used for each column pair in the VMM array 2701. The column pair output block 5800 receives current BL+ from a first bit line coupled to one column of nonvolatile memory cells in the VMM array 2701 and current BL- from a second bit line coupled to another column of nonvolatile memory cells in the VMM array 2701, generating a digital output DOUT[n:0].

[0161] The output block 5800 for the row pair comprises a current-voltage (ITV) converter 5801 and a differential analog-to-digital converter (ADC) 5802. The ADC 5802 may be, but is not limited to, a SAR ADC (successive approximate register ADC), a slope ADC, a sigma-delta ADC, or an algorithm (also known as cyclic) ADC. The current-voltage converter 5801 comprises a BL+ adjustment circuit 5817, a BL- adjustment circuit 5817, switches 5820 and 5821, and a load 5819 (which may comprise one or more resistors, capacitors, MOS transistors, or other loads). The current-voltage converter 5801 converts the current BL+ to a voltage Vinp (first voltage) and the current BL- to a voltage Vinn (second voltage).

[0162] The BL+ adjustment circuit 5817 comprises a regulator 5803 (sometimes called a forcing regulator or current carrier regulator), a first switch set 5805 (equipped with one or more switches), an adjustment (cascode) NMOS transistor 5807, a switch 5809, and a switch 5811.

[0163] The BL-adjustment circuit 5818 comprises a regulator 5804 (which can be called a forcing regulator or current-carrying regulator), a second switch set 5806 (which includes one or more switches), an adjustment (cascode) NMOS transistor 5808, a switch 5810, and a switch 5812.

[0164] Regulator 5803 includes a third switch set 5813 (including one or more switches) and an operational amplifier 5815 (or equivalent adjustment circuit). Regulator 5804 includes a fourth switch set 5814 (including one or more switches) and an operational amplifier 5816 (or equivalent adjustment circuit).

[0165] In the case of a circuit path connecting bit line BL+ (the first bit line), switch sets 5805 and 5813 are part of a column multiplexer that multiplexes each first bit line from the VMM array 2701 to the current-voltage converter 5801. Specifically, the column multiplexer selects bit line BL+ by closing switch sets 5805 and 5813. Conventional column multiplexers use only the equivalent of switch set 5805, which conducts bit line current from the VMM array 2701 to the current-voltage converter 5801 (which may also be called the output circuit or sense circuit). The example shown here adds switch set 5813, which is part of a sense multiplexer (YMUX-S) that does not carry current due to the high impedance of the operational amplifier 5815. Under this configuration, the bit lines coupled to switch sets 5805 and 5813, namely the inverting input of operational amplifier 5815 and the source of NMOS transistor 5807 (the terminal of NMOS transistor 5807 coupled to bit line BL+), have substantially the same voltage, but switch set 5805 carries current, while switch set 5813 does not carry substantially current. When switch sets 5805 and 5813 are closed, the bit line voltage is initially lower or higher than VBLRD, which increases or decreases the output voltage of operational amplifier 5815, thereby turning on NMOS transistor 5807 more strongly or weaker, and maintaining the voltage at BL+ to be the same as VBLRD. As the gate voltage of NMOS transistor 5807 increases, the current flowing through NMOS transistor 5807 increases, and the source voltage of NMOS transistor 5807 also increases until the bit line voltage becomes equal to VBLRD.

[0166] In the case of a circuit path connecting bit line BL- (first bit line), switch sets 5806 and 5814 are part of a column multiplexer that multiplexes each bit line from the VMM array 2701 to the current-voltage converter 5801. Specifically, the column multiplexer selects each bit line BL- by closing switch sets 5806 and 5814. Conventional column multiplexers use only the equivalent of switch set 5806, which conducts bit line current from the VMM array 2701 to the current-voltage converter 5801 (which may also be called the output circuit or sense circuit). The example shown here adds switch set 5814, which is part of a sense multiplexer (YMUX-S) that does not carry current due to the high impedance of the operational amplifier 5816. Under this configuration, the lines coupled to switch sets 5806 and 5814, namely the inverting input of operational amplifier 5816 and the source of NMOS transistor 5808 (the terminal of NMOS transistor 5808 coupled to bit line BL-), have substantially the same voltage, but switch set 5806 carries current and switch set 5814 does not carry substantially current. When switch sets 5806 and 5814 are closed, the voltage on the bit line is initially lower or higher than VBLRD, which increases or decreases the output voltage of operational amplifier 5816, thereby turning on NMOS transistor 5808 more strongly or weakly, maintaining the voltage at BL- the same as VBLRD. As the voltage at the gate of NMOS transistor 5808 increases, the current flowing through NMOS transistor 5808 increases, and the voltage at the source of NMOS transistor 5808 also increases until the voltage on the bit line becomes equal to VBLRD. The shared ITV load 5819 is shared between two bit lines (differential bit lines BL+ and BL-), and the first end of the load 5819 is coupled to the drains of NMOS transistors 5807 and 5808, respectively, via switches 5811 and 5812. It will convert the current from IBL+ or IBL- into a voltage applied to the ADC 5802 in a time-multiplexed manner, first to operate IBL+, then IBL-. Sharing the load in this way reduces the area. The second end of the load 5819 is coupled to VDD or VSUP.Alternatively, the ITV load 5819 can be shared by more than two bit lines, such as four or 128.

[0167] Figure 59 shows a column pair output block 5900. Although only one column pair output block 5900 is shown, it should be understood that an instantiation of the column pair output block 5900 is used for each column pair in the VMM array 2701. The column pair output block 5900 receives current BL+ from a first bit line coupled to one column of nonvolatile memory cells in the VMM array 2701 and current BL- from a second bit line coupled to another column of nonvolatile memory cells in the VMM array 2701, generating a digital output DOUT[n:0].

[0168] The output block 5900 of the row pair comprises a current-voltage (ITV) converter 5901 and a differential analog-to-digital converter (ADC) 5902. The ADC 5902 may be, but is not limited to, a SAR ADC (successive approximate register ADC), a slope ADC, a sigma-delta ADC, or an algorithm (also known as cyclic) ADC. The current-voltage converter 5901 converts the current BL+ to the voltage Vinp (first voltage) and the current BL- to the voltage Vinn (second voltage).

[0169] The current-voltage converter 5901 comprises the BL+ adjustment circuit 5817 described above with reference to Figure 58, which is not described again for efficiency reasons. The current-voltage converter 5901 further comprises the BL- adjustment circuit 5903, which comprises a regulator 5904, a third switch set 5905 (equipped with one or more switches), a fourth switch set 5906 (equipped with one or more switches), an adjustment (cascode) NMOS transistor 5907, and switches 5909 and 5910. The current-voltage converter 5901 further comprises switches 5912, 5913, and 5914 and a load 5915 (which may comprise a capacitor, resistor, or other load).

[0170] The circuit path connecting bit line BL+ (the first bit line) operates as shown in Figure 58.

[0171] In the case of a circuit path connecting bit line BL- (the first bit line), switch sets 5905 and 5906 are part of a column multiplexer that multiplexes the bit line from the VMM array 2701 to the current-voltage converter 5901. Specifically, the column multiplexer selects bit line BL- by closing switch sets 5905 and 5906. Conventional column multiplexers use only the equivalent of switch set 5906 that conducts the bit line current from the VMM array 2701 to the current-voltage converter 5901 (which may also be called the output circuit or sense circuit). The example shown here adds switch set 5905, which is part of a sense multiplexer (YMUX-S) that does not carry current due to the high impedance of the operational amplifier 5815. Under this configuration, the lines coupled to switch sets 5905 and 5906 have substantially the same voltage, but switch set 5906 carries current, while switch set 5905 does not carry current. When switch sets 5905 and 5906 are closed, the bit line voltages initially become lower or higher than VBLRD, which increases or decreases the output voltage of operational amplifier 5815, thereby turning on NMOS transistor 5907 more strongly or weaker, maintaining the voltage at BL- equal to VBLRD. As the gate voltage of NMOS transistor 5907 increases, the current flowing through NMOS transistor 5907 increases, and the source voltage of NMOS transistor 5907 also increases until the bit line voltage becomes equal to VBLRD. In this example, operational amplifier 5815 is shared between two bit lines BL+ and BL-, and load 5915 is shared between two bit lines BL+ and BL-. Alternatively, operational amplifier 5815 may be shared by more than two bit lines, and load 5915 may be shared by more than two bit lines.

[0172] Figure 60 shows an output block 6000 for multiple row pairs. The output block 6000 for a row pair comprises a current-voltage (ITV) converter 6001, a multiplexer 6050, and a differential analog-to-digital converter (ADC) 6002. The ADC 6002 may be, but is not limited to, a SAR ADC (successive approximate register ADC), a slope ADC, a sigma-delta ADC, or an algorithm (also known as cyclic) ADC.

[0173] The multiplexer 6050 is coupled to multiple row pairs within the VMM array 2701, and any pair within those row pairs can be connected to the current-voltage converter 6001. The connected row pair carries the currents BL+ and BL-, and this is understood to be the row pair selected by the multiplexer 6050.

[0174] The current-voltage converter 6001 converts current BL+ to voltage Vinp (first voltage) and current BL- to voltage Vinn (second voltage). The current-voltage converter 6001 includes the BL+ adjustment circuit 5817 described above with reference to Figure 58, which is not described again for efficiency reasons. The current-voltage converter 6001 further includes a BL- adjustment circuit 6003, which includes a regulator 6004, a third switch set 6005 (equipped with one or more switches), and a fourth switch set 6006 (equipped with one or more switches). The current-voltage converter 6001 further includes switches 6008 and 6009 and a load 6010 (which may be a capacitor, resistor, or other load).

[0175] The circuit path connecting bit line BL+ (the first bit line) operates as shown in Figure 58.

[0176] In the case of a circuit path connecting bit line BL- (first bit line), switch sets 6005 and 6006 are part of a column multiplexer that multiplexes bit lines from the VMM array 2701 to the current-voltage converter 6001. Specifically, the column multiplexer selects each bit line BL- by closing switch sets 6005 and 6006. Conventional column multiplexers use only a switch set equivalent to 6006 that conducts bit line current from the VMM array 2701 to the current-voltage converter 6001 (which may also be called the output circuit or sensing circuit). In the example shown here, a switch set 6005 is added that is part of a sensing multiplexer (YMUX-S) that does not carry current due to the high impedance of the operational amplifier 5815. In this configuration, the lines coupled to switch sets 6005 and 6006 have substantially the same voltage, but switch set 6006 carries current while switch set 6005 does not carry current. When switch sets 6005 and 6006 are closed, the bit line voltage is initially lower or higher than VBLRD, causing the output voltage of operational amplifier 5815 to increase or decrease, and NMOS transistor 5807 to turn on more strongly or weaker. This keeps the BL+ and BL- voltages the same as VBLRD. As the gate voltage of NMOS transistor 5807 increases, the current flowing through NMOS transistor 5807 increases, and the source voltage of NMOS transistor 5807 also increases until the bit line voltage becomes equal to VBLRD.

[0177] Figure 61 shows an output block 6100 for multiple columns, comprising a current-voltage (ITV) converter 6101, an ADC 6102, and a multiplexer 6150. The ADC 6102 may, but is not limited to, a SAR ADC (successive approximate register ADC), a slope ADC, a sigma-delta ADC, or an algorithm (also known as cyclic) ADC.

[0178] The multiplexer 6150 is coupled to multiple row pairs within the VMM array 2701, and any pair within those row pairs can be connected to the current-voltage converter 6101. The connected row pair carries the currents BL+ and BL-, and this is understood to be the row pair selected by the multiplexer 6150.

[0179] The current-voltage converter 6101 converts current BL+ to voltage Vinp (first voltage) and current BL- to voltage Vinn (second voltage). The current-voltage converter 6101 includes a BL+ adjustment circuit 5817 and a BL- adjustment circuit 5818, which have been previously described with reference to Figure 58 and will not be described again for efficiency.

[0180] The current-voltage converter 6101 further comprises switches 6103 and 6104 and a load circuit 6105. The load circuit 6105 is shared among multiple instances of the output block 6100 for multiple row pairs. The load circuit 6105 comprises a load 6106 (which may comprise a capacitor, resistor, MOS transistor, or other load), a load 6107 (which may comprise a capacitor, resistor, or other load), and switches 6108 and 6109. When switch 6103 is closed, load 6106 is coupled between the output of the BL+ adjustment circuit 5817 and VDD or VSUPP. When switch 6104 is closed, load 6107 is coupled between the output of the BL- adjustment circuit 5818 and VDD or VSUPP.

[0181] Figure 62 shows the VMM system 6200. The VMM system 6200 includes VMM arrays 6201 and 6202 (each an instance of VMM array 2701, indicated as BANK0 and BANK1, respectively), column multiplexers 6203 and 6204, and current-voltage converter and analog-to-digital converter block 6205 (including multiple output blocks based on the column pair output block 5800 in Figure 58, the column pair output block 5900 in Figure 59, the multi-column output block 6000 in Figure 60, or the multi-column output block 6100 in Figure 61). In this example, unselected bit lines from the unselected array of VMM arrays 6201 and 6202 are used as capacitive loads that function as loads for load 5819 in Figure 58, load 5915 in Figure 59, load 6010 in Figure 60, and loads 6106 and 6107 in Figure 61.

[0182] Figure 63 shows a load 6300 that can be used for any of the loads 5302 and 5305 in Figure 53, loads 5403 and 5404 in Figure 54, load 5819 in Figure 58, load 5915 in Figure 59, load 6010 in Figure 60, and loads 6106 and 6107 in Figure 61. The load 6300 includes one or more resistors, capacitors, transistors, bit lines (such as unselected bit lines in an unselected memory array as described above with reference to Figure 62), or other devices 6301 coupled to the first terminal 6302 and the second terminal 6303.

[0183] The high supply for the ITV load in Figures 49, 50, 51, 53, 54, 58, 59, 60, and 61 can come from a global voltage regulation circuit or a local voltage regulation circuit such as a local replica voltage supply circuit.

[0184] It should be noted that, as used herein, the terms “over” and “on” both encompass “directly” (no intermediate material, element, or gap is located between them) and “indirectly to” (intermediate material, element, or gap is located between them). Similarly, the term “adjacent” includes “directly adjacent” (no intermediate material, element, or gap is located between them) and “indirectly adjacent” (intermediate material, element, or gap is located between them); “attached” includes “directly attached” (no intermediate material, element, or gap is located between them) and “indirectly attached to” (intermediate material, element, or gap is located between them); and “electrically coupled” includes “directly electrically coupled” (no intermediate material or element electrically connecting the elements together between them) and “indirectly electrically coupled to” (intermediate material or element electrically connecting the elements together between them). For example, forming an element "on top of a substrate" may include forming the element directly on the substrate without any intermediate materials / elements between them, and forming the element indirectly on the substrate with one or more intermediate materials / elements between them.

Claims

1. It is a system, An array of non-volatile memory cells arranged in multiple rows and multiple columns, wherein the array comprises a first bit line coupled to a first column of non-volatile memory cells and a second bit line coupled to a second column of non-volatile memory cells. An output block coupled to the array, wherein the output block is A current-voltage converter for converting a first current on the first bit line into a first voltage and a second current on the second bit line into a second voltage, A system comprising: an output block, which includes an analog-to-digital converter for converting one or more of the first voltage and the second voltage into a set of output bits.

2. The system according to claim 1, further comprising a first switch that, when closed, applies the first voltage to the first input of the analog-to-digital converter.

3. The system according to claim 2, further comprising a second switch that, when closed, applies the second voltage to the first input of the analog-to-digital converter.

4. The system according to claim 1, wherein the analog-to-digital converter has a reference input that receives a reference voltage, and the set of output bits is generated by comparing one or more of the first voltage and the second voltage with the reference voltage.

5. The system according to claim 4, further comprising a first switch that, when closed, applies the first voltage to the first input of the analog-to-digital converter.

6. The system according to claim 1, wherein the analog-to-digital converter comprises a comparator having an inverting input and a non-inverting input, the non-inverting input receiving a reference voltage.

7. The system according to claim 1, wherein the analog-to-digital converter comprises a successive approximation (SAR) analog-to-digital converter.

8. The current-voltage converter is A first switch set coupled to the first bit line, A second switch set coupled to the first bit line, A third switch set coupled to the second bit line, The system according to claim 1, further comprising a fourth switch set coupled to the second bit line.

9. The system according to claim 1, wherein the current-voltage converter comprises one or more resistors and capacitors for converting current to voltage.

10. The system according to claim 9, wherein the voltage is referenced to a voltage supply or ground.

11. The current-voltage converter comprises a load shared across multiple bit lines for converting current to voltage, according to claim 1.

12. The system according to claim 11, wherein the analog-to-digital converter is shared by a plurality of current-voltage converters.

13. The system according to claim 11, wherein the load comprises one or more of a resistor and a capacitor.

14. The system according to claim 11, wherein the load includes an unselected bit line.

15. The system according to claim 14, wherein the unselected bit lines are located in an unselected memory array.

16. The system according to claim 9, wherein one or more terminals of the resistor and the capacitor are connected to a supply voltage.

17. The system according to claim 16, wherein the current-voltage converter comprises the capacitor, and the capacitor is shared with the analog-to-digital converter.

18. The system according to claim 1, wherein the output bits indicate the difference weights stored in the array.

19. It is a circuit, A current-voltage converter for converting a first current to a first voltage and a second current to a second voltage, wherein the first current and the second current are differential currents, A level shifter for converting the first voltage to a third voltage and the second voltage to a fourth voltage, A circuit comprising: an analog-to-digital converter for converting the third voltage and the fourth voltage into a set of output bits.

20. The aforementioned level shifter is A first transistor comprising a first terminal coupled to a supply voltage, a gate for receiving the first voltage, and a second terminal for providing the third voltage, The circuit according to claim 19, comprising a first current source having a first terminal coupled to the second terminal of the first transistor and a second terminal coupled to a common node.

21. The aforementioned level shifter is A second transistor comprising a first terminal coupled to the supply voltage, a gate for receiving the second voltage, and a second terminal for providing the fourth voltage, The circuit according to claim 20, comprising a second current source having a first terminal connected to the second terminal of the second transistor and a second terminal connected to a common node.

22. It is a circuit, A current-voltage converter for converting a first current to a first voltage, A level shifter for converting the first voltage to a second voltage, A circuit comprising: an analog-to-digital converter for converting the second voltage into digital output bits.

23. The aforementioned level shifter is A transistor comprising a first terminal coupled to a source voltage, a gate for receiving the first voltage, and a second terminal for providing the second voltage, The circuit according to claim 22, comprising a current source having a first terminal coupled to the second terminal of the transistor and a second terminal coupled to a common node.

24. It is a circuit, A first bit line coupled to the first column of memory cells in the array of memory cells, A second bit line coupled to the second column of memory cells in the array, A first current-voltage converter, A first load having a first terminal and a second terminal coupled to a voltage source, A first transistor comprising a first terminal coupled to the second terminal of the first load, a gate, and a second terminal coupled to the first bit line, A first current-voltage converter comprising: a first operational amplifier having an inverting input coupled to the first bit line, an inverting input coupled to a first reference voltage, and an output coupled to the gate of the first transistor; A second current-voltage converter, A second load having a first terminal and a second terminal coupled to the voltage source, A second transistor comprising a first terminal coupled to the second terminal of the second load, a gate, and a second terminal coupled to the second bit line, A second current-voltage converter comprising: a second operational amplifier having an inverting input coupled to the second bit line, a non-inverting input coupled to a second reference voltage, and an output coupled to the gate of the second transistor; A circuit comprising: a first input coupled to the second terminal of the first load; a second input coupled to the second terminal of the second load; and an analog-to-digital converter having an output for generating a set of output bits.

25. The method according to claim 24, wherein the analog-to-digital converter includes a successive approximation (SAR) analog-to-digital converter.

26. It is a circuit, Bit lines coupled to rows of memory cells in an array of memory cells, A multiplexer that selects the bit line for verification, An operational amplifier comprising a non-inverting input for receiving a first reference voltage, an inverting input coupled to the bit line by the multiplexer during the verification operation, and an output, A capacitor coupled between the inverting input and the output of the operational amplifier, A circuit comprising: a comparator that compares the output of the operational amplifier with a reference voltage.

27. It is a system, An array of non-volatile memory cells arranged in multiple rows and multiple columns, wherein the array comprises a first bit line coupled to a first column of non-volatile memory cells and a second bit line coupled to a second column of non-volatile memory cells. An output block coupled to the array, wherein the output block is A current-voltage converter for converting the current on the first bit line into a first voltage and the current on the second bit line into a second voltage, A system comprising: an analog-to-digital converter for converting the first voltage and the second voltage into a set of output bits.

28. The current-voltage converter converts the first current to the first voltage by passing the first current through a shared load, according to claim 27.

29. The system according to claim 28, wherein the voltage is based on the supply voltage or ground.

30. It is a method, A step of converting a first current on a first bit line coupled to a first column of a nonvolatile memory cell in an array of nonvolatile memory cells arranged in multiple rows and multiple columns into a first voltage, The steps include converting a second current on a second bit line coupled to a second column of non-volatile memory cells in the array into a second voltage, A method comprising the step of converting one or more of the first voltage and the second voltage into a set of output bits.

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