Multi-chip module and method for manufacturing the same

Abstract

This specification discloses a multichip module having an open / exposed / bare back surface including a heatsink. The heatsink is configured for heat dissipation from the multichip module and comprises one or more electronic components and a front surface including a coreless interposer, each of which layers comprises a plurality of conductive wires / pads and one or more gaps between the plurality of conductive wires / pads, the one or more gaps being filled with insulating material, the one or more electronic components being positioned between the coreless interposer and the heatsink, and the front surface being configured for electrical communication with external electrical components.

Description

Technical Field

[0001] The present disclosure generally relates to semiconductor devices, and more particularly, to multi-chip modules and methods of manufacturing the same.

Background Art

[0002] The continuing need and effort to minimize semiconductor devices, reduce power consumption, and improve their performance currently faces several challenges. One of the main challenges is due to the use of a printed circuit board (PCB) and a package assembly of semiconductor dies, chips, or integrated circuits mounted thereon. The purpose of the substrate is to connect packaged integrated circuits, passive electronic components, and other components to a working device / system. However, since the substrate is prone to warping, it is difficult to manufacture a flat base. Packaged dies are typically connected to the substrate via solder bumps. These solder bumps are melted and re-solidified during the manufacturing process. Since there are limitations to soldering techniques, combined with surface warping, this leads to placing solder bumps at least 0.5 millimeters apart. As a result, a large distance is required between each circuit component, thus resulting in a decrease in signal transmission speed, an increase in power consumption, low resolution (due to an increase in the distance between conductive pads on the printed circuit board), and inefficient heat transfer. In other words, package design is currently limited by the number / density of inputs / outputs and heat dissipation, and thus limits the speed of the device and increases power consumption. This bottleneck is particularly important for data-intensive applications such as graphics (rendering), machine learning, etc.

[0003] To overcome these challenges, several approaches have been developed, such as system-on-a-chip (SoC) design, in which a single large chip integrates different components such as a central processing unit, graphics, and memory interfaces, instead of each component being mounted separately. SoC chips improve performance by shortening the distance between each component. However, when an SoC is mounted on a substrate, it inevitably loses its advantages due to the limitations of the substrate. Furthermore, the increasing size and complexity of each SoC increases the number of defects during the advanced and expensive manufacturing process, leading to a decrease in yield.

[0004] Instead of integrating all or most components onto a single chip, an additional current approach is to fabricate smaller modules that contain multiple integrated circuits embedded in a single device (a multi-chip module (MCM)). Conventional MCMs typically mount an interposer fabricated from a silicon or glass substrate with drilled vertical electrical connections (e.g., through-vias). Mounting components directly onto the interposer solves several challenges. However, the interposer needs to have large contact pads that must be mounted on the substrate, thereby limiting their resolution and heat dissipation. Furthermore, fabricating through-vias to interconnect the top and bottom contact pads of the interposer (to enable interconnection between the chip and the PCB) is expensive, especially for thin interposers, which are prone to cracking and warping and are limited by line / space resolution. [Overview of the project]

[0005] Aspects of this disclosure, according to some embodiments thereof, relate to semiconductor devices. More specifically, aspects of this disclosure, though not exclusive, according to some embodiments thereof, relate to multichip modules and methods for manufacturing the same.

[0006] Accordingly, according to one aspect of several embodiments, a multichip module is provided. According to some embodiments, the multichip model comprises an open / exposed / bare back surface including a heatsink, a front surface including an interposer, and one or more electronic components. The one or more electronic components are positioned between the interposer and the heatsink, and the front surface is configured for electrical communication with other / external components or devices.

[0007] According to some embodiments, a multi-chip module is provided comprising an open / exposed / bare back surface including a heatsink, one or more electronic components, and a front surface including a coreless interposer. The heatsink is configured for heat dissipation from the multi-chip module. The coreless interposer comprises a plurality of layers, each of which comprises a plurality of conductive wires / pads and one or more gaps between the plurality of conductive wires / pads. The one or more gaps are filled with insulating material, the one or more electronic components are positioned between the coreless interposer and the heatsink, and the front surface is configured for electrical communication with external electrical components.

[0008] According to some embodiments, the disclosed multichip module includes conductive wires dispersed between dielectric layers and one or more electronic components (including, but not limited to, bare integrated circuit dies) arranged and connected to the conductive wires. Advantageously, in some embodiments, it enables the design and manufacture of small and lightweight electronic devices (including, but not limited to, wearable electronic devices). Advantageously, in some embodiments, it enables the design and manufacture of high-performance computers, service centers, and the like.

[0009] According to some embodiments, the disclosed multichip module includes electrical connections between each of one or more electronic components, having lengths and widths substantially similar to those of the electrical connections within one or more electronic components. Advantageously, in some embodiments, the number of electrical connections between each of the one or more electronic components can be increased. This enables miniaturization, high-speed signal / data transfer, and consequently, reduced power consumption.

[0010] Advantageously, the disclosed multi-chip module configuration allows for enhanced heat dissipation. This can improve thermal performance, reduce power consumption, and enhance yield and performance. In some embodiments, placing powerful dies substantially directly on a heatsink substantially / effectively eliminates limitations on heat dissipation.

[0011] Those skilled in the art will understand that defects and malfunctions (including fatal defects) are possible during die manufacturing. Furthermore, the probability of defects increases exponentially with increasing die area. Advantageously, in some embodiments, the disclosed multi-chip modules and their manufacturing methods significantly reduce the probability of such defects (as small bare dies are mounted and electrically interconnected therein), resulting in high yield.

[0012] It can be further understood by those skilled in the art that one of the major losses in the yield of microcircuits is due to the ultra-high density of the underlying metal layer (e.g., the solder layer), and also to the aforementioned manufacturing defects (e.g., particularly, large transistors (in terms of area)). In some embodiments, the multichip modules disclosed herein may be advantageously devoid of large transistors (e.g., by arranging small and / or individual and / or bare dies / transistors). In some embodiments, the multichip modules disclosed herein may be advantageously devoid of the ultra-high density of the underlying metal layer, thereby increasing their reliability and yield.

[0013] Advantageously, multichip modules and methods for manufacturing them, as disclosed in some embodiments, may lack packaging. Advantageously, multichip modules and methods for manufacturing them, as disclosed in some embodiments, do not include a printed circuit board (PCB), thus eliminating the limitations associated therewith. As a result, in some embodiments, the input / output ports of one or more electronic components (e.g., chips) of the multichip module may be located at significantly smaller distances compared to the distance between them in a typical board (e.g., a distance of about 500 μm in a typical board design). According to some embodiments, the distance between the input / output ports of one or more electronic components of a multichip module disclosed herein may be about 20 μm or less, about 10 μm or less, about 8 μm or less, about 6 μm or less, about 5 μm or less, about 4 μm or less, about 2.5 μm or less, about 2.5 to 10 μm, about 5 to 10 μm, or about 2.5 to 5 μm. Each possibility is a separate embodiment. In some embodiments, the disclosed multi-chip module may enable an increase in the number of input / output ports by approximately 2500 times (for example, without using a case as a space converter).

[0014] Advantageously, in some embodiments, the disclosed multi-chip modules enable heterogeneous integration of one or more electronic components, thereby enabling the design and manufacture of a wide variety of systems. According to some embodiments, the disclosed multi-chip modules enable the combination of different die types, generations, materials, and technologies. As non-limiting examples, Si, SiC, GaN, GaAs, and InP transistors and / or diodes, resistors, capacitors, inductors, optical devices, RF and DC component elements, or any combination thereof, can be conveniently integrated into a single system / module.

[0015] According to some embodiments, the input / output port pitch of a multichip module may be approximately 20 µm or less.

[0016] According to some embodiments, one or more electrical components of a multichip module may include one or more of the following: bare dies, chips, micromechanical systems (MEMS), memory interfaces, input / output devices, graphics processing units, wireless modems, passive components, processors, analog integrated circuits, RF integrated circuits, voltage regulator modules, or any combination thereof. According to some embodiments, passive components may include inductors and / or capacitors, etc.

[0017] According to some embodiments, the insulating material of the coreless interposer may be made from or include one or more polymers.

[0018] According to some embodiments, the space between one or more electronic components may be filled with a molding material.

[0019] According to some embodiments, the molding material may be selected from polyimide, epoxy, benzocyclobutene (BCB), or any combination thereof.

[0020] According to some embodiments, the multi-chip module may further include a thermal interface material (TIM) configured to attach a heatsink to the back surface of one or more components.

[0021] According to some embodiments, the thermal interface material (TIM) may have a thickness of less than about 50 nanometers.

[0022] According to some embodiments, the multiple conductive wires / pads may be made from or include copper, silver, gold, or other metals.

[0023] According to some embodiments, multichips may be suitable for use in analog circuits, digital circuits, RF circuits, and / or high-power circuits.

[0024] According to some embodiments, the multi-chip module may be a stand-alone system-in-package (SiP) module.

[0025] According to some embodiments, the distance between one or more electrical components may be about 100 um or less.

[0026] According to some embodiments, a method for manufacturing a multi-chip module is provided. The method includes positioning one or more electronic components on an inert carrier. The carrier includes a coating that enables controlled peeling from the carrier. The method further includes coating the one or more electronic components with a molding material such that the one or more electronic components are covered by the molding material and the space between the one or more electronic components is filled with the molding material, thereby obtaining a molded multi-component structure; grinding the molded multi-component structure until all of the back surfaces of the one or more electronic components within the multi-component structure are exposed; attaching a heat sink to the exposed back surfaces such that the front surface of the molded multi-component structure faces the carrier and the back surface of the multi-component structure faces the heat sink; and constructing a coreless interposer on the front surface of the multi-component structure.

[0027] According to some embodiments, the method further includes separating the inert carrier from the multi-component structure.

[0028] According to some embodiments, the method disclosed herein for manufacturing a multi-chip module is technically simple, highly reliable, and suitable for cost-effective mass production.

[0029] According to some embodiments, the method may not include a drilling step.

[0030] According to some embodiments, the interposer of the disclosed method may include multiple layers. Each of the multiple layers includes multiple conductive wires / pads and one or more voids between the multiple conductive wires / pads, the one or more voids being filled with insulating material.

[0031] According to some embodiments, the method may further include applying a coating to the carrier before positioning. The coating is configured to allow the penetration of a columnar object (pillar) attached to one or more electronic components while preventing the penetration of one or more electronic components.

[0032] According to some embodiments, the method may further include partially curing the coating before positioning one or more electronic components.

[0033] According to some embodiments, the method may further include curing a coating after positioning one or more electronic components.

[0034] According to some embodiments, the method may further include flattening the front surface of the multi-component structure after removal from the carrier and before the generation of the coreless interposer.

[0035] Certain embodiments of this disclosure may include some or all of the above advantages, or none of them. One or more other technical advantages will be readily apparent to those skilled in the art from the drawings, description and claims contained herein. Furthermore, while certain advantages have been listed above, various embodiments may include all or some of the listed advantages, or none of them.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meanings as those generally understood by those skilled in the art to whom this disclosure relates. In case of any conflict, the patent specification containing the definitions shall prevail. As used herein, the indefinite articles "a" and "an" mean "at least one" or "one or more" unless the context explicitly indicates otherwise.

[0037] Several embodiments of this disclosure are described herein with reference to the accompanying drawings. The description, together with the drawings, will make it clear to those skilled in the art how some embodiments may be carried out. The drawings are for illustrative purposes only and are not intended to show structural details of the embodiments in more detail than necessary for a basic understanding of this disclosure. For clarity, some objects shown in the drawings are not drawn to a constant scale. Furthermore, two different objects in the same drawing may be drawn to different scales. In particular, the scale of some objects may be significantly exaggerated compared to other objects in the same drawing. [Brief explanation of the drawing]

[0038] [Figure 1] Figure 1 schematically shows cross-sectional side views of a multi-chip module (MCM) according to several embodiments. [Figure 2A] Figure 2A schematically illustrates examples of methods for manufacturing MCM according to several embodiments. [Figure 2B] Figure 2B schematically illustrates examples of methods for manufacturing MCM according to several embodiments. [Figure 3A] Figure 3A schematically depicts side views of coreless interposers of MCM according to several embodiments. [Figure 3B] Figure 3B schematically depicts a top view of the coreless interposer shown in Figure 3A, according to several embodiments. [Figure 3C] Figure 3C schematically depicts top views of each of the multiple layers of the coreless interposer shown in Figure 3A, according to several embodiments. [Figure 4] Figure 4 shows flowcharts of methods for manufacturing a coreless interposer according to several embodiments. [Figure 5] Figure 5 schematically illustrates examples of additive manufacturing methods for forming conductive regions of coreless interposers according to several embodiments. [Figure 6] Figure 6 schematically illustrates examples of semiconductor additive manufacturing methods for forming conductive regions of coreless interposers according to several embodiments. [Modes for carrying out the invention]

[0039] (Detailed explanation) The principles, use, and implementation of the teachings herein can be better understood by referring to the accompanying description and drawings. A person skilled in the art will be able to implement the teachings herein without excessive effort or experimentation after carefully examining the description and drawings herein.

[0040] In the description and claims of this application, the words “include” and “have,” and their forms, are not limited to members of the list to which the words may be associated.

[0041] As used herein, the term “about” can be used to specify a value of a quantity or parameter (e.g., the length of a member) within a continuous range of values ​​in the vicinity (and including) a given (stated) value. According to some embodiments, “about” can specify a parameter value such that it is between 80% and 120% of a given value. For example, the statement “The length of the member is about 1 m” is equivalent to the statement “The length of the member is between 0.8 m and 1.2 m.” According to some embodiments, “about” can specify a parameter value such that it is between 90% and 110% of a given value. According to some embodiments, “about” can specify a parameter value such that it is between 95% and 105% of a given value.

[0042] As used herein, the terms “substantially” and “about” may be interchangeable according to some embodiments.

[0043] As used herein, according to some embodiments, the term “one or more electronic components” may refer to any circuit and / or electronic components mounted, attached, fixed, or otherwise incorporated into a multichip module. According to some embodiments, one or more electronic components may include, among other things, one or more of chips, semiconductor dies, semiconductor devices, micromechanical systems (MEMS), integrated circuits (e.g., application-specific integrated circuits), memory interfaces, input / output devices, graphics processing units, microprocessors, microcontrollers, logic chips (e.g., analog-to-digital converters), wireless modems, passive components, or any components thereof, and any combination thereof. Each possibility is a distinct embodiment. According to some embodiments, one or more electronic components may include, among other things, one or more silicon dies, silicon carbide dies (e.g., SiC metal oxide silicon field-effect transistors (MOSFETs)), gallium nitride dies (e.g., bare GaN high electron-mobility transistors (HEMTs), gallium arsenide (GaAs) dies, etc.), or any combination thereof. Each possibility is a separate embodiment. According to some embodiments, one or more electronic components may refer to bare components (such as bare dies, etc., but not limited to them).

[0044] In use herein, according to some embodiments, the terms “conductive region,” “electrical connection,” “contact pad,” “conductive line,” and “conductive pad” can be used interchangeably and may refer to any conductive portion, such as a conductive portion of a coreless interposer. According to some embodiments, conductive wires may be made from, or include, metals such as copper (Cu), gold (Au), silver (Ag), nickel (Ni), tin (Sn), titanium (Ti), or any alloy thereof, or may include them. Each possibility is a separate embodiment. According to some embodiments, conductive regions are configured to electrically interconnect, route, and / or reroute integrated circuit devices and / or components thereof, such as, but not limited to, microprocessors, memory devices, chipsets, graphics devices, one or more dies, or any combination thereof. According to some embodiments, conductive wires may refer, among other things, to electrical traces. In addition, or alternatively, in some embodiments, conductive wires may form conductive paths (vertical electrical connections) between multiple layers of a coreless interposer, as further detailed elsewhere herein. According to some embodiments, the conductive wire can form various types of vias, including, but not limited to, through vias, tented vias, blind vias, embedded vias, stacked vias, or any combination thereof. Each possibility is a separate embodiment. According to some embodiments, the vias disclosed herein are formed without perforation, in contrast to conventionally formed vias. According to some embodiments, the vias disclosed herein may be formed without etching, in contrast to conventionally formed vias.

[0045] According to several embodiments, a multi-chip model and a method for manufacturing the same are provided herein. According to some embodiments, the multi-chip model comprises a heatsink, one or more electronic components, and an open / exposed / bare back surface including a front surface with an interposer. The one or more electronic components are positioned between the interposer and the heatsink, and the front surface is configured for electrical communication with other / external components or devices.

[0046] Advantageously, the disclosed multi-chip module configuration allows for increased heat dissipation, thereby improving thermal performance, reducing power consumption, and enhancing the yield and performance of the electronic device. According to some embodiments, the electronic device may refer to, among other things, smartphones, tablets, laptops, televisions, wearable electronic devices (e.g., smartwatches), robots, video game consoles, network systems, digital cameras, aerospace electronics, RF modules, high-power communication devices, or any combination thereof.

[0047] According to some embodiments, the methods disclosed herein for manufacturing multichip modules are technically simple, cost-effective, reliable, and readily suitable for cost-effective mass production of multichip modules, as will be described in more detail elsewhere herein.

[0048] Refer to Figure 1, which schematically shows a cross-sectional side view of a multi-chip module (MCM) 100 according to several embodiments. Advantageously, in some embodiments, the MCM 100 enables miniaturization of the electronic device, improving the performance of the electronic device due to increased data transmission speed to and from it, and due to increased heat dissipation from the electronic device. Advantageously, in some embodiments, the MCM 100 reduces the power required for its operation.

[0049] According to some embodiments, the MCM100 may be a standalone system-in-package (SiP) module.

[0050] According to some embodiments, the MCM100 is suitable for use in analog, digital, RF, and / or high-power circuits.

[0051] According to some embodiments, the MCM100 includes a back surface 150 that exposes a heat sink 152, a front surface 160 having an interposer 162, and one or more electronic components 170a to d disposed between them.

[0052] According to some embodiments, the heatsink 152 on the back surface 150 is configured to directly dissipate heat (i.e., dissipate thermal energy) from the MCM 100 into the environment surrounding the MCM 100. Scenarios in which utilizing the heatsink 152 to improve heat dissipation may be particularly beneficial include MCMs used in high-power applications (e.g., MCM 100), in which a considerable amount of thermal energy is generated by the MCM.

[0053] According to some embodiments, the heat sink 152 may be made from or include SiC, AlN, diamond, Cu, or any combination thereof. According to some embodiments, the heat sink 152 may also include a fluid cooling sink / plate (e.g., a water cooling plate).

[0054] According to some embodiments, the heat sink 152 may be attached to the MCM 100 by an adhesive (e.g., a permanent adhesive film / layer). According to some embodiments, the heat sink 152 may be attached to the MCM 100 by a die mounting film. According to some embodiments, the heat sink 152 may be attached to the MCM 100 by a thermal interface material (TIM) 176. According to some embodiments, the thickness of the TIM 176 is selected to facilitate heat dissipation (e.g., by its phonon scattering properties). According to some embodiments, the thickness of the TIM 176 may be about 50 nm or less. According to some embodiments, the thickness of the TIM 176 may be about 40 nm or less. According to some embodiments, the thickness of the TIM 176 may be about 35 nm or less. According to some embodiments, the thickness of the TIM 176 may be about 30 nm or less. According to some embodiments, the thickness of the TIM 176 may be about 25 nm or less. According to some embodiments, the thickness of the TIM 176 may be about 20 nm or less. According to some embodiments, the thickness of the TIM 176 may be about 15 nm or less. According to some embodiments, the thickness of the TIM 176 may be about 10 nm or less. Each possibility is a separate embodiment. According to some embodiments, the MCM 100 includes a front surface 160 configured for electrical communication with external electrical components. According to some embodiments, an interposer 162 may be defined / formed / generated on the front surface 160. Alternatively, in some embodiments, the interposer 162 may be mounted on the front surface 160 of the MCM 100. According to some embodiments, the input / output ports of the interposer 162 are configured for electrical communication with external electrical components.

[0055] According to some embodiments, the interposer 162 may be a coreless (substrate-less) interposer, as will be described in more detail elsewhere in this specification. Alternatively, in some embodiments, the interposer 162 may include a substrate (not shown), such as glass, silicon, organic, or any other type of substrate. Each possibility is a separate embodiment.

[0056] According to some embodiments, the interposer 162 comprises multiple layers. According to some embodiments, each of the multiple layers comprises multiple conductive wires / pads 164 and one or more voids between the multiple conductive wires / pads 164. According to some embodiments, one or more voids are filled with thermal insulation material 166, as will be described in more detail elsewhere in this specification.

[0057] According to some embodiments, the multiple conductive wires / pads 164 may be made from or contain copper (Cu), silver (Ag), gold (Au), titanium (Ti), nickel (Ni), tin (Sn), or other metals or alloys thereof. According to some embodiments, the thermal insulation material 166 of the interposer 162 may contain one or more polymers. According to some embodiments, the thermal insulation material 166 may be made from or contain polyimide.

[0058] According to some embodiments, defining an interposer 162 on the front surface 160 allows for the formation of a fan-out package on the front surface 160, leaving the back surface 150 bare / open / exposed, thereby advantageously facilitating heat dissipation and minimizing warping of the MCM 100.

[0059] According to some embodiments, the MCM100 includes one or more electronic components 170a to d. In some embodiments, the MCM100 may include one electronic component (e.g., one chip). In other words, in some embodiments, the MCM100 may refer to a single-chip module.

[0060] According to some embodiments, the space between one or more electronic components 170a to d is filled with a molding material 174. According to some embodiments, the molding material 174 may be selected from polyimide, epoxy, benzocyclobutene (BCB), or any combination thereof.

[0061] According to some embodiments, the back surfaces of one or more electronic components 170a-d may be assembled / placed on the coating 106, as described in more detail elsewhere in this specification.

[0062] According to some embodiments, the input / output port pitch of the MCM100 may be about 20 μm or less. According to some embodiments, the input / output port pitch of the MCM100 may be about 15 μm or less. According to some embodiments, the input / output port pitch of the MCM100 may be about 10 μm or less. According to some embodiments, the input / output port pitch of the MCM100 may be about 8 μm or less. According to some embodiments, the input / output port pitch of the MCM100 may be about 5 μm or less. Each possibility is a separate embodiment.

[0063] As a non-limiting example, the input / output port pitch of the MCM100 may be approximately 10 μm or less. In contrast, the conventional input / output port pitch of a chip on a printed circuit board is approximately 500 μm. As a result, the MCM100 allows for the manufacture of an MCM100 that has the same area as a printed circuit board while increasing the number of input / output ports by 2500. Thus, advantageously, it is possible to obtain an electronic device with a smaller size, increased data transmission speed, reduced heat generation, easier heat dissipation, and therefore a higher yield.

[0064] A flowchart 200 of a method for manufacturing MCM according to several embodiments is shown, and Figures 2A-2B schematically illustrate the steps of this method.

[0065] According to several embodiments, Figures 2A-2B schematically illustrate an example of a method for manufacturing an MCM such as the MCM100 in Figure 1.

[0066] According to some embodiments, step 202 may include providing a carrier substrate 104. According to some embodiments, the carrier substrate 104 may be provided in an uncoated form (i.e., an uncoated carrier substrate). Alternatively, in some embodiments, the carrier substrate 104 may have a coating 106.

[0067] According to some embodiments, in step 202, the carrier substrate 104 may be inert. According to some embodiments, the carrier substrate 104 may be made from or include glass (e.g., coated glass, uncoated glass, etc.). As a non-limiting example, the carrier substrate 104 may be made from or include glass coated with a polyimide coating (e.g., coating 106). According to some embodiments, the carrier substrate 104 may be made from or include glass, ceramic material, polymer, stainless steel, etc., or any combination thereof. Each possibility is a separate embodiment. According to some embodiments, the carrier substrate 104 may be made from or include SiC. According to some embodiments, the carrier substrate 104 may be made from or include AlN. According to some embodiments, the carrier substrate 104 may be made from or include polyimide. Each possibility is a separate embodiment.

[0068] According to some embodiments, the carrier substrate 104 may be rigid (e.g., having a Shore hardness of about 85D to 96D). According to some embodiments, the carrier substrate 104 may be flexible. As a non-limiting example, the Shore hardness of the carrier substrate 104 may be in the range of about 50D to 70D, among other things. According to some embodiments, the carrier substrate 104 may be semi-rigid (e.g., a composite Shore hardness of a rigid substrate and a flexible substrate). Each possibility is a separate embodiment.

[0069] According to some embodiments, the carrier substrate 104 may be a temporary substrate (i.e., it may be removed during manufacturing).

[0070] According to some embodiments, step 204 may optionally include applying the coating 106 onto the carrier substrate 104. According to some embodiments, step 204 may optionally include applying the coating 106 onto the carrier substrate 104 before positioning one or more electronic components 170a-d, as described in more detail elsewhere in this specification. According to some embodiments, the coating 106 is capable of controlled peeling from the carrier substrate 104.

[0071] According to some embodiments, the coating 106 may be made from or comprise one or more polymers. According to some embodiments, the coating 106 is configured to allow the penetration of one or more pillars of one or more electronic components 170a to d while preventing penetration of one or more electronic components 170a to d.

[0072] According to some embodiments, the coating 106 may be made from or comprise one or more epoxy resins. According to some embodiments, the coating 106 may be made from or comprise polyimide.

[0073] According to some embodiments, in step 206, the method may optionally include performing a first curing of the coating 106 before positioning one or more electronic components 170a-d. According to some embodiments, the first curing may be partial curing. According to some embodiments, the first curing may be performed until the coating 106 is about 10% to 80% cured. As a non-limiting example, the first curing may be performed until the coating 106 is about 10%, 20%, 30%, 40%, 50%, 60%, 70%, or 80% cured. Each possibility is a separate embodiment.

[0074] According to some embodiments, step 208 may include positioning / assembling one or more electronic components 170a-d onto the carrier substrate 104. According to some embodiments, one or more electronic components 170a-d may include, among other things, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 15, 20 or more electronic components. Each possibility is a separate embodiment.

[0075] According to some embodiments, each of the one or more electronic components 170a to d may have different dimensions (i.e., height, width, length, or any combination thereof). According to some embodiments, each of the one or more electronic components 170a to d may have different power consumption, different potentials, etc.

[0076] According to some embodiments, one or more electronic components 170a to d are bare, for example, bare semiconductor dies, bare chips, etc., or any combination thereof.

[0077] According to some embodiments, one or more electronic components 170a to d are arranged / assembled in a downward orientation. According to some embodiments, one or more electronic components 170a to d may be arranged / assembled within a single layer (i.e., a single floor / plane).

[0078] According to some embodiments, the distance between one or more electronic components 170a-d may be about 100 μm or less. According to some embodiments, the distance between one or more electronic components 170a-d may be about 150 μm or less. According to some embodiments, the distance between one or more electronic components 170a-d may be in the range of about 50-200 μm. According to some embodiments, the distance between one or more electronic components 170a-d may be in the range of about 50-150 μm. According to some embodiments, the distance between one or more electronic components 170a-d may be about 90 μm or less. Each possibility is a distinct embodiment. As a non-limiting example, the method may include positioning one or more electronic components 170a-d to obtain an inter-chip distance of less than about 100 μm. Thus, in some embodiments, the method advantageously allows for reduced signal transfer time, space saving, and reduced energy consumption.

[0079] According to some embodiments, step 210 may include performing a second curing of the coating 106 (i.e., performing curing after positioning one or more electronic components). According to some embodiments, the second curing is configured to facilitate the fixing of the positions of one or more electronic components 170a-d.

[0080] According to some embodiments, step 212 may include coating / covering one or more electronic components 170a-d with a molding material 174. According to some embodiments, the coating / covering with the molding material 174 may be performed such that one or more electronic components 170a-d are covered with the molding material 174, and the spaces between the one or more electronic components 170a-d are filled with the molding material 174, thereby obtaining a multi-component structure 180.

[0081] According to some embodiments, the molding material 174 may be made from or comprise one or more polymers, among other things. According to some embodiments, the molding material 174 may be made from or comprise polyimide, epoxy, benzocyclobutene (BCB), or any combination thereof.

[0082] According to some embodiments, step 214 may include grinding the multi-component structure 180 until all back surfaces of one or more electronic components 170a to d are exposed to the multi-component structure 180. According to some embodiments, grinding the multi-component structure 180 may include grinding the molding material 174 and one or more electronic components 170a to d.

[0083] According to some embodiments, grinding of a multi-part structure 180 can be performed, among other things, by using a schematicly drawn grinding tool / machine 182.

[0084] According to some embodiments, step 216 may optionally include applying a thermal interface material (TIM) 176 configured to attach a heat sink 152 to the back surface of one or more electronic components 170a-d. According to some embodiments, the TIM 176 may be a permanent adhesive.

[0085] According to some embodiments, the thickness of TIM176 may be about 50 nm or less. According to some embodiments, the thickness of TIM176 may be about 40 nm or less. According to some embodiments, the thickness of TIM176 may be about 35 nm or less. According to some embodiments, the thickness of TIM176 may be about 30 nm or less. According to some embodiments, the thickness of TIM176 may be about 25 nm or less. According to some embodiments, the thickness of TIM176 may be about 20 nm or less. According to some embodiments, the thickness of TIM176 may be about 15 nm or less. According to some embodiments, the thickness of TIM176 may be about 10 nm or less. Each possibility is a separate embodiment.

[0086] According to some embodiments, step 218 may include mounting the heatsink 152 to the exposed back surface such that the front surface of the multi-component structure 180 faces the carrier 104 and the back surface of the multi-component structure 180 faces the heatsink 152.

[0087] According to some embodiments, step 220 may optionally include removing the carrier 104 from the multi-part structure 180.

[0088] According to some embodiments, in step 222, the method may include planarizing the front / surface layer of the multi-component structure 180. According to some embodiments, step 222 may be performed after removal from the carrier 104 (i.e., after step 220) and before the generation of the coreless interposer 162.

[0089] According to some embodiments, a surface planning tool / machine may be used to perform planarization of a layer having electrically insulating (e.g., polymer) areas (e.g., molding material 174) and conductive areas. According to some embodiments, the conductive areas may include pillars or balls 172 of one or more electronic components 170a-d. According to some embodiments, the pillars or balls 172 may have non-uniform heights, as shown in Figure 2B. According to some embodiments, a surface planarization tool / machine may use a diamond bit for grinding / planarization to facilitate planarization of ductile materials (Cu, Au, etc., but not limited thereto), resins (polyimide, etc., but not limited thereto), or any combination thereof. According to some embodiments, planarizing the front / top layer of a multi-component surface 180 can improve the reliability of electrical interconnections between the multi-component surface 180 and other devices or components.

[0090] According to some embodiments, planarization makes it possible to obtain a total thickness variation (TTV) of a multi-component structure 180 of less than about 1 μm. According to some embodiments, planarization makes it possible to obtain a total thickness variation (TTV) of a multi-component structure 180 of less than about 0.8 μm. According to some embodiments, planarization makes it possible to obtain a total thickness variation (TTV) of a multi-component structure 180 of less than about 0.5 μm without the planarization procedure causing the formation of cracks or other defects.

[0091] According to some embodiments, in step 224, the method includes constructing / forming an interposer 162 on the front surface of a multi-component structure, thereby obtaining a multi-chip module (MCM) 100.

[0092] According to some embodiments, the method for manufacturing the MCM100 does not involve drilling (e.g., laser drilling, or any other type of drilling). Therefore, in some embodiments, the resolution of the MCM100 is not limited by the aspect ratio (i.e., height versus diameter) of the vertical electrical connections. As a result, in some embodiments, it becomes easier to enable the formation of high-density, complex routing patterns and vias and input / output ports with substantially unlimited via heights. According to some embodiments, the method for manufacturing the MCM100 does not involve drilling, which is advantageous in that it minimizes / prevents the risk of cracking and warping as well as other defects / deformations, thereby increasing the reliability of the performance of the MCM100.

[0093] According to some embodiments, the interposer 162 may be a coreless interposer, as will be described in more detail elsewhere in this specification. According to some embodiments, the interposer 162 may be a 3D interposer.

[0094] Next, we refer to Figure 3A, which schematically shows a side view of the MCM coreless interposer 300, Figure 3B, which schematically shows a top view thereof, and Figure 3C, which schematically shows top views of multiple layers of the coreless interposer 300 according to several embodiments.

[0095] According to some embodiments, the coreless interposer 300 may be similar to or identical to the interposer 162 in Figure 1 within the MCM 100.

[0096] According to some embodiments, the coreless interposer 300 is configured to enable electrical interconnection, routing, and rerouting between one or more electronic components of the MCM and external components / devices.

[0097] According to some embodiments, the coreless interposer 300 is configured to electrically interconnect various types of bare electronic components, such as bare dies, but is not limited to them. According to some embodiments, the coreless interposer 300 is configured to electrically interconnect microprocessors (e.g., single-core and / or multi-core processors), microcontrollers, memory chips (volatile memory, non-volatile memory, etc.), logic chips, integrated circuits, any passive and / or active components or devices, or any other electrical components, semiconductor devices, or any combination thereof.

[0098] Advantageously, in some embodiments, the line / spatial resolution of the coreless interposer 300 may be at least about 5 / 5 μm. In some embodiments, the line / spatial resolution of the coreless interposer 300 may be at least about 4 / 4 μm. In some embodiments, the line / spatial resolution of the coreless interposer 300 may be at least about 3 / 3 μm. Each possibility is a distinct embodiment.

[0099] According to some embodiments, the contact pitch (spatial separation between the nearest vias) of the coreless interposer 300 may be less than about 5 μm. According to some embodiments, the contact pitch of the coreless interposer 300 may be less than about 4 μm. According to some embodiments, the contact pitch of the coreless interposer 300 may be less than about 3 μm. According to some embodiments, the contact pitch of the coreless interposer 300 may be less than about 2.5 μm. Each possibility is a separate embodiment.

[0100] According to some embodiments, the coreless interposer 300 has a substrate-less structure. According to some embodiments, the conductive wires of the coreless interposer 300 are formed without perforation, etching, or other means of penetration, thereby minimizing / preventing cracking or other deformation of the conductive wires (and vias formed by the conductive wires, as further detailed elsewhere herein).

[0101] According to some embodiments, the coreless interposer 300 is a three-dimensional (3D) interposer. According to some embodiments, the coreless interposer 300 may include a plurality of high-density conductive wires defined therein. According to some embodiments, the coreless interposer 300 may include a plurality of ultrathin and high-density vertical electrical interconnections formed therein. Advantageously, in some embodiments, the coreless interposer 300 enables miniaturization of electronic devices while improving interconnection, thereby improving the performance of electronic devices and reducing power consumption.

[0102] According to some embodiments, the coreless interposer 300 may have an ultra-thin structure with a thickness of, for example, about 50 μm or less. According to some embodiments, the coreless interposer 300 may have an ultra-thin structure with a thickness of, for example, about 40 μm or less. According to some embodiments, the coreless interposer 300 may have an ultra-thin structure with a thickness of, for example, about 30 μm or less. According to some embodiments, the coreless interposer 300 may have an ultra-thin structure with a thickness of, for example, about 20 μm or less. According to some embodiments, the coreless interposer 300 may have an ultra-thin structure with a thickness of, for example, about 10 μm or less. According to some embodiments, the coreless interposer 300 may have an ultra-thin structure with a thickness in the range of, for example, about 5 to about 500 μm. Each possibility is a separate embodiment. In some embodiments, the coreless interposer 300 may have any desired thickness (i.e., substantially unlimited height).

[0103] According to some embodiments, the coreless interposer 300 may have multiple layers (e.g., 2, 3, 4, 5, 6, 7, 8, 9, 10 or more layers). Each possibility is a separate embodiment. According to some embodiments, the thickness of each of the multiple layers may be substantially the same. In some embodiments, the thickness of each of the multiple layers may be different.

[0104] According to some embodiments, each of the multiple layers is laminated on top of a previous (bottom) layer. According to some embodiments, each of the multiple layers includes conductive regions and electrically insulating regions (i.e., electrically insulating material) that fill the gaps between the conductive regions.

[0105] According to some embodiments, each insulating region is positioned between each conductive region, thereby preventing the flow of (horizontal) current (i.e., short circuits) between each of the conductive regions in a particular layer of the multiple layers. In other words, the multiple layers are stacked substantially vertically, forming vertical electrical connections between the insulating regions, thereby allowing the flow of vertical current through the multiple layers according to a predetermined pattern / path.

[0106] Advantageously, in some embodiments, the structure of the coreless interposer 300 allows for on-the-fly formation of vertical electrical connections between electrical insulating materials. According to some embodiments, the vertical electrical connections of each of multiple layers may be formed simultaneously. Advantageously, in some embodiments, the vertical electrical connections are formed without perforation. Advantageously, in some embodiments, the vertical electrical connections are formed without etching (e.g., chemical etching). Advantageously, the vertical electrical connections may be formed in any desired pattern and / or height to facilitate the routing of electrical signals.

[0107] As shown in Figures 3A-C, according to some embodiments, the multiple layers of the coreless interposer 300 may include four layers. According to some embodiments, as shown in Figure 3A, the first layer 310 of the multiple layers includes multiple conductive regions 310a and multiple electrically insulating regions 310b. According to some embodiments, as shown in Figure 3A, each of the second layer 312, the third layer 314, and the fourth layer 316 of the multiple layers includes multiple conductive regions 312a, 314a, and 316a and multiple electrically insulating regions 312b, 314b, and 316b, respectively. The number of multiple layers of the coreless interposer 300 may vary and can be understood as including substantially any required number. According to some embodiments, the number of multiple layers may include, among other things, 2, 3, 4, 5, 6, 7, 8, 9, 10, 15, 20, 25, 30, or more layers. Each possibility is a separate embodiment. According to some embodiments, as will be explained in more detail in Figure 4, there is virtually no upper limit on the number of layers.

[0108] As shown in Figures 3A-C, according to some embodiments, a plurality of conductive regions 310a of the first layer 310 may include a plurality of first contact pads configured to electrically interconnect with external components / devices (for example, configured to interconnect the MCM to external components / devices). According to some embodiments, the dimensions of each of the first plurality of contact pads may be about 100 μm × 100 μm. According to some embodiments, the dimensions of each of the first plurality of contact pads may be in the range of about 100 to 500 μm × 100 to 500 μm. According to some embodiments, the dimensions of each of the first plurality of contact pads may be in the range of about 50 to 500 μm × 50 to 500 μm. Each possibility is a separate embodiment.

[0109] According to some embodiments, a plurality of conductive regions 312a of the second layer 312 may be configured to facilitate / form vertical electrical connections of a desired pattern and / or size. According to some embodiments, a plurality of conductive material regions 314a of the third layer 314 optionally include and / or serve as redistribution layers (RDLs) configured to redistribute vertical electrical connections at desired locations. According to some embodiments, a plurality of conductive regions 316a of the fourth layer 316 may include a second plurality of contact pads configured to interconnect the coreless interposer 300 to one or more electronic components of the MCM. According to some embodiments, the dimensions of each of the second plurality of contact pads may be about 10 × 10 μm or less. According to some embodiments, the dimensions of each of the second plurality of contact pads may be about 8 × 8 μm or less. According to some embodiments, the dimensions of each of the second plurality of contact pads may be about 6 × 6 μm or less. According to some embodiments, the dimensions of each of the second plurality of contact pads may be about 5 × 5 μm or less. According to some embodiments, the dimensions of each of the second plurality of contact pads may be about 4 × 4 μm or less. According to some embodiments, the dimensions of each of the second plurality of contact pads may be about 3 × 3 μm or less. According to some embodiments, the dimensions of each of the second plurality of contact pads may be about 2.5 × 2.5 μm or less. Each possibility is a separate embodiment.

[0110] According to some embodiments, the lines and / or contact pads in the conductive material region may have a thickness of about 5 to 7 μm or 3 to 6 μm. According to some embodiments, the lines and / or pads may have a thickness of less than about 5 μm.

[0111] According to some embodiments, the conductive regions 310a / 312a / 314a / 316a may include or be in the form of contact pads. According to some embodiments, the form / shape of the conductive regions 310a / 312a / 314a / 316a may include or be in the form of circular, square, oval, rectangular, rounded rectangle, chamfered rectangle, octagon, donut, n-sided polygon, etc. (when viewed from above), or any combination thereof. According to some embodiments, the conductive regions 310a / 312a / 314a / 316a may include or be in the form of electrical lines.

[0112] According to some embodiments, the vertical electrical connections formed by the conductive regions 310a / 312a / 314a / 316a may be, among other things, through vias, tented vias, blind vias, embedded vias, stacked vias, or any combination thereof, or may include them. Each possibility is a separate embodiment.

[0113] Refer to Figure 4, which is a flowchart of a method for manufacturing a coreless interposer of an MCM according to several embodiments.

[0114] According to some embodiments, in step 402, the method may include forming a plurality of conductive regions. According to some embodiments, the plurality of conductive regions may include conductive lines or be in the form of conductive lines. According to some embodiments, the plurality of conductive regions may include contact pads or be in the form of contact pads. According to some embodiments, the plurality of conductive regions may be formed according to a predetermined pattern.

[0115] According to some embodiments, the multiple conductive regions may be made of metal or may contain metal. According to some embodiments, the multiple conductive regions may contain copper (Cu), gold (Au), silver (Ag), tin (Sn), titanium (Ti), nickel (Ni), or any alloy thereof. Each possibility is a separate embodiment. According to some embodiments, each of the multiple layers of the coreless interposer may be made of or contain a different material (e.g., a different metal). According to some embodiments, each of the multiple layers of the coreless interposer may be made of or contain the same material (e.g., each of the multiple layers may be made of or contain the same metal).

[0116] According to some embodiments, in step 402, the method may include forming a plurality of conductive regions on a temporary carrier substrate. According to some embodiments, the temporary carrier substrate may be made from, but is not limited to, an inert material such as glass, silicon, ceramic, stainless steel, SiC, AlN, polyimide, or polyimide on glass. According to some embodiments, the temporary carrier substrate may be rigid, semi-rigid, or flexible. Each possibility is a separate embodiment.

[0117] According to some embodiments, the temporary carrier substrate may not be coated. According to some embodiments, the carrier substrate may include a coating.

[0118] Those skilled in the art will understand that in some embodiments, the coreless interposers shown in Figures 1-2 may be manufactured without using a temporary carrier substrate (i.e., they may be manufactured directly on the multi-component structure 180). Alternatively, in some embodiments, the coreless interposers may be manufactured separately / independently (i.e., on a temporary carrier substate) and then mounted on the multi-component structure 180.

[0119] According to some embodiments, multiple conductive regions may be formed by performing an additive manufacturing process (step 402a), such as but not limited to selective laser sintering, as detailed in Figure 5.

[0120] According to some embodiments, multiple conductive regions may be formed by carrying out semi-additive manufacturing methods such as photolithography, as further detailed in Figure 6 (step 402b).

[0121] According to some embodiments, step 404 may include filling one or more voids between a plurality of conductive regions with an electrical insulating material. According to some embodiments, filling may include pouring / spreading the electrical insulating material over the plurality of conductive regions and one or more voids between them.

[0122] According to some embodiments, the electrical insulating material may include a dielectric material. According to some embodiments, the electrical insulating material may include one or more polymers. According to some embodiments, the electrical insulating material may be made from polyimide or may include polyimide. According to some embodiments, the electrical insulating material may be photosensitive. As a non-limiting example, the electrical insulating material may be made from or may include photocurable epoxy. According to some embodiments, the electrical insulating material may be photoinsensitive. According to some embodiments, the electrical insulating material may have a thickness-to-diameter ratio of at least about 5:1. According to some embodiments, the thickness of the electrical insulating material layer is in the range of about 3–30 μm. According to some embodiments, the electrical insulating material has a coefficient of thermal expansion of about 15–20 ppm / °C.

[0123] According to some embodiments, the CTE of a conductive region may substantially coincide with the CTE of an electrical insulating material, thereby facilitating heat management and heat dissipation generated by the MCM away from it. It can be understood by those skilled in the art that insufficient heat transfer can lead to a decrease in the performance of an electronic device or its components. Furthermore, a mismatch in thermal expansion can lead to increased mechanical stress, which in turn can lead to a decrease in performance.

[0124] According to some embodiments, each of the multiple layers of the coreless interposer may be made from or contain different electrical insulating materials. According to some embodiments, each of the multiple layers of the coreless interposer may be made from or contain the same electrical insulating material.

[0125] According to some embodiments, step 406 may optionally include heat-treating, curing, and / or polymerizing an electrical insulating material that fills one or more voids between a plurality of conductive regions.

[0126] According to some embodiments, step 408 may include removing / scraping off excess electrical insulating material to obtain a first layer of multiple layers of the coreless interposer.

[0127] According to some embodiments, removing / scraping off excess electrical insulating material may include planarizing using a surface planarizing device / machine so that a substantially flat surface is formed of the first layer (and / or each of the additional one or more layers) of the coreless interposer. According to some embodiments, the excess electrical insulating material may be removed until a portion of the conductive area (e.g., the surface or top layer of the conductive area) is exposed.

[0128] According to some embodiments, step 410 may include repeating the above steps to generate one or more additional layers of the coreless interposer. In other words, the above steps may be repeated until the required number of layers is obtained (for example, until the required height / depth of the vertical electrical connections is achieved).

[0129] According to some embodiments, the above iteration may include aligning the conductive regions of the front / bottom layers of multiple layers with additional layers of the multiple layers of the coreless interposer. According to some embodiments, the alignment may be performed according to a reference / marker of the front / bottom layer. According to some embodiments, the alignment between each conductive region of multiple layers may be about 1 μm or less. According to some embodiments, the alignment between each conductive region of multiple layers may be about 0.5 μm or less. Each possibility is a separate embodiment. In some embodiments, the methods disclosed herein enable the manufacture of coreless interposers with mismatch losses of less than about 10% or less than about 5%.

[0130] According to some embodiments, the method may optionally include step 412 of removing the temporary carrier from the interconnect structure.

[0131] According to some embodiments, the method may optionally include performing electrical measurements to test / verify at least a portion of multiple layers during and / or after the manufacturing of the coreless interposer (steps not shown).

[0132] According to some embodiments, the method provides "on-the-fly" formation of vertical electrical connections between electrical insulating materials.

[0133] In some embodiments, the methods disclosed herein do not involve any drilling steps. In some embodiments, the methods do not involve mechanical or laser drilling. Therefore, advantageously, the disclosed methods are not limited to the aspect ratio of via height to diameter, in contrast to methods that involve drilling vias, which tend to cause the interposer or a portion thereof to crack. In other words, in some embodiments, the aspect ratio can be substantially infinite.

[0134] Advantageously, because there is no limitation on the height-to-diameter aspect ratio, in some embodiments there is virtually no upper limit on the number of layers that can be stacked on top of each other, thereby enabling the formation of vertical electrical connections (e.g., vias) between electrical insulating materials with virtually unlimited height / depth.

[0135] According to some embodiments, the predetermined patterns of each of the multiple layers may be different. According to some embodiments, complex and high-density patterns can be obtained regardless of the number of layers of the coreless interposer. Advantageously, in some embodiments, the methods disclosed herein combine additive manufacturing techniques for generating the coreless interposer interconnect structure. As a result, the interposer is produced by either a semi-additive or additive (e.g., fully additive) method. This makes it possible, in some embodiments, to obtain a wide range of patterns (e.g., interconnect schemes) and via architectures. Thus, the required signal routing, signal integrity, and power delivery can be achieved while facilitating thermal management. In some embodiments, complex patterns of vertical electrical connections can be substantially achieved without reducing or limiting the resolution (i.e., density of conductive areas) of the coreless interposer. According to some embodiments, the line / spatial resolution of the interconnect structure may be at least about 5 / 5 μm.

[0136] In some embodiments, coreless interposers and MCMs manufactured according to the methods disclosed herein comply with military standard testing of 1,000 cycles from -45°C to +145°C. In some embodiments, coreless interposers and MCMs manufactured according to the methods disclosed herein comply with Joint Electron Device Engineering Council (JEDEC) standards, including testing of 1,000 cycles from -25°C to +125°C.

[0137] In some embodiments, the methods disclosed herein enable the manufacture of coreless interposers with mismatch losses of less than about 10% or less than about 5%. In some embodiments, the methods disclosed herein enable the manufacture of coreless interposers having a total thickness variation (TTV) of conductive material of less than about 1 μm or less than about 0.5 μm. In some embodiments, the methods disclosed herein enable the manufacture of coreless interposers with a total thickness variation (TTV) of conductive material of about 1 × 10⁻¹⁶. -6 Ω / cm 2 This makes it possible to manufacture coreless interposers with interlayer contact resistivity of less than a certain value.

[0138] Refer to Figure 5, which schematically shows an example of an additive manufacturing process 502a for forming a conductive region (i.e., in step 402a of Figure 4) according to several embodiments. According to several embodiments, the additive manufacturing process may include, but is not limited to, selective laser sintering (SLS) methods such as direct SLS, direct metal laser sintering (DMLS), selective laser melting (SLM), metal wire 3D printing, electron beam melting (EBM), or any other additive manufacturing process. According to several embodiments, the additive manufacturing process may include any type of directed energy deposition method, powder-based fusion additive manufacturing, or any combination thereof. According to several embodiments, the additive manufacturing process may include a micrometal additive manufacturing (MMAM) method.

[0139] According to some embodiments, in step 502a-1, the additive process may include cleaning the carrier 504. According to some embodiments, the carrier 504 may be a temporary carrier. Alternatively, in some embodiments, the carrier may be a non-temporary carrier.

[0140] According to some embodiments, cleaning of the carrier 504 may include performing a plasma surface treatment. According to some embodiments, the plasma surface treatment may be performed by atmospheric pressure plasma. According to some embodiments, cleaning of the carrier 504 may include chemical etching (i.e., wet etching or dry etching) of the surface of the carrier 504. According to some embodiments, cleaning of the carrier 504 may include dry etching of the surface of the carrier 504. According to some embodiments, cleaning of the carrier 504 may include ultrasonic cleaning. According to some embodiments, cleaning of the carrier 504 may include ozone treatment of the carrier surface. According to some embodiments, cleaning of the carrier 504 may include any combination of the cleaning methods described above or any other surface treatment / cleaning.

[0141] According to some embodiments, in step 502a-2, the additive process may include spreading / applying the ink coating 508 to the surface of the carrier 504.

[0142] According to some embodiments, the ink coating 508 may comprise a structural powder (i.e., a high-melting-point powder such as a metal or alloy) and a binder / solvent (i.e., a powder having a lower melting point than the structural powder). According to some embodiments, the ink coating 508 may be made from or comprise a mixture of two or more powders. According to some embodiments, the ink coating 508 may comprise a mixture of conductive materials (e.g., a mixture of metals). According to some embodiments, the ink coating 508 may comprise copper (Cu), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), tin (Sn), etc., or any combination thereof in the coating. Each possibility is a separate embodiment. As a non-limiting example, the ink coating 508 may be a copper ink coating.

[0143] According to some embodiments, the binder / solvent of the ink coating may include, among other things, water, ethylene glycol, diethylene glycol monomethyl ether, and the like. Each possibility is a separate embodiment. It can be understood by those skilled in the art that different binders and / or solvents produce metallic inks with different viscosities, thereby affecting their filling ability / properties.

[0144] According to some embodiments, the coating of the carrier 304 with the ink coating 508 can be carried out, among other things, by an ink spy coater, a slot die coater, an ultrasonic spin spy coater, or any combination thereof. According to some embodiments, the coating of the carrier 504 may include a doctor blade coating to facilitate the formation of a distinct coating thickness.

[0145] According to some embodiments, step 502a-2 may include drying the ink coating 508. According to some embodiments, drying may be carried out by means of a blower, an oven, etc.

[0146] According to some embodiments, in steps 502a-3, the additive manufacturing process may include performing selective laser sintering to form a conductive region 510a according to a predetermined pattern. According to some embodiments, a direct laser writer may be used to perform selective laser sintering. According to some embodiments, step 502a-3 may include 3D printing, electron beam melting, or any other additive manufacturing process.

[0147] According to some embodiments, in steps 502a-4, the additive process may include removing the non-sintered material (e.g., the non-sintered copper ink of the ink coating 508) by washing or other means, thereby obtaining a pattern of the conductive region 510a. According to some embodiments, the pattern may include conductive lines having the required width, length, and inter-line distance, as essentially disclosed herein.

[0148] According to some embodiments, the additive process 502a does not include a step of removing material.

[0149] Refer to Figure 6, which schematically shows an example of a semi-additive manufacturing method 602b for obtaining a conductive region (i.e., step 402b in Figure 4) according to several embodiments.

[0150] According to some embodiments, the semi-additive method 602b may be based on or include a lithography method. According to some embodiments, the lithography method may, among other things, include a maskless lithography method. According to some embodiments, the lithography may, among other things, include fluoroscopy, electron beam and / or optical lithography (i.e., photolithography), etc. Each possibility is a separate embodiment. According to some embodiments, the lithography may, among other things, include nanolithography, plasmon-assisted lithography, laser interference lithography, nanosphere lithography, etc. Each possibility is a separate embodiment.

[0151] According to some embodiments, the semi-additive method 602b may include photolithography.

[0152] According to some embodiments, in step 602b-1, the semi-additive method may include providing a carrier substrate 604. According to some embodiments, the carrier 604 may be a temporary carrier. According to some embodiments, step 602b-1 may include cleaning the carrier 604. According to some embodiments, carrier cleaning may include performing a plasma surface treatment. According to some embodiments, carrier cleaning may include chemical etching (i.e., wet etching) of the surface of the carrier 604. According to some embodiments, carrier cleaning may include ultrasonic cleaning, ozone treatment, plasma treatment, etc., of the carrier surface, or any combination thereof. Each possibility is a separate embodiment. According to some embodiments, carrier cleaning may include any combination of the cleaning methods described above, or any other suitable surface treatment / cleaning.

[0153] According to some embodiments, in step 602b-2, the semi-additive method may include forming a seed layer 606 on the carrier 604. According to some embodiments, the seed layer 606 may be made from or include one or more metals. According to some embodiments, the seed layer 606 may include TiW and copper (Cu).

[0154] According to some embodiments, the seed layer 606 can be formed by a metallization process. According to some embodiments, the seed layer 506 can be formed by a physical vapor deposition (PVD) method such as sputtering or thermal deposition. According to some embodiments, the seed layer 606 can be formed by a chemical vapor deposition (CVD) method such as atomic layer deposition (ALD). Each possibility is a distinct embodiment.

[0155] According to some embodiments, in steps 602b-3, the semi-additive method may include applying a radiosensitive compound onto the seed layer 606. According to some embodiments, the radiosensitive compound may include a resist such as a positive resist (i.e., the pattern formed in the positive resist is the same as the pattern on the mask) or a negative resist (i.e., the pattern formed is the inverse of the mask pattern). According to some embodiments, the resist may include a photoresist 608.

[0156] According to some embodiments, the carrier 604 may be placed on a vacuum spindle while the photoresist is being applied. According to some embodiments, the carrier 604 can then be rotated (e.g., for about 15 seconds, about 30 seconds, about 60 seconds, etc.) to facilitate obtaining a uniform coating of the photoresist 606. According to some embodiments, the coated carrier 604 may optionally undergo a pre-patterning heat treatment (e.g., baking) to remove solvent from the photoresist 608 and / or to enhance the adhesion of the photoresist 608 to the seed layer 606.

[0157] According to some embodiments, in steps 602b-4, the semi-additive method may include photoresist illumination and development (pattern transfer). According to some embodiments, step 602b-4 may be performed in a cleanroom illuminated with yellow light. According to some embodiments, step 602b-4 may include applying irradiation, such as ultraviolet irradiation, to transfer a desired pattern to the photoresist 608 and form the photoresist pattern 610b.

[0158] According to some embodiments, after the pattern transfer is complete, any residue of the photoresist 608 can be removed from the unpatterned areas, thereby exposing the photoresist pattern 610b formed on the seed layer 606. According to some embodiments, any residue of the photoresist 608 can be removed from the unpatterned areas by washing, sonication, etching, and / or rinsing in a solution, plasma oxidation, or any combination thereof.

[0159] According to some embodiments, a second heat treatment (e.g., post-baking) may be optionally performed after developing the pattern on the carrier 604. According to some embodiments, the carrier 604 and the developed photoresist pattern 610b may be dried in the ambient environment.

[0160] According to some embodiments, in steps 602b-5, the semi-additive method may include filling one or more voids between the photoresist patterns 610b with a conductive material so that a plurality of conductive regions 610a are formed. According to some embodiments, the plurality of conductive regions 610a may be formed, among other things, by electroplating. As a non-limiting example, steps 604b-5 may include copper electroplating.

[0161] According to some embodiments, in steps 602b-6, the semi-additive method may include removing the photoresist pattern 610b. According to some embodiments, the photoresist pattern 610b may be removed by wet chemical techniques. According to some embodiments, an AZ100 remover may be used to remove the photoresist pattern 610b. According to some embodiments, an AZ920 remover may be used to remove the photoresist pattern 610b. According to some embodiments, a 1-methyl-2-pyrrolidone (NMP) remover may be used to remove the photoresist pattern 610b. According to some embodiments, dimethyl sulfoxide (DMSO) may be used to remove the photoresist pattern 610b (e.g., by ultrasonic cleaning).

[0162] According to some embodiments, in steps 602b-7, the semi-additive method may include removing residue from the seed layer 606 between the multiple conductive regions 610a to prevent horizontal current flow between each of the multiple conductive regions 610a through each of the multiple layers of the coreless interposer, thereby enabling vertical current flow.

[0163] According to some embodiments, the remainder of the seed layer 606 may be removed by etching or any other suitable removal technique.

[0164] For clarity, it should be understood that certain features of the Disclosure described in the context of separate embodiments may be provided in combination in a single embodiment. Conversely, for brevity, various features of the Disclosure described in the context of a single embodiment may be provided separately, in any suitable combination, or as appropriate in any other described embodiment of the Disclosure. Features described in the context of an embodiment should not be considered essential features of that embodiment unless expressly designated as such.

[0165] The steps of the method may be described in a specific order according to some embodiments, but the method of this disclosure may include some or all of the described steps which are performed in a different order. In particular, it should be understood that the order of any of the stages and substages of the described method may be rearranged, except, for example, when a later stage requires an output or input of a earlier stage, or when a later stage requires the product of a earlier stage, unless the context otherwise explicitly indicates otherwise. The method of this disclosure may include some or all of the described steps. No particular step in the disclosed method should be considered an essential step of the method unless it is expressly designated as such.

[0166] While this disclosure is described in conjunction with its specific embodiments, it is evident that numerous alternative, modified, and variant forms may exist that are apparent to those skilled in the art. Accordingly, this disclosure encompasses all such alternative, modified, and variant forms that fall within the scope of the appended claims. It should be understood that, in its application, this disclosure is not necessarily limited to the details of the configuration and arrangement of the components and / or methods described herein. Other embodiments may be implemented, and embodiments may be carried out in a variety of ways.

[0167] The language and terminology used herein are for illustrative purposes only and should not be construed as limiting. No citation or identification of a citation in this application shall be construed as an admission that such citation is available as prior art of the disclosure. Section headings are used herein to facilitate understanding of this specification and should not be construed as limiting.

Claims

1. It is a multi-chip module, An open / exposed / bare back surface equipped with a heatsink, wherein the heatsink is configured for heat dissipation from the multi-chip module, and One or more electronic components, It has a front panel equipped with a coreless interposer, The aforementioned coreless interposer is A plurality of layers, each of which has a plurality of conductive wires / pads, The one or more gaps between the plurality of conductive wires / pads, wherein the one or more gaps are filled with insulating material, and the voids comprise one or more voids, The one or more electronic components are placed between the coreless interposer and the heat sink. The aforementioned front panel is a multi-chip module configured for electrical communication with external electrical components.

2. The multichip according to claim 1, wherein the input / output port pitch of the multichip module is approximately 20 µm or less.

3. The multichip according to claim 1 or 2, wherein the one or more electrical components comprises one or more of a bare die, a chip, a micromechanical system (MEMS), a memory interface, an input / output device, a graphics processing unit, a wireless modem, a passive component, a processor, an analog integrated circuit, an RF integrated circuit, a voltage regulator module, or any combination thereof.

4. The multichip according to any one of claims 1 to 3, wherein the insulating material of the coreless interposer is made from or comprises one or more polymers.

5. The multi-chip module according to any one of claims 1 to 4, wherein the space between one or more electronic components is filled with a molding material.

6. The multi-chip module according to claim 5, wherein the molding material is selected from polyimide, epoxy, benzocyclobutene (BCB), or any combination thereof.

7. The multichip according to any one of claims 1 to 6, further comprising a thermal interface material (TIM) configured to attach the heat sink to the back surface of one or more components.

8. The multi-chip according to claim 7, wherein the thermal interface material (TIM) has a thickness of less than approximately 50 nanometers.

9. The multichip module according to any one of claims 1 to 8, wherein the plurality of conductive wires / pads are made of or include copper, silver, gold, or other metals.

10. The multichip module according to any one of claims 1 to 9, wherein the multichip is suitable for use in analog, digital, RF, and / or high-power circuits.

11. The multichip module according to any one of claims 1 to 10, wherein the multichip module is a standalone system-in-package (SiP) module.

12. The multichip module according to any one of claims 1 to 11, wherein the distance between one or more electrical components is approximately 100 μm or less.

13. A method for manufacturing a multichip module, A step of positioning one or more electronic components on an inert carrier, wherein the carrier includes a coating that can be peeled off from the carrier in a controlled manner; A step of covering one or more electronic components with a molding material so that the spaces between one or more electronic components are filled with the molding material, thereby obtaining a molded multi-component structure by coating / covering one or more electronic components with the molding material. The steps include grinding the multi-component structure until the back surfaces of all one or more electronic components within the multi-component structure are exposed, The steps include: attaching a heatsink to the exposed back surface such that the front surface of the molded multi-component structure faces the carrier and the back surface of the multi-component structure faces the heatsink; A method comprising the steps of constructing a coreless interposer on the front of a multi-component structure.

14. The method according to claim 13, further comprising removing the inert carrier from the multi-component structure.

15. The method according to claim 13 or 14, wherein the method does not include a drilling step.

16. The method according to any one of claims 13 to 15, wherein the interposer comprises a plurality of layers, each of which comprises a plurality of conductive wires / pads and one or more voids between the plurality of conductive wires / pads, and the one or more voids are filled with an insulating material.

17. The method according to any one of claims 13 to 16, further comprising applying the coating onto the carrier before positioning, wherein the coating is configured to allow a columnar object attached to the one or more electronic components to penetrate while preventing penetration of the one or more electronic components.

18. The method according to any one of claims 13 to 17, further comprising partially curing the coating before positioning the one or more electronic components.

19. The method according to any one of claims 13 to 18, further comprising curing the coating after the positioning of the one or more electronic components.

20. The method according to any one of claims 13 to 19, further comprising flattening the front surface of the multi-component structure after the removal from the carrier and before the generation of the coreless interposer.

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