Method for forming microelectronic devices, and related microelectronic devices, memory devices, and electronic systems.

Abstract

A method for forming a microelectronic device, comprising the step of forming a first assembly including a semiconductor substrate structure, a first circuit region including a first device at a first boundary of the semiconductor substrate structure, and a second circuit region including a second device at a second boundary perpendicularly offset from the first boundary of the semiconductor substrate structure. A microelectronic device structure is formed, which includes a stack structure including layers of a conductive material and an insulating material perpendicularly adjacent to the conductive material, and a cell pillar structure including a semiconductor material extending perpendicularly to the stack structure. A second assembly is formed by joining the first assembly to the microelectronic device structure. Furthermore, microelectronic devices, memory devices, and electronic systems are also described.

Description

Technical Field

[0001] Priority Claim This application claims the benefit of the filing date of U.S. Patent Application No. 18 / 424,713, filed on January 26, 2024, and further claims the benefit of U.S. Provisional Patent Application No. 63 / 493,176, filed on March 30, 2023, under 35 U.S.C. § 119(e). The disclosures of each are hereby incorporated by reference in their entireties.

[0002] In various embodiments, the present disclosure generally relates to the field of design and manufacture of microelectronic devices. More specifically, the present disclosure relates to methods of forming microelectronic devices, as well as related microelectronic devices, memory devices, and electronic systems.

Background Art

[0003] Designers of microelectronic devices often desire to increase the integration or feature density within a microelectronic device by reducing the dimensions of individual features and shortening the spacing between adjacent features. Additionally, designers of microelectronic devices often seek to design architectures that are not only compact, but also provide performance advantages and are simple, easy, and low-cost to manufacture.

[0004] Memory devices are an example of microelectronic devices. Memory devices are generally provided as internal integrated circuits in computers and other electronic devices. There are many, and not limited, types of memory devices, including, for example, non-volatile memory devices (e.g., NAND flash memory devices). One way to increase storage density in non-volatile memory devices is to use a vertical memory array (also called a "three-dimensional (3D) memory array") architecture. Conventional vertical memory arrays have vertical memory strings that extend through openings in one or more decks (stack structures) containing layers of conductive and dielectric materials. Each vertical memory string may consist of a series combination of vertically stacked memory cells connected in series, with at least one selected device coupled in series. Such a configuration allows for more switching devices (e.g., transistors) per die area unit (i.e., length and width of the effective area used) by building the array upward (e.g., vertically) on the die, compared to conventional planar (e.g., two-dimensional) transistor array structures.

[0005] Control logic devices within a base control logic structure located beneath a memory array of a memory device (e.g., a non-volatile memory device) have been used to control the operation of the memory cells of the memory device (e.g., access, read, and write operations). The collection of control logic devices may be electrically connected to the memory cells of the memory array via wiring and interconnect structures. However, process conditions for forming the memory array on the base control logic structure (e.g., temperature, pressure, and materials) can constrain the configuration and performance of the control logic devices within the base control logic structure. Furthermore, the number, dimensions, and arrangement of different control logic devices used within the base control logic structure can undesirably hinder the reduction of the memory device size (e.g., horizontal footprint) and / or the improvement of its performance (e.g., faster on / off speed of memory cells, reduced threshold switching voltage). [Overview of the project]

[0006] In some embodiments, a method for forming a microelectronic device includes the step of forming a first assembly which includes a semiconductor substrate structure, a first circuit region containing a first device at a first boundary of the semiconductor substrate structure, and a second circuit region containing a second device at a second boundary perpendicular to the first boundary. A microelectronic device structure is formed, which comprises a stack structure having multiple layers, each containing a conductive material and an insulating material perpendicular to the conductive material, and a cell pillar structure containing a semiconductor material perpendicularly penetrating the stack structure. The first assembly is joined to the microelectronic device structure to form a second assembly.

[0007] In yet another embodiment, the microelectronic device includes a stack structure, a cell pillar structure, a semiconductor structure, a first device, a second device, and a conductive contact structure. The stack structure comprises multiple layers, each containing a conductive material and an insulating material perpendicular to the conductive material. The cell pillar structure includes a semiconductor material extending perpendicularly through the stack structure. The semiconductor structure is located perpendicularly above the stack structure. The first device is located at the lower boundary of the semiconductor structure. The second device is located at the upper boundary of the semiconductor structure. The conductive contact structure extends from at least some of the vertical positions of the second device, completely through the semiconductor structure, and to at least some of the additional vertical positions of the first device.

[0008] In yet another embodiment, the memory device includes a stack structure, a string of memory cells, a source structure, digit lines, a semiconductor structure, capacitors, a control logic device, and a conductive contact structure. The stack structure comprises multiple layers, each containing a conductive material and an insulating material perpendicular to the conductive material. The string of memory cells extends perpendicularly through the stack structure. The source structure is located perpendicularly below the stack structure and is coupled to the string of memory cells. The digit lines are located perpendicularly above the stack structure and are coupled to the string of memory cells. The semiconductor structure is located perpendicularly above the digit lines. The capacitors partially overlap perpendicularly with the bottom boundary of the semiconductor structure. The control logic device partially overlaps perpendicularly with the top boundary of the semiconductor structure and is coupled to the string of memory cells. The conductive contact structure extends perpendicularly through the semiconductor structure and couples at least some of the capacitors to some of the control logic devices. [Brief explanation of the drawing]

[0009] [Figure 1A] This is a simplified partial longitudinal cross-sectional view showing different processing steps in a method for forming a microelectronic device according to an embodiment of the present disclosure. [Figure 1B] This is a simplified partial longitudinal cross-sectional view showing different processing steps in a method for forming a microelectronic device according to an embodiment of the present disclosure. [Figure 1C] This is a simplified partial longitudinal cross-sectional view showing different processing steps in a method for forming a microelectronic device according to an embodiment of the present disclosure. [Figure 1D] This is a simplified partial longitudinal cross-sectional view showing different processing steps in a method for forming a microelectronic device according to an embodiment of the present disclosure. [Figure 1E] This is a simplified partial longitudinal cross-sectional view showing different processing steps in a method for forming a microelectronic device according to an embodiment of the present disclosure. [Figure 1F]This is a simplified partial longitudinal cross-sectional view showing different processing steps in a method for forming a microelectronic device according to an embodiment of the present disclosure. [Figure 2] This is a schematic block diagram of an electronic system according to one embodiment of the present disclosure. [Modes for carrying out the invention]

[0010] The following description provides specific details such as material composition, shape, and dimensions to give a sufficient explanation of the embodiments of the disclosure. However, those skilled in the art will understand that the embodiments of the disclosure can be implemented without using these specific details. In fact, the embodiments of the disclosure can be implemented in combination with conventional microelectronic device manufacturing techniques used in the art. Furthermore, the description below does not constitute a complete process flow in the manufacture of a microelectronic device (e.g., a memory device). The structures described below do not constitute a complete microelectronic device. Only the process operations and structures necessary to understand the embodiments of the disclosure are described in detail below. Additional operations to form a complete microelectronic device from these structures can be performed by conventional manufacturing techniques.

[0011] The drawings shown herein are for illustrative purposes only and do not represent the actual shapes of any particular material, component, structure, device, or system. It is naturally expected that actual shapes may differ from those shown due to manufacturing techniques and / or tolerances. Therefore, embodiments described herein should not be interpreted as being limited to any specific shape or area shown, but rather include variations in shape due to manufacturing, for example. For instance, an area shown or described as box-shaped may have features that are not perfectly box-shaped and / or not linear. Similarly, an area shown or described as circular may include features that are not perfectly circular and / or linear. Furthermore, acute angles shown may be rounded, and vice versa. Therefore, the areas shown in the drawings are schematic, and their shapes are not intended to represent the exact shape of the area and do not limit the scope of the claims. The drawings are not necessarily to scale. Furthermore, elements common to multiple drawings may share the same reference numeral.

[0012] In this specification, “memory device” means and includes, but is not necessarily limited to, microelectronic devices having memory functionality. In other words, as an unrestricted example, the term “memory device” includes not only conventional memory (e.g., conventional non-volatile memory, conventional volatile memory), but also application-specific integrated circuits (ASICs) (e.g., system-on-a-chip (SoC)), microelectronic devices combining logic and memory, and even graphics processing units (GPUs) with integrated memory.

[0013] In this specification, the terms “configured” and “configuration” refer to dimensions, shape, material composition, material distribution, orientation, and arrangement that enable at least one feature (e.g., at least one structure, at least one material, at least one region, at least one device) to be used in a predetermined manner.

[0014] In this specification, the terms “vertical,” “longitudinal,” “horizontal,” and “lateral” are defined relative to the main plane of the structure and not necessarily by the Earth’s gravitational field. “Horizontal” or “lateral” means a direction substantially parallel to the main plane of the structure, while “vertical” or “longitudinal” means a direction substantially perpendicular to the main plane of the structure. The main plane of the structure is defined by a surface having a relatively large area compared to other surfaces of the structure. In drawings, “horizontal” or “lateral” is perpendicular to the indicated “Z” axis and parallel to the indicated “X” axis or “Y” axis. “Vertical” or “longitudinal” is parallel to the indicated “Z” axis and perpendicular to the “X” and “Y” axes.

[0015] In this specification, features described as “neighboring” (e.g., structures, materials, regions, devices) mean, and include, features that have the same disclosed attributes (or sets of attributes) and are located closest to each other (e.g., in the nearest location). Additional features that do not match the same attributes (or sets of attributes) of the “neighboring” features (e.g., additional regions, additional structures, additional elements) may be located between these “neighboring” features. In other words, “neighboring” features may be located directly adjacent to each other without any other features intervening between them, or they may be located indirectly adjacent to each other by the placement of at least one feature having attributes different from those associated with at least one of the “neighboring” features. Thus, features described as “vertically adjacent” mean, and include, features that have the same disclosed attributes (or sets of attributes) and are located closest to each other in the vertical direction (e.g., in the nearest vertical location). Furthermore, features described as “horizontally adjacent” mean, and include, features that have the same disclosed attributes (or sets of attributes) and are located closest to each other in the horizontal direction (e.g., in the nearest horizontal location).

[0016] In this specification, terms indicating positional relationships such as "beneath", "below", "lower", "bottom", "over / above", "upper", "top", "front", "rear", "left", and "right" are used for the convenience of explaining the relationship between elements or features shown in the drawings and other elements or features. Unless otherwise specified, these terms indicating positional relationships are intended to include different orientations of the material in addition to the orientation shown in the figure. For example, when the material shown in the figure is reversed, an element described as "below" or "beneath" or "under" or "on bottom of" another element or feature will be located "above" or "on top of" the other element or feature. Therefore, those skilled in the art should understand that the term "below" can include both the "above" and "below" orientations depending on the context in which it is used. The material can be arranged in other orientations (e.g., rotated 90 degrees, reversed, inverted arrangement), and in that case, the description of the positional relationship used in this specification will be interpreted accordingly.

[0017] In this specification, unless an element is clearly indicated as singular in context, the element shall also include the case where it is plural.

[0018] In this specification, items listed with "and / or" shall include any one of the listed items or any combination of two or more of them.

[0019] In this specification, the expression "coupled to" refers to a structure connected in an operatively linked manner, including, for example, an electrical connection by a direct ohmic connection or an indirect connection through other structures (e.g., a connection via other structures).

[0020] In this specification, the term “substantially” means, and includes, that a given parameter, characteristic, or condition is met to the extent that a person skilled in the art would understand that such parameter, characteristic, or condition is met within an acceptable range of variation. For example, depending on the specific parameter, characteristic, or condition that is substantially met, that parameter, characteristic, or condition may be met at least 90.0%, at least 95.0%, at least 99.0%, at least 99.9%, or 100.0%.

[0021] In this specification, the terms “about” or “approximately” refer to a numerical value relating to a particular parameter and include both the numerical value itself and the degree of variation that a person skilled in the art would understand to be acceptable with respect to that parameter. For example, “about” or “approximately” with respect to a numerical value may include a value in the range of 90.0% to 110.0%, a value in the range of 95.0% to 105.0%, a value in the range of 97.5% to 102.5%, a value in the range of 99.0% to 101.0%, a value in the range of 99.5% to 100.5%, or a value in the range of 99.9% to 100.1%.

[0022] As used herein, the term "conductive material" means a material having electrical conductivity and includes such materials. Materials having electrical conductivity include, for example, metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pd), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al)), alloys (e.g., Co-based alloys, Fe-based alloys, Ni-based alloys, Fe-Ni-based alloys, Co-Ni-based alloys, Fe-Co-based alloys, Co-Ni-Fe-based alloys, Al-based alloys, Cu-based alloys, Mg-based alloys, Ti-based alloys, steels, low-carbon steels, stainless steels), conductive metal-containing materials (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides), and conductive doped semiconductor materials (e.g., conductive doped polycrystalline silicon, conductive doped germanium (Ge), conductive doped silicon germanium (SiGe)). Further, the term "conductive structure" refers to a structure formed from a conductive material or a structure including a conductive material.

[0023] In this specification, "insulative material" means, and includes, materials that are electrically insulating. Examples of electrically insulating materials include the following: In other words, it may include one or more dielectric oxide materials (e.g., silicon oxide (SiOx), silicate glass phosphate, silicate glass borate, silicate glass borate, silicate glass fluoride, aluminum oxide (AlOx), hafnium oxide (HfOx), niobium oxide (NbOx), titanium oxide (TiOx), zirconium oxide (ZrOx), tantalum oxide (TaOx), magnesium oxide (MgOx)), one or more dielectric nitride materials (e.g., silicon nitride (SiNy)), one or more dielectric oxynitride materials (e.g., silicon oxynitride (SiOxNy)), one or more dielectric oxycarbide materials (e.g., silicon oxycarbide (SiOxCy)), one or more hydrogenated dielectric oxycarbide materials (e.g., silicon hydride oxycarbide (SiCxOyHz)), and one or more dielectric carbonate nitride materials (e.g., silicon carbonate (SiOxCzNy)). In this specification, formulas containing "x", "y", and "z" (e.g., SiOx, AlOx, HfOx, NbOx, TiOx, SiNy, SiOxNy, SiOxCy, SiCxOyHz, SiOxCzNy) represent materials having an average ratio of "x" atoms, "y" atoms of another element, and (if any) "z" atoms of an additional element for every atom of one element (e.g., Si, Al, Hf, Nb, Ti). Because these formulas represent relative atomic ratios rather than exact chemical structures, insulating materials may contain one or more stoichiometric compounds and / or one or more non-stoichiometric compounds. The values ​​of "x", "y", and "z" (if any) may be integers or non-integers. In this specification, "non-stoichiometric compound" means, and includes, compounds whose elemental composition cannot be expressed by clear natural number ratios and which do not obey the law of constant proportions. Furthermore, an "insulative structure" refers to a structure formed from an insulating material, or an insulating material itself.

[0024] In this specification, "semiconductor material" means, and includes, a material having electrical conductivity between that of an insulating material and a conductive material. For example, a semiconductor material has an electrical conductivity of about 10 at room temperature. -8 Siemens per centimeter (S / cm) to approximately 10 4 S / cm(10 6 The semiconductor material may have an electrical conductivity in the range of S / m. Examples of semiconductor materials include elements belonging to Group IV of the periodic table, such as silicon (Si), germanium (Ge), and carbon (C). Other examples include, but are not limited to, compound semiconductor materials, such as binary compound semiconductor materials (e.g., gallium arsenide (GaAs)), ternary compound semiconductor materials (e.g., AlXGa1-XAs), and quaternary compound semiconductor materials (e.g., GaXIn1-XAsYP1-Y). Compound semiconductor materials may include, but are not limited to, combinations of elements from Groups III and V of the periodic table (Group III-V semiconductor materials), or combinations of elements from Groups II and VI of the periodic table (Group II-VI semiconductor materials). Furthermore, other examples of semiconductor materials include oxide semiconductor materials, such as zinc tin oxide (ZnxSnyO, known as "ZTO"), indium zinc oxide (InxZnyO, known as "IZO"), zinc oxide (ZnxO), indium gallium zinc oxide (InxGayZnzO, known as "IGZO"), indium gallium silicon oxide (InxGaySizO, known as "IGSO"), indium tungsten oxide (InxWyO, known as "IWO"), indium oxide (InxO), tin oxide (SnxO), titanium oxide (TixO), and oxynitride. Examples include lead (ZnxONz), magnesium zinc oxide (MgxZnyO), indium zirconium zinc oxide (ZrxInyZnnzO), indium hafnium zinc oxide (HfxInyZnnzO), indium tin zinc oxide (SnxInyZnnzO), indium aluminum tin zinc oxide (AlxSnyInzZnaO), indium silicon zinc oxide (SixInyZnnzO), zinc tin aluminum oxide (AlxZnySnzO), zinc tin gallium oxide (GaxZnySnzO), zinc tin zirconium oxide (ZrxZnySnzO), and similar materials.

[0025] In this specification, “homogeneous” means that the relative amounts of elements contained in a feature (e.g., material, structure) do not vary across different parts of the feature (e.g., different horizontal parts, different vertical parts). Conversely, “heterogeneous” means that the relative amounts of elements contained in a feature vary across different parts of the feature. If a feature is heterogeneous, the amounts of one or more elements contained in the feature may vary discontinuously (e.g., abruptly) or continuously (e.g., gradually, linearly, parabolicly, etc.). For example, the feature may be formed from, or containing, a stack of at least two different materials.

[0026] Unless otherwise specified, the materials described herein may be formed by any suitable technique. This includes, but is not limited to, spin coating, full coating, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), physical vapor deposition (PVD) (e.g., sputtering), or epitaxial growth. Depending on the specific material to be formed, a person skilled in the art may select the deposition or growth technique. Furthermore, unless otherwise specified, the materials described herein may be removed by any suitable technique. This includes, but is not limited to, etching (e.g., dry etching, wet etching, vapor etching), ion milling, polishing planarization (e.g., chemical mechanical planarization (CMP)), or other known methods.

[0027] Figures 1A to 1F are simplified partial cross-sectional views showing different processing steps in a method for forming a microelectronic device (e.g., a memory device such as a 3D NAND flash memory device) according to the embodiments of this disclosure. Those skilled in the art will readily understand from the following description that the methods and structures described herein are applicable to the formation of various devices and electronic systems.

[0028] Referring to Figure 1A, the first microelectronic device structure 100 may be formed to include a first base structure 102 and a first circuit region 104 (e.g., a control circuit region) located at least partially on the first base structure 102. The first circuit region 104 may be located on the front side of the first base structure 102 and can therefore be considered a front-side circuit region with respect to the first base structure 102. Additional (e.g., a second) circuit regions may be formed on the back side of the first base structure 102 and can therefore be considered a back-side circuit region with respect to the first base structure 102, as will be described in more detail below. The first circuit region 104 may include a transistor 106, a first wiring structure 116, a first contact structure 118, and a first insulating material 122. The first circuit region 104 of the first microelectronic device structure 100 may be used in a microelectronic device (e.g., a memory device such as a 3D NAND flash memory device) later formed using the first microelectronic device structure 100 and at least one additional microelectronic device structure. The transistor 106, first wiring structure 116, and first contact structure 118 of the first microelectronic device structure 100 may constitute various first devices 120 (e.g., control logic circuits) of the first circuit region 104, as will be described in more detail below.

[0029] The first base structure 102 of the first microelectronic device structure 100 includes a base material or base structure on which additional features (e.g., materials, structures, devices) of the first microelectronic device structure 100 are formed. The first base structure 102 may include a semiconductor structure (e.g., a semiconductor wafer) or a base semiconductor material on a support structure. For example, the first base structure 102 may include a conventional silicon substrate (e.g., a conventional silicon wafer) or another bulk substrate containing a semiconductor material. In some embodiments, the first base structure 102 includes a silicon wafer. Furthermore, the first base structure 102 may include one or more layers, structures, and / or regions formed inside and / or on it. For example, the first base structure 102 may include conductive doped regions and undoped regions.

[0030] The transistors 106 of the first circuit region 104 may be formed to be interposed vertically between a portion of the first base structure 102 and the first wiring structure 116 of the first circuit region 104. Each transistor 106 may be formed to include a conductive doped region 108 formed within the first base structure 102 (e.g., functioning as the source and drain regions of the transistor 106), a channel region 110 (located within the first base structure 102) interposed horizontally between the conductive doped regions 108, a gate structure 112 (e.g., a gate electrode) positioned vertically above the channel region 110, and a gate insulating material 114 interposed vertically (e.g., in the Z direction) between the channel region 110 and the gate structure 112 and overlapping with the channel region 110 horizontally (e.g., in the X and Y directions).

[0031] For each transistor 106 in the first circuit region 104, the conductive doped regions 108 within its first base structure 102 may be doped with one or more desired dopants (e.g., chemical species). In some embodiments, the conductive doped regions 108 of each transistor 106 are doped with at least one N-type dopant (e.g., one or more of phosphorus, arsenic, antimony, and bismuth). In some such embodiments, the channel region 110 of the transistor 106 is doped with at least one P-type dopant (e.g., one or more of boron, aluminum, and gallium). In other such embodiments, the channel region 110 of the transistor 106 is substantially undoped. In yet another embodiment, the conductive doped regions 108 of each transistor 106 are doped with at least one P-type dopant (e.g., one or more of boron, aluminum, and gallium). In some of these additional embodiments, the channel region 110 of transistor 106 is doped with at least one N-type dopant (e.g., one or more of phosphorus, arsenic, antimony, and bismuth). In other such additional embodiments, the channel region 110 of transistor 106 is substantially undoped.

[0032] The gate structure 112 extends horizontally (e.g., in the Y direction) and can be used between multiple transistors 106 in the first circuit region 104. The gate structure 112 may be formed from or in combination with conductive materials. As a non-limiting example, the gate structure 112 may be formed from or in combination with at least one metal, at least one alloy, and at least one conductive metal-containing material (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). Each of the gate structures 112 may be substantially homogeneous or heterogeneous.

[0033] The gate insulating material 114 may be formed from, or contain, a dielectric material, such as a dielectric oxide material (e.g., silicon oxide). In some embodiments, the gate insulating material 114 is formed from, or containing, silicon dioxide (SiO2).

[0034] The first wiring structure 116 is located above the first base structure 102 in the vertical direction (e.g., the Z direction) and can be electrically connected to at least some of the transistors 106. The first wiring structure 116 can function as a local wiring structure for a microelectronic device later formed using the first microelectronic device structure 100 and at least one additional microelectronic device structure. The first group 118A of the first contact structure 118 extends vertically and can connect at least some of the transistors 106 to one or more of the first wiring structures 116. Furthermore, the second group 118B of the first contact structure 118 extends vertically and can connect some of the first wiring structures 116 to each other.

[0035] Each first wiring structure 116 may be formed from or containing a conductive material. In non-limiting examples, each first wiring structure 116 may be formed from or containing at least one metal, at least one alloy, and at least one conductive metal-containing material (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). In some embodiments, each first wiring structure 116 may be formed from or containing copper (Cu). In yet other embodiments, each first wiring structure 116 may be formed from or containing tungsten (W).

[0036] The first contact structures 118 (including the first group 118A and the second group 118B) may each be formed from or containing conductive materials. In non-limiting examples, the first contact structures 118 may be formed from or containing at least one metal, at least one alloy, and at least one conductive metal-containing material (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides). In some embodiments, the first contact structures 118 may each be formed from or containing copper (Cu). In yet other embodiments, the first contact structures 118 may each be formed from or containing tungsten (W). In further embodiments, the first group 118A of the first contact structure 118 may be formed from only the first conductive material (e.g., W) or including the first conductive material (e.g., W), and the second group 118B of the first contact structure 118 may be formed from only a second different conductive material (e.g., Cu) or including the second different conductive material (e.g., Cu).

[0037] As described above, the transistor 106, the first wiring structure 116, and the first contact structure 118 may constitute circuits (e.g., control logic circuits) of various first devices 120 (e.g., control logic devices) in the first circuit region 104. In some embodiments, one or more of the first devices 120 constitute control logic devices, each including complementary metal-oxide-semiconductor (CMOS) circuits. The first devices 120 may be configured to control various operations of other components (e.g., memory cells) of a microelectronic device (e.g., a memory device such as a 3D NAND flash memory device) that is later formed using the first microelectronic device structure 100 and at least one additional microelectronic device structure. In a non-limiting example, the first devices 120 (e.g., each) may include a charge pump (e.g., V CCP Charge pump, V NEGWLCharge pumps (DVC2 charge pumps), delay-locked loop (DLL) circuits (e.g., ring oscillators), V dd It may include one or more of the following: regulators, drivers (e.g., string drivers), page buffers, decoders (e.g., local deck decoders, column decoders, row decoders), sense amplifiers (e.g., equalization (EQ) amplifiers, isolation (ISO) amplifiers, NMOS sense amplifiers (NSAs), PMOS sense amplifiers (PSAs)), repair circuits (e.g., column repair circuits, row repair circuits), I / O devices (e.g., local I / O devices), memory test devices, array multiplexers (MUX), error detection and correction (ECC) devices, self-refresh / wear leveling devices, and other chip / deck control circuits.

[0038] Continuing to refer to Figure 1A, the first insulating material 122 may be formed to cover and surround a portion of the transistor 106, the first wiring structure 116, and the first contact structure 118. In some embodiments, the first insulating material 122 is formed to substantially cover the uppermost surface of the first wiring structure 116 at the top of the first microelectronic device structure 100, so that the uppermost surface of the first insulating material 122 is located vertically above the uppermost surface of the first wiring structure 116. In yet another embodiment, the first insulating material 122 is formed such that its uppermost surface is substantially coplanar with the uppermost surface of the first wiring structure 116 at the top of the first microelectronic device structure 100. Thus, the uppermost surface of the first wiring structure 116 is not covered by the first insulating material 122.

[0039] The first insulating material 122 may be formed from or comprising at least one insulating material. As a non-limiting example, the first insulating material 122 may be formed from or comprising at least one dielectric oxide material (e.g., one or more of SiOx, silicate glass phosphate, silicate glass borate, silicate glass borate, silicate glass fluorine, silicate glass, AlOx, HfOx, NbOx, and TiOx), at least one dielectric nitride material (e.g., SiNy), at least one dielectric oxynitride material (e.g., SiOxNy), at least one dielectric carboxynitride material (e.g., SiOxCzNy), and one or more amorphous carbon. In some embodiments, the first insulating material 122 may be formed from or comprising SiOx (e.g., SiO2). The first insulating material 122 may be substantially homogeneous or heterogeneous.

[0040] Referring next to Figure 1B, the first microelectronic device structure 100 (Figure 1A) may be joined (e.g., bonded) to the second microelectronic device structure 124 to form the first microelectronic device structure assembly 126. The second microelectronic device structure 124 may include a second base structure 128 and a second insulating material 130 formed on or inside it.

[0041] The second base structure 128 of the second microelectronic device structure 124 includes a base material or base structure on which additional features (e.g., materials, structures, devices) are formed. In some embodiments, the second base structure 128 includes a wafer. The second base structure 128 includes a semiconductor material (e.g., one or more silicon materials such as single-crystal silicon or polycrystalline silicon (also referred to herein as "polysilicon"), silicon germanium, germanium, gallium arsenide, gallium nitride, gallium phosphide, indium phosphide, indium gallium nitride, and aluminum gallium nitride), a base semiconductor material on a support structure, a glass material (e.g., borate silicate glass (BSP), phosphate silicate glass (PSG), fluorine silicate glass (F The second base structure 128 may be formed from, or include, one or more of the following: SG), boric acid silicate glass (BPSG), aluminosilicate glass, alkaline earth borate aluminosilicate glass, quartz, titania silicate glass, soda-lime glass, and ceramic materials (e.g., one or more of polyaluminum nitride (p-AlN), silicon on polyaluminum nitride (SOPAN), aluminum nitride (AlN), aluminum oxide (e.g., sapphire, α-Al2O3), and silicon carbide). As a non-limiting example, the second base structure 128 may include a semiconductor wafer (e.g., a silicon wafer), a glass wafer, or a ceramic wafer. The second base structure 128 may include one or more layers, structures, and / or regions inside and / or on its interior. Furthermore, the second base structure 128 may be configured to allow for safe handling of the first microelectronic device structure assembly 126 for later bonding to an additional (e.g., a third) microelectronic device structure, as will be described in more detail below.

[0042] The second insulating material 130 of the second microelectronic device structure 124 may be formed from or comprising at least one insulating material. The material composition of the second insulating material 130 of the second microelectronic device structure 124 may be substantially the same as the material composition of the first insulating material 122 of the first microelectronic device structure 100, or it may be different from the material composition of the first insulating material 122. In some embodiments, the second insulating material 130 may be formed from or comprising only a dielectric oxide material such as SiOx (e.g., SiO2). The second insulating material 130 may be substantially homogeneous or heterogeneous.

[0043] To join the second microelectronic device structure 124 to the first microelectronic device structure 100, the second microelectronic device structure 124 is inverted vertically (for example, upside down in the Z direction), and its second insulating material 130 is in physical contact with the first insulating material 122 of the first microelectronic device structure 100 at an initial interface 125 (shown by a dashed line in Figure 1B). The second insulating material 130 and the first insulating material 122 are then exposed to annealing conditions, and a bond (e.g., an oxide-oxide bond) may be formed between them. As a non-limiting example, the second insulating material 130 and the first insulating material 122 may be exposed to temperatures above about 400°C (e.g., in the range of about 400°C to about 800°C, or above about 800°C), and an oxide-oxide bond may be formed between them. In some embodiments, the first insulating material 122 and the second insulating material 130 are exposed to at least one temperature above about 800°C to form an oxide-oxide bond between them. After the bonding process, the resulting first microelectronic device structure assembly 126 can be inverted vertically (e.g., upside down in the Z direction) as shown in Figure 1B, with the first base structure 102 positioned vertically above the second base structure 128. In yet another embodiment, the first microelectronic device structure 100 is inverted vertically (e.g., upside down in the Z direction), with its first insulating material 122 in physical contact with the second insulating material 130 of the second microelectronic device structure 124, and the first insulating material 122 and the second insulating material 130 can be exposed to annealing conditions to form a bond (e.g., an oxide-oxide bond) between them. In such embodiments, it is not necessary to invert the first microelectronic device structure assembly 126 after the bonding process described above in order to position the first base structure 102 vertically above the second base structure 128.

[0044] A first connecting insulating structure 132 can be formed by bonding a second insulating material 130 to a first insulating material 122. In Figure 1B, the first insulating material 122 and the second insulating material 130 of the first connecting insulating structure 132 are distinguished by a dashed line representing the initial interface 125 before the bonding process (e.g., oxide-oxide bonding process), but after the bonding process, the first insulating material 122 and the second insulating material 130 can be integral and continuous. In other words, the first connecting insulating structure 132 can be a substantially monolithic (e.g., integrated) structure in which the first insulating material 122 is its first region (e.g., first vertical region) and the second insulating material 130 is its second region (e.g., second vertical region). In the first connecting insulating structure 132, the first insulating material 122 can be bonded to the second insulating material 130 without a bond line.

[0045] Referring now to Figure 1C, the first microelectronic device structure assembly 126 (Figure 1B) may be further processed to form a modified first microelectronic device structure assembly 127. For example, as will be described in more detail below, a portion of the first base structure 102 may be removed, and a second circuit region 146 containing additional circuits and devices may be formed inside, on, or above the remaining portion of the first base structure 102 (e.g., the unremoved portion), and one or more second contact structures 136 (e.g., interconnection structures) may be formed vertically so as to completely penetrate the remaining portion of the first base structure 102. The modified first microelectronic device structure assembly 127 may be formed to include additional features (e.g., structures, materials, regions, devices), as will be described in more detail below.

[0046] A portion of the first base structure 102 (e.g., a back portion, an upper portion) may be removed through one or more separation steps (e.g., a conventional separation step) and grinding steps (e.g., a conventional grinding step). The material removal steps thin the first base structure 102 (e.g., reduce its vertical thickness), and the material of the first base structure 102 may then be subjected to further processing, as described in detail below.

[0047] As shown in Figure 1C, the second circuit region 146 may be located on the back side of the remaining portion of the first base structure 102. Thus, the second circuit region 146 can be considered a back-side circuit region with respect to the first base structure 102. The remaining portion of the first base structure 102 may be interposed perpendicularly between the second circuit region 146 (e.g., back-side circuit region) and the first circuit region 104 (e.g., front-side circuit region) of the modified first microelectronic device structure assembly 127. The second circuit region 146 may include a second device 144 that constitutes and contains additional circuitry. The second device 144 may be configured to control or assist various operations of other components of a microelectronic device (e.g., a memory device such as a 3D NAND flash memory device) that is later formed using the modified first microelectronic device structure assembly 127 and at least one additional microelectronic device structure.

[0048] In some embodiments, the second device 144 of the second circuit region 146 may include one or more capacitors 129 formed inside, on, or above the remaining portion of the first base structure 102. Each capacitor 129 may include an insulating material 133 interposed between the first material 131 (e.g., a semiconductor material, a metallic material) and the second material 134. The first material 131 may be formed inside or on the remaining portion of the first base structure 102 (e.g., on or near the back surface of the remaining portion), the insulating material 133 may be formed on the first material 131, and the second material 134 may be formed on the insulating material 133. In some embodiments, one or more of the capacitors 129 are metal-insulator-semiconductor (MIS) capacitors, where the first material 131 is formed from or including a semiconductor material (e.g., silicon), and the second material 134 is formed from or including a metallic material (e.g., a metal such as tungsten (W)). In some such embodiments, the insulating material 133 of one or more MIS capacitors is formed from or including a dielectric oxide (e.g., SiOx, silicon dioxide (SiO2), etc.), thereby making the one or more MIS capacitors metal-oxide-semiconductor (MOS) capacitors. In yet another embodiment, one or more capacitors 129 are metal-insulator-metal (MIM) capacitors, where the first material 131 is formed from or including a metallic material (e.g., a first metal, tungsten (W), etc.), and the second material 134 is formed from or including an additional metallic material (e.g., an additional metal, tungsten (W), etc.).

[0049] In yet another embodiment, the second device 144 of the second circuit region 146 may include additional devices (e.g., devices other than the capacitor 129, or devices further included in addition to the capacitor 129) that are at least partially formed within the remaining portion of the first base structure 102. For example, one or more additional transistors similar to transistor 106 may be formed on or near the back surface (e.g., the top surface) of the remaining portion of the first base structure 102. For each additional transistor, its conductive doped region (e.g., similar to conductive doped region 108) and channel region (e.g., similar to channel region 110) may be formed on or near the back surface (e.g., the top surface) of the remaining portion of the first base structure 102, and its gate structure (e.g., similar to gate structure 112) and gate insulating material (e.g., similar to gate insulating material 114) may be formed on its back surface. Therefore, the remaining portion of the first base structure 102 may include a transistor 106 on its surface side (e.g., the bottom surface) or in its vicinity, and may include an additional transistor on the opposing back surface or in its vicinity.

[0050] Continuing to refer to Figure 1C, one or more second contact structures 136 may be formed extending vertically to completely penetrate the remaining portion of the first base structure 102. The second contact structures 136 may be formed to at least partially fill vias (e.g., through-silicon vias (TSVs)) formed to vertically penetrate the remaining portion of the first base structure 102. The second contact structures 136 may be formed to extend vertically to reach and contact the first wiring structure 116 located vertically below the remaining portion of the first base structure 102.

[0051] The second contact structure 136 may be formed from or including a conductive material. The second contact structure 136 may enable electrical connection between a feature (e.g., structure, material, circuit, device) located vertically above the remaining portion of the first base structure 102 and an additional feature (e.g., additional structure, additional material, additional circuit, additional device) located vertically below the remaining portion of the first base structure 102. In some embodiments, each second contact structure 136 includes a metallic material, which includes at least one metal, at least one alloy, and at least one conductive metal-containing material (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). In some embodiments, the second contact structure 136 may be formed from or including tungsten(W).

[0052] Continuing to refer to Figure 1C, the first insulating liner material 138 may be formed to extend substantially continuously over and substantially cover one or more second contact structures 136. The first insulating liner material 138 may partially fill one or more vias (e.g., one or more TSVs) containing one or more second contact structures 136. The first insulating liner material 138 may be interposed horizontally between the second contact structures 136 and the remaining portion of the first base structure 102. The first insulating liner material 138 is formed of or comprising at least one insulating material, for example, at least one dielectric oxide material (e.g., one or more of SiOx, silicate glass phosphate, silicate glass borate, silicate glass borate, silicate glass fluorine, silicate glass AlOx, HfOx, NbOx, TiOx, ZrOx, TaOx, MgOx), at least one dielectric nitride material (e.g., SiNy), at least one dielectric oxynitride material (e.g., SiOxNy), and at least one dielectric carboxynitride material (e.g., SiOxCzNy). In some embodiments, the first insulating liner material 138 is formed from or comprising a dielectric oxide material (e.g., SiOx, silicon dioxide (SiO2), etc.).

[0053] Continuing to refer to Figure 1C, the second wiring structure 140 may be formed to be positioned vertically (e.g., in the Z direction) above different devices (e.g., capacitors 129, transistors) formed inside, above, or above the second contact structure 136 and the remaining portion of the first base structure 102. A portion of the second wiring structure 140 may be in contact (e.g., physical contact, electrical contact) with the second contact structure 136. At least a portion of the second wiring structure 140 may be used as an additional local wiring structure for a microelectronic device (e.g., a memory device such as a 3D NAND flash memory device). The second wiring structure 140 may constitute part of the circuit of at least a portion of the second device 144 in the second circuit region 146 and / or may be coupled to different second devices 144 in the second circuit region 146 and / or to the second contact structure 136. Each second wiring structure 140 may be formed from or including conductive material alone. As a non-limiting example, the second wiring structure 140 may be formed from or comprising one or more of the following: at least one metal, at least one alloy, and at least one conductive metal-containing material (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). In some embodiments, the second wiring structure 140 is formed from or comprising copper (Cu). In yet another embodiment, the second wiring structure 140 is formed from or comprising tungsten (W).

[0054] Furthermore, the third contact structure 142 may be formed to extend vertically from at least a portion of the second wiring structure 140 toward at least a portion of a device (e.g., a capacitor 129) formed inside, on, or above the remaining portion of the first base structure 102. For example, as shown in Figure 1C, each third contact structure 142 may be formed to be vertically interposed between and in contact with (e.g., physical contact, electrical contact) each individual capacitor 129 and each individual second wiring structure 140. The second contact structure 136 and the third contact structure 142 may be formed after the formation of the capacitor 129 (and / or additional devices, e.g., additional transistors), after which the second wiring structure 140 may be formed on and in contact with at least a portion of the second contact structure 136 and at least a portion of the third contact structure 142. Each third contact structure 142 may be formed from or containing a conductive material. As a non-limiting example, the third contact structure 142 may be formed from or comprising one or more of the following: at least one metal, at least one alloy, and at least one conductive metal-containing material (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). In some embodiments, the third contact structure 142 is formed from or comprising copper (Cu). In yet another embodiment, the third contact structure 142 is formed from or comprising tungsten (W).

[0055] By forming the first circuit region 104 and the second circuit region 146 on opposite sides of the first base structure 102 (e.g., the front side and the back side, respectively), the surface area of ​​the first base structure 102 can be effectively increased and utilized for forming the desired circuit or device, compared to a configuration in which only one side of the base structure (e.g., the front side or the back side) is used to form the desired circuit or device. Therefore, by forming the first circuit region 104 and the second circuit region 146 on opposite sides of the first base structure 102, it is possible to promote an improvement in feature density compared to conventional microelectronic device configurations, thereby relatively improving the performance of microelectronic devices (e.g., memory devices such as 3D NAND devices) and electronic systems that depend on a high feature density.

[0056] In some cases, the modified first microelectronic device structure assembly 127 may further include a first bonding pad 150 on or above the upper surface of the second wiring structure 140. The first bonding pad 150 is formed on the upper surface of the second wiring structure 140 and may be bonded to individual second wiring structures 140. The first bonding pad 150 may be in direct physical contact with the second wiring structure 140, or it may be bonded to the second wiring structure 140 via an intervening conductive structure (e.g., a contact structure). If the first bonding pad 150 is formed, it is used to bond at least a portion of the second wiring structure 140 to an additional conductive structure (e.g., a bonding pad or a conductive contact structure). Also, at least a portion of the first bonding pad 150 thus formed may be configured to connect (e.g., bond) to an additional (e.g., second) bonding pad of an additional (e.g., third) microelectronic device structure to be joined later. On the other hand, in another embodiment, the first bonding pad 150 may be omitted (i.e., not formed) and may not be included in the modified first microelectronic device structure assembly 127.

[0057] The first bonding pad 150, if present, is formed from or containing a conductive material. In non-limiting examples, the first bonding pad 150 may be formed from or containing one or more of at least one metal, at least one alloy, and at least one conductive metal-containing material. In some embodiments, the first bonding pad 150 is formed from or containing copper (Cu) alone.

[0058] Continuing to refer to Figure 1C, at least one third insulating material 148 may be formed to cover and surround the capacitor 129 (and / or additional devices such as additional transistors formed on or over the remaining portion of the first base structure 102), the second contact structure 136, the first insulating liner material 138, the second wiring structure 140, the third contact structure 142, the second device 144, and the first bonding pad 150 (if present), in addition to the remaining portion of the first base structure 102. The third insulating material 148 may be formed from or including at least one insulating material. As a non-limiting example, the third insulating material 148 may be formed from or comprising one or more of the following: at least one dielectric oxide material (e.g., one or more of SiOx, silicate glass phosphate, silicate glass borate, silicate glass borate, silicate glass fluorine, silicate glass, AlOx, HfOx, NbOx, TiOx), at least one dielectric nitride material (e.g., SiNy), at least one dielectric oxynitride material (e.g., SiOxNy), at least one dielectric carboxynitride material (e.g., SiOxCzNy), and amorphous carbon. In some embodiments, the third insulating material 148 may be formed from or comprising only SiOx (e.g., SiO2). The third insulating material 148 may be substantially homogeneous or heterogeneous. When the first bonding pad 150 is formed, the upper surface of the third insulating material 148 may be substantially coplanar with the upper surface of the first bonding pad 150, or the upper surface of the third insulating material 148 may be located vertically above the upper surface of the first bonding pad 150.

[0059] Referring next to Figure 1D, a third microelectronic device structure 152 may be formed, which will later be joined to the modified first microelectronic device structure assembly 127 (Figure 1C). The third microelectronic device structure 152 may be formed to include a third base structure 154 and a memory array region 156 located vertically above it. The memory array region 156 includes a stack structure 166, a deep contact structure 174 and a cell pillar structure 178 extending vertically through the stack structure 166, a source layer 158 located vertically below the stack structure 166, a digit line layer 182 located vertically above the stack structure 166, an insulating line structure 188 located vertically above the digit line layer 182, and a fourth contact structure 190 that penetrates vertically through the insulating line structure 188 to reach the digit line layer 182. The third microelectronic device structure 152 (including the third base structure 154 and the memory array region 156) comprises additional features (e.g., structures, materials, devices), as will be described in more detail below.

[0060] The third base structure 154 includes a base material or base structure on which additional features (e.g., materials, structures, devices) of the third microelectronic device structure 152 are formed. The third base structure 154 may include a semiconductor structure (e.g., a semiconductor wafer) or a base semiconductor material on a support structure. For example, the third base structure 154 may include a conventional silicon substrate (e.g., a conventional silicon wafer) or another bulk substrate containing a semiconductor material. In some embodiments, the third base structure 154 includes a silicon wafer. The third base structure 154 may include one or more layers, structures, and / or regions formed inside and / or on it.

[0061] The source layer 158 of the additional conductive line structure 186 may be interposed vertically between the third base structure 154 and the stack structure 166 located vertically above it. The source layer 158 may include at least one source structure 160 (e.g., a source plate) and at least one contact pad 162. The source structure 160 and the contact pad 162 may be arranged horizontally to each other (e.g., in the X or Y direction) within the source layer 158. The source structure 160 may be electrically insulated from the contact pad 162 and positioned substantially identically vertically to the contact pad 162 (e.g., in the Z direction). At least one insulating material may be interposed between the source structure 160, the contact pad 162, the third base structure 154, and the stack structure 166, as will be described in more detail below.

[0062] The source structure 160 and the contact pad 162 may each be formed from or containing a conductive material. The material composition of the source structure 160 may be substantially the same as that of the contact pad 162. In some embodiments, the source structure 160 and the contact pad 162 may be formed from or containing one or more metals, alloys, and conductive metal-containing materials (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides). As a non-limiting example, the source structure 160 and the contact pad 162 may be formed from or containing tungsten (W) alone. In yet another embodiment, the source structure 160 and the contact pad 162 may be formed from or containing one or more conductive doped forms of conductive doped semiconductor materials, such as silicon materials such as single-crystal silicon or polycrystalline silicon, silicon germanium materials, germanium materials, gallium arsenide materials, gallium nitride materials, and indium phosphide materials. As a non-limiting example, the source structure 160 and the contact pad 162 may be formed from, or comprising, silicon (e.g., polycrystalline silicon) doped with one or more of at least one dopants (e.g., at least one N-type dopant, at least one P-type dopant, or at least another dopant).

[0063] The source structure 160 of the source layer 158 may be connected to the cell pillar structure 178. In some embodiments, the source structure 160 is in direct physical contact with the cell pillar structure 178. In yet another embodiment, a contact structure may be interposed vertically between the source structure 160 and the cell pillar structure 178. In addition, the source structure 160 may be connected to, or subsequently connected to, additional structures (e.g., contact structures, wiring structures, pad structures) provided within the boundary of the third microelectronic device structure 152 or provided by a later processing step. This will be described in more detail below.

[0064] The contact pad 162 of the source layer 158 may be connected to additional conductive features (e.g., conductive contact structures, conductive pillars, conductive-filled vias) within the stack structure 166. For example, as shown in Figure 1D, the contact pad 162 may be connected to one or more deep contact structures 174 that extend vertically through the stack structure 166. In some embodiments, the contact pad 162 directly physically contacts the deep contact structure 174. In yet another embodiment, an additional contact structure may be interposed vertically between the contact pad 162 and the deep contact structure 174, connecting the contact pad 162 to the deep contact structure 174. In addition, the contact pad 162 may be connected to, or may be connected to, additional structures (e.g., interconnection structures, wiring structures, pad structures) provided within or provided by a later processing step within the third microelectronic device structure 152. This will be described in more detail below.

[0065] As shown in Figure 1D, the fifth contact structure 164 may be formed to interpose vertically between the source layer 158 and the third base structure 154. The fifth contact structure 164 may extend vertically from the source layer 158 (e.g., source structure 160 or contact pad 162) toward the third base structure 154. The fifth contact structure 164 may terminate vertically, for example, above, on, or within the third base structure 154. The fifth contact structure 164 may connect, for example, the source structure 160 and / or contact pad 162 of the source layer 158 to a feature (e.g., structure, material, region, device) of the third base structure 154. The fifth contact structure 164 may be formed from or including conductive material alone. As a non-limiting example, the fifth contact structure 164 may be formed from or comprising one or more of the following: at least one metal, at least one alloy, and at least one conductive metal-containing material (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). In some embodiments, the fifth contact structure 164 may be formed from or comprising copper (Cu) alone. In yet another embodiment, the fifth contact structure 164 may be formed from or comprising tungsten (W) alone.

[0066] Continuing to refer to Figure 1D, the stack structure 166 may be formed to be located vertically above the source layer 158 and may include a configuration in which conductive material 168 and insulating material 170 are alternately arranged vertically (e.g., in the Z direction) within the layers 172. Each layer 172 of the stack structure 166 may include conductive material 168 adjacent to insulating material 170 in the vertical direction. The stack structure 166 may be formed to include a desired number of layers 172, for example, 16 or more layers, 32 or more layers, 64 or more layers, 128 or more layers, or 256 or more layers.

[0067] The conductive material 168 of layer 172 of the stack structure 166 may be formed from or comprising one or more of the following: at least one metal, at least one alloy, at least one conductive metal-containing material, or at least one conductive doped semiconductor material. In some embodiments, the conductive material 168 of one or more layers 172 of the stack structure 166 (e.g., each) is formed from or comprising tungsten (W) alone. The conductive material 168 of individual layers 172 may be substantially homogeneous or substantially heterogeneous.

[0068] In some cases, one or more liner materials (e.g., insulating liner material, conductive liner material) may be formed around the conductive material 168 of one or more layers 172 of the stack structure 166 (e.g., each of them). The liner material may be formed from, and may include, one or more metals (e.g., titanium, tantalum), alloys, metal nitrides (e.g., tungsten nitride, titanium nitride, tantalum nitride), and metal oxides (e.g., aluminum oxide). In some embodiments, the liner material includes at least one conductive material used as a seed material for forming the conductive material 168. In some embodiments, the liner material includes titanium nitride (TiNx). In yet another embodiment, the liner material further includes aluminum oxide (AlOx). As a non-limiting example, AlOx may be formed directly adjacent to the insulating material 170 of one or more layers 172 (e.g., each of them), TiNx may be formed directly adjacent to AlOx, and W may be formed directly adjacent to TiNx. To facilitate understanding, the liner material is not shown in Figure 1D, but it will be understood that the liner material may be placed around the conductive material 168 of one or more (e.g., each) layers 172 of the stack structure 166.

[0069] The insulating material 170 of layer 172 of the stack structure 166 may be formed from and include one or more of the following: at least one dielectric oxide material (e.g., one or more of SiOx, silicate glass phosphate, silicate glass borate, silicate glass borate, silicate glass fluorine, AlOx, HfOx, NbOx, TiOx, ZrOx, TaOx, MgOx), at least one dielectric nitride material (e.g., SiNy), at least one dielectric oxynitride material (e.g., SiOxNy), and at least one dielectric carboxynitride material (e.g., SiOxCzNy). In some embodiments, the insulating material 170 of one or more layers 172 of the stack structure 166 (e.g., each) is formed from and includes a dielectric oxide material such as SiOx (e.g., SiO2). The insulating material 170 of individual layers 172 may be substantially homogeneous or substantially heterogeneous.

[0070] The cell pillar structure 178 may extend vertically through layer 172 of the stack structure 166 and connect to the source structure 160 of the source layer 158. Each cell pillar structure 178 may be formed from or including a laminate of materials. As a non-limiting example, each cell pillar structure 178 may be formed to include a first dielectric oxide material (e.g., SiOx [SiO2, etc.], AlOx [Al2O3, etc.]), a dielectric nitride material (e.g., SiNy [Si3N4, etc.]), a second oxide dielectric material (e.g., SiOx [SiO2, etc.]), a semiconductor material (e.g., Si [polycrystalline Si, etc.]), and a dielectric filler material (e.g., dielectric oxide, dielectric nitride, air). The first dielectric oxide material may be formed on or on the surface of the conductive material 168 and insulating material 170 of layer 172 of the stack structure 166, which at least partially define the horizontal boundary of the cell pillar structure 178. A dielectric nitride material may be surrounded horizontally by a first dielectric oxide material. A second oxide dielectric material may be surrounded horizontally by a dielectric nitride material. A semiconductor material may be surrounded horizontally by a second oxide dielectric material. Furthermore, a dielectric filler material may be surrounded horizontally by a semiconductor material.

[0071] Continuing to refer to Figure 1A, the intersection of the cell pillar structure 178 and the conductive material 168 of layer 172 of the stack structure 166 may define a vertically extending string of memory cells 180 connected in series with each other within the stack structure 166. In some embodiments, the memory cells 180 formed at the intersection of the conductive material 168 in different layers 172 of the stack structure 166 and the cell pillar structure 178 include so-called "MONOS" (metal-oxide-nitride-oxide-semiconductor) memory cells. In yet another embodiment, the memory cell 180 includes so-called "TANOS" (tantalum nitride-aluminum oxide-nitride-oxide-semiconductor) memory cells, or so-called "BETANOS" (band / barrier-engineered TANOS) memory cells, all of which are subsets of MONOS memory cells. In yet another embodiment, the memory cell 180 includes so-called "floating-gate" memory cells, which include a floating gate (e.g., a metal floating gate) as a charge-holding structure. A floating gate may be interposed horizontally between the central structure of the cell pillar structure 178 and the conductive material 168 of different layers 172 of the stack structure 166.

[0072] As shown in Figure 1D, the deep contact structures 174 may also extend vertically through the layer 172 of the stack structure 166. The deep contact structures 174 may be configured and positioned to electrically connect one or more features (e.g., structures, materials, devices) of a third microelectronic device structure 152 located vertically above the stack structure 166 to one or more additional features of the third microelectronic device structure 152 located vertically below the stack structure 166. One or more deep contact structures 174 may be connected to the source structure 160 of the source layer 158. Another or more deep contact structures 174 may be connected to the contact pads 162 of the source layer 158. The deep contact structures 174 may be formed from or including conductive material alone. In some embodiments, each deep contact structure 174 is formed from or including tungsten (W) alone. In yet another embodiment, each deep contact structure 174 is formed from or including conductive doped polycrystalline silicon alone.

[0073] The insulating liner structure 176 may be formed to substantially continuously cover and substantially coat the sides of the deep contact structure 174. The insulating liner structure 176 may be interposed horizontally between the deep contact structure 174 and the conductive material 168 (and insulating material 170) of layer 172 of the stack structure 166. The insulating liner structure 176 may be formed from and include at least one insulating material. For example, it may include at least one dielectric oxide material (one or more of SiOx, silicate glass phosphate, silicate glass borate, silicate glass borate, silicate glass fluorine silicate glass, AlOx, HfOx, NbOx, TiOx, ZrOx, TaOx, MgOx), at least one dielectric nitride material (SiNy), at least one dielectric oxynitride material (SiOxNy), and at least one dielectric carboxynitride material (SiOxCzNy). In some embodiments, the insulating liner structure 176 is formed from or comprising a dielectric oxide material (e.g., SiOx [SiO2, etc.]).

[0074] Continuing to refer to Figure 1D, the digit line layer 182 may be interposed vertically between the stack structure 166 and the insulating line structure 188 located vertically above it. The digit line layer 182 may include digit line structures 184 (e.g., digit lines, bit lines, data lines) and one or more additional conductive line structures 186. The digit line structures 184 and the additional conductive line structures 186 may be adjacent to each other horizontally (e.g., in the X and Y directions) within the digit line layer 182. The digit line structures 184 may be electrically insulated from the additional conductive line structures 186 and may be located in substantially the same vertical position as the additional conductive line structures 186 (e.g., in the Z direction). The possibility of at least one insulating material interposing between the digit line structures 184 and the additional conductive line structures 186 will be described in further detail below.

[0075] The digit wire structure 184 and the additional conductive line structure 186 are each formed from and may contain a conductive material. The material composition of the digit wire structure 184 may be substantially identical to that of the additional conductive line structure 186. In some embodiments, the digit wire structure 184 and the additional conductive line structure 186 may be formed from or containing one or more metals, alloys, and conductive metal-containing materials (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides). As a non-limiting example, the digit wire structure 184 and the additional conductive line structure 186 may be formed from or containing tungsten (W) alone. In yet another embodiment, the digit wire structure 184 and the additional conductive line structure 186 may be formed from or containing a conductive doped semiconductor material. As a non-limiting example, the digit line structure 184 and the additional conductive line structure 186 may be formed from, or including, silicon (e.g., polycrystalline silicon) doped with one or more of at least one dopant (e.g., at least one N-type dopant, at least one P-type dopant, or other dopants).

[0076] The digit line structures 184 are formed vertically above the cell pillar structures 178 (and thus the vertically extending strings of memory cells 180) and may be electrically connected to them. The digit line structures 184 exhibit an elongated shape extending horizontally and may extend parallel to one another along a first horizontal direction (e.g., the Y direction). As used herein, “parallel” means substantially parallel. Each of the digit line structures 184 may exhibit substantially identical dimensions (e.g., width in the X direction, length in the Y direction, height in the Z direction), shape, and spacing (e.g., spacing in the X direction). In yet another embodiment, one or more digit line structures 184 may exhibit at least one dimension (e.g., length, width, or height) and a different shape from the other digit line structures 184. Or, the spacing (e.g., in the X direction) between at least two horizontally adjacent digit line structures 184 may differ from the spacing between at least two other horizontally adjacent digit line structures 184.

[0077] Additional conductive line structures 186 of the digit line layer 182 may be connected to additional conductive features (e.g., conductive contact structures, conductive pillars, conductive vias) within the stack structure 166. For example, as shown in Figure 1D, the additional conductive line structure 186 may be connected to one or more deep contact structures 174 that extend perpendicularly through the stack structure 166. In some embodiments, the additional conductive line structure 186 is in direct physical contact with the deep contact structure 174. In yet another embodiment, an additional contact structure may be interposed perpendicularly between the additional conductive line structure 186 and the deep contact structure 174, electrically connecting the additional conductive line structure 186 to the deep contact structure 174.

[0078] The insulating line structure 188 may be formed on or above the digit line structure 184 and additional conductive line structure 186 of the digit line layer 182. The insulating line structure 188 may function as an insulating cap structure (e.g., a dielectric cap structure) for the digit line structure 184 and additional conductive line structure 186. The insulating line structure 188 may have an elongated shape extending horizontally and may extend parallel to each other along a first horizontal direction (e.g., the Y direction). The horizontal dimensions, horizontal paths, and horizontal spacing of the insulating line structure 188 may be substantially identical to the horizontal dimensions, horizontal paths, and horizontal spacing of the digit line structure 184 and additional conductive line structure 186.

[0079] The insulating line structures 188 may be formed from or in part with insulating material. In non-limiting examples, each insulating line structure 188 may be formed from or in part with dielectric nitride material, such as SiNy (Si3N4, etc.). Each insulating line structure 188 may be substantially homogeneous or heterogeneous.

[0080] The fourth contact structure 190 is formed to extend vertically through the insulating line structure 188 and may contact the digit line structure 184 of the digit line layer 182 and the additional conductive line structure 186. Each individual fourth contact structure 190 may have a portion located vertically above one of the insulating line structures 188, and another portion extending vertically through the insulating line structure 188 and making contact (e.g., physical contact, electrical contact) with one of the digit line structures 184 or the additional conductive line structures 186. Each individual fourth contact structure 190 may be aligned at least partially (e.g., substantially) horizontally with the individual insulating line structure 188 in the X direction. For example, the horizontal centerline of the fourth contact structure 190 in the X direction may be substantially aligned with the horizontal centerline of the insulating line structure 188 in the X direction. Furthermore, the fourth contact structure 190 may be formed at a desired position in the Y direction along the insulating line structure 188. In some embodiments, at least a portion of the fourth contact structure 190 may be positioned at different locations in the Y direction from each other. For example, the first fourth contact structure 190 may be located along the Y-length of the first insulating line structure 188 and at a different location from the second fourth contact structure 190 along the Y-length. At least a portion (e.g., all) of the fourth contact structures 190 may be offset horizontally from each other in the Y direction. In yet another embodiment, two or more fourth contact structures 190 may be aligned horizontally from each other in the Y direction.

[0081] Each of the fourth contact structures 190 may be formed from or in part with a conductive material. In non-limiting examples, each of the fourth contact structures 190 may be formed from or in part with at least one metal, at least one alloy, or at least one conductive metal-containing material (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). In some embodiments, the fourth contact structure 190 may be formed from or in part with copper (Cu). In yet another embodiment, the fourth contact structure 190 may be formed from or in part with tungsten (W).

[0082] Continuing to refer to Figure 1D, the third microelectronic device structure 152 may further include a second bonding pad 194 formed on or above the fourth contact structure 190. The second bonding pad 194 may be formed on or above the upper surface of the fourth contact structure 190. One or more of the second bonding pads 194 may be formed to extend horizontally over a plurality of insulating line structures 188. Each second bonding pad 194 may be connected to an individual fourth contact structure 190. The second bonding pads 194 may be used to connect at least some of the fourth contact structures 190 to additional conductive structures (e.g., bonding pads, conductive contact structures). This will be described in more detail below. In an embodiment, if the modified first microelectronic device structure assembly 127 (Figure 1C) is formed to include a first bonding pad 150 (Figure 1C), then at least a portion of the second bonding pad 194 of the third microelectronic device structure 152 may be configured to be later connected (e.g., later bonded) to at least a portion of the first bonding pad 150 (Figure 1C) of the modified first microelectronic device structure assembly 127 (Figure 1C).

[0083] Each second bonding pad 194 may be formed from or containing a conductive material. In non-limiting examples, the second bonding pad 194 may be formed from or containing one or more metals, alloys, or conductive metal-containing materials. The material composition of the second bonding pad 194 may be substantially the same as that of the fourth contact structure 190, or it may be different from that of the fourth contact structure 190. In one embodiment, the second bonding pad 194 is formed from or containing copper (Cu).

[0084] Continuing to refer to Figure 1D, at least one fourth insulating material 192 may be formed to cover and surround a portion of the third base structure 154, the source structure 160, the contact pad 162, the stack structure 166 (including the conductive material 168 and insulating material 170 in its layer 172), the digit line structure 184, the additional conductive line structure 186, the insulating line structure 188, the fourth contact structure 190, and the second bonding pad 194. The fourth insulating material 192 may be formed from or comprising at least one insulating material. As a non-limiting example, the fourth insulating material 192 may be formed from or comprising one or more dielectric oxide materials, dielectric nitride materials, dielectric oxynitride materials, dielectric carbonitride materials, and amorphous carbon. In one embodiment, the fourth insulating material 192 is formed from or comprising SiOx (e.g., SiO2). The fourth insulating material 192 may be substantially homogeneous or heterogeneous. The upper surface of the fourth insulating material 192 may be substantially coplanar with the upper surface of the second bonding pad 194, or the upper surface of the fourth insulating material 192 may vertically cover the upper surface of the second bonding pad 194.

[0085] Referring to Figure 1E, after forming the modified first microelectronic device structure assembly 127 and separately forming the third microelectronic device structure 152, the modified first microelectronic device structure assembly 127 may be inverted vertically (e.g., upside down in the Z direction) and brought into physical contact with the third microelectronic device structure 152 at the initial interface 195 (shown by a dashed line in Figure 1E). Subsequently, the modified first microelectronic device structure assembly 127 may be bonded to the third microelectronic device structure 152 to form the second microelectronic device structure assembly 196. Alternatively, the third microelectronic device structure 152 may be inverted vertically (e.g., upside down in the Z direction) and bonded to the modified first microelectronic device structure assembly 127 in physical contact to form the second microelectronic device structure assembly 196. Subsequently, the second microelectronic device structure assembly 196 may be inverted vertically (for example, upside down in the Z direction) so that the second base structure 128 vertically covers the third base structure 154. In Figure 1E, the vertical boundary between the two before the modified first microelectronic device structure assembly 127 is joined to the third microelectronic device structure 152 to form the second microelectronic device structure assembly 196 is shown by a dashed line indicating the initial interface 195 before the joining process.

[0086] Bonding the modified first microelectronic device structure assembly 127 to the third microelectronic device structure 152 may include bonding (e.g., oxide film bonding) the third insulating material 148 of the modified first microelectronic device structure assembly 127 to the fourth insulating material 192 of the third microelectronic device structure 152. In a non-limiting example, the third insulating material 148 and the fourth insulating material 192 may be exposed to an annealing temperature of about 400°C or higher (e.g., in the range of about 400°C to about 800°C, or above about 800°C) to form an oxide film bond between them. In one embodiment, the third insulating material 148 and the fourth insulating material 192 may be exposed to a temperature of at least about 800°C to form an oxide film bond between them. As shown in Figure 1E, a second connecting insulating structure 198 may be formed by bonding the third insulating material 148 and the fourth insulating material 192. In Figure 1E, the third insulating material 148 and the fourth insulating material 192 of the second connection insulating structure 198 are distinguished by a dashed line indicating the initial interface 195 before the bonding process, but after the bonding process, the third insulating material 148 and the fourth insulating material 192 can become an integrated and continuous structure. In other words, the second connection insulating structure 198 can be a substantially single (e.g., integrated) structure with the third insulating material 148 as its first region (e.g., first vertical region) and the fourth insulating material 192 as its second region (e.g., second vertical region). In the second connection insulating structure 198, the third insulating material 148 can be bonded to the fourth insulating material 192 without a bond line.

[0087] In embodiments where the modified first microelectronic device structure assembly 127 is formed to include a first bonding pad 150, bonding the modified first microelectronic device structure assembly 127 to the third microelectronic device structure 152 may further include bonding (e.g., metal-to-metal bonding) at least a portion of the first bonding pad 150 of the modified first microelectronic device structure assembly 127 to at least a portion of the second bonding pad 194 of the third microelectronic device structure 152. In non-limiting examples, the first bonding pad 150 and the second bonding pad 194 may be exposed to an annealing temperature of about 400°C or higher (e.g., in the range of about 400°C to about 800°C, or above about 800°C) to form a metal-to-metal bond between at least a portion of the first bonding pad 150 and at least a portion of the second bonding pad 194. In one embodiment, the first bonding pad 150 and the second bonding pad 194 are exposed to temperatures exceeding at least about 800°C, and a metallic bond can be formed between the first bonding pad 150 and the second bonding pad 194. As shown in Figure 1E, individual connecting pad structures 200 can be formed by bonding individual first bonding pads 150 to individual second bonding pads 194. In Figure 1E, the first bonding pad 150 and the second bonding pad 194 of the connecting pad structure 200 are distinguished by a dashed line indicating the initial interface 195 before the bonding process, but after the bonding process, the first bonding pad 150 and the second bonding pad 194 can become an integrated and continuous structure. In other words, each connecting pad structure 200 may be a substantially single (e.g., integrated) structure in which each first bonding pad 150 constitutes its first region (e.g., first vertical region) and each second bonding pad 194 constitutes its second region (e.g., second vertical region). In each connecting pad structure 200, the first bonding pad 150 can be joined to the second bonding pad 194 without a bond line.

[0088] Bonding the first bonding pad 150 (if present) of the modified first microelectronic device structure assembly 127 to the second bonding pad 194 of the third microelectronic device structure 152 can be done in addition to bonding the third insulating material 148 of the modified first microelectronic device structure assembly 127 to the fourth insulating material 192 of the third microelectronic device structure 152. Thus, if the modified first microelectronic device structure assembly 127 is formed to include the first bonding pad 150, the modified first microelectronic device structure assembly 127 can be bonded to the third microelectronic device structure 152 by a combination of oxide-to-oxide bonding (e.g., oxide-oxide bonding) between the third insulating material 148 and the fourth insulating material 192 and metal-to-metal bonding (e.g., metal-metal bonding) between the first bonding pad 150 and the second bonding pad 194. Bonding between the first bonding pad 150 and the second bonding pad 194 can be achieved by the same annealing process used for bonding between the third insulating material 148 and the fourth insulating material 192.

[0089] Referring to Figure 1F, after the formation of the second microelectronic device structure assembly 196 (Figure 1E), the second base structure 128 (Figure 1E) may be removed. Subsequently, an interconnect region 224 including a back-end-of-line (BEOL) structure may be formed vertically above the first circuit region 104. Furthermore, optionally, one or more through-contact structures 202 may be formed before at least some of the BEOL structures are formed, penetrating the first circuit region 104 and the second circuit region 146 completely vertically to reach the memory array region 156.

[0090] The second base structure 128 (Figure 1E) can be removed by one or more separation and grinding processes. As shown in Figure 1F, in some embodiments, after the material removal process, at least a portion of the first connection insulation structure 132 remains on the uppermost surface of the first wiring structure 116. In yet another embodiment, the material removal process substantially removes the portion of the first connection insulation structure 132 that vertically covers the uppermost surface of the first wiring structure 116, exposing a portion of the first wiring structure 116.

[0091] If formed, the through-contact structures 202 may penetrate vertically through the first wiring structure 116, the first connection insulation structure 132, the remainder of the first base structure 102, and the second connection insulation structure 198, respectively. The through-contact structures 202 may extend vertically into or into layer 172 of the stack structure 166. As shown in Figure 1E, in some embodiments, the through-contact structures 202 extend into and contact with a portion of a deep contact structure 174 that penetrates layer 172 vertically. The through-contact structures 202 may be configured and positioned to electrically connect one or more features (e.g., structures, materials, devices) formed vertically on the first wiring structure 116 to one or more of the deep contact structures 174 (and therefore additional features of a third microelectronic device structure 152 located vertically below the stack structure 166, e.g., a source structure 160). The through-contact structures 202 may be formed from a conductive material. In some embodiments, the through-contact structures 202 may be formed from W. In yet other embodiments, the through-contact structures 202 may be formed from conductively doped polycrystalline silicon.

[0092] The additional insulating liner structure 204 may be formed to substantially continuously cover and substantially coat the sides of the through-contact structure 202 (if formed). The additional insulating liner structure 204 may be horizontally interposed between the through-contact structure 202 and additional features (e.g., structures, materials, devices) in the first circuit region 104, the second circuit region 146, and the memory array region 156. The additional insulating liner structure 204 may be formed from and include one or more insulating materials. For example, they may be formed from one or more dielectric oxide materials (e.g., one or more of SiOx, silicate glass phosphate, silicate glass borate, silicate glass borate, silicate glass fluorine, AlOx, HfOx, NbOx, TiOx, ZrOx, TaOx, MgOx), one or more dielectric nitride materials (e.g., SiNy), one or more dielectric oxynitride materials (e.g., SiOxNy), and one or more dielectric carboxynitride materials (e.g., SiOxCzNy). In some embodiments, additional insulating liner structures 204 are formed from or comprising a dielectric oxide material (e.g., SiOx, SiO2).

[0093] Continuing to refer to Figure 1F, the BEOL structure formed vertically above the first circuit region 104 may include a third wiring structure 206, a conductive pad structure 208, a sixth contact structure 210, a seventh contact structure 212, and an eighth contact structure 216. The third wiring structure 206 may be positioned vertically above the first wiring structure 116. The conductive pad structure 208 may be positioned vertically above the third wiring structure 206. The sixth contact structure 210 may extend vertically between a portion of the third wiring structure 206 and a portion of a feature at least partially located within the first circuit region 104 (e.g., a portion of the first wiring structure 116 or a through-contact structure 202 (if formed)), connecting them. The seventh contact structure 212 may extend vertically between a portion of the third wiring structure 206 and another third wiring structure 206, connecting them. The eighth contact structure 216 may extend vertically between a portion of the third wiring structure 206 and the conductive pad structure 208 to connect them. In yet another embodiment, one or more conductive pad structures 208 are formed to be in direct physical contact with one or more third wiring structures 206.

[0094] The third wiring structure 206, the conductive pad structure 208, the sixth contact structure 210, the seventh contact structure 212, and the eighth contact structure 216 may each be formed from or in part with a conductive material. As a non-limiting example, the third wiring structure 206, the conductive pad structure 208, the sixth contact structure 210, the seventh contact structure 212, and the eighth contact structure 216 may each be formed from or in part with one or more metals, one or more alloys, and one or more conductive metal-containing materials (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides). In some embodiments, the third wiring structure 206 may each be formed from or in part with Cu, the conductive pad structure 208 may each be formed from or in part with Al, and the sixth contact structure 210, the seventh contact structure 212, and the eighth contact structure 216 may each be formed from or in part with W.

[0095] Continuing to refer to Figure 1F, the fifth insulating material 218 may be formed to cover and surround the third wiring structure 206, the conductive pad structure 208, the seventh contact structure 212, and the eighth contact structure 216. In some embodiments, the fifth insulating material 218 is formed from or comprising at least one dielectric oxide material such as SiOx (e.g., SiO2). In yet other embodiments, the fifth insulating material 218 is formed from or comprising at least one low-k dielectric material such as one or more of SiOxCy, SiOxNy, SiCxOyHz, and SiOxCzNy. The fifth insulating material 218 may be substantially homogeneous or heterogeneous. Furthermore, one or more openings 220 may be formed within the fifth insulating material 218 to expose one or more conductive pad structures 208. For example, the opening 220 facilitates access to the conductive pad structure 208 by additional structures (e.g., wires such as bonding wires) in relatively large devices.

[0096] The interconnect region 224 may include a third wiring structure 206, a conductive pad structure 208, a sixth contact structure 210, a seventh contact structure 212, an eighth contact structure 216, and a fifth insulating material 218. Furthermore, the formation of the interconnect region 224 may form a microelectronic device 226 (e.g., a memory device such as a 3D NAND flash memory device). The microelectronic device 226 may, but is not limited to, include the interconnect region 224, a first circuit region 104 located vertically below the interconnect region 224, a second circuit region 146 located vertically below the first circuit region 104, and a memory array region 156 located vertically below the second circuit region 146. At least the third wiring structure 206 and the conductive pad structure 208 of the interconnect region 224 may function as a global wiring structure for the microelectronic device 226. For example, the third wiring structure 206 and the conductive pad structure 208 may be configured to receive a global signal from an external bus and relay that global signal to other components (e.g., structures, devices) of the microelectronic device 226.

[0097] The processing steps and structural configurations described above with reference to Figures 1A to 1F can eliminate the structural and performance limitations (e.g., speed, data transfer rate, power consumption) imposed by the conventional formation and / or processing of arrays (e.g., memory cell arrays, memory element arrays, access device arrays) in conventional microelectronic devices. For example, by forming the modified first microelectronic device structure assembly 127 (Figure 1C) separately from the third microelectronic device structure 152 (Figure 1D) and then joining them (e.g., bonding), the circuits and devices in at least the first circuit region 104 and the second circuit region 146 of the modified first microelectronic device structure assembly 127 (Figure 1C) can be preserved without being damaged by the processing conditions (e.g., temperature, pressure, material) required for the formation of circuits and devices (e.g., memory cells) in at least the memory array region 156 of the third microelectronic device structure 152 (Figure 1D).

[0098] Accordingly, a method for forming a microelectronic device according to the embodiment of this disclosure includes the step of forming a first assembly which includes a semiconductor substrate structure, a first circuit region including a first device at a first boundary, and a second circuit region including a second device at a second boundary perpendicularly offset from the first boundary. A microelectronic device structure is formed, which includes a stack structure consisting of layers containing a conductive material and a perpendicularly adjacent insulating material, and a cell pillar structure containing a semiconductor material perpendicularly penetrating the stack structure. The first assembly is joined to this microelectronic device structure to form a second assembly.

[0099] Furthermore, according to embodiments of the present disclosure, the microelectronic device includes a stack structure, a cell pillar structure, a semiconductor structure, a first device, a second device, and a conductive contact structure. The stack structure comprises layers, each containing a conductive material and an insulating material perpendicularly adjacent thereto. The cell pillar structure includes a semiconductor material extending perpendicularly through the stack structure. The semiconductor structure is positioned perpendicularly above the stack structure. The first device is located at the lower boundary of the semiconductor structure, and the second device is located at the upper boundary of the semiconductor structure. The conductive contact structure extends perpendicularly from at least a portion of the second device's vertical position, completely through the semiconductor structure, and further reaches at least a portion of the first device's vertical position.

[0100] Furthermore, a memory device according to an embodiment of the present disclosure includes a stack structure, a string of memory cells, a source structure, digit lines, a semiconductor structure, capacitors, a control logic device, and a conductive contact structure. The stack structure comprises layers, each containing a conductive material and an insulating material perpendicularly adjacent to the conductive material. The string of memory cells extends perpendicularly through the stack structure. The source structure is located perpendicularly below the stack structure and is connected to the string of memory cells. The digit lines are located perpendicularly above the stack structure and are connected to the string of memory cells. The semiconductor structure is located perpendicularly above the digit lines. The capacitors partially overlap the bottom boundary of the semiconductor structure perpendicularly. The control logic device partially overlaps the top boundary of the semiconductor structure perpendicularly and is connected to the string of memory cells. The conductive contact structure extends perpendicularly through the semiconductor structure and connects at least some of the capacitors to some of the control logic devices.

[0101] A microelectronic device according to an embodiment of this disclosure (e.g., microelectronic device 226 (Figure 1F)) can be used in embodiments of the electronic system of this disclosure. For example, Figure 2 is a schematic block diagram of an electronic system 300 according to an embodiment of this disclosure. The electronic system 300 may include, for example, a computer or computer hardware component, a server or other network hardware component, a mobile phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a tablet with Wi-Fi or cellular capabilities (e.g., an iPad® or SURFACE® tablet), an e-book reader, a navigation device, and the like. The electronic system 300 includes at least one memory device 302. The memory device 302 may include, for example, the aforementioned microelectronic device (e.g., microelectronic device 226 (Figure 1F)). The electronic system 300 may further include at least one electronic signal processing device 304 (often referred to as a “microprocessor”). The electronic signal processing device 304 may optionally include the aforementioned microelectronic device (e.g., microelectronic device 226 (Figure 1F)). In Figure 2, the memory device 302 and the electronic signal processing device 304 are shown as two separate devices; however, in other embodiments, the electronic system 300 includes a single (i.e., only one) memory / processor device that combines the functions of the memory device 302 and the electronic signal processing device 304. In such embodiments, the memory / processor device may include the aforementioned microelectronic device (e.g., microelectronic device 226 (Figure 1F)). Furthermore, the electronic system 300 may include one or more input devices 306 for the user to input information into the electronic system 300. Examples of input devices 306 include a mouse or other pointing device, a keyboard, a touchpad, buttons, an operation panel, etc. The electronic system 300 may further include one or more output devices 308 for outputting information (e.g., visual or audio output) to the user. Examples of output devices 308 include a monitor, a display, a printer, an audio output jack, a speaker, etc.In some embodiments, the input device 306 and the output device 308 are integrated into a single touchscreen device that can be used to input information into the electronic system 300 and output visual information to the user. The input device 306 and the output device 308 can communicate electrically with one or more of the memory device 302 and the electronic signal processing device 304.

[0102] The structures, devices, and methods disclosed herein can advantageously facilitate improved performance of microelectronic devices, reduced costs (e.g., manufacturing costs, material costs), further miniaturization of components, and higher mounting density compared to conventional structures, devices, and methods. Furthermore, the structures, devices, and methods disclosed herein can also contribute to improved scalability, efficiency, and simplicity compared to conventional structures, devices, and methods.

[0103] Additional, non-limiting embodiments of the present disclosure are described below.

[0104] Embodiment 1: A method for forming a microelectronic device, comprising the steps of: forming a first assembly, wherein the first assembly comprises a semiconductor substrate structure, a first circuit region including a first device at a first boundary of the semiconductor substrate structure, and a second circuit region including a second device at a second boundary perpendicularly offset from the first boundary of the semiconductor substrate structure; forming a microelectronic device structure, wherein the microelectronic device structure comprises a stack structure consisting of layers each containing a conductive material and an insulating material perpendicularly adjacent to the conductive material, and a cell pillar structure including a semiconductor material extending perpendicularly to the stack structure; and joining the first assembly to the microelectronic device structure to form a second assembly.

[0105] Embodiment 2: The method according to Embodiment 1, wherein the step of forming the first assembly includes the following steps: a step of forming an additional microelectronic device structure having an initial semiconductor substrate structure including a first device in a first circuit region; a step of forming a further microelectronic device structure having an additional substrate structure; a step of bonding the additional microelectronic device structure to the further microelectronic device structure; a step of forming the semiconductor substrate structure by removing a part of the initial semiconductor substrate structure after bonding the additional microelectronic device structure to the further microelectronic device structure; and a step of forming the second device in the second circuit region after forming the semiconductor substrate structure.

[0106] Embodiment 3: A method according to Embodiment 1, wherein the step of forming the first assembly includes the steps of forming a control logic device as a first device in the first circuit region, which includes a transistor that overlaps perpendicularly with the semiconductor substrate structure and is partially defined by the semiconductor substrate structure, and forming a capacitor as a second device in the second circuit region.

[0107] Embodiment 4: The method according to Embodiment 3, further comprising the step of forming the capacitor to include one or both of a metal-insulator-semiconductor (MIS) capacitor and a metal-insulator-metal (MIM) capacitor.

[0108] Embodiment 5: A method according to any one of Embodiments 1 to 4, further comprising the step of forming the first assembly to include a conductive contact structure that extends perpendicularly from the first circuit region and completely penetrates the semiconductor substrate structure to reach the second circuit region.

[0109] Embodiment 6: A method according to any one of Embodiments 1 to 5, wherein bonding the first assembly to the microelectronic device structure includes bonding the dielectric oxide material of the first assembly to an additional dielectric oxide material of the microelectronic device structure.

[0110] Embodiment 7: A method according to Embodiment 6, wherein bonding the first assembly to the microelectronic device structure further comprises bonding the conductive bonding pads of the first assembly embedded in the dielectric oxide material to additional conductive bonding pads of the microelectronic device structure embedded in the additional dielectric oxide material.

[0111] Embodiment 8: A method according to any one of Embodiments 1 to 7, comprising the step of further forming the microelectronic device structure, wherein the microelectronic device structure includes a digit wire structure that vertically covers the stack structure and is connected to the cell pillar structure, a source structure that vertically supports the stack structure below and is connected to the cell pillar structure, and conductive contact structures that are horizontally offset from the cell pillar structure and vertically penetrate the stack structure to the vertical position of the source structure.

[0112] Embodiment 9: A method according to any one of Embodiments 1 to 8, further comprising the step of forming a conductive contact structure that, after forming the second assembly, penetrates vertically through the second circuit region, the semiconductor substrate structure, and the first circuit region of the first assembly, and reaches at least the stack structure of the microelectronic device structure.

[0113] Embodiment 10: A method according to any one of Embodiments 1 to 9, further comprising the step of forming an interconnect region above a second assembly, wherein the interconnect region includes a conductive wiring structure located vertically above and connected to at least a portion of the first device, and a conductive pad structure located vertically above and connected to at least a portion of the conductive wiring structure.

[0114] Embodiment 11: A microelectronic device comprising: a stack structure comprising layers comprising a conductive material and an insulating material perpendicularly adjacent to the conductive material; a cell pillar structure comprising a semiconductor material extending perpendicularly to the stack structure; a semiconductor structure positioned perpendicularly above the stack structure; a first device located at the lower boundary of the semiconductor structure; a second device located at the upper boundary of the semiconductor structure; and a conductive contact structure extending perpendicularly from at least a portion of the vertical position of the second device, completely penetrating the semiconductor structure, and reaching at least an additional vertical position of at least a portion of the first device.

[0115] Embodiment 12: A microelectronic device according to Embodiment 11, wherein the first device includes one or more metal-insulator-semiconductor (MIS) capacitors or metal-insulator-metal (MIM) capacitors.

[0116] Embodiment 13: A microelectronic device according to Embodiment 12, wherein the second device includes a control logic device that includes a transistor partially perpendicularly overlapping with the semiconductor structure.

[0117] Embodiment 14: A microelectronic device according to any one of Embodiments 11 to 13, further comprising: a source structure positioned vertically below the stack structure and coupled to the cell pillar structure; a digit line structure interposed vertically between the first device and the stack structure and coupled to the cell pillar structure; and additional contact structures offset horizontally from the cell pillar structure and formed to completely penetrate the stack structure vertically and reach the source structure.

[0118] Embodiment 15: A microelectronic device according to Embodiment 14, further comprising a digit wire contact structure interposed perpendicularly between the first device and the digit wire structure and coupled to the digit wire structure, and a conductive bond pad structure interposed perpendicularly between the first device and the digit wire contact structure and coupled to the digit wire contact structure.

[0119] Embodiment 16: A microelectronic device according to any one of Embodiments 11 to 15, further comprising a conductive wiring structure positioned perpendicularly on the second device and a conductive pad structure positioned perpendicularly on at least a portion of the conductive wiring structure and coupled thereto.

[0120] Embodiment 17: A microelectronic device according to Embodiment 16, further comprising an additional conductive contact structure coupled to a portion of the conductive wiring structure and extending continuously vertically from a position perpendicular to at least a portion of the second device to the stack structure.

[0121] Embodiment 18: A memory device comprising: a stack structure in which each layer comprises a conductive material and an insulating material perpendicularly adjacent to the conductive material; a string of memory cells extending perpendicularly to the stack structure; a source structure located perpendicularly below the stack structure and coupled to the string of memory cells; a digit line located perpendicularly above the stack structure and coupled to the string of memory cells; a semiconductor structure located perpendicularly above the digit line; a capacitor partially perpendicularly overlapping the lowest boundary of the semiconductor structure; a control logic device partially perpendicularly overlapping the uppermost boundary of the semiconductor structure and coupled to the string of memory cells; and a conductive contact structure extending perpendicularly to the semiconductor structure and coupling at least some of the capacitors to some of the control logic devices.

[0122] Embodiment 19: A memory device according to Embodiment 18, further comprising a conductive wiring structure positioned vertically on the control logic device, wherein a portion of the conductive wiring structure is coupled to a portion of the control logic device, and another portion of the conductive wiring structure is coupled to the source structure.

[0123] Embodiment 20: A memory device according to Embodiment 19, further comprising an additional conductive contact structure that couples the source structure to another part of the conductive wiring structure, wherein at least a portion of the additional conductive contact structure overlaps horizontally with respect to each other and extends vertically between the source structure and the other part of the conductive wiring structure.

[0124] This disclosure is readily applicable to various modifications and alternative forms, but specific embodiments are illustrated with reference to the drawings and described in detail herein. However, this disclosure is not limited to any specific form disclosed. Rather, this disclosure encompasses all modifications, equivalents, and alternatives that fall within the scope of the claims and their legal equivalents attached below. For example, elements and features disclosed in relation to one embodiment can be combined with elements and features disclosed in relation to other embodiments of this disclosure. This disclosure is readily applicable to various modifications and alternative forms, but specific embodiments are illustrated with reference to the drawings and described in detail herein. However, this disclosure is not limited to any specific form disclosed. Rather, this disclosure encompasses all modifications, equivalents, and alternatives that fall within the scope of the claims and their legal equivalents attached below. For example, elements and features disclosed in relation to one embodiment can be combined with elements and features disclosed in relation to other embodiments of this disclosure.

Claims

1. A method for forming a microelectronic device, This is the process of forming the first assembly. The first assembly is A first circuit region containing a first device is located at the first boundary of the semiconductor substrate structure, The semiconductor substrate structure comprises a second circuit region including a second device, which is located at a second boundary that is vertically offset from the first boundary of the semiconductor substrate structure. The process, This is a process for forming a microelectronic device structure. The aforementioned microelectronic device structure is A stack structure comprising layers containing a conductive material and an insulating material perpendicularly adjacent to the conductive material, The stack structure includes a cell pillar structure comprising a semiconductor material extending vertically. The process, The steps include: joining the first assembly to the microelectronic device structure to form a second assembly; A method for forming a microelectronic device, including [a specific component].

2. A method for forming a microelectronic device according to claim 1, The step of forming the first assembly is: A step of forming an initial semiconductor substrate structure and an additional microelectronic device structure including a first device in the first circuit region, A step of forming yet another microelectronic device structure including an additional substrate structure, A step of joining the additional microelectronic device structure to yet another microelectronic device structure, The process of forming the semiconductor substrate structure by bonding the additional microelectronic device structure to yet another microelectronic device structure, and then removing a portion of the initial semiconductor substrate structure, The steps include forming the semiconductor substrate structure, followed by forming the second device in the second circuit region, A method for forming a microelectronic device, including [a specific component].

3. A method for forming a microelectronic device according to claim 1, The step of forming the first assembly is: A step of making the first device in the first circuit region a control logic device including a transistor that overlaps perpendicularly with the semiconductor substrate structure and is partially defined by the semiconductor substrate structure, A step of making the second device in the second circuit region a capacitor, A method for forming a microelectronic device, including [a specific component].

4. A method for forming a microelectronic device according to claim 3, A method for forming a microelectronic device, further comprising the step of forming the capacitor to include one or both of a metal-insulator-semiconductor (MIS) capacitor and a metal-insulator-metal (MIM) capacitor.

5. A method according to any one of claims 1 to 4, A method for forming a microelectronic device, further comprising the step of forming the first assembly to include a conductive contact structure that extends perpendicularly from the first circuit region, completely penetrates the semiconductor substrate structure, and reaches the second circuit region.

6. A method according to any one of claims 1 to 4, A method for forming a microelectronic device, wherein joining the first assembly to the microelectronic device structure includes the step of joining the dielectric oxide material of the first assembly to an additional dielectric oxide material of the microelectronic device structure.

7. The method according to claim 6, A method for forming a microelectronic device, wherein bonding the first assembly to the microelectronic device structure further includes the step of bonding a conductive bond pad of the first assembly, embedded in the dielectric oxide material, to an additional conductive bond pad of the microelectronic device structure, embedded in the additional dielectric oxide material.

8. A method according to any one of claims 1 to 4, The aforementioned microelectronic device structure is A digit line structure positioned vertically above the stack structure and connected to the cell pillar structure, A source structure positioned vertically below the stack structure and connected to the cell pillar structure, A conductive contact structure is offset horizontally from the cell pillar structure and individually penetrates the stack structure vertically to reach the vertical position of the source structure, A method for forming a microelectronic device, comprising the step of forming it to further include the following.

9. A method according to any one of claims 1 to 4, A method for forming a microelectronic device, further comprising the step of forming a conductive contact structure that penetrates vertically through the second circuit region, the semiconductor substrate structure, and the first circuit region of the first assembly, to at least the stack structure of the microelectronic device structure, after forming the second assembly.

10. A method according to any one of claims 1 to 4, The process further includes forming an interconnect region on the second assembly, The aforementioned interconnect area is A conductive wiring structure located vertically on at least a portion of the first device and connected to the first device, A conductive pad structure located vertically on at least a portion of the conductive wiring structure and connected to the conductive wiring structure, A method for forming a microelectronic device, including [a specific component].

11. A microelectronic device, A stack structure comprising layers containing a conductive material and an insulating material perpendicularly adjacent to the conductive material, The aforementioned stack structure includes a cell pillar structure containing a semiconductor material extending vertically, A semiconductor structure positioned vertically on the aforementioned stack structure, A first device located at the lower boundary of the semiconductor structure, A second device located at the upper boundary of the semiconductor structure, A conductive contact structure extending vertically from at least a portion of the vertical position of the second device, completely penetrating the semiconductor structure, and reaching at least an additional vertical position of the first device, Microelectronic devices, including those mentioned above.

12. A microelectronic device according to claim 11, A microelectronic device in which the first device includes one or both of a metal-insulator-semiconductor (MIS) capacitor and a metal-insulator-metal (MIM) capacitor.

13. A microelectronic device according to claim 12, A microelectronic device in which the second device includes a control logic device that includes a transistor partially superimposed perpendicularly with the semiconductor structure.

14. A microelectronic device according to any one of claims 11 to 13, further, A source structure is located vertically below the aforementioned stack structure and is coupled to the aforementioned cell pillar structure, A digit line structure is interposed perpendicularly between the first device and the stack structure and coupled to the cell pillar structure, Additional contact structures are offset horizontally from the cell pillar structure and extend vertically, each penetrating the stack structure completely vertically to reach the source structure. Microelectronic devices, including those mentioned above.

15. A microelectronic device according to claim 14, further, A digit line contact structure is interposed perpendicularly between the first device and the digit line structure and coupled to the digit line structure, A conductive bond pad structure is interposed perpendicularly between the first device and the digit line contact structure and coupled to the digit line contact structure, Microelectronic devices, including those mentioned above.

16. A microelectronic device according to any one of claims 11 to 13, further, A conductive wiring structure positioned vertically on the second device, A conductive pad structure is positioned vertically on at least a portion of the conductive wiring structure and coupled to at least a portion of these conductive wiring structures, Microelectronic devices, including those mentioned above.

17. A microelectronic device according to claim 16, further, A microelectronic device comprising an additional conductive contact structure coupled to a portion of the conductive wiring structure and extending continuously vertically from a position perpendicular to at least a portion of the second device to the stack structure.

18. A memory device, A stack structure comprising layers containing a conductive material and an insulating material perpendicularly adjacent to the conductive material, The aforementioned stack structure consists of a string of memory cells extending vertically, A source structure located vertically below the stack structure and coupled to the string of the memory cell, The stack structure is positioned vertically above and has digit lines coupled to the string of memory cells, The aforementioned digit line is located vertically above the semiconductor structure, A capacitor partially overlapping the lowest boundary of the semiconductor structure perpendicularly, A control logic device partially overlaps perpendicularly to the uppermost boundary of the semiconductor structure and is coupled to the string of memory cells, A conductive contact structure extends vertically over the semiconductor structure and connects at least a portion of the capacitor to a portion of the control logic device, A memory device that includes this.

19. A memory device according to claim 18, The control logic device further includes a conductive wiring structure positioned vertically above it. One or more of the conductive wiring structures are coupled to one or more of the control logic devices. One or more of the conductive wiring structures are connected to the source structure. Memory device.

20. A memory device according to claim 19, The system further includes an additional conductive contact structure that connects the source structure to one or more other conductive wiring structures, At least a portion of the additional conductive contact structures overlap each other horizontally and extend vertically between the source structure and one or more other conductive wiring structures. Memory device.

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