Growth of thin oxide layers by silicon nitride conversion

Abstract

A method for forming an oxide layer includes forming a protective interlaminar oxide on the sidewalls of trenches formed on a substrate, forming a silicon nitride layer on the protective interlaminar oxide by a plasma atomic layer deposition (PE-ALD) process using a nitrogen-containing treatment gas, wherein the silicon nitride layer has a nitrogen concentration gradient that fluctuates from a high concentration away from the protective interlaminar oxide to a low concentration near the protective interlaminar oxide, and performing a conversion process to oxidize the formed silicon nitride layer and convert the formed silicon nitride layer into a silicon oxide layer, at least partially.

Description

Technical Field

[0001]

[0001] The embodiments described herein generally relate to semiconductor device manufacturing, and more specifically, to a method of forming a high-quality thin oxide layer in a high aspect ratio semiconductor structure.

Background Art

[0002] Description of Related Art

[0002] The production of silicon integrated circuits has placed difficult demands on the fabrication process in order to increase the number of elements while reducing the minimum feature size on the chip. These requirements extend to manufacturing processes that include depositing layers on difficult topologies while maintaining device reliability. For example, buried word line (bWL) structures used in dynamic random access memory (DRAM) devices can have aspect ratios of 6:1, 10:1, or more and may require a thin and reliable gate oxide layer.

[0003]

[0003] Conventional methods of forming an oxide layer within such structures are plagued by one or more of three problems. The first problem is the high silicon consumption for thermal oxidation growth. That is, the oxide layer may not be formed thin enough for a high aspect ratio structure. The second problem is the low quality of oxide layers formed by deposition, which can contain internal defects and traps and thus lead to a decrease in device reliability. The third problem is the low and non-uniform nitrogen incorporation into the oxide layer.

[0004]

[0004] Therefore, an improved process for forming a thin and high-quality oxide layer is needed that minimizes silicon consumption and defects in the formed oxide layer and enables control over the incorporation of nitride into the oxide layer.

Summary of the Invention

[0005]

[0005] Embodiments of the present disclosure provide a method for forming an oxide layer. The method includes forming a protective interlaminar oxide on the sidewalls of a trench formed on a substrate, forming a silicon nitride layer on the protective interlaminar oxide by a plasma atomic layer deposition (PE-ALD) process using a nitrogen-containing treatment gas, wherein the silicon nitride layer has a nitrogen concentration gradient that fluctuates from a high concentration away from the protective interlaminar oxide to a low concentration near the protective interlaminar oxide, and performing a conversion process to oxidize the formed silicon nitride layer to at least partially convert the formed silicon nitride layer into a silicon oxide layer.

[0006]

[0006] Embodiments of the present disclosure also provide a method for forming an oxide layer. The method includes forming a protective interlayer oxide on the sidewalls of a trench formed on a substrate; forming a bilayer of a bottom nitrogen-rich silicon nitride layer on the protective interlayer oxide and an upper silicon nitride layer on the bottom nitrogen-rich silicon nitride layer by an atomic layer deposition (ALD) process; and performing a conversion process to oxidize the formed bottom nitrogen-rich silicon nitride layer to convert the formed bottom nitrogen-rich silicon nitride layer into a silicon oxide layer.

[0007]

[0007] Embodiments of the present disclosure further provide a method for forming an oxide layer. The method includes forming a protective interlaminar oxide on the sidewalls of a trench formed on a substrate; forming a hybrid layer of a bottom silicon nitride layer on a layer on the protective interlaminar oxide and an upper silicon oxide layer on the bottom silicon nitride layer by an atomic layer deposition (ALD) process; and performing a conversion process to oxidize the formed bottom silicon nitride layer to convert the formed bottom silicon nitride layer into a silicon oxide layer.

[0008]

[0008] To enable a more detailed understanding of the above-described features of the Disclosure, a more detailed description of the Disclosure, which is briefly summarized above, can be obtained by referring to embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings show only typical embodiments of the Disclosure, as the Disclosure may also permit other equally valid embodiments, and therefore should not be considered to limit the scope of the Disclosure. [Brief explanation of the drawing]

[0009] [Figure 1] This is a schematic diagram of a substrate processing system according to one embodiment. [Figure 2] This is a process flow diagram of a method for forming an oxide layer in a semiconductor structure according to one embodiment. [Figure 3A] This is a schematic diagram of a buried wordline (bWL) structure according to one embodiment. [Figure 3B] This is a schematic diagram of a buried wordline (bWL) structure according to one embodiment. [Figure 3C] This is a schematic diagram of a buried wordline (bWL) structure according to one embodiment. [Figure 3D] This is a schematic diagram of a buried wordline (bWL) structure according to one embodiment. [Figure 4A] This is a schematic diagram of a part of a buried wardline (bWL) structure according to one embodiment. [Figure 4B] This is a schematic diagram of a part of a buried wardline (bWL) structure according to one embodiment. [Modes for carrying out the invention]

[0010]

[0013] For ease of understanding, the same reference numerals were used where possible to indicate identical elements common to multiple figures. It is assumed that components and features of one embodiment can be usefully incorporated into other embodiments without further description.

[0011]

[0014] The embodiments described herein relate to embedded word line (bWL) structures used in dynamic random access memory (DRAM) devices, and methods for forming high-quality thin oxide layers in semiconductor devices such as thin nanowire field-effect transistors (FETs). Thin oxide layers that can be used as gate oxide layers in such devices can be formed by first depositing a silicon nitride layer on a substrate and then oxidizing the silicon nitride layer by a conversion process.

[0012]

[0015] The method herein for forming a thin oxide layer can reduce silicon consumption, improve the quality of the formed oxide layer, and thus enable more reliable gate oxide scaling. The method herein also provides the ability to selectively adjust the thickness of the oxide layer and the nitride incorporation distribution. For example, a gate oxide layer formed on the sidewall of a trench can have a uniform nitrogen concentration from the top to the bottom of the trench, or, if desired, a controlled level of nitrogen concentration.

[0013]

[0016] Figure 1 shows a processing platform 100 according to one or more embodiments of the present disclosure. The embodiments shown in Figure 1 represent only one possible configuration and should not be considered as limiting the scope of the present disclosure. For example, in some embodiments, the processing platform 100 has a different number of processing chambers 102, buffer stations 104 and / or robot 106 configurations than those shown in the illustrated embodiments.

[0014]

[0017] The processing chamber 102 includes multiple processing stations 108. The processing stations 108 are spatially separated within the internal space 110 of the processing chamber 102. Each processing station 108 independently has a processing chamber temperature that may differ from the temperatures of the other processing stations.

[0015]

[0018] The processing station 108 may be configured to perform any suitable process and provide any suitable process conditions. For example, a processing station 108 configured to operate as an atomic layer deposition (ALD) apparatus may have a showerhead or vortex-type gas injector. In contrast, a processing station 108 configured to operate as a plasma station may have one or more electrodes and / or a grounding plate configuration that generates plasma while allowing plasma gas to flow toward the wafer. Suitable processing stations 108 include, but are not limited to, inductively coupled plasma (ICP) processing stations, capacitively coupled plasma (CCP) processing stations, etching soak processing stations, thermal processing stations, microwave plasma stations, UV exposure stations, laser processing stations, pumping chamber stations, annealing stations, and measurement stations.

[0016]

[0019] An exemplary processing platform 100 includes a central transfer station 112 having multiple sides 114, 116, 118, and 120. The illustrated central transfer station 112 has a first side 114, a second side 116, a third side 118, and a fourth side 120. Although four sides are shown, those skilled in the art will understand that the central transfer station 112 may have any appropriate number of sides, depending on the overall configuration of the processing platform 100, for example. In some embodiments, the transfer station 112 has three, four, five, six, seven, or eight sides.

[0017]

[0020] Transfer station 112 has a robot 106 located therein. Robot 106 can be any suitable robot capable of moving wafers during processing. In some embodiments, robot 106 has a first arm 122 and a second arm 124. The first arm 122 and the second arm 124 can be moved independently of the other arm. The first arm 122 and the second arm 124 can move within the X-Y plane and / or along the Z-axis. In some embodiments, robot 106 includes a third arm (not shown) or a fourth arm (not shown). Each arm can move independently of the other arms.

[0018]

[0021] The illustrated embodiment includes six processing chambers 102, two of which are connected to each of the second side 116, third side 118, and fourth side 120 of the central transfer station 112. Each of the processing chambers 102 can be configured to perform a different process.

[0019]

[0022] The processing platform 100 can further include one or more buffer stations 104 connected to the first side 114 of the central transfer station 112. The buffer stations 104 can perform the same function or different functions. For example, the buffer station 104 may hold a cassette of wafers that are processed and returned to the original cassette, or one of the buffer stations 104 may hold unprocessed wafers that are moved to another buffer station 104 after processing. In some embodiments, one or more of the buffer stations 104 are configured to pre-process, pre-heat, or clean the wafers before and / or after processing.

[0020]

[0023] The processing platform 100 may further include one or more slit valves 126 between the central transfer station 112 and any processing chamber 102. The slit valve 126 can be opened and closed to isolate the internal space 110 in the processing chamber 102 from the environment in the central transfer station 112. For example, if the processing chamber 102 generates plasma during processing, it may be useful to close the slit valve 126 of that processing chamber 102 to prevent the floating plasma from damaging the robot 106 in the central transfer station 112.

[0021]

[0024] The processing platform 100 can be connected to the factory interface 128, thereby enabling the loading of wafers or wafer cassettes onto the processing platform 100. Using the robot 130 within the factory interface 128, wafers or cassettes can be moved into and out of the buffer station 104. The robot 106 within the central transfer station 112 can move wafers or cassettes within the processing platform 100. In some embodiments, the factory interface 128 is the central transfer station 112 of another cluster tool (i.e., another multi-chamber processing platform).

[0022]

[0025] A controller 132 can be provided and connected to the various components of the processing platform 100 to control their operations. The controller 132 can be a single controller that controls the entire processing platform 100, or a plurality of controllers that control individual parts of the processing platform 100. For example, the processing platform 100 may include separate controllers for each of the individual processing chambers 102, the central transfer station 112, the factory interface 128, and the robot 106.

[0023]

[0026] In some embodiments, the controller 132 includes a central processing unit (CPU) 134, memory 136, and support circuitry 138. The controller 132 can control the processing platform 100 directly or via a computer (or controller) associated with a particular processing chamber and / or component of the support system.

[0024]

[0027] The controller 132 may be one of any form of general-purpose computer processors that can be used in an industrial environment to control various chambers and subprocessors. The memory or computer-readable medium 136 of the controller 132 may be one or more of readily available memories, such as random access memory (RAM), read-only memory (ROM), floppy disks, hard disks, optical storage media (e.g., compact discs or digital video discs), flash drives, or any other form of local or remote digital storage. The memory 136 may hold an instruction set that can be operated by the processor (CPU 134) to control the parameters and components of the processing platform 100.

[0025]

[0028] Support circuits 138 are connected to the CPU 134 to support the processor in a conventional manner. These circuits include caches, power supply units, clock circuits, input / output circuits, and subsystems. One or more processes may be stored in memory 136 as software routines that cause the processor to control the operation of the processing platform 100 or individual processing chambers in the manner described herein when executed or invoked by the processor. Software routines may also be stored and / or executed by a second CPU (not shown) located remotely from the hardware controlled by the CPU 134.

[0026]

[0029] Some or all of the processes and methods of this disclosure may also be performed in hardware. Thus, the processes may be implemented in software and executed using a computer system, for example, in hardware as an application-specific integrated circuit or other types of hardware implementation, or as a combination of software and hardware. When executed by a processor, the software routines transform a general-purpose computer into a dedicated computer (controller) that controls the chamber operation so that the processes can be executed.

[0027]

[0030] In some embodiments, the controller 132 has one or more configurations for executing individual processes or subprocesses to carry out the method. The controller 132 may be connected to intermediate components and configured to actuate the intermediate components to perform the functions of the method. For example, the controller 132 may be connected to one or more gas valves, actuators, motors, slit valves, vacuum controls, or other components and configured to control them.

[0028]

[0031] Figure 2 is a process flow diagram of Method 200 for forming an oxide layer in a semiconductor structure, such as the embedded word line (bWL) structure 300 shown in Figure 3A or any subset of the bWL structure 300, relating to one or more implementations of the present disclosure. Figures 3B, 3C, and 3D are cross-sectional views of parts of the bWL structure 300 corresponding to various stages of Method 200. The bWL structure 300 may be used in dynamic random access memory (DRAM) devices. Furthermore, Method 200 may be used to form bWL structures having various configurations or other semiconductor devices such as nanowires, which require high-quality thin oxide layers. It should also be understood that the steps shown in Figure 2 may be performed simultaneously and / or in an order different from that shown in Figure 2.

[0029]

[0032] The bWL structure 300 includes a substrate 302 on which one or more trenches 304 are formed. In some embodiments, the substrate 302 may have a substantially flat surface, a non-planar surface, or a substantially flat surface on which the structure is formed. The substrate 302 is made of crystalline silicon (e.g., Si <100> or Si <111> The materials may include doped or undoped polysilicon, doped or undoped silicon wafers, and patterned or unpatterned wafers, silicon-on-insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, or sapphire. The substrate 302 may have various shapes and dimensions, such as wafers with a diameter of 200 or 300 mm and rectangular or square panels. Unless otherwise specified, the embodiments and examples described herein refer to a substrate with a diameter of 300 mm. In some embodiments, the substrate 302 may be a crystalline silicon substrate (e.g., single-crystal silicon or polycrystalline silicon).

[0030]

[0033] Trench 304 may have a width between approximately 8 nm and 15 nm, a depth between approximately 80 nm and 160 nm, and therefore an aspect ratio greater than approximately 6:1 or 10:1.

[0031]

[0034] A pad oxide layer 306 and a nitride layer 308 are formed on the upper surface of the substrate 302. The pad oxide layer 306 may be made of silicon oxide (SiO2). The nitride layer 308 may be made of silicon nitride (Si3N4). A gate oxide layer 310 is formed on the upper surface of the substrate 302 and on the inner surface of the trench 304.

[0032]

[0035] In conventional methods for forming the gate oxide layer 310, silicon oxide is deposited in the gas phase using silicon-containing and oxygen-containing precursors by ALD or CVD processes and densified by annealing. Subsequently, nitrogen is incorporated into the silicon oxide by remote plasma and thermal methods. The resulting silicon oxide has relatively low and non-uniform nitrogen incorporation. Specifically, silicon oxide formed on the sidewalls of high aspect ratio trenches may have large variations in nitrogen content between the bottom and top of the trench. Furthermore, the deposited silicon oxide may contain stoichiometric and structural defects (resulting in the disruption of the tetrahedral crystal structure of the silicon oxide formed by the ALD or CVD process), boundary traps at a distance of about 10 Å to about 15 Å from the interface with the substrate 302, and interface traps at this interface (e.g., within about 5 Å from the interface), which leads to a decrease in the device reliability of the bWL structure 300. Radical oxidation and / or annealing processes can reduce defects in deposited silicon oxide; however, the treatment is only effective on the surface of the deposited silicon oxide to a depth of approximately 10 Å to 30 Å, and therefore, the reliability of the device may not be significantly improved.

[0033]

[0036] In the embodiments described herein, the gate oxide layer 310 is formed by first depositing a silicon nitride layer on the substrate 302, and then transforming the deposited silicon nitride layer by a transformation process. Since Method 200 does not involve directly depositing silicon oxide on the substrate, the formed gate oxide layer 310 is free of defects and traps. Furthermore, nitrogen incorporation into the gate oxide layer 310 is carried out by a plasma atomic layer deposition (PE-ALD) process using a nitrogen-containing treatment gas, a combination of nitrogen (N2) gas and ammonia (NH3) gas. By controlling the ratio of nitrogen (N2) and ammonia (NH3) gas content, the nitrogen content distribution (e.g., uniform from the bottom to the top of the trench) can be controlled and adjusted.

[0034]

[0037] Method 200 begins in block 210. In block 210, as shown in Figure 3B, a protective interlaminar oxide 312 is formed on the sidewalls of the trench 304 and on the exposed surfaces of the substrate 302, at least partially filling the trench 304. The protective interlaminar oxide 312 may be formed by thermal oxidation growth of silicon oxide (SiO2) having a thickness between approximately 5 Å and approximately 15 Å. The protective interlaminar oxide 312 allows for adjustment of the amount of nitrogen atoms incorporated into the gate oxide layer 310, from high concentrations away from the protective interlaminar oxide 312 to low concentrations near the protective interlaminar oxide 312.

[0035]

[0038] In block 220, as shown in Figure 3C, a silicon nitride layer 314 is formed on the protective interlayer oxide 312.

[0036]

[0039] In some embodiments, the silicon nitride layer 314 has a nitrogen concentration gradient that varies from a high concentration far from the protective interlaminar oxide 312 to a low concentration near the protective interlaminar oxide 312. The silicon nitride layer 314 is formed by a plasma atomic layer deposition (PE-ALD) process, which can be performed at a processing station such as one of the processing stations 108 shown in Figure 1. Due to the properties of ALD, the silicon nitride layer 314 has substantially the same thickness at the bottom as the thickness at the sidewall of the trench 304. The silicon nitride layer 314 can be formed of silicon nitride (Si3N4) with a thickness between about 5 Å and about 25 Å, depending on the desired thickness of the gate oxide layer 310 to be formed.

[0037]

[0040] The PE-ALD process, utilizing a nitrogen-containing treatment gas and a carrier gas containing argon (Ar) (100-60%), is performed at a temperature of approximately 300°C to 650°C for 0-10 seconds under a chamber pressure of approximately 50 mTorr to 20 Torr. The substrate 302 is exposed to dichlorosilane (DCS) gas for approximately 100 ms to 5 seconds. The nitrogen-containing treatment gas may contain nitrogen (N2) only, ammonia (NH3) (0-20%) and nitrogen (N2) only, or ammonia (NH3) only. The use of nitrogen (N2) gas, the formation of nitrogen radicals, and the use of ammonia (NH3) gas, the formation of amino radicals (NH2·) can result in different nitrogen content in the deposited silicon nitride layer. Therefore, the nitrogen content and / or nitrogen content distribution in the deposited silicon nitride layer can be controlled and adjusted to a desired predetermined nitrogen content distribution by selecting the ratio of nitrogen (N2) and ammonia (NH3) content in the nitrogen-containing treatment gas.

[0038]

[0041] After a cycle of the PE-ALD process, one or more cycles are repeated with purging periods of 0 to approximately 10 seconds between cycles until the desired thickness of the silicon nitride layer 314 is achieved. In the PE-ALD process, the fit of the deposited silicon nitride layer increases with each repeated cycle.

[0039]

[0042] In some other embodiments, the silicon nitride layer 314 is a bilayer consisting of a bottom nitrogen-rich silicon nitride layer 314A on a protective interlayer oxide 312 and an upper silicon nitride layer 314A' on the bottom nitrogen-rich silicon nitride layer 314A, as shown in Figure 4A.

[0040]

[0043] The bottom nitrogen-rich silicon nitride layer 314A may have a nitrogen concentration between approximately 15 atomic percent (at%) and approximately 60 at%, which is below the stoichiometric concentration of silicon nitride (Si3N4).

[0041]

[0044] The upper silicon nitride layer 314A' may have a nitrogen concentration between approximately 5 atomic percent (at%) and approximately 25 at%.

[0042]

[0045] The bilayer, consisting of a bottom nitrogen-rich silicon nitride layer 314A and an upper silicon nitride layer 314A', can be formed in two steps by an atomic layer deposition (ALD) process within a processing station, such as one of the processing stations 108 shown in Figure 1.

[0043]

[0046] In the first step of the ALD process, the bWL structure 300 is exposed to a silicon-containing precursor and a nitrogen source, forming a silicon nitride layer 314B at the bottom. The silicon-containing precursor is silane (SiH4), disilane (Si2H6), tetrasilane (Si4H 10 ), or combinations thereof. The nitrogen source may be ammonia (NH3) or nitrogen (N2), etc.

[0044]

[0047] In the second step of the ALD process, the bWL structure 300 is exposed to a silicon-containing precursor to form the upper silicon oxide layer 314B'. The silicon-containing precursors are silane (SiH4), disilane (Si2H6), and tetrasilane (Si4H 10 ), or combinations thereof.

[0045]

[0048] In some other embodiments, the silicon nitride layer 314 is a hybrid layer consisting of a bottom silicon nitride layer 314B on a protective interlayer oxide 312 and an upper silicon oxide layer 314B' on the bottom silicon nitride layer 314B, as shown in Figure 4B.

[0046]

[0049] The silicon nitride layer 314B at the bottom may have a thickness of approximately 5 Å to approximately 20 Å.

[0047]

[0050] The upper silicon dioxide layer 314B' may have a thickness of approximately 5 Å to approximately 20 Å.

[0048]

[0051] The hybrid layer of the bottom silicon nitride layer 314B and the top silicon oxide layer 314B' can be formed in two steps by an atomic layer deposition (ALD) process within a processing station, such as one of the processing stations 108 shown in Figure 1.

[0049]

[0052] In the first step of the ALD process, the bWL structure 300 is exposed to a silicon-containing precursor and a nitrogen source, forming a silicon nitride layer 314B at the bottom. The silicon-containing precursor is silane (SiH4), disilane (Si2H6), tetrasilane (Si4H 10 ), or combinations thereof. The nitrogen source may be ammonia (NH3) or nitrogen (N2), etc.

[0050]

[0053] In the second step of the ALD process, the bWL structure 300 is exposed to a silicon-containing precursor and an oxygen source to form the upper silicon oxide layer 314B'. The silicon-containing precursor is silane (SiH4), disilane (Si2H6), tetrasilane (Si4H 10 ), or a combination thereof. The oxygen source may include water (H2O) or ozone (O3).

[0051]

[0054] In block 230, as shown in Figure 3D, the silicon nitride layer 314 is oxidized by a plasma radical oxidation process such as remote plasma oxidation (RPO) or a thermal radical oxidation process such as an in-situ vapor generation (ISSG) process using hydrogen (H2) and oxygen (O2) gases, and converted to a silicon oxide layer 316 at the interface on the protective interlayer oxide 312. The conversion process may be carried out at a processing station such as one of the processing stations 108 shown in Figure 1. The silicon oxide layer 316 may be used as a gate oxide layer 310, as shown in Figure 3A.

[0052]

[0055] In the plasma radical oxidation process, oxygen radicals (O * The ) is directed towards the silicon nitride layer 314 formed at the interface on the protective interlayer oxide 312 within the trench 304, and thus oxidation of the silicon nitride layer 314 occurs. In some embodiments, the plasma radical oxidation process involves oxygen radicals (O *To provide the oxidizing agent, oxidizing agents such as oxygen (O2), nitric oxide (NO), and nitrous oxide (N2O) may be used. These can be used alone or in combination. Furthermore, the plasma radical oxidation process may use source gases to generate a plasma, including, among other things, any combination of hydrogen (H2) (in proportions of 0% and about 80%), argon (Ar), helium (He), and xenon (Xe). These can be used alone or in combination. In some embodiments, the plasma radical oxidation process may allow the oxidation reaction to occur over a soak time of about 3 seconds to about 3 minutes at a temperature between about 900°C and 1500°C to ensure the high quality of the oxidized silicon.

[0053]

[0056] In some embodiments, the plasma radical oxidation process may be carried out under a pressure between approximately 500 mTorr and approximately 10 Torr. The pressure can control the inflow of the oxidizing agent introduced into the trench 304. The inflow of the oxidizing agent into the trench 304 can also be controlled by applying a bias during the plasma radical oxidation process. Thus, the thickness and nitrogen content of the silicon oxide layer 316 can be controlled and adjusted by adjusting the oxidation temperature and oxidation time of the plasma radical oxidation process. For example, a plasma radial oxidation process at a higher oxidation temperature and a longer oxidation time results in a thicker silicon oxide layer 316. The nitrogen content increases as the thickness of the silicon nitride layer 314 increases, and the nitrogen content increases as the oxidation time decreases and the oxidation temperature decreases.

[0054]

[0057] The thermal radical oxidation process is carried out at a low pressure of about 10 Torr and a temperature between about 700°C and about 1050°C, using oxygen radicals (O * This may be a combustion process that utilizes H2 and O2 gases to provide ).

[0055]

[0058] In some embodiments, the silicon oxide layer 316 consumes, for example, a silicon nitride layer 314 having a nitrogen concentration gradient to a depth between about 0.5 nm and about 4 nm at the interface on the protective interlayer oxide 312.

[0056]

[0059] In some other embodiments, the nitrogen-rich silicon nitride layer 314A at the bottom of the bilayer at the interface on the protective interlayer oxide 312 is completely oxidized and densified where stoichiometric and structural defects caused by nitrogen are minimized. Using a low-temperature oxidation process at temperatures between approximately 25°C and 250°C, the upper silicon nitride layer 314A' can be completely converted to a silicon oxide layer to remove nitrogen from the upper silicon nitride layer 314A'.

[0057]

[0060] In some other embodiments, the bottom silicon nitride layer 314B of the hybrid layer is oxidized at the interface on the protective interlayer oxide 312.

[0058]

[0061] In block 240, an optional post-oxidation densification treatment is performed to increase the density of the silicon oxide layer 316 (for example, by removing nitrogen and rearranging the internal bonding structure).

[0059]

[0062] The post-oxidation densification treatment may be a plasma treatment such as a decoupled plasma (DPHe) process or a remote plasma oxidation (RPO2) process, performed at a temperature between approximately 400°C and approximately 650°C for a period of approximately 10 seconds to approximately 200 seconds.

[0060]

[0063] In embodiments described herein, a bWL structure 300 having trenches 304 is used as an exemplary structure that can benefit from method 200 for forming a high-quality thin oxide layer. Method 200 can also be used to form a high-quality thin oxide layer in a structure having convex features (e.g., protrusions) or flat features (e.g., within a thin nanowire field-effect transistor (FET)).

[0061]

[0064] Embodiments described herein provide a method for forming a high-quality thin oxide layer within a semiconductor device, such as a buried word line (bWL) used in a dynamic random access memory (DRAM) device, and a thin nanowire field-effect transistor (FET) of thin nanowires. In the method described herein, the thin oxide layer may be formed by first depositing a silicon nitride layer on a substrate and then oxidizing the silicon nitride layer by a conversion process. The method described herein for forming the oxide layer can reduce silicon consumption and improve the quality of the formed oxide layer. The method described herein also provides the ability to adjust the thickness and nitride content distribution of the formed oxide layer.

[0062]

[0065] While the above description applies to embodiments of the present disclosure, other embodiments and further embodiments of the present disclosure may be devised without departing from the basic scope of the present disclosure, and the scope of the present disclosure is determined by the following claims.

Claims

1. A method for forming an oxide layer, Forming a protective interlayer oxide on the sidewalls of trenches formed on the substrate, The process involves forming a silicon nitride layer on the protective interlaminar oxide by a plasma atomic layer deposition (PE-ALD) process using a nitrogen-containing treatment gas, wherein the silicon nitride layer has a nitrogen concentration gradient that fluctuates from a high concentration far from the protective interlaminar oxide to a low concentration near the protective interlaminar oxide. The process involves oxidizing the formed silicon nitride layer and performing a conversion process to at least partially convert the formed silicon nitride layer into a silicon oxide layer. Methods that include...

2. The method according to claim 1, further comprising performing a densification treatment to increase the density of the silicon oxide layer.

3. The method according to claim 2, wherein the densification process is a decoupled plasma process or a remote plasma oxidation process.

4. The nitrogen-containing treatment gas is nitrogen (N ２ ) gas and ammonia (NH ３ The method according to claim 1, comprising at least one of the gases.

5. The silicon nitride layer is silicon nitride (Si) having a thickness between 5 Å and 25 Å. ３ N ４ The method according to claim 1, including )

6. The aforementioned protective interlayer oxide is silicon oxide (SiO₂) having a thickness of 5 Å to 15 Å. ２ The method according to claim 1, including )

7. The aforementioned conversion process involves oxygen (O ２ An oxidizing agent containing ) and hydrogen (H ２ The method according to claim 1, comprising a plasma radical oxidation process utilizing a source gas comprising any combination of ), argon (Ar), and helium (He).

8. where the conversion process includes an in-situ steam generation (ISSG) process that utilizes hydrogen (H ２ 2) gas and oxygen (O ２ 2) gas, the method according to claim 1.

9. A method for forming an oxide layer, Forming a protective interlayer oxide on the sidewalls of trenches formed on the substrate, By an atomic layer deposition (ALD) process, a bilayer is formed consisting of a bottom nitrogen-rich silicon nitride layer on the protective interlayer oxide and an upper silicon nitride layer on the bottom nitrogen-rich silicon nitride layer. The process involves oxidizing the formed bottom nitrogen-rich silicon nitride layer and performing a conversion process to convert the formed bottom nitrogen-rich silicon nitride layer into a silicon oxide layer. Methods that include...

10. The method according to claim 9, further comprising performing a densification process for increasing the density of the silicon oxide layer.

11. The method according to claim 9, wherein the bottom nitrogen-rich silicon nitride layer has a nitrogen concentration between 15 atomic percent (at%) and 60 at%, and the upper silicon nitride layer has a nitrogen concentration between 5 atomic percent (at%) and 25 at%.

12. The aforementioned protective interlayer oxide is silicon oxide (SiO₂) having a thickness of 5 Å to 15 Å. ２ The method according to claim 9, including ).

13. The aforementioned conversion process involves oxygen (O ２ An oxidizing agent containing ) and hydrogen (H ２ The method according to claim 9, comprising a plasma radical oxidation process utilizing a source gas comprising any combination of ), argon (Ar), and helium (He).

14. The aforementioned conversion process involves hydrogen (H ２ ) gas and oxygen (O ２ ) gas, the Insulator Steam Generation (ISSG) process that utilizes it, and hydrogen (H ２ The method according to claim 9, comprising an insitu vapor generation (ISSG) process utilizing a source gas comprising any combination of ), argon (Ar), and helium (He).

15. A method for forming an oxide layer, Forming a protective interlayer oxide on the sidewalls of trenches formed on the substrate, A hybrid layer is formed by an atomic layer deposition (ALD) process, consisting of a bottom silicon nitride layer on the protective interlayer oxide and an upper silicon oxide layer on the bottom silicon nitride layer. The process involves oxidizing the formed bottom silicon nitride layer and performing a conversion process to convert the formed bottom silicon nitride layer into a silicon oxide layer. Methods that include...

16. The method according to claim 15, further comprising performing a densification process.

17. The method according to claim 15, wherein the bottom silicon nitride layer has a thickness between 5 Å and 20 Å, and the upper silicon oxide layer has a thickness between 5 Å and 20 Å.

18. The aforementioned protective interlayer oxide is silicon oxide (SiO₂) having a thickness of 5 Å to 15 Å. ２ The method according to claim 17, including )

19. The aforementioned conversion process involves oxygen (O ２ An oxidizing agent containing ) and hydrogen (H ２ The method according to claim 15, comprising a plasma radical oxidation process utilizing a source gas comprising any combination of ), argon (Ar), and helium (He).

20. The aforementioned conversion process involves hydrogen (H ２ ) gas and oxygen (O ２ ) Insulated steam generation (ISSG) process that utilizes gas, hydrogen (H ２ The method according to claim 15, comprising an insitu vapor generation (ISSG) process utilizing a source gas comprising any combination of ), argon (Ar), and helium (He).

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