High-quality SiC crystals, ingots, substrates and methods for manufacturing the same, and semiconductor devices

Abstract

This application relates to the technical field of silicon carbide wafers, providing high-quality SiC crystals, ingots, substrates, and semiconductor devices. The SiC crystal includes faceted and non-faceted regions, the faceted regions being located on the outer edge of the SiC crystal, and the distance between the edge away from the outer edge in the faceted region and the outer edge is 3% or less of the diameter of the SiC crystal. The SiC crystal is obtained by direct growth by the PVT method without subsequent processing. The faceted regions are removed during subsequent crystal processing, achieving a low loss rate and ensuring that the entire ingot and the subsequently processed wafers and substrates are free of faceted regions. This ensures that the devices have higher yield, performance, and reliability.

Description

[Technical Field]

[0001] This application relates to the technical field of silicon carbide wafers, and more specifically to high-quality SiC crystals, ingots, substrates and The method for manufacturing the same, and Regarding semiconductor devices.

[0002] This application relates to a Chinese patent application filed with the China National Intellectual Property Office on September 28, 2023, with application number 202311265574.7, titled "High-Quality Silicon Carbide Substrate and Semiconductor Device," and a Chinese patent application filed with the China National Intellectual Property Office on November 3, 2023, with application number 202311464892.6, titled "SiC Crystal with Facets Located at the Edge, Wafer thereof, and Semiconductor Device." Furthermore, an application number 202410586417.4 was filed with the China National Intellectual Property Office on May 13, 2024, with the title of the invention being "High-quality silicon carbide substrate and method for manufacturing the same, and semiconductor device." Priority was claimed from the Chinese patent application, and all of its contents were incorporated into this application by reference. [Background technology]

[0003] Currently, silicon carbide crystals face two main problems: 1) quality issues affecting the yield, performance, and reliability of silicon carbide devices, and 2) cost issues affecting the application of silicon carbide at the terminal. Of these, the loss of material and device yield due to material quality is a major reason why the current cost of silicon carbide crystals is high and difficult to apply.

[0004] The quality issues of silicon carbide crystals include two types: firstly, material quality and yield problems due to defect issues, which are apparent quality problems; and secondly, material yield and device performance reliability problems due to consistency issues.

[0005] Currently, growth feature surfaces are inherent attributes of SiC crystals produced by the sublimation method, and therefore, such growth feature surfaces exist in both SiC crystals and substrates produced by the conventional physical vapor transport method (abbreviated as PVT). In this field, these growth feature surfaces are commonly referred to as "facets," "growth facets," or "characteristic growth surfaces," and the corresponding English term is "facet." In this application, the term "growth feature surface" does not refer to the growth interface.

[0006] Improving quality and reducing costs are the goals of the continued development of silicon carbide crystalline materials. In particular, the silicon carbide industry is now rapidly entering the stage of large-scale production and application, and the stability, consistency, and reliability of the performance of silicon carbide materials will play a crucial role in the industry's development. [Overview of the project] [Means for solving the problem]

[0007] To solve the above problems, a first aspect of the present invention provides a SiC crystal in which facets are located at the edges, the SiC crystal comprising a faceted region and a non-faceted region, the faceted region being located at the outer peripheral end face of the SiC crystal, the distance between the edge away from the outer peripheral end face in the faceted region and the outer peripheral end face being 3% or less of the diameter of the SiC crystal, and the SiC crystal being obtained by direct growth by the PVT method without subsequent processing.

[0008] The outer periphery face is the edge position of the crystal's lateral growth, or is also called the crystal edge position. An edge far from the outer periphery face in a facet region is the edge of the facet region that is closer to the silicon carbide crystal center.

[0009] In some embodiments, the maximum cross-sectional area of ​​the facet region is SiC The cross-sectional area in the diametrical direction of the crystal is 10% or less, and / or the volume of the facet region is SiC It is less than 2% of the total volume of the crystal. For example, the facet region is SiC It may be located on the edge of the crystal at an oblique upward or oblique downward angle.

[0010] In some embodiments, the maximum cross-sectional area of ​​the facet region is SiC The cross-sectional area in the diametrical direction of the crystal is 5% or less, and / or the volume of the facet region is SiC It is 0.6% or less of the total volume of the crystal. The overall shape of the facet region may be triangular, conical, spherical, ellipsoidal, or rhombic. However, this application is not limited thereto, and the facet region may have an irregular shape.

[0011] In some embodiments, the difference in intrafacet resistivity of the faceted region is five times or more than the difference in intrafacet resistivity of the non-faceted region, and / or the difference in light transmittance of the faceted region is five times or more than the difference in light transmittance of the non-faceted region, and / or the TDV of the faceted region is six times or more than the TDV of the non-faceted region.

[0012] In some embodiments, the difference in intrafacet resistivity of the faceted region is 8 times or more than the difference in intrafacet resistivity of the non-faceted region, and / or the difference in light transmittance of the faceted region is 14 times or more than the difference in light transmittance of the non-faceted region, and / or the TDV of the faceted region is 10 times or more than the TDV of the non-faceted region.

[0013] In some embodiments, the facet region has an elliptical, crescent-shaped, or circular cross-section in the diametrical direction. However, the present application is not limited thereto, and the diametrical cross-section of the facet region may have an irregular shape.

[0014] A second aspect of the present invention provides a facetless silicon carbide ingot obtained by removing the facet region using a SiC crystal in which the facets are located at the edges.

[0015] In the third aspect of the present application, a SiC wafer is provided. The SiC wafer is obtained by removing a facet region using a SiC crystal in which the facet is located at an edge to obtain a non-faceted silicon carbide ingot, and further cutting the non-faceted silicon carbide ingot. The SiC wafer does not include any one or two or more of a facet, a highly doped region, and a defect aggregation region within the entire area range.

[0016] In some embodiments, the difference in resistivity within the facet of the SiC wafer is 2 mΩ·cm or less, and / or the difference in light transmittance is 3% or less, and / or the TDV is less than 200 cm -2 more.

[0017] In some embodiments, the difference in resistivity within the facet of the SiC wafer is 1 mΩ·cm or less, and / or the difference in light transmittance is 2% or less, and / or the TDV is less than 100 cm -2 more.

[0018] In some embodiments, the SiC wafer is a silicon carbide wafer of any thickness. For example, the SiC wafer has a thickness of 200 μm or more, or the silicon carbide wafer has a thickness of 300 μm or more, or the silicon carbide wafer has a thickness of 400 μm or more.

[0019] In some embodiments, the SiC wafer may be doped with N2 or co-doped with any other element. Optionally, the nitrogen gas may be co-doped with any one or two or more elements of P, As, Ge, Sn, B, Al, and the obtained silicon carbide wafer is of a conductive type.

[0020] In the present application, the silicon carbide substrate is obtained by removing the facet region using a SiC crystal in which the facet is located at the edge to obtain a non-faceted silicon carbide ingot, then sequentially cutting to obtain a peeled sheet, sequentially thinning the peeled sheet, polishing, and cleaning to obtain a silicon carbide substrate sheet. Conventional technology However, the silicon carbide wafer is obtained by direct cutting.

[0021] In a fourth aspect of the present application, a high-quality silicon carbide substrate is provided, the high-quality silicon carbide substrate is obtained by processing a SiC crystal in which the facets are located at the edges and removing the facet regions, the silicon carbide substrate is conductive and does not contain one or more of the growth feature surfaces, highly doped regions and defect cluster regions within its entire area, and the silicon carbide substrate is obtained by manufacturing by the PVT method.

[0022] Growth feature planes are an inherent attribute of SiC crystals produced by the PVT method. The high-quality silicon carbide substrate of this application allows the movement tendency of the growth feature planes to be altered during growth by the PVT method, causing them to move to the crystal edge and be fixed within a 5 mm range from the crystal edge. In actual use of the crystal, the edge is cut, so a silicon carbide substrate without growth feature planes can be obtained by processing such as cutting, polishing, etc.

[0023] In the original substrate, defects are concentrated in the areas where growth features are present, and during the elemental doping process, elements also accumulate and increase on these growth features. This results in a doping-like unevenness, with higher resistivity on the growth features than on other areas, and poor uniformity of light transmission throughout the substrate. As described above, this limits the large-scale use of silicon carbide substrates.

[0024] The high-quality silicon carbide substrate in this application has a growth-free characteristic surface, and the entire substrate exhibits a uniform distribution in both the radial and axial directions. This fundamentally suppresses the occurrence and concentration of defects, avoids the aggregation of elements during the doping process, and achieves uniform elemental doping. As a result, the uniformity of substrate doping, resistivity, and light transmittance is improved. Therefore, devices produced using this silicon carbide substrate not only have good performance themselves, but also exhibit good consistency in mass production, making them advantageous for industrialization, widespread adoption, and use.

[0025] In some embodiments, the silicon carbide substrate is N-type element It is doping, specifically N-type element doping. doping concentration but 1e18 cm -3 Larger than In case The properties within the entire surface area of ​​the silicon carbide substrate satisfy the following conditions: a. The difference in resistivity within the facet is 2.0 mΩ·cm or less. and / or b. The difference in light transmittance is 3% or less.

[0026] For example, the difference in resistivity within each facet is 1.0 mΩ·cm or less, or 0.9 mΩ·cm or less, or 0.7 mΩ·cm or less. The resistivity within each facet is the resistivity at any test location within the facets of the silicon carbide substrate.

[0027] In some embodiments, the doping concentration but 2e 18 ~7e 18 cm -3 dea In the case The difference in resistivity within the aforementioned facets is 0.62 to 0.86 mΩ·cm.

[0028] In some embodiments, the difference in light transmittance is 2% or less, or the difference in light transmittance is 1% or less, or the difference in light transmittance is 0.8% or less.

[0029] In some embodiments, the difference in light transmittance is 0.5% to 1.6%. Selectively, the difference in light transmittance is 0.5% to 1%. In some embodiments, the substrate is a silicon carbide substrate of any thickness. For example, the silicon carbide substrate may be 200 μm or thicker, or 300 μm or thicker, or 400 μm or thicker.

[0030] For example, the N-type element doping is doped with N2 doping or any other element, the difference in resistivity within the facet is 0.62 to 0.86 mΩ·cm, and the difference in light transmittance is 0.5% to 1.6%. Optionally, nitrogen gas may be co-doped with any one or more of the elements P, As, Ge, Sn, B, and Al, and the obtained silicon carbide wafer is still of the conductive type.

[0031] The N-type element doping doping The concentration is greater than 1e18 cm -3 and belongs to medium-high nitrogen doping. For those skilled in the art, the higher the doping concentration, the more likely there is a non-uniformity in doping. However, the difference in resistivity within the facet increases. In this application, in the process of controlling the movement tendency of the growth characteristic surface, in order to fix the growth characteristic surface to the crystal edge, the uniformity of doping can be improved during the doping process, and the light transmittance of the substrate can be made more uniform.

[0032] The light transmittance depends on the doping concentration and uniformity in the crystal. The fact that the difference in the light transmittance of the silicon carbide substrate in this application is 3% or less can represent the uniformity of the light transmittance of the silicon carbide substrate, which is beneficial for improving the quality of the downstream device-side lithography process and further improving the device performance.

[0033] In some embodiments, the TDV of the silicon carbide substrate is less than 200 cm -2 Optionally, the TDV of the silicon carbide substrate is less than 100 cm -2 Optionally, the TDV of the silicon carbide substrate is less than 10 cm -2It is smaller than that. Of these, the total density variation (abbreviated as TDV) is defined as dividing the substrate into n grids of a specific area, for example, with areas of 1mmx1mm, 2mmx2mm, 5mmx5mm, and 10mmx10mm, and the densities of edge dislocations (abbreviated as TED) or helical dislocations (abbreviated as TSD) within the grids being d1, d2, d3...dn. TDV is the difference dmax-dmin between the case where the TED / TSD density is maximum and the case where the TED / TSD density is minimum.

[0034] The silicon carbide substrate of this invention eliminates growth characteristic surfaces and allows for a more uniform distribution of TED and TSD, resulting in a lower TDV value and a uniform distribution of dislocations across the entire substrate. This eliminates the problem of low overall defect density but high localized density that was present in conventional substrates.

[0035] When the above substrate is used to manufacture power electronic devices, its characteristics of low difference in resistivity within facets and low light transmittance ensure that the device has excellent electrical performance and reliability during the device production process.

[0036] In some embodiments, the size of the silicon carbide wafer or silicon carbide substrate may be 4 inches, 6 inches, 8 inches, 10 inches, or 12 inches.

[0037] A fifth aspect of the present application provides a semiconductor device comprising the above-mentioned SiC wafer or a high-quality silicon carbide substrate.

[0038] The sixth aspect of the present application So, A method for manufacturing the aforementioned high-quality silicon carbide substrate is provided. The silicon carbide substrate is obtained from a crystal that has undergone at least a cutting process.Facets are an inherent attribute of SiC crystals produced by the sublimation method, and such facet regions exist in both SiC crystals and wafers produced by conventional physical vapor transport methods. In order to fix facets to the crystal edge and remove them in the subsequent crystal processing process, thereby achieving a facet-free ingot and subsequently processed wafers and substrates, the SiC crystal processing method of the present invention, in which facets are located at the edge, includes a crystal stabilization growth stage, and the growth process conditions of the crystal stabilization growth stage include the following steps.

[0039] S1: A limiting edge exists near the crystal growth edge, the distance between the limiting edge and the crystal growth edge is 5 mm or less, a negative radial temperature gradient of -5°C / mm to -0.1°C / mm is set within the range between the limiting edge and the crystal growth edge, a continuous positive temperature gradient is set from the limiting edge to the crystal center, and the value of the continuous positive temperature gradient is ≤3°C / cm.

[0040] S2: Goal of By using a seed crystal with a diameter larger than that of the silicon carbide crystal, The aforementioned The diameter of the seed crystal is The aforementioned the goal silicon carbide The high-quality silicon carbide substrate is at least 5 mm larger than the diameter of the crystal and the substrate. The aforementioned the goal silicon carbide It is obtained by processing crystals.

[0041] In some embodiments, the distance between the limiting edge and the crystal growth edge is 3 mm or less.

[0042] In some embodiments, in step S1, a negative radial temperature gradient of -5°C / mm to -0.1°C / mm is set within a range smaller than 5 mm from the crystal growth edge, and a continuous positive temperature gradient is set within a range larger than 5 mm from the crystal growth edge. of The value is ≤3°C / cm.

[0043] In some embodiments, in step S1, a negative radial temperature gradient of -3°C / mm to -1°C / mm is set within a range of less than 5 mm from the crystal growth edge.

[0044] The radial temperature gradient is calculated as the ratio of the difference (T2-T1) between the temperature T1 at a point close to the wafer center and the temperature T2 at a point far from the wafer center, radiating radially outward from the wafer center, with respect to the distance d between the two points. A positive (positive direction) temperature gradient is ΔT = (T2-T1) / d, and conversely, a negative temperature gradient is ΔT = (T1-T2) / d.

[0045] The manufacturing method employed in this application allows the growth feature plane to be driven to move to the crystal edge in step S1, fixed within a 5 mm range from the crystal edge, and a high-quality silicon carbide substrate to be obtained. However, as those skilled in the art will understand, it is possible to obtain the silicon carbide substrate of this application by controlling the tendency of the growth feature plane's movement in other ways. Therefore, this application only describes the manufacturing method for the high-quality silicon carbide substrate obtained in this application, but other methods for controlling the tendency of the growth feature plane are outside the scope of this research.

[0046] The radial temperature gradient of crystal growth in step S1 can be set by conventional technical means in the industry, and can be adjusted overall by adjusting parameters such as the temperature or pressure inside the growth chamber or the thickness of the insulation layer material. Setting a discontinuous temperature gradient can be achieved by improving the structuring inside the crystal growth chamber and optimizing the temperature distribution at the crystal growth interface, thereby enabling controllable adjustment of the temperature gradient. For example, by placing a material with lower thermal conductivity than the central region at the edge of the crystal growth chamber to reduce edge heat loss, a jump in the temperature distribution at the crystal growth interface can be achieved. Conversely, a reverse temperature gradient distribution can be set by placing a material with higher thermal conductivity at the crystal growth edge or by reducing the thickness of the edge insulation layer. Furthermore, the temperature distribution can also be adjusted by placing different thermal field structures or novel materials inside the growth chamber. For example, by placing and applying a TaC coating material with high reflectivity to the graphite ring at the crystal growth edge, thermal radiation inside the growth chamber is concentrated at the crystal growth edge, thereby achieving a jump in the temperature gradient. By using the above-mentioned most common technical means in the industry, the objective of adjusting the temperature gradient inside the crystal growth chamber can be achieved by arranging solutions according to actual needs.

[0047] In some embodiments, in the crystal growth stabilization step, the temperature inside the growth chamber is first raised to 2200°C or higher at a rate of 10-50°C / min, and the pressure inside the growth chamber is reduced to 1-100 mbar, after which the crystal is maintained to grow for 50 hours or more according to the settings of steps S1 and S2.

[0048] In some embodiments, in the crystal growth stabilization step, the temperature in the growth chamber is first raised to 2200°C or higher at a rate of 10-30°C / min, and the pressure is reduced to 5-50 mbar, after which the crystal is maintained for 50 hours or more according to the settings of steps S1 and S2.

[0049] In this application, silicon carbide crystals are produced by the PVT method, and crystal growth is carried out using isotropic graphite as the raw material for the growth chamber (crucible) and SiC powder as the raw material for crystal growth. In order to guarantee the excellent and stable electrical performance of silicon carbide, in several embodiments of this application, silicon carbide of a certain purity is used to synthesize the powder, and the total impurity content of the silicon carbide powder is 1E19cm -3 The following applies, and in some embodiments, the total impurity content in the silicon carbide powder is 1E 17 cm -3 The following applies:

[0050] In this invention, during silicon carbide crystal growth, SiC powder is placed inside a graphite crucible, a SiC seed crystal is positioned at the top of the growth chamber, the crucible is sealed, and the crucible is placed inside an insulating material made of soft or hard graphite felt to enclose it, and then moved to a crystal growth equipment chamber to grow the crystal.

[0051] In some embodiments, a crystal nucleation step is further included before the crystal stabilization growth step, and the growth process conditions for the crystal nucleation step include the following steps.

[0052] After sealing the crystal growth chamber, the growth chamber is 10 -3 The process begins by evacuating the chamber to below Pa, and after the vacuum level stabilizes for a certain period, introducing an inert gas. The pressure inside the growth chamber is then gradually increased to 100-1000 mbar and then stabilized, while nitrogen gas is introduced into the chamber at a rate of 1 ml / min to 100 ml / min.

[0053] In some embodiments, during the crystal nucleation stage, the pressure inside the growth chamber is increased, and the temperature inside the growth chamber is gradually raised from room temperature to 1600-2100°C and then kept constant. After maintaining this constant temperature and pressure for 5-50 hours, the crystal stabilization growth stage is performed.

[0054] In some embodiments, during the crystal nucleation stage, the temperature inside the growth chamber is kept constant at 1800-2100°C, and the pressure inside the growth chamber is kept constant at 300-800 mbar. After maintaining constant temperature and pressure for 30-50 hours, the crystal stabilization growth stage is performed.

[0055] In the crystal nucleation stage, silicon carbide powder sublimes to form crystal nuclei, and in the subsequent crystal stabilization growth stage, the silicon carbide powder sublimes sufficiently and is transferred to the seed crystal for stable growth, ultimately yielding a silicon carbide crystal. The diameter of the seed crystal in step S2 is the target. silicon carbide Because the seed crystal diameter is at least 5 mm larger than the substrate diameter, the manufactured SiC crystal has a margin for edge processing, and high-quality silicon carbide crystals can be obtained by cutting the edges. For example, by setting the seed crystal diameter to 160 mm and the substrate diameter to 150 mm, or the seed crystal diameter to 210 mm and the substrate diameter to 200 mm, the smooth manufacture of large silicon carbide substrates can be guaranteed, and the quality of the manufactured silicon carbide substrates can be improved. [Effects of the Invention]

[0056] Compared to the prior art, this invention can achieve at least one of the following beneficial effects.

[0057] (1) In this invention, for SiC crystals where facets are located at the edges, the facet region is fixed away from the crystal edge during the direct PVT growth process, and the distance between the edge away from the outer peripheral end face in the facet region and the outer peripheral end face is 3% or less of the diameter of the SiC crystal. The facet region is removed during the subsequent crystal processing process, achieving a low loss rate and ensuring that the entire ingot and the subsequently processed wafers and substrates are free of facet regions.

[0058] (2) In this application, the SiC wafer has high uniformity, such as electrical uniformity (e.g., uniformity of resistivity), uniformity of light transmittance, and uniformity of defect distribution. Furthermore, in this application, the silicon carbide wafer does not have any facet regions that can be seen with the naked eye.

[0059] (3) In this invention, the silicon carbide substrate has high electrical uniformity (e.g., uniformity of resistivity), high uniformity of light transmittance, and high uniformity of defect distribution. When the substrate is cut and used in the manufacture of semiconductor devices, the utilization rate of the effective area can be improved. The semiconductor devices manufactured not only have better performance than other substrates of the same area, but are also produced in larger quantities, which can reduce the production cost of semiconductor devices.

[0060] (4) In this application, the silicon carbide substrate has a total area of ​​200 cm². -2 It is smaller than conventional substrates, has a lower overall defect density, but eliminates the problem of localized high density, and has virtually no dislocations or stacking faults, making it more suitable for widespread use and application.

[0061] (5) In this application, the silicon carbide substrate has no visible growth features, the difference in resistivity is 2.0 mΩ·cm or less within the entire area, and the difference in light transmittance is 3% or less, thus demonstrating high uniformity of the silicon carbide substrate and higher yield, performance, and reliability of semiconductor devices manufactured on this silicon carbide substrate. [Brief explanation of the drawing]

[0062] The above and / or additional aspects and advantages of the present application will become apparent and readily apparent from the description of the embodiments in conjunction with the following drawings.

[0063] [Figure 1] An exemplary embodiment is shown, including a schematic diagram of the faceted silicon carbide substrate as observed visually. [Figure 2] An exemplary example of the schematic diagram of the facet growth process of the present invention is shown. [Figure 3] This example shows a schematic diagram of the structure of a SiC crystal in which the facets of the present invention are located at the edges. [Figure 4] The graph shows the light transmittance test method. [Figure 5] The resistivity mapping graph of the silicon carbide substrate of Embodiment 1 of this application is shown. [Figure 6] The resistivity mapping graph of the silicon carbide substrate in Embodiment 2 of this application is shown. [Figure 7] The resistivity mapping graph of the silicon carbide substrate in Embodiment 3 of this application is shown. [Figure 8] The resistivity mapping graph of the silicon carbide substrate in Embodiment 4 of this application is shown. [Figure 9] The resistivity mapping graph of the silicon carbide substrate of Comparative Example 1 of this application is shown. [Figure 10] The resistivity mapping graph of the silicon carbide substrate of Comparative Example 1 of this application is shown. [Figure 11] The resistivity mapping graph of the silicon carbide substrate of Comparative Example 1 of this application is shown. [Figure 12] The resistivity mapping graph of the silicon carbide substrate of Comparative Example 1 of this application is shown. [Figure 13] This graph shows a comparison of the light transmittance of the silicon carbide substrate of Example 2 of the present application and the silicon carbide substrate of Comparative Example 1. [Figure 14] The graph shows the change in light transmittance of the silicon carbide substrate in Example 3 of this application. [Figure 15] A schematic diagram of the silicon carbide substrate structure of the non-growth characteristic surface of the present invention is shown. [Modes for carrying out the invention]

[0064] To provide a clearer understanding of the above-mentioned objectives, features, and advantages of this application, the present application will be described in further detail below with reference to the drawings and specific embodiments. The embodiments and features of the present application can be combined with each other, as long as they do not contradict each other.

[0065] While the following description provides many specific details to facilitate a thorough understanding of the present application, the application may also be implemented in ways other than those described herein, and therefore the scope of protection is not limited to the specific embodiments disclosed below.

[0066] Currently, conventional silicon carbide substrates or wafers have growth feature surfaces, and the resistivity of these growth feature surfaces is too low. As a result, the resistivity distribution, light transmittance distribution, and carrier concentration fluctuation rate are non-uniform across the entire surface area of ​​the silicon carbide substrate. Furthermore, dislocations and stacking faults may occur in these regions, potentially leading to problems such as the expansion of stacking faults during subsequent use of the device. To solve the above problems, this application provides a high-quality silicon carbide substrate that does not have visible growth feature surfaces across the entire surface area of ​​the silicon carbide substrate, and exhibits high uniformity in resistivity, doping concentration, light transmittance, and carrier concentration across the entire surface area of ​​the silicon carbide substrate.

[0067] In the silicon carbide crystal manufacturing process of Examples 1 to 5 below, growth feature planes can be fixed to the silicon carbide crystal edges. As the crystal edges are processed, a silicon carbide substrate or silicon carbide wafer with no growth feature planes is obtained. Because the unique structural attributes such as growth feature planes are eliminated, the number of defects in the silicon carbide substrate or silicon carbide wafer itself decreases without aggregation. At the same time, aggregation of elements during doping, i.e., the existence of highly doped regions, can be avoided. As a result, the uniformity of doping, uniformity of light transmission, and uniformity of resistivity of the silicon carbide substrate or silicon carbide wafer with a structure like that of no growth feature planes are all improved. [Examples]

[0068] This embodiment relates to a method for manufacturing a 6-inch high-quality silicon carbide substrate, and specifically includes the following steps.

[0069] (1) In the crystal nucleation stage After placing silicon carbide powder and seed crystals into a crucible, the growth chamber is sealed and heated using a mechanical pump and a vacuum pump for 10°C. -3 The chamber was evacuated to below Pa, and after the vacuum level stabilized for a certain period, an inert gas was introduced. The pressure inside the growth chamber was gradually increased to 100 mbar, while nitrogen gas was introduced into the chamber at a rate of 100 ml / min. During the crystal nucleation stage, as the pressure inside the growth chamber increased, the furnace temperature was gradually raised from room temperature to 1600°C by adjusting the power setting and maintained for 50 hours.

[0070] (2) In the crystal growth stabilization stage After the crystal nucleation stage was completed, the temperature was increased to 2200°C at a rate of 20°C / min, and the pressure inside the growth chamber was reduced to 50 mbar by adjusting the pressure control device and maintained at that level for 50 hours. Specifically, the following was done:

[0071] S1: A negative radial temperature gradient of -0.1°C / mm is set within a range smaller than 5mm from the crystal growth edge, and a continuous positive temperature gradient is set within a range larger than 5mm from the crystal growth edge, with a continuous positive temperature gradient of 1°C / cm.

[0072] S2: Goal of The silicon carbide crystal is grown using a seed crystal with a diameter larger than that of the target crystal. silicon carbide It was 5mm larger than the crystal. The goal achieved through growth. silicon carbide By processing the crystal through cutting, polishing, and other methods, we were able to obtain the target silicon carbide substrate. [Examples]

[0073] This embodiment relates to a method for manufacturing a 6-inch high-quality silicon carbide substrate, and specifically includes the following steps.

[0074] (1) In the crystal nucleation stage After placing silicon carbide powder and seed crystals into a crucible, the growth chamber is sealed and heated using a mechanical pump and a vacuum pump for 10°C. -3 The chamber was evacuated to below Pa, and after the vacuum level stabilized for a certain period, an inert gas was introduced. The pressure inside the growth chamber was gradually increased to 300 mbar, while nitrogen gas was introduced into the chamber at a rate of 40 ml / min. During the crystal nucleation stage, as the pressure inside the growth chamber increased, the furnace temperature was gradually raised from room temperature to 1800°C by adjusting the power setting and maintained for 30 hours.

[0075] (2) In the crystal growth stabilization stage After the crystal nucleation stage was completed, the temperature was increased to 2400°C at a rate of 30°C / min, and the pressure inside the growth chamber was reduced to 10 mbar by adjusting the pressure control device and maintained at that level for 70 hours. Specifically, the following was done:

[0076] S1: A negative radial temperature gradient of -5°C / mm is set within a range smaller than 4.5mm from the crystal growth edge, and a continuous positive temperature gradient is set within a range larger than 4.5mm from the crystal growth edge, with the continuous positive temperature gradient being 1°C / cm.

[0077] S2: Goal of The silicon carbide crystal is grown using a seed crystal with a diameter larger than that of the target crystal. silicon carbide It was 6mm larger than the crystal. The goal achieved through growth. silicon carbide By processing the crystal through cutting, polishing, and other methods, we were able to obtain the target silicon carbide substrate. [Examples]

[0078] This embodiment relates to a method for manufacturing a 6-inch high-quality silicon carbide substrate, and specifically includes the following steps.

[0079] (1) In the crystal nucleation stage After placing silicon carbide powder and seed crystals into a crucible, the growth chamber is sealed and heated using a mechanical pump and a vacuum pump for 10°C. -3 The chamber was evacuated to below Pa, and after the vacuum level stabilized for a certain period, an inert gas was introduced. The pressure inside the growth chamber was gradually increased to 500 mbar, while nitrogen gas was introduced into the chamber at a rate of 40 ml / min. During the crystal nucleation stage, as the pressure inside the growth chamber increased, the furnace temperature was gradually raised from room temperature to 2100°C by adjusting the power setting and maintained for 50 hours.

[0080] (2) In the crystal growth stabilization stage After the crystal nucleation stage was completed, the temperature was increased to 2500°C at a rate of 10°C / min, and the pressure inside the growth chamber was reduced to 20 mbar by adjusting the pressure control device and maintained there for 70 hours. Specifically, the following was done:

[0081] S1: With a boundary of 3.5 mm from the crystal growth edge, a negative radial temperature gradient of -3°C / mm is set in the range smaller than 3.5 mm from the crystal growth edge, and a continuous positive temperature gradient is set in the range larger than 3.5 mm from the crystal growth edge, with the continuous positive temperature gradient being 3°C / cm.

[0082] S2: Goal of The silicon carbide crystal is grown using a seed crystal with a diameter larger than that of the target crystal. silicon carbide It was 6mm larger than the crystal. The goal achieved through growth. silicon carbide By processing the crystal through cutting, polishing, and other methods, we were able to obtain the target silicon carbide substrate. [Examples]

[0083] This embodiment relates to a method for manufacturing a 6-inch high-quality silicon carbide substrate, and specifically includes the following steps.

[0084] (1) In the crystal nucleation stage After placing silicon carbide powder and seed crystals into a crucible, the growth chamber is sealed and heated using a mechanical pump and a vacuum pump for 10°C. -3 The chamber was evacuated to below Pa, and after the vacuum level stabilized for a certain period, an inert gas was introduced. The pressure inside the growth chamber was gradually increased to 300 mbar, while nitrogen gas was introduced into the chamber at a rate of 30 ml / min, and phosphorus was doped into the material. During the crystal nucleation stage, as the pressure inside the growth chamber increased, the furnace temperature was gradually raised from room temperature to 2000°C by adjusting the power setting and maintained for 50 hours.

[0085] (2) In the crystal growth stabilization stage After the crystal nucleation stage was completed, the temperature was increased to 2600°C at a rate of 40°C / min, and the pressure inside the growth chamber was reduced to 20 mbar by adjusting the pressure control device and maintained at that level for 80 hours. Specifically, the following was done:

[0086] S1: With a boundary of 3 mm from the crystal growth edge, a negative radial temperature gradient of -4°C / mm is set in the range smaller than 3 mm from the crystal growth edge, and a continuous positive temperature gradient is set in the range larger than 3 mm from the crystal growth edge, with the continuous positive temperature gradient being 0.5°C / cm.

[0087] S2: Goal of The silicon carbide crystal is grown using a seed crystal with a diameter larger than that of the target crystal. silicon carbide It was 8mm larger than the crystal. The goal achieved through growth. silicon carbide By processing the crystal through cutting, polishing, and other methods, we were able to obtain the target silicon carbide substrate. [Examples]

[0088] A key difference between this embodiment and Example 2 is that in step S1, a negative radial temperature gradient of -1°C / mm is set within a range smaller than 4.5 mm from the crystal growth edge, and an 8-inch silicon carbide substrate is manufactured in this embodiment, while the other steps are the same as in Example 2. Comparative Example 1

[0089] The main difference between this embodiment and Example 2 is that in step S1, a continuous positive temperature gradient is set from the crystal center to the edge, and the continuous positive temperature gradient is 3°C / cm, while the other steps are the same as in Example 2. Comparative Example 2

[0090] The difference between this comparative example and Example 2 is that in step S1, a negative radial temperature gradient of -6°C / mm was set in a range smaller than 4.5 mm from the crystal growth edge, and an 8-inch silicon carbide substrate was manufactured in this example, while the other steps were the same as in Example 2. Experimental Example 1

[0091] Table 1 shows the positional tests of facet regions in a SiC crystal where facets are located at the edges, manufactured using the method described above. The volume of the facet region can be calculated using calculus or modeling.

[0092] [Table 1]

[0093] As shown in Table 1, in the SiC crystal of the present invention, the distance between the facet region and the crystal edge is controlled to be within a range of 5 mm. In the PVT production process, the facet region is directly controlled to move away from the outer edge of the crystal, and the facets are moved to a region outside the target diameter of the crystal. This allows for the removal of the facet region with a low loss rate in the subsequent crystal processing process, thereby obtaining a SiC crystal with fewer defects. In Comparative Examples 1 and 2, the facet region is in an intermediate position and is located within the range of the target diameter of the crystal, resulting in lower yield, performance, and reliability for the devices obtained through subsequent processing.

[0094] The SiC crystal obtained in the example, in which the facets are located at the edge, was processed to remove the facet region, and then directly cut to obtain a SiC wafer. Comparative Example 1 was then cut to form a silicon carbide wafer, and the performance test results of the SiC wafers are shown in Table 2.

[0095] The difference in resistivity within a facet is "maximum resistivity within a facet - minimum resistivity within a facet," and the difference in light transmittance is "maximum light transmittance - minimum light transmittance."

[0096] [Table 2]

[0097] As shown in Table 2, the SiC wafer of this application has no visible facets, uniform resistivity within the facets of the SiC wafer, no abnormally low-resistivity regions, and high uniformity of light transmittance and TDV.

[0098] Based on Examples 1-4, the SiC crystals produced in Examples 1-4 were directly cut to obtain SiC wafers with facets located at the edges. The results of performance tests performed on the resulting silicon carbide wafers containing the facets are shown in Table 3.

[0099] [Table 3]

[0100] As shown in Table 3, the difference in resistivity within facets in the facet region is more than four times greater than the difference in resistivity within facets in the non-facet region, the difference in light transmittance in the facet region is more than five times greater than the difference in light transmittance in the non-facet region, and the TDV of the facet region is more than six times greater than the TDV of the non-facet region.

[0101] This invention provides a method for obtaining SiC crystals with facets only on the edges by direct PVT growth without subsequent processing. By fixing the facet regions to the outer edge of the SiC crystal and removing them during subsequent crystal processing, it achieves a low loss rate, ensuring that the entire ingot and the subsequently processed wafers and substrates are free of facet regions. This reduces the production cost of silicon carbide crystals and guarantees the acquisition of silicon carbide wafers with fewer defects and high uniformity. Experimental Example 2

[0102] In both the above examples and comparative examples, silicon carbide crystals were produced by the PVT crystal growth method. Both examples and comparative examples used silicon carbide substrates obtained by the same edge cutting (5 mm cut), radial cutting, polishing, and grinding processes. The results of performance detection on the obtained silicon carbide substrate samples are shown in Table 4. The specific test method is as follows.

[0103] The resistivity was measured using a Semilab WT-2000 low-resistivity test meter, testing 73 points uniformly and symmetrically distributed within the silicon carbide substrate sheet. In this application, a mapping graph is used to characterize the resistivity distribution of the substrate sheet.

[0104] Light transmittance was measured using a haze meter CS-700, testing multiple points along the diameter of the substrate sheet, passing through the center and the growth feature area. The test method is shown in Figure 4.

[0105] Silicon carbide substrates with non-growing characteristic surfaces of different sizes and doping concentrations were manufactured using the above method, and the performance tests of the non-growing characteristic surface silicon carbide substrates of Examples 6-10 and Comparative Example 2 are shown in Table 4.

[0106] The difference in resistivity within a facet is "maximum resistivity within a facet - minimum resistivity within a facet," and the difference in light transmittance is "maximum light transmittance - minimum light transmittance."

[0107] [Table 4]

[0108] This invention sets a discontinuous temperature gradient distribution in the radial direction of the crystal growth surface, ensuring sufficient driving force for lateral growth of the crystal edge and continuously guaranteeing the ability to expand the diameter of the crystal edge. The crystals of the examples and comparative examples do not change the quality of the substrate even after undergoing the same conventional edge cutting, radial cutting, polishing, and grinding processes. Therefore, from the data in Table 1, the manufacturing method of this invention can control the tendency of movement of the growth feature surface and fix it to the crystal edge. This control of the tendency of movement is shown in Figure 2, and as shown in Figure 3, the growth feature surface on the crystal edge can be removed by cutting the crystal edge. Therefore, the substrates of Examples 1 to 5 have no growth feature surface, and in both the conventional positive temperature gradient of Comparative Example 1 and the edge -6°C / mm temperature gradient of Comparative Example 2, the growth feature surface cannot be moved to and fixed to the edge.

[0109] The silicon carbide substrates of Comparative Examples 1 and 2 both contain growth feature surfaces with the structure shown in Figure 1, which are visible to the naked eye, and do not contain black spots like "nevi" within the entire area of ​​the silicon carbide substrate with no growth feature surfaces. The silicon carbide substrates produced in Examples 1 to 5 do not contain growth feature surfaces with the structure shown in Figure 15, which are visible to the naked eye. From the above examples and comparative examples and Figures 1 and 15, it can be seen that although silicon carbide substrates with no growth feature surfaces were produced using the manufacturing method of the present invention, when combined with the other parameters disclosed in Table 4, structures like growth feature surfaces do not exist, so the difference in resistivity within the facets of the silicon carbide substrate is 2.0 mΩ·cm or less, the difference in light transmittance is 3% or less, and the TDV is 200 cm². -2 This indicates that the performance of the silicon carbide substrate as a whole has improved, with the difference in resistivity within the facets of the silicon carbide substrate, including the growth feature surface of Comparative Examples 1 and 2, being greater than 5 mΩ·cm, the difference in light transmittance being greater than 10%, and the TDV being 400 cm². -2 This is a significant improvement, indicating that the overall performance of the silicon carbide substrate is inferior.

[0110] Figure 5 shows the resistivity mapping graph of the silicon carbide substrate of Embodiment 1 of the present application, Figure 6 shows the resistivity mapping graph of the silicon carbide substrate of Embodiment 2 of the present application, Figure 7 shows the resistivity mapping graph of the silicon carbide substrate of Embodiment 3 of the present application, and Figure 8 shows the resistivity mapping graph of the silicon carbide substrate of Embodiment 4 of the present application. As shown in Figures 5 to 8, the horizontal coordinate represents the diameter of the silicon carbide substrate, the center point of the silicon carbide substrate is point 00, the test area of ​​the equipment in the mapping graph is (-60 mm, 60 mm), the vertical coordinate represents the resistivity, and the color change indicates the resistivity distribution. It can be seen that the resistivity distribution within the facets of the silicon carbide substrate of the present application is uniform, there are no abnormally low-resistivity regions, and the difference in resistivity within the facets is <3 mΩ·cm. In some embodiments, the difference in resistivity within the facets is <1 mΩ·cm.

[0111] Figures 9, 10, 11, and 12 show the resistivity mapping graphs of the silicon carbide substrate of Comparative Example 1 of the present application, respectively. The inventors performed four sets of repeated experiments on Comparative Example 1, and as shown in Figures 9, 10, 11, and 12, the center point of the silicon carbide substrate is point 00, the horizontal coordinate indicates that the area of ​​the test silicon carbide substrate is (-60 mm, 60 mm), and the vertical coordinate indicates the resistivity. It can be seen that due to the presence of growth characteristic surfaces, there is a significant low-resistivity abnormality region in the resistivity distribution, and the difference in resistivity within facets is usually >5 mΩ·cm.

[0112] Figure 13 shows a graph comparing the light transmittance of the silicon carbide substrate of Example 2 of the present application and the silicon carbide substrate of Comparative Example 1. In Figure 13, the horizontal axis represents the test point, the vertical axis represents the light transmittance, the circles represent the graph of the light transmittance of the silicon carbide substrate of Example 2, and the squares represent the graph of the light transmittance of the silicon carbide substrate of Comparative Example 1. From Figure 13, it can be seen that in Comparative Example 1, the dopant concentration and carrier concentration in the growth feature surface region are much higher than in other regions, and the wavelength band of the visible light portion is absorbed, so the visible light transmittance in the growth feature surface region decreases sharply. Furthermore, the silicon carbide substrate manufactured in Example 2 of the present application does not have the problem of excessively high doping and carrier concentrations in the growth feature surface, so the distribution of impurities and carrier concentrations within the substrate facets is uniform, and the uniformity and consistency of the transmittance within the visible light facets are greatly improved.

[0113] Figure 14 shows a graph of the change in light transmittance of the silicon carbide substrate in Embodiment 3 of the present application. The horizontal axis represents the coordinate points of different tests of the silicon carbide substrate, and the vertical axis represents the light transmittance. From Figure 14, it can be seen that the distribution of light transmittance within the facet is uniform.

[0114] This invention eliminates growth feature surfaces, significantly improving the uniformity of internal resistivity and light transmittance of the substrate. It also eliminates the accumulation of defects such as inclusions, dislocations, and micropipes that are normally present in substrates due to growth feature surfaces, resulting in a significant improvement in substrate quality and yield. Consequently, the substrate exhibits greatly improved performance and reliability during subsequent device processing and use.

[0115] As can be seen from the above analysis, the silicon carbide substrates manufactured as shown in Examples 1 to 5 have a processing method that breaks away from the conventional design of a continuous positive radial temperature distribution. Instead, an innovative negative radial temperature gradient is designed at the crystal growth edge, driving the growth feature surface to change its movement tendency, thereby fixing the growth feature surface in the crystal edge region. This is achieved by referring to the fact that the diameter of the seed crystal is at least 5 mm larger than the target diameter, and finally fixing the growth feature surface within a 5 mm range from the crystal edge. Subsequently, by processing such as cutting, polishing, etc., a silicon carbide substrate without the growth feature surface can be obtained from the crystal.

[0116] Since the elimination of growth feature planes is completed during the crystal growth stage and the subsequent substrate processing process does not affect the electrical performance, this application does not particularly limit the substrate processing method and is a normal operation for those skilled in the art. Such a growth method is simple and easy to implement and can ensure stress and defect control with a continuous and small temperature gradient in the central region of the crystal. With the above innovative means, growth feature planes can be fixed at the crystal edge and removed during the subsequent crystal processing process, achieving the absence of growth feature planes in the entire ingot and the subsequently processed substrate, achieving the objective of eliminating defect cluster regions, and ensuring yield and reliability on the device side.

[0117] However, the manufacturing method of the silicon carbide substrate that does not include the growth feature surface of the present application includes, but is not limited to, that such surface. Since a person skilled in the art can also manufacture the silicon carbide substrate in other ways in which the characteristic growth surface can be controlled, the manufacturing method disclosed herein is merely illustrative and does not constitute a limitation on the performance of the silicon carbide substrate itself. A person skilled in the art can also consider new manufacturing methods for obtaining the silicon carbide substrate of the present application by adding creative effort to the prior art means, and other manufacturing methods are not within the scope of the research of the present application and therefore will not be studied.

[0118] The above description is merely a preferred embodiment of the present application and does not limit it, and various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present application should be included within the scope of protection of the present application.

Claims

1. A SiC crystal in which facets are located at the edges, The SiC crystal is characterized in that it includes a faceted region and a non-faceted region, the faceted region is located on the outer peripheral end face of the SiC crystal, the distance between the edge in the faceted region that is away from the outer peripheral end face and the outer peripheral end face is 3% or less of the diameter of the SiC crystal, and the SiC crystal is obtained by direct growth by the PVT method without subsequent processing.

2. The maximum cross-sectional area of ​​the facet region is 10% or less of the cross-sectional area in the diametrical direction of the crystal, and / or The SiC crystal according to claim 1, characterized in that the volume of the facet region is 2% or less of the total volume of the crystal.

3. The maximum cross-sectional area of ​​the facet region is 5% or less of the cross-sectional area in the diametrical direction of the crystal, and / or The SiC crystal according to claim 2, characterized in that the volume of the facet region is 0.6% or less of the total volume of the crystal.

4. The difference in resistivity within the facet region is five times or more the difference in resistivity within the facet region, and / or The difference in light transmittance of the faceted region is five times or more the difference in light transmittance of the non-faceted region, and / or The SiC crystal according to claim 1, characterized in that the TDV of the faceted region is six times or more than the TDV of the non-faceted region.

5. The difference in resistivity within the facet region is eight times or more the difference in resistivity within the facet region of the non-facet region, and / or The difference in light transmittance of the faceted region is 14 times or more the difference in light transmittance of the non-faceted region, and / or The SiC crystal according to claim 4, characterized in that the TDV of the faceted region is 10 times or more the TDV of the non-faceted region.

6. It is a facetless silicon carbide ingot, A facetless silicon carbide ingot characterized by being obtained by removing the facet region using a SiC crystal in which the facets described in any one of claims 1 to 5 are located at the edge.

7. High-quality silicon carbide substrate, The high-quality silicon carbide substrate is characterized in that it is obtained by processing a SiC crystal in which the facets described in any one of claims 1 to 5 are located at the edge, the silicon carbide substrate is conductive, and does not contain one or more of the growth feature surfaces, high-doping regions, and defect cluster regions within its entire area, and the silicon carbide substrate is obtained by manufacturing by the PVT method.

8. The silicon carbide substrate is N-type doped, and the N-type element doping concentration is 1e １８ cm －３ The properties of the silicon carbide substrate within its entire surface area are greater than the following conditions: a. The difference in resistivity within the facets is 2.0 mΩ·cm or less. b. A high-quality silicon carbide substrate according to claim 7, characterized in that the difference in light transmittance is 3% or less.

9. The high-quality silicon carbide substrate according to claim 8, characterized in that the difference in resistivity within the facets is 1.0 mΩ·cm or less.

10. The doping concentration is 2e １８ ~7e １８ cm －３ The high-quality silicon carbide substrate according to claim 9, wherein the difference in resistivity within the facets is 0.62 to 0.86 mΩ·cm.

11. The high-quality silicon carbide substrate according to claim 8, characterized in that the difference in light transmittance is 0.5% to 1.6%.

12. The aforementioned N-type element doping is N ２ The high-quality silicon carbide substrate according to claim 8, characterized in that it is doped, the difference in resistivity within the facets is 0.62 to 0.86 mΩ·cm, and the difference in light transmittance is 0.5% to 1.6%.

13. The TDV of the silicon carbide substrate is 200 cm². －２ A high-quality silicon carbide substrate according to claim 8, characterized in that it is smaller than the specified size.

14. The TDV of the silicon carbide substrate is 100 cm². －２ A high-quality silicon carbide substrate according to claim 13, characterized in that it is smaller than [a certain size].

15. The high-quality silicon carbide substrate according to claim 7, characterized in that the size of the silicon carbide substrate is 6 inches, 8 inches, 10 inches, or 12 inches.

16. It is a semiconductor device, A semiconductor device characterized by comprising a high-quality silicon carbide substrate as described in claim 7.

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