Floating gate biosensor

Abstract

Embodiments relating to a field-effect transistor (FET) device are disclosed. The FET device includes a semiconductor channel. In addition, the FET device includes a first gate dielectric in contact with the semiconductor channel. Furthermore, the FET device includes a metal-insulator-metal (MIM) structure. The MIM structure includes a liner containing a first metal, an insulator, and a second metal. The first metal is in contact with the first gate dielectric. In addition, the insulator is in contact with the first metal and the second metal. Furthermore, the FET device includes a floating gate. The floating gate includes a first metal and an extension. In addition, the extension is located on one side of the MIM structure and includes a surface for sensing a sample in contact with that surface.

Description

Technical Field

[0001] The present disclosure relates to biosensors, and more particularly to floating gate biosensors.

Background Art

[0002] A biosensor can be an electrical device that detects a particular situation based on the concentration or presence of an analyte in a medium. Analytes can include ions, proteins, deoxyribonucleic acid (DNA), and the like. For example, a biosensor can measure the concentration of sodium ions in human sweat to determine whether a person is dehydrated.

Summary of the Invention

[0003] Embodiments related to field effect transistor (FET) devices are disclosed. The FET device includes a semiconductor channel. In addition, the FET device includes a first gate dielectric in contact with the semiconductor channel. Further, the FET device includes a metal-insulator-metal (MIM) structure. The MIM structure includes a liner including a first metal, an insulator, and a second metal. The first metal is in contact with the first gate dielectric. In addition, the insulator is in contact with the first metal and the second metal. Further, the FET device includes a floating gate. The floating gate includes a first metal and an extension. In addition, the extension is disposed on one side of the MIM structure and includes a surface for detecting a sample that is a surface and contacts the surface.

[0004] Embodiments relating to a field-effect transistor (FET) device are disclosed. The FET device includes a semiconductor channel. In addition, the FET device includes a first gate dielectric in contact with the semiconductor channel. Furthermore, the FET device includes a metal-insulator-metal (MIM) structure. The MIM structure includes a liner containing a first metal, an insulator, and a second metal. The first metal is in contact with the first gate dielectric. In addition, the insulator is in contact with the first metal and the second metal. Furthermore, the FET device includes a floating gate. The floating gate includes a first metal and an extension. In addition, the extension is located on one side of the MIM structure and includes a surface for sensing a sample in contact with that surface. Furthermore, the FET device comprises an additional layer covering the sensing surface. The additional layer includes a material selected from the group consisting of conductive materials and insulating materials.

[0005] Embodiments relating to a field-effect transistor (FET) device are disclosed. The FET device includes a semiconductor channel. In addition, the FET device includes a first gate dielectric in contact with the semiconductor channel. Furthermore, the FET device includes a metal-insulator-metal (MIM) structure. The MIM structure includes a liner containing a first metal, an insulator, and a second metal. The first metal is in contact with the first gate dielectric. In addition, the insulator is in contact with the first metal and the second metal. Furthermore, the FET device includes a floating gate. The floating gate includes a first metal and an extension. In addition, the extension is located on one side of the MIM structure and includes a surface for sensing a sample in contact with that surface. Furthermore, the FET device comprises a well having sensing surfaces on its sides and bottom. The well is configured to contain a sample.

[0006] Embodiments relating to a field-effect transistor (FET) device are disclosed. The FET device includes a semiconductor channel. In addition, the FET device includes a first gate dielectric in contact with the semiconductor channel. Furthermore, the FET device includes a metal-insulator-metal (MIM) structure. The MIM structure includes a liner containing a first metal, an insulator, and a second metal. The first metal is in contact with the first gate dielectric. In addition, the insulator is in contact with the first metal and the second metal. Furthermore, the FET device includes a floating gate. The floating gate includes a first metal and an extension. In addition, the extension is located on one side of the MIM structure and includes a surface for sensing a sample in contact with that surface. Furthermore, the FET device comprises a well having a sensing surface at its bottom. The well is configured to contain a sample. In addition, the FET device comprises an additional layer covering the sensing surface.

[0007] Embodiments of a method for manufacturing an FET device are disclosed. The method includes the step of forming a replacement gate by depositing a metal-insulator-metal structure in a recessed gate space. In addition, the method includes the step of recessing a spacer surrounding the replacement gate. Furthermore, the method includes the step of filling the recessed space with a first metal. In addition, the method includes the step of selectively recessing the filled recessed space. Furthermore, the method includes the step of filling the selectively recessed space with spacer material. In addition, the method includes the step of forming a mask covering the spacer, the replacement gate, and the interlayer dielectric (ILD) surrounding the spacer. Furthermore, the method includes the step of recessing the ILD. In addition, the method includes the step of forming a gate sensing surface by filling the recessed ILD space with a first metal. [Brief explanation of the drawing]

[0008] [Figure 1A] These are cross-sectional views of exemplary floating gate biosensor devices and test solutions according to some embodiments of the present disclosure.

[0009] [Figure 1B] These are cross-sectional views of exemplary floating gate biosensor devices and test solutions according to some embodiments of the present disclosure.

[0010] [Figure 1C] These are cross-sectional views of exemplary floating gate biosensor devices and test solutions according to some embodiments of the present disclosure.

[0011] [Figure 2] This figure shows a manufacturing process for an exemplary floating gate biosensor device according to one or more embodiments of the present disclosure.

[0012] [Figure 3] This figure shows a manufacturing process for an exemplary floating gate biosensor device according to one or more embodiments of the present disclosure.

[0013] [Figure 4] This figure shows a manufacturing process for an exemplary floating gate biosensor device according to one or more embodiments of the present disclosure.

[0014] [Figure 5] This figure shows a manufacturing process for an exemplary floating gate biosensor device according to one or more embodiments of the present disclosure.

[0015] [Figure 6] This figure shows a manufacturing process for an exemplary floating gate biosensor device according to one or more embodiments of the present disclosure.

[0016] [Figure 7] This figure shows a manufacturing process for an exemplary floating gate biosensor device according to one or more embodiments of the present disclosure.

[0017] [Figure 8] A diagram showing the manufacturing process of an exemplary floating gate biosensor device according to one or more embodiments of the present disclosure.

[0018] [Figure 9] A diagram showing the manufacturing process of an exemplary floating gate biosensor device according to one or more embodiments of the present disclosure.

[0019] [Figure 10] A diagram showing the manufacturing process of an exemplary floating gate biosensor device according to one or more embodiments of the present disclosure.

[0020] [Figure 11] A diagram showing the manufacturing process of an exemplary floating gate biosensor device according to one or more embodiments of the present disclosure.

[0021] [Figure 12] A diagram showing the manufacturing process of an exemplary floating gate biosensor device according to one or more embodiments of the present disclosure.

[0022] [Figure 13] A diagram showing the manufacturing process of an exemplary floating gate biosensor device according to one or more embodiments of the present disclosure.

[0023] [Figure 14] A process flowchart of a method for manufacturing a floating gate biosensor device according to some embodiments of the present disclosure.

[0024] While this disclosure is accommodating various modifications and alternative forms, the specific content of this disclosure is illustrated by examples in the drawings and will be described in detail thereafter. However, it should be understood that the intention is not to limit this disclosure to the embodiments described. On the contrary, it is intended to encompass all modifications, equivalents, and alternatives that fall within the spirit and scope of this disclosure. [Modes for carrying out the invention]

[0025] As mentioned earlier, biosensors can measure analytes in solution. While field-effect transistors (FETs) can be useful in biosensors, such biosensors may include a reference electrode, which can be difficult to fabricate on a silicon device containing the FET. More specifically, fabricating a silicon device with a reference electrode increases manufacturing costs and the footprint of the biosensor. In addition, the reference electrode is immersed in solution when not in use, which may make silicon devices unsuitable for wearable applications.

[0026] Accordingly, some embodiments of the present disclosure may provide silicon biosensor devices equipped with a FET that does not include a reference electrode. Furthermore, the removal of the reference electrode reduces the footprint, design complexity, and cost of producing the biosensor. In this way, such embodiments may be useful as portable biosensors (for example, used in wearable applications).

[0027] For the sake of brevity, conventional techniques for the manufacture of semiconductor silicon devices may or may not be described in detail herein. Furthermore, various tasks and process steps described herein can be incorporated into more comprehensive procedures or processes that have additional steps or functionalities not described in detail herein. The various steps in the manufacture of semiconductor silicon devices are well known, and therefore, for the sake of brevity, many conventional steps will be mentioned only briefly herein or will be omitted entirely without providing details of the well known process.

[0028] Figure 1A is a cross-sectional view of an exemplary floating gate biosensor device 100A, a test medium 101, and a floating gate 106A-FG according to several embodiments of the present disclosure. The test medium 101 may include aqueous and non-aqueous solutions of the object of test; air; and solid culture media (e.g., soil, tissue); and similar. For example, aqueous solutions may include preservatives, water, and the target analyte to be detected. Further examples may include genetic material, sweat, blood, or any other medium containing an analyte suitable for biosensing.

[0029] An exemplary floating-gate biosensor device 100A includes an FET 102, a gate dielectric 104, a replacement gate 106, an oxide 108, and a floating gate 106A-FG. The FET 102 includes a silicon (Si) substrate 102-1, a source 102-S, a drain 102-D, and a semiconductor channel 102-C. The channel 102-C may include a nanosheet material that is conductive within the transistor in the "on" state or highly resistive within the transistor in the "off" state. For example, the channel 102-C may be silicon. Furthermore, the gate dielectric 104 may consist of a material such as silicon oxide (SiO2) or a bilayer of SiO2 and a high k material (e.g., k=7 or greater). Thus, the material for the gate dielectric 104 may differ based on the type of FET 102 (e.g., N-type or P-type). Furthermore, the conductivity of the semiconductor channel 102-C can be controlled by the gate dielectric 104.

[0030] The replacement gate 106 may have a structure comprising a floating gate 106A-FG, a gate dielectric 106-D, and a control gate 106-G. The floating gate 106A-FG may include a replacement gate liner 106-L and a sensing surface 106-X. The replacement gate liner 106-L may extend to the sensing surface 106-X. The gate dielectric 106-D may be similar to the gate dielectric 104 but have a different composition and / or different material. For example, the gate dielectric 106-D may be composed of hafnium oxide (HfO2). Furthermore, the control gate 106-G may be in contact with a bond pad (not shown). The bond pad provides an interconnect for applying a voltage to activate the exemplary floating gate biosensor 100. Thus, when the target analyte in the test medium 101 is bonded to the floating gate 106-FG, the surface potential changes. When the exemplary floating gate biosensor 100 is operated, the drain current flowing between the source 102-S and the drain 102-D is the detection signal. A change in the detection signal detects the target analyte bound to the detection surface 106-X that is in contact with the test solution.

[0031] Figure 1B is a cross-sectional view of an exemplary floating gate biosensor device 100B, a test medium 101, and a floating gate 106B-FG according to some embodiments of the present disclosure. The exemplary floating gate biosensor device 100B is similar to the exemplary floating gate biosensor device 100A. Furthermore, the floating gate 106B-FG is similar to the floating gate 106A-FG. However, the floating gate 106B-FG further includes an additional layer 116. The additional layer 116 is positioned above the sensing surface 106-X and may therefore be in contact with the test medium 101. According to some embodiments of the present disclosure, the additional layer may be conductive (e.g., platinum (Pt), Pt silicide, graphene, gold) or insulating (e.g., SiO2, HfO2, Al2O3) and vary based on the sensing application. With respect to the conductive additional layer, for example, thiol chemistry has been developed to functionalize the sensing surface of gold. Regarding additional insulating layers, for example, insulating layers may be useful for detecting proteins, nucleotide sequences, and viruses at very low concentrations.

[0032] Figure 1C shows an exemplary floating gate biosensor device 100C, a test medium 101, a cross-sectional view of the floating gate 106C-FG, and a top view of the sensing surface 106-W according to several embodiments of the present disclosure. The exemplary floating gate biosensor device 100C is similar to the exemplary floating gate biosensor device 100A. Furthermore, the floating gate 106C-FG is similar to the floating gate 106A-FG. However, the floating gate 106C-FG may include a replacement gate liner 106-L and a sensing surface 106-W. The sensing surface 106-W may be a three-dimensional (3D) structure forming a well that holds the test medium 101. Thus, such embodiments can increase the amount of sensing surface without increasing the footprint of the exemplary floating gate biosensor device 100C. As shown, in the top view, the sensing surface 106-W may include an additional layer (not shown) covering the sensing surface 106-W along the bottom and sides of the well, similar to the additional layer 116 described with respect to Figure 1B.

[0033] Furthermore, some embodiments of the present disclosure provide methods for manufacturing biosensors such as exemplary floating gate biosensor devices 100A, 100B, and 100C. Such embodiments may manufacture the exemplary floating gate biosensor 100 on a silicon-on-insulator (SOI) wafer or a bulk wafer.

[0034] Figure 2 is a cross-sectional view of an exemplary floating-gate biosensor 200 after an initial manufacturing step, according to several embodiments of the present disclosure. In this manufacturing step, the exemplary floating-gate biosensor 200 includes a silicon device 202, a gate dielectric 204, a spacer 206, an interlayer dielectric (ILD) 208, and a gate stack 210. The ILD 208 is formed by a deposition process, followed by a planarization process that exposes the gate stack 210. The spacer 206 may be formed from a dielectric material such as silicon nitride, SiBCN, SiNC, SiN, SiCO, SiNOC, or a combination thereof. The gate stack 210 may consist of a work function setting metal (e.g., TiN) and a low resistivity metal (e.g., W or Al) and may be formed by a substitution metal gate process. The silicon device 202 includes a silicon (Si) substrate 2, a shallow trench isolation (STI) 4, a source 6-S, a drain 6-D, and a silicide 8. STI4 can isolate neighboring devices from each other. Silicide 8 can provide contact to source 6-S and drain 6-D. Note that while the figure illustrates a planar device, the manufacturing method is also applicable to nanosheet and FinFET devices.

[0035] Figure 3 is a cross-sectional view of an exemplary floating-gate biosensor 200 shown after an exemplary manufacturing process according to some embodiments of the present disclosure. In the illustrated manufacturing step, the gate stack 210 is recessed. Recessing involves removing the gate dielectric 204 and a portion of the gate stack 210.

[0036] Figure 4 is a cross-sectional view of an exemplary floating-gate biosensor 200 shown after an exemplary manufacturing process according to several embodiments of the present disclosure. In the illustrated manufacturing step, a metal-insulating metal (MIM) structure is deposited in a recessed gate space (e.g., a space created by recessing a gate dielectric 204 and a gate stack 210). The MIM structure includes a control gate 212, a dielectric 214, and a replacement gate liner 216-L, similar to the replacement gate 106 described with respect to Figure 1A. The control gate 212 is similar to the control gate 106-G. In addition, the dielectric 214 is similar to the dielectric 106-D. Furthermore, the replacement gate liner 216-L is similar to the replacement gate liner 106-L. According to several embodiments of the present disclosure, two metals (e.g., the metal of the control gate 212 and the metal of the replacement gate liner 216-L) can be selectively etched. Furthermore, the replacement gate liner 216-L may be thicker than the dielectric 214. In some embodiments, the replacement gate liner 216-L may be less than 5 nanometers thick, and the dielectric 214 may be less than 1 nanometer thick.

[0037] Figure 5 is a cross-sectional view of an exemplary floating gate biosensor 200 shown after an exemplary manufacturing process according to several embodiments of the present disclosure. In the illustrated manufacturing step, a chemical-mechanical planarization (CMP) process is performed on the structure. Performing the CMP process reduces the size of the gate stack 210 and further exposes the spacer 206.

[0038] Figure 6 is a cross-sectional view of an exemplary floating gate biosensor 200 shown after an exemplary manufacturing step according to some embodiments of the present disclosure. In the illustrated manufacturing step, the spacer 206 is recessed. Recessing may include reactive ion etching and / or wet etching of the spacer 206.

[0039] Figure 7 is a cross-sectional view of an exemplary floating gate biosensor 200 shown after an exemplary manufacturing process according to several embodiments of the present disclosure. In the illustrated manufacturing step, a metal filler is provided in the space created by recessing the spacer 206. The metal may have the same composition as the replacement gate liner 216-L and thus form part of the replacement gate liner 216-L.

[0040] Figure 8 is a cross-sectional view of an exemplary floating-gate biosensor 200 shown after an exemplary manufacturing step according to several embodiments of the present disclosure. In the illustrated manufacturing step, the replacement gate liner 216-L is selectively recessed. Selective recessing of the replacement gate liner 216-L may involve a chemical etching process that affects the replacement gate liner 216-L but does not affect the dielectric 214 and the control gate 212.

[0041] Figure 9 is a cross-sectional view of an exemplary floating gate biosensor 200 shown after an exemplary manufacturing process according to some embodiments of the present disclosure. In the illustrated manufacturing step, the recessed liner space is filled with spacer material. Filling this space with spacer material may include a deposition process and a subsequent CMP process.

[0042] Figure 10 is a cross-sectional view of an exemplary floating gate biosensor 200 shown after an exemplary manufacturing process according to some embodiments of the present disclosure. In the illustrated manufacturing step, the mask 218 is deposited and patterned on the structure, and the ILD 208 is recessed to form a recessed ILD space.

[0043] Figure 11 is a cross-sectional view of an exemplary floating gate biosensor 200 shown after an exemplary manufacturing step according to several embodiments of the present disclosure. In the illustrated manufacturing step, a sensing surface is formed. Forming the sensing surface may include removing the mask 218, filling the recessed ILD space with metal, and performing a CMP process on the structure. The metal may have the same composition as the replacement gate liner 216-L and form the sensing surface 216-X of the floating gate 216. According to several embodiments of the present disclosure, the sensing surface 216-X is thicker than the thickness of the replacement gate liner 216-L. In this way, the sensing surface 216-X may have reduced resistance. Furthermore, in the illustrated manufacturing step, the exemplary floating gate biosensor 200 is similar to the exemplary floating gate biosensor device 100A described with respect to Figure 1A.

[0044] Figure 12 is a cross-sectional view of an exemplary floating-gate biosensor 200 shown after an exemplary manufacturing process according to several embodiments of the present disclosure. In the illustrated manufacturing step, the floating-gate surface is coated with a sensing surface 220. The sensing surface 220 is similar to the additional layer 116 described with respect to Figure 1B. As previously stated, the sensing surface 220 may be conductive or insulating. Furthermore, in the illustrated manufacturing step, the exemplary floating-gate biosensor 200 is similar to the exemplary floating-gate biosensor device 100B described with respect to Figure 1B.

[0045] Figure 13 is a cross-sectional view of an exemplary floating-gate biosensor 200 shown after an exemplary manufacturing step according to several embodiments of the present disclosure. In the illustrated manufacturing step, a sensing reservoir may be formed. Forming the sensing reservoir may include depositing additional ILD 208 onto the structure and recessing a portion of the ILD to form the sensing reservoir and expose the sensing surface 220. Furthermore, in the illustrated manufacturing step, the exemplary floating-gate biosensor 200 is similar to the exemplary floating-gate biosensor device 100C described with respect to Figure 1C.

[0046] Figure 14 is a process flowchart of Method 300 for manufacturing a floating gate biosensor device according to some embodiments of the present disclosure. The manufacturing steps shown in Method 300 are illustrated and described above with reference to one or more of Figures 2 to 13 of the drawings. Method 300 illustrated herein is illustrative. Many variations of the diagrams or steps described may exist without departing from the spirit of the embodiments. For example, the steps may be performed in a different order, or the steps may be added, deleted, or modified.

[0047] In block 302, method 300 may begin by forming a replacement gate by depositing a metal-insulator-metal structure in a recessed gate space. As previously described, the MIM structure is similar to the replacement gate 106 described with respect to Figure 1A and includes a control gate 212, a dielectric 214, and a titanium nitride (TiN) liner 216-L described with respect to Figures 2 to 13. According to some embodiments of the present disclosure, the two metals (e.g., the control gate 212 and the replacement gate liner 216-L) can be selectively etched. Furthermore, the replacement gate liner 216-L may be thicker than the dielectric 214.

[0048] In block 304, method 300 proceeds to recess a spacer surrounding the replacement gate. As previously stated, recessing involves removing a portion of the gate dielectric 204 and the gate stack 210.

[0049] In block 306, method 300 proceeds to fill the recessed space with a first metal. Filling the recessed space involves filling the space created by recessing the spacer 206 with metal. The metal may have the same composition as the replacement gate liner 216-L and thus form part of the replacement gate liner 216-L.

[0050] In block 308, method 300 proceeds to selectively recess the filled recessed space. Selective recessing of the replacement gate liner 216-L may involve a chemical etching process that affects the replacement gate liner 216-L but does not affect the dielectric 214 and the control gate 212.

[0051] In block 310, method 300 proceeds to fill a selectively recessed space with spacer material. Filling this space with spacer material may include a deposition process and a subsequent CMP process.

[0052] In block 312, method 300 proceeds to form a spacer, a replacement gate, and a mask (e.g., mask 218) covering the ILD surrounding the spacer. The mask 218 is deposited and patterned on the structure so that the ILD 208 is recessed.

[0053] In block 314, method 300 proceeds to recess the ILD. Recessing the ILD includes removing a portion of the ILD 208.

[0054] In block 316, method 300 proceeds to form a gate sensing surface. Forming the sensing surface may include removing the mask 218, filling the recessed ILD space with a first metal, and performing a CMP process on the structure. According to some embodiments of the present disclosure, the sensing surface 216-X is thicker than the thickness of the replacement gate liner 216-L. In this way, the sensing surface 216-X can reduce resistance. Furthermore, in the illustrated manufacturing steps, the exemplary floating gate biosensor 200 is similar to the exemplary floating gate biosensor device 100A described with respect to Figure 1A.

[0055] The descriptions of various embodiments of the present invention are presented for illustrative purposes only and are not intended to be exhaustive or limit the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used herein have been selected to best describe the principles of the embodiments, their practical applications or technical improvements to the technology available on the market, or to enable other those skilled in the art to understand the embodiments disclosed herein.

Claims

1. Field-effect transistor (FET) with a semiconductor channel; A first gate dielectric in contact with the semiconductor channel; A liner comprising a first metal, wherein the first metal is in contact with the first gate dielectric; An insulator in contact with the first metal; and The second metal in contact with the insulator A metal-insulator-metal (MIM) structure having; and A floating gate having the first metal and an extension, wherein the extension is located on one side of the MIM structure, and the extension includes a surface for detecting a sample in contact with the surface. FET devices, including those mentioned above.

2. The FET device according to claim 1, further comprising an additional layer covering the sensing surface.

3. The FET device according to claim 2, wherein the additional layer has a conductive material.

4. The FET device according to claim 2, wherein the additional layer has an insulating material.

5. The FET device according to claim 1, further comprising a well having the sensing surface on the side and bottom of the well, wherein the well is configured to contain the sample.

6. The FET device according to claim 1, wherein the FET has a nanosheet device.

7. The FET device according to claim 1, wherein the FET has a planar type device.

8. The FET device according to claim 1, wherein the FET has a FinFET device.

9. The FET device according to claim 1, wherein the FET device comprises a silicon-on-insulator device.

10. The FET device according to claim 1, wherein the semiconductor channel includes a silicon channel.

11. Field-effect transistor (FET) with a semiconductor channel; A first gate dielectric in contact with the semiconductor channel; A liner comprising a first metal, wherein the first metal is in contact with the first gate dielectric; An insulator in contact with the first metal; and The second metal in contact with the insulator A metal-insulator-metal (MIM) structure having; A floating gate having the first metal and extension, wherein the extension is located on one side of the MIM structure, wherein the extension includes a surface for detecting a sample in contact with the surface; and An additional layer covering the sensing surface, wherein the additional layer is made of a material selected from the group consisting of conductive materials and insulating materials. FET devices, including those mentioned above.

12. The FET device according to claim 11, further comprising a well having the detection surface on the side and bottom of the well, wherein the well is configured to contain the sample.

13. The FET device according to claim 11, wherein the FET has a nanosheet device.

14. The FET device according to claim 11, wherein the FET has a planar type device.

15. The FET device according to claim 11, wherein the FET has a FinFET device.

16. The FET device according to claim 11, wherein the FET device comprises a silicon-on-insulator device.

17. The FET device according to claim 11, wherein the semiconductor channel includes a silicon channel.

18. Field-effect transistor (FET) with a semiconductor channel; A first gate dielectric in contact with the semiconductor channel; A liner comprising a first metal, wherein the first metal is in contact with the first gate dielectric; An insulator in contact with the first metal; and The second metal in contact with the insulator A metal-insulator-metal (MIM) structure having; A floating gate having the first metal and extension, wherein the extension is located on one side of the MIM structure, wherein the extension includes a surface for detecting a sample in contact with the surface; and A well having the sensing surface on its sides and bottom, wherein the well is configured to contain the sample. FET devices, including those mentioned above.

19. The FET device according to claim 18, further comprising an additional layer covering the sensing surface, wherein the additional layer is made of a material selected from the group consisting of conductive materials and insulating materials.

20. The FET device according to claim 18, wherein the semiconductor channel includes a silicon channel.

21. Field-effect transistor (FET) with a semiconductor channel; A first gate dielectric in contact with the semiconductor channel; A liner comprising a first metal, wherein the first metal is in contact with the first gate dielectric; An insulator in contact with the first metal; and The second metal in contact with the insulator A metal-insulator-metal (MIM) structure having; A floating gate having the first metal and an extension, wherein the extension is located on one side of the MIM structure, and the extension includes a surface for detecting a sample in contact with the surface; A well having the detection surface at its bottom, wherein the well is configured to contain the sample; and an additional layer covering the detection surface An FET device equipped with the following features.

22. The step of forming a replacement gate by depositing a metal-insulator-metal structure within a recessed gate space; The step of creating a recess for the spacer surrounding the replacement gate; A step of filling the recessed space with the first metal; A step of selectively creating recesses in the aforementioned filled recessed space; A step of filling the selectively recessed space with spacer material; A step of forming a mask that covers the spacer, the replacement gate, and the interlayer dielectric (ILD) surrounding the spacer; The step of creating a recess in the ILD; and The step of forming a gate detection surface by filling the recessed ILD space with the first metal. A method for manufacturing FET devices, including [the specified element].

23. The method according to claim 22, further comprising the step of coating the gate detection surface with an additional layer of material.

24. The method according to claim 23, wherein the material of the additional layer includes a conductive material.

25. The method according to claim 23, wherein the material of the additional layer includes an insulating material.

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