Piezoelectric on-insulator (POI) substrate and process for manufacturing piezoelectric on-insulator (POI) substrate

Abstract

The present invention relates to a piezoelectric on-insulator (POI) substrate (130) comprising a carrier substrate (100), a trap layer (102) on the free surface (104) of the carrier substrate (100), a piezoelectric layer (114), particularly a lithium tantalate (LTO) or lithium niobate (LNO) piezoelectric layer (114), and an intermediate structure (120) sandwiched between the piezoelectric layer (114) and the trap layer (102) of the carrier substrate (100), wherein the intermediate structure (120) contains at least one tantalum nitride (TaN) or silicon carbonitride (SiO2) material that prevents the diffusion of metallic elements. x N y The invention also relates to a process for manufacturing piezoelectric on-insulator (POI) substrates.

Description

Technical Field

[0001] The present invention relates to a piezoelectric-on-insulator (POI) substrate and a process for manufacturing such a piezoelectric-on-insulator (POI) substrate.

Background Art

[0002] Piezoelectric-on-insulator (POI) substrates are used in acoustic wave devices such as sensors and filters to achieve good performance due to better values of quality factor Q and electromechanical coefficient k compared to other substrates in the prior art.

[0003] Such a substrate includes a thin layer of piezoelectric material on a dielectric layer, and the dielectric layer is itself disposed on a carrier substrate. In certain applications, a trap layer is placed between the carrier substrate and the dielectric layer. The trap layer is typically an amorphous layer having structural defects such as dislocations, grain boundaries, amorphous regions, voids, inclusions, and / or pores. These structural defects function as traps for charges that can circulate within the material. Thus, the trap layer has a high resistivity, resulting in a reduction of charge conduction within the layer and, consequently, a reduction of the current within the trap layer. The trap layer reduces losses due to parasitic conduction effects at the interface between the carrier substrate and the dielectric layer. In fact, the trap layer serves to reduce the lifetime of charges in this region.

[0004] When manufacturing such a piezoelectric-on-insulator (POI) substrate, a donor substrate to which a piezoelectric material substrate is bonded to a handling substrate is used. Next, the donor substrate undergoes a thinning step of the piezoelectric substrate to form a thinner piezoelectric layer before being bonded to the carrier substrate. Finally, the transfer of the piezoelectric thin film onto the carrier substrate is mechanically or thermally transferred to the carrier substrate at a pre-formed fracture zone in the piezoelectric layer of the donor substrate. The final heat treatment of the resulting substrate (POI) is required to repair the damage incurred in the piezoelectric layer transferred during the fracture step.

[0005] However, this final annealing process leads to the diffusion of metallic elements from the piezoelectric layer to the trap layer. When metallic elements (Li, Fe, Cu, Ni) diffuse into the trap layer, they neutralize (occupy) the electrical traps present in the trap layer. This neutralization of electrical traps in the trap layer degrades the electrical performance of the trap layer, particularly its Q factor and radio frequency performance, and consequently, the electrical performance of the POI substrate manufactured in this manner is also reduced.

[0006] Therefore, one objective of the present invention is to improve upon the aforementioned drawbacks, and in particular to design a piezoelectric on-insulator (POI) substrate having improved characteristics for use in acoustic devices.

[0007] The object of the present invention is realized by a piezoelectric on-insulator (POI) substrate comprising: a carrier substrate, which is particularly a silicon-based substrate, and includes a trap layer on the free surface of the carrier substrate, particularly a polycrystalline, amorphous, or porous silicon-based layer; a piezoelectric layer, particularly a lithium tantalate (LiTaO3) or lithium niobate (LiNbO3) layer; and an intermediate structure sandwiched between the piezoelectric layer and the trap layer of the carrier substrate, which includes at least one diffusion barrier layer for metallic elements, particularly lithium, of a tantalum nitride (TaN) or silicon carbonitride (SiCN) system.

[0008] The presence of a metal element diffusion barrier structure between the piezoelectric layer and the trap layer reduces the diffusion of metal elements from the piezoelectric layer to the trap layer during the manufacturing process. In this way, the neutralization of charge traps in the trap layer by metal elements is reduced. Therefore, the trap layer in the final point of interest (POI) has high resistivity, resulting in a substrate (POI) with improved performance.

[0009] According to a modified embodiment of the present invention, the barrier layer can have a thickness tu greater than a predetermined thickness, wherein the dose of metal elements in the trap layer is less than the threshold dose of metal elements that causes deterioration of the trap layer, particularly 10 12 at / cm 2 Less than, especially 5 x 10 11 at / cm 2 The threshold thickness of the barrier layer is determined as a function of the thickness of the trap layer and the threshold dose of metal elements present in the trap layer, such that the trap layer still possesses electrical properties that enable the acquisition of an improved POI substrate.

[0010] According to a modified version of the present invention, the barrier layer can have a thickness of 5 nm to 150 nm, particularly 10 nm to 100 nm, and the trap layer has a thickness of 50 nm to 5 μm. The barrier layer is much thinner than the trap layer.

[0011] According to one modified embodiment of the present invention, the intermediate structure is in contact with at least one barrier layer, particularly silicon dioxide or silicon nitride (SiN) or silicon oxynitride (SiO2). x N y It may include at least one dielectric layer of the ) system. The dielectric layer ensures good adhesion between the piezoelectric material and the carrier substrate in the POI substrate.

[0012] In one embodiment, the barrier layer may be sandwiched between two dielectric layers.

[0013] According to one variant of the present invention, the intermediate structure may additionally include a second barrier layer. The second barrier layer provides improved electrical properties to the substrate (POI) and therefore better performance for SAW applications. In fact, the second barrier layer may be a second diffusion barrier layer for blocking the same metallic elements as the first diffusion barrier layer from the piezoelectric layer to the trap layer, or the second barrier layer may be a diffusion barrier layer for blocking different metallic elements in the composite substrate than the first barrier layer.

[0014] According to a variant of the present invention, the second barrier layer may be, in particular, a silicon nitride (SiN) or aluminum nitride (AlN) or silicon oxynitride (SiO x N y ) - based hydrogen diffusion barrier layer. In a piezoelectric - on - insulator (POI) substrate, hydrogen diffusion into the piezoelectric layer and / or trap layer that occurs during the heat treatment step in the process for manufacturing such a substrate also degrades the performance of the piezoelectric - on - insulator (POI) substrate. In this way, the presence of the hydrogen barrier layer reduces hydrogen diffusion inside the piezoelectric - on - insulator (POI) substrate during the manufacture of the substrate (POI), resulting in a POI substrate with improved performance.

[0015] According to a variant of the present invention, the intermediate layer can include at least one layer having a hydrogen concentration of less than 10 20 at / cm 3 and, in particular, less than 10 18 at / cm 3 . A layer having a hydrogen concentration of less than 10 20 at / cm 3 corresponds to a hydrogen diffusion barrier layer. As a result, the POI substrate has improved performance due to the presence of such a layer in its structure.

[0016] The object of the present invention is also to provide a carrier substrate, in particular a silicon - based substrate, comprising a trap layer, in particular a polycrystalline or amorphous or porous silicon - based layer, and to provide a substrate comprising a piezoelectric layer, in particular lithium tantalate (LiTaO3) or lithium niobate (LiNbO3), and to form an intermediate structure on and / or on the substrate comprising the piezoelectric layer and on the carrier substrate, the formation of the intermediate structure comprising the formation of at least one metal - element barrier layer of tantalum nitride (TaN) or silicon carbonitride (SiCN) - based, in particular blocking lithium, and to bond the substrate comprising the piezoelectric layer to the carrier substrate, which is also achieved by the aforementioned process for manufacturing a piezoelectric - on - insulator (POI) substrate.

[0017] Therefore, the step of forming an intermediate structure on a substrate containing a piezoelectric layer and / or on a carrier substrate in the process according to the present invention makes it possible to form a metal element diffusion barrier layer in order to reduce the diffusion of metal elements from the piezoelectric layer to the trap layer during the heat treatment step of the process. This process makes it possible to obtain a substrate that effectively reduces the adverse effects of metal elements diffusing into the carrier substrate, particularly into the trap layer of the carrier substrate.

[0018] According to one variant of the present invention, the step of forming an intermediate structure may additionally include the formation of a second barrier layer. The second barrier layer may be a barrier layer of a metallic element, or a barrier layer of another element in the structure, particularly a non-metallic element. By using this process, a substrate can be obtained that more effectively reduces the adverse effects of elemental diffusion to the carrier substrate by reducing both the diffusion of metallic elements from the piezoelectric layer and the diffusion of other elements into the structure of the POI substrate.

[0019] According to one modified embodiment of the present invention, the step of forming an intermediate structure is 10 20 at / cm 3 Less than, especially 10 18 at / cm 3 The step may further include forming a layer having a hydrogen concentration of less than 1.5%. Forming a layer with reduced hydrogen concentration restricts hydrogen diffusion into the structure during subsequent heat treatment, which is known to promote hydrogen diffusion into the piezoelectric layer and / or trap layer.

[0020] According to one modified embodiment of the present invention, the step of forming a second barrier layer is to use silicon nitride (SiN), aluminum nitride (AIN), or silicon oxynitride (SiO2). x N y This may include the formation of a layer of the material system. Such a layer of material system provides a barrier that blocks hydrogen diffusion toward the piezoelectric layer and / or trapping layer.

[0021] According to a modified embodiment of the present invention, the process may further include a step of forming a dielectric layer on a carrier substrate and / or on a substrate containing a piezoelectric layer prior to the bonding step, such that the bonding interface is an oxide-oxide bonding interface. The assembled interface between the carrier substrate and the substrate containing the piezoelectric layer is fabricated at the interface between the two dielectric layers using an oxide-oxide type bond, in particular a Si-O-Si type bond, which is a type of bond known to be stable. In this way, the piezoelectric-on-insulator substrate obtained by the process according to the present invention has a stable bond between the piezoelectric layer and the carrier substrate.

[0022] According to one variant of the present invention, the manufacturing process may further include, prior to the assembly step, forming a dielectric layer of a first material on a carrier substrate and / or a dielectric layer of a second material different from the first material on a substrate including a piezoelectric layer. For example, the first material may be silicon nitride, particularly of the Si3N4 type, and the second material may be silicon oxynitride (SiO2). x N y ), especially those of the SiON system. Therefore, the bonding interface is Si3N4-SiO x N y It is a bonding interface. Such an interface offers advantages in terms of the acoustic impedance of the fabricated structure and is also a stable assembly interface. [Brief explanation of the drawing]

[0023] The present invention and its advantages are described in more detail below with reference to preferred embodiments, particularly the following appended drawings, where reference numerals highlight the features of the invention.

[0024] [Figure 1] A schematic diagram illustrates the process for manufacturing a piezoelectric on-insulator (POI) substrate according to a first embodiment of the present invention. [Figure 2a] A schematic diagram of the process for manufacturing a piezoelectric on-insulator (POI) substrate according to a second embodiment of the present invention is shown. [Figure 2b]A schematic diagram shows a process for manufacturing a donor substrate according to the first modified form of the second embodiment of the present invention, and a donor substrate. [Figure 2c] A schematic diagram illustrates the process for manufacturing a piezoelectric on-insulator (POI) substrate according to a second modification of the second embodiment of the present invention. [Figure 3] A schematic diagram illustrates the process for manufacturing a piezoelectric on-insulator (POI) substrate according to a third embodiment of the present invention.

[0025] The present invention will be described in more detail with reference to the drawings, using advantageous embodiments in an exemplary manner. It should be noted that the embodiments described are merely possible configurations, and the individual features described above may be provided independently of each other or may be omitted entirely when carrying out the invention.

[0026] Figure 1 schematically shows the process for manufacturing a piezoelectric on-insulator (POI) substrate according to a first embodiment of the present invention.

[0027] The process for manufacturing piezoelectric on-insulator (POI) substrates begins with step I) providing a carrier substrate 100, in particular a bulk substrate. The bulk substrate is typically a single-material substrate with a thickness of 200 μm to 1 mm.

[0028] The carrier substrate 100 may be silicon, sapphire, aluminum nitride (AIN), silicon carbide (SiC), or gallium arsenide (GaAs) based. The carrier substrate 100 may be a crystalline substrate or a polycrystalline substrate.

[0029] The carrier substrate 100 includes a trap layer 102 deposited on the free surface 104 of the carrier substrate by a deposition method such as sub-atmospheric pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PCVD). The deposition temperature is 200°C to 1100°C. The trap layer 102 is a silicon-based layer, for example, polycrystalline silicon, amorphous silicon, or porous silicon. The thickness of the trap layer 102 is t. p The size is 5 nm to 5 μm.

[0030] The trap layer 102 has structural defects such as dislocations, grain boundaries, amorphous regions, gaps, inclusions, and / or pores. These structural defects form traps for charges that are likely to circulate within the material, for example, in incomplete chemical bonds or pendant chemical bonds. Therefore, the trap layer 102 has high resistivity, resulting in reduced charge conduction within the layer, and consequently, a decrease in current within the trap layer.

[0031] In step II) of the process according to the first embodiment, a substrate comprising a piezoelectric layer 106 is provided. Preferably, this is a thick layer of piezoelectric material 108 with a thickness ti provided on a base substrate 110.

[0032] The piezoelectric material 106 may be a lithium-rich piezoelectric material, such as lithium tantalate (LiTaO3) or lithium niobate (LiNbO3).

[0033] A substrate having a piezoelectric layer 106 may first undergo one or more steps of cleaning, brushing, or polishing the free surface of the piezoelectric layer 106 in order to remove particles or dust and thus obtain a cleaner and higher quality free surface for subsequent deposition of a continuous layer.

[0034] According to the present invention, step III) is performed, in which an intermediate structure 120 is deposited on the free surface 102a of the trap layer 102 of the carrier substrate 100, preferably directly on the free surface 102a.

[0035] Step III), which involves forming the intermediate structure 120, includes forming at least one metal element diffusion barrier layer 122. The barrier layer 122 may be a lithium diffusion barrier layer 122.

[0036] According to the present invention, the barrier layer 122 may be a tantalum nitride (TaN)-based layer deposited by atomic layer deposition (ALD) or plasma-enhanced atomic layer deposition (PE-ALD). In this case, the ALD deposition temperature is 25°C to 100°C.

[0037] Alternatively, the barrier layer 122 may be a silicon carbonitride (SiCN) layer deposited by plasma chemical vapor deposition (PECVD). In this case, the deposition temperature is approximately 400°C.

[0038] The barrier layer 122 has a thickness t greater than a predetermined thickness. EM The trap layer 102 has a predetermined thickness such that the dose of metal elements in the trap layer 102 is less than the threshold dose of metal elements that causes deterioration of the trap layer 102. p It is defined as a function of .

[0039] To calculate the threshold dose of a metal element, a person skilled in the art can calculate the diffusion gradient of the metal element from its diffusion coefficient, and thus ensure that the predetermined threshold dose of the metal element does not exceed the thickness t of the barrier layer 122. EM You will be able to figure out how to adjust it. This calculation also depends on the heat treatment applied to the structure during the manufacturing process, as well as the thickness of the trap layer 102.

[0040] For example, in the case of a layer of lithium tantalate (LiTaO3) or lithium niobate (LiNbO3), and with a thickness of 1 μm t p In the case of a trap layer 102 having a , the threshold dose of lithium in the trap layer 102 is 10 12 at / cm 2 It must be less than 0.5 μm thick. p In the case of the trap layer 102 having the following, the threshold dose of lithium is 5 × 10 11 at / cm 2 It will be to that extent.

[0041] To obtain these values, the thickness t of the barrier layer 122 is required. EM It must be between 5nm and 150nm, especially between 10nm and 100nm.

[0042] In step IIa), a brittle zone 112 is formed within the piezoelectric layer 108 of the substrate containing the piezoelectric layer 106, so as to define the piezoelectric layer 114 that is moved away from the remaining portion 116 of the piezoelectric layer 108 of the substrate containing the piezoelectric layer 106.

[0043] Step IIa) for forming the embrittlement zone 112 is performed by implanting atomic or ionic species into the piezoelectric layer 108 of the substrate containing the piezoelectric layer 106. The atomic or ionic implantation is performed such that the embrittlement zone 112 is located inside the piezoelectric layer 108 and the piezoelectric layer 116 is separated from the rest of the piezoelectric layer 108 114. The atomic or ionic species are implanted to a specific depth t3 of the piezoelectric layer 108, which determines the thickness t3 of the piezoelectric layer 114 to be moved. The thickness t3 is typically 50 nm to 1 μm, and particularly around 600 nm. The implantation dose of the atomic or ionic species is 10 16 at / cm 2 ~10 17 at / cm 2 That is the case.

[0044] Next, the carrier substrate 100 obtained after step III) is assembled with the donor substrate 110 obtained after step IIa) during assembly step IV) to obtain a heterostructure 124 corresponding to the carrier substrate / donor substrate assembly. Here, the assembly is bonded by molecular adhesion.

[0045] The substrate containing the piezoelectric layer 106 is assembled on the carrier substrate 100 such that the barrier layer 122 of the intermediate structure 120 is sandwiched between the piezoelectric layer 114 of the substrate containing the piezoelectric layer 106 and the trap layer 102 of the carrier substrate 100. The contact interface 126 is located between the piezoelectric layer 114 and the barrier layer 122 of the carrier substrate 100.

[0046] Next, step V) is performed to move the piezoelectric thin film 114. To do this, the donor substrate 124 is fractured in the embrittlement zone 112 by supplying thermal energy through a heat treatment at 100°C to 300°C in an Ar or N2 atmosphere and / or mechanically, in order to obtain a POI substrate containing a piezoelectric layer 114 having a thickness t3 of typically 50 nm to 1 μm, particularly about 600 nm.

[0047] The piezoelectric-on-insulator (POI) substrate 122 obtained after step V) is heat-treated to repair any damage caused to the piezoelectric layer 114 that was moved during the fracture step. This heat treatment is carried out at a temperature of 400-600°C, particularly around 500°C, in an atmosphere of Ar, O2, or N2.

[0048] During the heat treatment of the POI substrate, metallic elements may diffuse from the piezoelectric layer 114 toward the trap layer 102.

[0049] Thanks to the presence of the barrier layer 122, the barrier layer 122 functions as a metal element diffusion barrier layer, thereby reducing the diffusion of metal elements from the piezoelectric layer 114 to the trap layer 102. In this way, the passivation of charge traps in the trap layer 102 by metal elements from the piezoelectric layer 114 is reduced, and the trap layer 102 retains its ability to reduce parasitic currents.

[0050] In a modified version of the process according to the first embodiment, the intermediate structure 120, in this case the metallic element diffusion barrier layer 122, is formed on the piezoelectric layer 108 of the substrate containing the piezoelectric layer 106, instead of on the carrier substrate 100. In this case, the step of forming the barrier layer 122 is performed before or after the step of forming the embrittlement zone 112 in the piezoelectric layer 108. Then, the assembly interface between the carrier substrate 100 and the substrate containing the piezoelectric layer 106 is fabricated at the interface located between the barrier layer 122 of the substrate containing the piezoelectric layer 106 and the trapping layer 102 of the carrier substrate 100.

[0051] In another variation of the process according to the first embodiment, an intermediate structure 120, in this case a metallic element diffusion barrier layer 122, can be provided on the substrate containing the piezoelectric layer 106 and on the carrier substrate 100. In this case, the step of forming the barrier layer 122 is performed before or after the step of forming the embrittlement zone 112 in the piezoelectric layer 108. Then, an assembly interface between the carrier substrate 100 and the substrate containing the piezoelectric layer 106 is created at the interface between the two barrier layers. Assembling the substrate containing the piezoelectric layer on the carrier substrate by assembling the two barrier layers is advantageous for assembly because it is performed between two layers of the same material.

[0052] In one variant of this process, instead of performing step IIa) to form an embrittlement zone in the piezoelectric layer 108 of the substrate containing the piezoelectric layer 106, a direct assembly step IV) is performed between the substrate containing the piezoelectric layer 106 and the carrier substrate 100 after step III). Then, a thinning step IVa) (not shown) is performed to reduce the thickness of the substrate containing the piezoelectric layer 106. This thinning step may involve grinding the substrate containing the piezoelectric layer 106 to obtain a piezoelectric layer 114 having a thinner thickness than the piezoelectric layer 108.

[0053] Furthermore, in order to improve the quality of the free surface 128 of the piezoelectric layer 114, further processing of the free surface 128 of the piezoelectric layer 114 can be performed.

[0054] The piezoelectric on-insulator (POI) substrate 130, shown in step V) of Figure 1, which is obtained by having a carrier substrate 100, a trap layer 102, a metal element diffusion barrier layer 122, and a piezoelectric layer 114, also corresponds to the substrate according to the present invention according to the first embodiment.

[0055] Figure 2a schematically shows a process for manufacturing a piezoelectric on-insulator (POI) substrate according to a second embodiment of the present invention.

[0056] In this second embodiment, the only difference from the process according to the first embodiment is that step III) of forming the intermediate structure 120 additionally includes step Ilia) of forming a dielectric layer 132 on at least one barrier layer 122, in particular in direct contact with at least one barrier layer 122. Thus, the intermediate structure 120 includes a metallic element diffusion barrier layer 122 and a dielectric layer 132.

[0057] The other steps I) to V) are the same as in the first embodiment, except that in step IV) the dielectric layer 132 is bonded to the substrate containing the piezoelectric layer 106. All features common to the first embodiment and its variations, and using the same reference numerals as above, will not be described again, but refer to their detailed descriptions above.

[0058] The dielectric layer 132 is, for example, a silicon oxide-based layer. However, the dielectric layer 132 may be a silicon nitride (Si3N4) layer, or a combination of silicon nitride and oxide (SiO2 x N y A layer containing ) or a layer of silicon oxide, and a combination of silicon nitride and oxide (SiO x N y This may involve superimposing a layer of silicon dioxide, or superimposing a layer of silicon nitride.

[0059] The dielectric layer 132 is produced by a film deposition method such as CVD, LPCVD (chemical vapor deposition), PECVD (plasma-enhanced chemical vapor deposition), or PVD (physical vapor deposition), or by oxidation heat treatment. PVD deposition includes a deposition temperature range of room temperature to 400°C, while the PECVD method includes a deposition temperature range of 150°C to 400°C. LPCVD deposition includes a deposition temperature range of 600°C to 700°C. The dielectric layer 132 is deposited on the barrier layer 122, particularly in direct contact with the barrier layer 122.

[0060] A heat treatment, also known as densification, can be performed after the deposition of the dielectric layer 132 to degas excess hydrogen formed during deposition that occupies the traps within the trap layer 102. In addition to this, or instead, a surface treatment can be performed to improve the surface quality of the deposited dielectric layer 132.

[0061] The dielectric layer 132 is, for example, a silicon dioxide-based layer. However, the dielectric layer 132 is a combination of silicon nitride and oxide (SiO2). x N y A layer containing ) or a silicon oxide layer, and a combination of silicon nitride and oxide (SiO x N y ) superimposed with, or a layer of silicon nitride (Si3N4), or a combination of silicon nitride and oxide (SiO2 x N y ) may be a layer containing, or a layer of silicon oxide and a layer of silicon nitride superimposed on each other.

[0062] Therefore, in assembly step V), the substrate including the piezoelectric layer 106 is assembled with the carrier substrate 100 by bringing the dielectric layer 132 into direct contact with the piezoelectric layer 108 of the substrate including the piezoelectric layer 106 in order to form the heterostructure 134. Thus, in this second embodiment, the assembly interface 136 is located between the piezoelectric layer 108 and the dielectric layer 132 of the carrier substrate 100.

[0063] In one embodiment, the dielectric layer 132 is 10 20 at / cm 3 Less than, especially 10 18 at / cm 3 The layer may have a hydrogen concentration of less than 1000°C. Depending on the deposition method used, typically the dielectric layer 132 can be deposited at a temperature of room temperature to 1000°C, after which densification annealing can be performed to reduce the hydrogen concentration within the dielectric layer 132. For example, if the dielectric layer is produced by PVD deposition, the temperature is room temperature to 400°C; for PECVD deposition, it is between 150°C and 400°C; for LPCVD deposition, it is between 600°C and 700°C; and for thermal oxidation, the temperature is between 800°C and 1000°C.

[0064] This annealing is performed in a hydrogen-deficient atmosphere (i.e., less than 5 ppm) and exposes the silicon oxide-based dielectric layer 132 to a temperature higher than its deposition temperature. This can be a neutral or oxidizing atmosphere. Preferably, this temperature is higher than 800°C and typically falls within the range of 800°C to 1000°C. The annealing step is continued for at least one hour, preferably several hours, to allow hydrogen to eventually diffuse outward from the dielectric layer 132 and optionally from the trap layer 102. After this densification annealing, the dielectric layer 132 is 10 20 at / cm 3 It has a hydrogen concentration of less than [amount missing].

[0065] In one embodiment, the dielectric layer 132 can be provided on the piezoelectric layer 108 of a substrate containing the piezoelectric layer 106, instead of on the carrier substrate 100. In this case, the step of forming the dielectric layer 132 is performed before or after the step of forming the embrittlement zone 112 in the piezoelectric layer 108. In this case, the assembly of the carrier substrate 100 and the substrate containing the piezoelectric layer 106 is performed at the interface between the dielectric layer 132 of the piezoelectric substrate 106 and the barrier structure 120 of the carrier substrate 100.

[0066] In another variant, the dielectric layer can be provided on both the substrate containing the piezoelectric layer 106 and the carrier substrate 100. In this case, the step of forming the dielectric layer is performed before or after the step of forming the embrittlement zone 112 in the piezoelectric layer 108. Then, the assembly of the carrier substrate 100 and the substrate containing the piezoelectric layer 106 takes place at the interface between the two dielectric layers. For example, this assembly is performed using oxide-oxide bonds, particularly Si-O-Si bonds that enable stable intermolecular force bonding.

[0067] In another embodiment, the dielectric layer of the first material can be provided on a substrate including a piezoelectric layer 106, and the dielectric layer of the second material can be provided on a carrier substrate 100, and the first material is different from the second material. For example, the dielectric layer provided on the substrate including the piezoelectric layer 106 is a Si3N4 layer, while the dielectric layer provided on the carrier substrate 100 is SiO x N y , in particular, a SiON layer. Therefore, the assembly of the carrier substrate 100 and the substrate including the piezoelectric layer 106 is performed using two dielectric layers Si3N4-SiO x N y This process takes place at the interface between the two components, enabling a stable bond.

[0068] In one embodiment, the dielectric layer 132 and barrier layer 122 of the intermediate structure 120 can be provided on the piezoelectric layer 108 of a substrate including layer 106, instead of the carrier substrate 100. In this case, the step of forming the intermediate structure 120 is performed before or after the step of forming the embrittlement zone 112 in the piezoelectric layer 108. In this case, the assembly of the carrier substrate 100 and the substrate including the piezoelectric layer 106 is performed at the interface between the dielectric layer 132 of the intermediate structure 120 on the substrate including the piezoelectric layer 106 and the trap layer 102 of the carrier substrate 100.

[0069] The piezoelectric on-insulator (POI) substrate 138 shown in step V) of Figure 2a, which is obtained by having a carrier substrate 100, a trap layer 102, a metal element diffusion barrier layer 122, a dielectric layer 132, and a piezoelectric layer 114, also corresponds to the substrate according to the present invention according to the second embodiment.

[0070] In one modified form shown in Figure 2b, step IIIa) for forming the dielectric layer 132' is performed before step III) for forming at least one barrier layer 122'. The dielectric layer 132' and the barrier layer 122' are fabricated in the same manner as the dielectric layer 132 and barrier layer 122 described above in Figure 2a. Thus, the intermediate structure 120' includes the dielectric layer 132' and the metallic element diffusion barrier layer 122'.

[0071] Therefore, in assembly step IV), the substrate including the piezoelectric layer 106 is assembled with the carrier substrate 100 by bringing the barrier layer 122' into contact with the piezoelectric substrate 106 in order to form the heterostructure 140. Thus, in this modified form, the assembly takes place at the interface 142 between the piezoelectric layer 108 and the barrier layer 122' of the carrier substrate 100.

[0072] In one embodiment, the barrier layer 122' can be provided on the piezoelectric layer 108 of the substrate containing layer 106, instead of on the carrier substrate 100. In this case, the step of forming the barrier layer 122' is performed before or after the step of forming the embrittlement zone 112 in the piezoelectric layer 108. In this case, the assembly of the carrier substrate 100 and the substrate containing the piezoelectric layer 106 is performed at the interface between the barrier layer 122' on the substrate containing the piezoelectric layer 106 and the trap layer 132' of the carrier substrate 100.

[0073] In another variant, the barrier layer 122' can be provided on the substrate containing the piezoelectric layer 106 and on the carrier substrate 100. In this case, the step of forming the barrier layer 122' is performed before or after the step of forming the embrittlement zone 112 in the piezoelectric layer 108. Then, the assembly of the carrier substrate 100 and the substrate containing the piezoelectric layer 106 takes place at the interface between the two barrier layers 120'.

[0074] In another variant, the barrier layer 122 and dielectric layer 132' of the intermediate structure 120' can be provided on the piezoelectric layer 108 of the substrate containing layer 106, instead of on the carrier substrate 100. In this case, the step of forming the intermediate structure 120' is performed before or after the step of forming the embrittlement zone 112 in the piezoelectric layer 108. In this case, the assembly of the carrier substrate 100 and the substrate containing the piezoelectric layer 106 takes place at the interface between the barrier layer 122' of the intermediate structure 120' on the substrate containing the piezoelectric layer 106 and the trap layer 102 of the carrier substrate 100.

[0075] The piezoelectric on-insulator (POI) substrate 144 shown in step V) of Figure 2b comprises, in order of this variant of the second embodiment of the present invention, a carrier substrate 100, a trap layer 102, a dielectric layer 132', a metal element diffusion barrier layer 122', and a piezoelectric layer 114.

[0076] In the second modification of the second embodiment shown in Figure 2c, step IIIb) of forming the dielectric layer 146 is added compared to the embodiment shown in Figure 2b. In this step, the dielectric layer 146 is formed on the piezoelectric layer 108 of the substrate containing the piezoelectric layer 106, after step IIa) of forming the embrittlement zone 112 in the piezoelectric layer 108.

[0077] The dielectric layer 146 is, for example, a silicon oxide-based layer. However, the dielectric layer 146 may be a silicon nitride layer (Si3N4), or a combination of silicon nitride and an oxide (SiO2 x N y A layer containing ) or a layer of silicon oxide and a silicon nitride layer, or a silicon oxide layer and a silicon nitride layer and a silicon oxynitride layer (SiOx N y ) may be used in combination with other words.

[0078] The dielectric layer 146 is produced by a film deposition method such as CVD, LPCVD (chemical vapor deposition), PECVD (plasma chemical vapor deposition), or PVD (physical vapor deposition), or by oxidation heat treatment.

[0079] To improve the surface quality of the deposited dielectric layer 146, a surface treatment can be performed. Thus, in assembly step IV), the substrate containing the piezoelectric layer 106 is assembled with the carrier substrate 100 by bringing the barrier layer 122' into contact with the dielectric layer 146 to form a heterostructure 148. Thus, in this variant, the assembly takes place at the interface 150 between the dielectric layer 146 of the substrate containing the piezoelectric layer 106 and the barrier layer 122' of the carrier substrate 100. The barrier layer 122' is sandwiched between two dielectric layers 132' and 146.

[0080] Similar to the process variation according to the first embodiment, the dielectric layer 146 can be provided on the carrier substrate 100 on the barrier layer 122' instead of on the substrate containing the piezoelectric layer 106. In this case, the assembly between the carrier substrate 100 and the substrate containing the piezoelectric layer 106 takes place at the interface between the dielectric layer 146 of the carrier substrate 100 and the piezoelectric layer 108 of the substrate containing the piezoelectric layer 106.

[0081] Similar to other variations of the process according to the first embodiment, the dielectric layers can be provided on the piezoelectric substrate 106 and on the carrier substrate 100. The assembly of the carrier substrate 100 and the substrate containing the piezoelectric layer 106 is then carried out at the interface between the two dielectric layers of the same material using oxide-oxide type bonding, in particular Si-O-Si type bonding which enables stable molecular force bonding.

[0082] Similar to other variations, the dielectric layer of the first material can be provided on a substrate containing a piezoelectric layer 106, and the dielectric layer of the second material can be provided on a carrier substrate 100, and the first material is different from the second material. For example, the dielectric layer provided on a substrate containing a piezoelectric layer 106 is a Si3N4 layer, while the dielectric layer provided on a carrier substrate 100 is SiO x N y , in particular, a SiON layer. Therefore, the assembly of the carrier substrate 100 and the substrate including the piezoelectric layer 106 is performed using two dielectric layers Si3N4-SiO x N y This process takes place at the interface between the two components, enabling a stable bond.

[0083] Similar to other variations of the second embodiment, one or more layers of the intermediate structure 120' can be provided on the piezoelectric substrate 106 instead of on the carrier substrate 100.

[0084] The piezoelectric on-insulator (POI) substrate 152 shown in step V), comprising a carrier substrate 100, a trap layer 102, a dielectric layer 132', a metal element diffusion barrier layer 122', a second dielectric layer 146, and a piezoelectric layer 114, corresponds to the substrate according to the present invention in this second variant of the second embodiment.

[0085] Figure 3 schematically shows a process for manufacturing a piezoelectric on-insulator (POI) substrate according to a third embodiment of the present invention.

[0086] In this third embodiment, step III) forming the intermediate structure 120 of the process shown in Figure 2a further includes step IIIc) forming a second barrier layer 154 after step IIIa).

[0087] All other steps I), II), IIa), III), IIIa), IV), and V) are the same as in the second embodiment shown in Figure 2a, except that in step IV), assembly takes place between the second barrier layer 154 and the piezoelectric substrate 106. All features common to the first or second embodiment and their variations, and using the same reference numerals as above, will not be described again, but refer to their detailed descriptions above.

[0088] Therefore, the intermediate structure 120 includes a first metal element diffusion barrier layer 122, a dielectric layer 132, and second barrier layers 154, 156, 158, and 160.

[0089] These second barrier layers 154, 156, 158, and 160 are formed on a dielectric layer 132 which is deposited on the first barrier layer 122. The first barrier layer 122 and the second barrier layers 154, 156, 158, and 160 are separated by the dielectric layer 132.

[0090] In assembly step IV), the second barrier layers 154, 156, 158, and 160 are brought into contact with the substrate containing the piezoelectric layer 106 at interface 162 so as to form the donor substrate 164.

[0091] The second barrier layer 154 may be a second metallic element diffusion barrier layer 156. In this case, the second barrier layer 156 is formed in the same manner as the first barrier layer 122. The second metallic element diffusion barrier layer 156 may have the same properties as the first barrier layer 122, such as thickness or material, or the first metallic element diffusion barrier layer 122 and the second barrier layer 156 may differ in material and / or thickness. For example, the first diffusion barrier layer 122 may be tantalum nitride (TaN) and the second diffusion barrier layer 156 may be a silicon carbonitride (SiCN) layer, or vice versa. The second diffusion barrier layer 156 may also be tantalum oxide (Ta2O5) or aluminum oxide (Al2O3).

[0092] In the first embodiment, the second barrier layer 154 may be a hydrogen diffusion barrier layer 158 for restricting hydrogen diffusion of the piezoelectric substrate 106 and / or carrier substrate 100 to the trap layer 102. The hydrogen diffusion barrier layer 158 is silicon nitride (SiN) or silicon oxynitride (SiO2). x N y ) or aluminum nitride (AIN) based materials may also be silicon nitride (SiN) or silicon oxynitride (SiO x N y This second barrier layer 158, which is made of ) or aluminum nitride (AIN), is formed to a thickness in the range of 10 nm to 100 nm by PECVD (plasma chemical vapor deposition), PVD (physical vapor deposition), or ALD (atomic layer deposition) deposition methods.

[0093] In fact, in POI substrates, another cause of degradation of the substrate's radio frequency and electrical performance is the diffusion of hydrogen into the piezoelectric layer and / or trapping layer during the POI substrate manufacturing process. Hydrogen can be introduced from various sources, for example, from interfaces during assembly due to the hydrophilicity of layers at interfaces such as silicon-based substrates 100, or from hydrogen-rich dielectric layers due to the manufacturing process.

[0094] During heat treatments such as film deposition or fracture steps performed during the manufacturing process at a temperature of approximately 500°C, hydrogen may diffuse into the trap layer 102, as well as the metallic elements in the piezoelectric layer 114, and neutralize the charge traps in the trap layer 102. Furthermore, hydrogen may also diffuse into the piezoelectric layer / substrate, and the presence of hydrogen can lower the Curie temperature and lead to local piezoelectric domain inversion. This local inversion phenomenon of ferroelectric domains affects the propagation of sound waves in ferroelectric materials.

[0095] In the second modified form, the hydrogen diffusion barrier layer 158 is a silicon oxide-based layer 160. In this second modified form, the second barrier layer 160 is 10 20 at / cm 3 Less than, especially 10 18 at / cm 3It has a hydrogen concentration of less than 10. This can be achieved by depositing silicon oxide using plasma deposition (PECVD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or oxidation heat treatment. PVD deposition involves deposition temperatures from room temperature to 400°C, while the PECVD method involves deposition temperatures from 150°C to 400°C. LPCVD deposition involves deposition temperatures from 600°C to 700°C. This deposition is typically performed at temperatures from 600°C to 800°C. In this case, the dielectric layer 160 is 10 20 at / cm 3 It has a high hydrogen concentration exceeding [a certain level].

[0096] To reduce the hydrogen concentration in this second silicon oxide barrier layer 160, densification annealing is applied. This annealing is performed in a hydrogen-deficient atmosphere (i.e., less than 5 ppm) and exposes the silicon oxide layer 160 to a temperature higher than its deposition temperature. This can be a neutral or oxidizing atmosphere. Preferably, this temperature is higher than 800°C and typically falls within the 800°C-900°C range. The annealing step is continued for at least one hour, preferably several hours, to allow hydrogen to diffuse outward from the dielectric layer 160 and optionally from the trap layer 102. After this densification annealing, the dielectric layer 160 is 10 20 at / cm 3 It has a hydrogen concentration of less than [amount missing].

[0097] This type of densification annealing can, in particular, lead to a reduction in the diffusivity of hydrogen, i.e., the ability of this species to diffuse into the material constituting the dielectric layer 160, and as a result, hydrogen can be reduced even if 10 20 at / cm 3 Even at higher concentrations, the likelihood of diffusion toward the trap layer 102 decreases. As a result, the trap layer 102 also becomes less likely, especially at 10 18 at / cm 3 It has a reduced hydrogen concentration of less than [amount missing].

[0098] In one embodiment, one or more layers of the intermediate structure 120, namely the dielectric layer 132, the barrier layer 122, and the second barrier layers 154, 156, 158, 160, can be provided on the piezoelectric substrate 106 instead of on the carrier substrate 100. In this variant, the layers are deposited such that the final POI substrate obtained after assembly and fracture has the same arrangement of layers as the POI 166 substrate obtained in the above embodiment, i.e., the same order of deposited layers.

[0099] In another variation of this embodiment of the present invention, the dielectric layer can be provided on both the substrate containing the piezoelectric layer 106 and the carrier substrate 100. The assembly interface between the carrier substrate 100 and the substrate containing the piezoelectric layer 106 is formed at the interface between the two dielectric layers using oxide-oxide type bonding, in particular Si-O-Si type bonding, which is a type of bonding known to be stable.

[0100] In another variation of this embodiment of the present invention, the dielectric layer of the first material can be provided on a substrate including a piezoelectric layer 106, and the dielectric layer of the second material can be provided on a carrier substrate 100, and the first material is different from the second material. For example, the dielectric layer provided on the substrate including the piezoelectric layer 106 is a Si3N4 layer, while the dielectric layer provided on the carrier substrate 100 is SiO x N y , in particular, a SiON layer. Therefore, the assembly of the carrier substrate 100 and the substrate including the piezoelectric layer 106 is performed using two dielectric layers Si3N4-SiO x N y This process takes place at the interface between the two components, enabling a stable bond.

[0101] The piezoelectric on-insulator (POI) substrate 166 shown in step V) of Figure 3, produced by the manufacturing process according to the present invention, comprises a carrier substrate 100, a trap layer 102, a first metal element diffusion barrier layer 122, a dielectric layer 132, a second barrier layer 154, and a piezoelectric layer 114, thereby forming the POI substrate 166 according to the third embodiment.

[0102] It should be noted that the embodiments described are merely possible configurations, and the individual features of different embodiments can be combined with each other or provided independently.

Claims

1. A piezoelectric on-insulator (POI) substrate, - A carrier substrate (100), which is particularly a silicon-based substrate, and which includes a trap layer (102), particularly a polycrystalline, amorphous, or porous silicon-based layer, on the free surface (104) of the carrier substrate (100), - Piezoelectric layer (114), particularly lithium tantalate (LTO) layer or lithium niobate (LNO) layer, - A piezoelectric on-insulator (POI) substrate comprising an intermediate structure (120, 120') sandwiched between the piezoelectric layer (114) and the trap layer (102) of the carrier substrate (100), the intermediate structure (120, 120') comprising, in particular, at least one metallic element diffusion barrier layer (122, 122') made of lithium, which is of the tantalum nitride (TaN) or silicon carbonitride (SiCN) type.

2. The barrier layer (122, 122') has a thickness t greater than a predetermined thickness. ＥＭ The predetermined thickness is such that the dose of metal elements in the trap layer (102), particularly the dose of lithium, is such that the threshold dose of lithium that causes degradation of the trap layer (102) is particularly 10 １２ at / cm ２ Less than, especially 5 x 10 １１ at / cm ２ The piezoelectric on-insulator (POI) substrate according to claim 1, wherein the thickness of the trap layer (102) is determined as a function of the lithium threshold dose amount, such that the lithium threshold dose amount is less than less than less.

3. The metal element diffusion barrier layer (122, 122') has a thickness t of 5 nm to 150 nm, particularly 10 nm to 100 nm. ＥＭ The trap layer (102) has the thickness t ｐ The piezoelectric on-insulator (POI) substrate according to claim 1 or 2, wherein the thickness is 50 nm to 5 μm.

4. The intermediate structure (120) is in contact with the at least one metal element diffusion barrier layer (122, 122'), in particular at least one dielectric layer (132, 132') of silicon dioxide or silicon nitride (SiN) or silicon oxynitride (SiO ｘ N ｙ ), a piezoelectric on insulator (POI) substrate according to any one of claims 1 to 3.

5. The piezoelectric on-insulator (POI) substrate according to any one of claims 1 to 4, wherein the metal element diffusion barrier layer (122') is sandwiched between two dielectric layers (132', 146).

6. The piezoelectric on-insulator (POI) substrate according to any one of claims 1 to 5, wherein the intermediate structure (120, 120') further comprises a second barrier layer (154, 156, 158, 160).

7. The aforementioned intermediate structure (120, 120') is 10 ２０ at / cm ３ Less than, especially 10 １８ at / cm ３ A piezoelectric on-insulator (POI) substrate according to any one of claims 1 to 6, comprising at least one layer (160) having a hydrogen concentration of less than 1.

8. The second barrier layer (154, 158, 160) is particularly made of silicon nitride (SiN) or silicon oxynitride (SiO ｘ N ｙ A piezoelectric on-insulator (POI) substrate according to claim 6 or claim 7 in combination with claim 6, wherein the hydrogen diffusion barrier layer (156) is made of aluminum nitride (AIN) or aluminum nitride (AIN).

9. A process for manufacturing a piezoelectric on-insulator (POI) substrate (130, 138, 144, 152, 166) according to any one of claims 1 to 8, - A step of providing a carrier substrate (100), particularly a silicon-based substrate, which includes a trap layer (102), particularly a polycrystalline, amorphous, or porous silicon-based layer, - The step of providing a substrate including a piezoelectric layer (106), particularly a piezoelectric layer (108) of lithium tantalate (LTO) or lithium niobate (LNO) type, - A step of forming an intermediate structure (120, 120') on a substrate including the piezoelectric layer (106) and / or on the carrier substrate (100), wherein the formation of the intermediate structure (120, 120') includes the formation of at least one diffusion barrier layer (122, 122') of tantalum nitride (TaN) or silicon carbonitride (SiCN) that blocks metallic elements, particularly lithium, A process comprising the step of assembling the substrate including the piezoelectric layer (106) with the carrier substrate (100).

10. A process for manufacturing a piezoelectric on-insulator (POI) substrate (152, 166) according to claim 9, wherein the step of forming the intermediate structure (120, 120') further comprises forming a second barrier layer (154, 156, 158, 160).

11. The step of forming the intermediate structure (120, 120') is 10 ２０ at / cm ３ Less than, especially 10 １８ at / cm ３ A process for manufacturing a piezoelectric on-insulator (POI) substrate (152, 166) according to claim 9 or 10, further comprising the step of forming a layer (160) having a hydrogen concentration of less than 1.

12. The step of forming the second barrier layer (154) is performed using silicon nitride (SiN) or silicon oxynitride (SiO ｘ N ｙ A process for manufacturing a piezoelectric on-insulator (POI) substrate (152, 166) according to claim 10 or claim 11 in combination with claim 10, comprising forming a layer (158) of aluminum nitride (AIN) or aluminum nitride (AIN).

13. A process for manufacturing a piezoelectric on-insulator (POI) substrate (130, 138, 144, 152, 166) according to any one of claims 9 to 12, further comprising the step of forming dielectric layers (132, 146) on the carrier substrate (100) and / or on the substrate including the piezoelectric layer (106) prior to the assembly step, such that the assembly interface is an oxide-oxide assembly interface.

14. A process for manufacturing a piezoelectric on-insulator (POI) substrate (130, 138, 144, 152, 160) according to any one of claims 9 to 12, further comprising the step of forming a dielectric layer (132, 146) of a second material different from the first material on the carrier substrate (100) and / or on the substrate including the piezoelectric layer (106), prior to the assembly step.

15. The first material is silicon nitride, particularly Si ３ N ４ The system is such that the second material is silicon oxynitride (SiO ｘ N ｙ A process for manufacturing the piezoelectric on-insulator (POI) substrate (130, 138, 144, 152, 160) according to claim 14, particularly of the SiON type.

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