Process for forming silicon carbide layers

Abstract

The present invention relates to a process for forming a silicon carbide layer (20) on a silicon substrate, wherein the process is as follows: The steps include placing the silicon-based substrate (10) in the furnace, The steps include introducing a flow of a carbon-containing gas mixture into the furnace, Temperature (T) for forming the silicon carbide layer (20) F The step of raising the temperature to ) and forming a silicon carbide layer (20) on the base substrate (10) and a carbon layer (30) on the silicon carbide layer (20) by the reaction of propane with silicon, The steps of removing the carbon layer (30) and Includes.

Description

[Technical Field]

[0001] The present invention relates to a manufacturing process for semiconductor-on-insulator substrates or piezoelectric-on-insulator substrates for high-frequency applications. [Background technology]

[0002] Radiofrequency (RF) devices that process signals with frequencies between approximately 10 MHz and 300 GHz are particularly applicable to the telecommunications field.

[0003] Such a device can be formed from an insulator-based semiconductor substrate or an insulator-based piezoelectric substrate, and comprises, in order, a base substrate, a charge trapping layer (called a trap-rich layer), a dielectric layer disposed on the trap-rich layer, and a semiconductor active layer or piezoelectric active layer disposed on the dielectric layer. Active and / or passive components are formed in and / or on the active layer.

[0004] A trap-rich layer prevents the conductive surface from being exposed beneath the electrical insulating layer, thus preventing a decrease in the resistivity of the base substrate. Such a layer further eliminates substrate charge carriers that could generate harmonics, which tend to interfere with signals propagating within high-frequency devices and degrade signal quality.

[0005] The trap-rich layer may be made of silicon carbide (SiC). The formation of such a layer is typically carried out by epitaxy to the base substrate to obtain the crystalline quality necessary for effective harmonic suppression in the RF component. This step is followed by chemical-mechanical polishing (CMP) to obtain a uniform thickness and a sufficiently flat surface of the silicon carbide layer.

[0006] Epitaxial deposition of a sufficiently thick SiC layer is time-consuming and therefore expensive. In addition, an epitaxy chamber can only accommodate one or a few substrates.

[0007] Furthermore, during the epitaxy process, the base substrate is heated through the back surface. With this technique, precise control of the front surface temperature is impossible. This can lead to the loss of the deposited silicon carbide layer if the front surface temperature becomes excessively high. [Disclosure of the Invention]

[0008] One objective of the present invention is to design a process for manufacturing a SiC layer on a silicon substrate, particularly a process for forming substrates for high-frequency applications that is faster and less expensive than known processes.

[0009] For this purpose, the present invention proposes a process for forming a silicon carbide layer (20) on a silicon substrate, the process being, in order, The steps include placing the silicon-based substrate in the furnace, The steps include introducing a flow of a carbon-containing gas mixture into the furnace, The steps include raising the temperature to a level suitable for forming a silicon carbide layer, and forming a silicon carbide layer on the base substrate and a carbon layer on the silicon carbide layer by the reaction of propane with silicon, The steps of removing each carbon layer and Includes.

[0010] The carbon-containing gas is preferably propane or acetylene.

[0011] The carrier gas is preferably argon or a mixture of argon and hydrogen.

[0012] The optimal temperature for forming the silicon carbide layer is between 750°C and 1100°C.

[0013] The temperature for removing the carbon layer is typically between 600 °C and 950 °C.

[0014] The silicon substrate preferably has an electrical resistivity exceeding 500 ohm·cm.

[0015] The thickness of the silicon carbide layer is advantageously between 2 and 5 nm.

[0016] This process further includes, before the step of introducing a propane stream, heating the furnace to the decomposition temperature of native silicon oxide, removing the native silicon oxide layer from the base substrate by thermal decomposition of the oxide, and cooling the furnace to the temperature for introducing the propane stream. It is advantageous to further include.

[0017] It is advantageous to arrange a plurality of vertically stacked base substrates in the furnace, create a vertical space between two adjacent base substrates, and simultaneously form a silicon carbide layer and a carbon layer on the respective surfaces of the base substrates.

[0018] The formation of the silicon carbide layer and the removal of the carbon layer are preferably carried out in the same furnace.

[0019] In certain embodiments, the removal of the carbon layer is carried out by introducing an oxygen stream into the furnace and reacting the carbon layer with the oxygen stream.

[0020] In other embodiments, the removal of the carbon layer is carried out by an oxygen plasma etching process.

[0021] The present invention also relates to a process for manufacturing a semiconductor-on-insulator substrate or a piezoelectric-on-insulator substrate for high-frequency applications, the process comprising forming a silicon carbide layer on the silicon substrate described above to form a carrier substrate, Forming a weakened zone by implanting atomic species into a donor substrate made of a semiconductor material or a piezoelectric material; Bonding the donor substrate to the front surface of a carrier substrate, the bonding step including disposing a dielectric layer between a silicon carbide layer and the donor substrate; Peeling the donor substrate along the weakened zone and transferring a layer of semiconductor material or piezoelectric material to the carrier substrate; and including.

[0022] Other features and advantages of the present invention will become apparent from the following detailed description when taken in conjunction with the accompanying drawings below.

Brief Description of the Drawings

[0023] [Figure 1A] Schematic view of a base substrate prior to the process according to the present invention. [Figure 1B] Schematic view of a base substrate prior to the process according to the present invention. [Figure 2] Schematic view of a base substrate including a silicon carbide layer and a carbon layer. [Figure 3] Schematic view of a base substrate including a silicon carbide trap-rich layer. [Figure 4] Temperature profile used in the process according to the present invention. [Figure 5A] Diagram showing steps of manufacturing a semiconductor-on-insulator substrate or a piezoelectric-on-insulator substrate. [Figure 5B] Diagram showing steps of manufacturing a semiconductor-on-insulator substrate or a piezoelectric-on-insulator substrate. [Figure 5C] Diagram showing steps of manufacturing a semiconductor-on-insulator substrate or a piezoelectric-on-insulator substrate. [Figure 5D] Diagram showing steps of manufacturing a semiconductor-on-insulator substrate or a piezoelectric-on-insulator substrate. [Figure 6] Diagram showing an annealing furnace suitable for forming a silicon carbide layer on a base substrate and a carbon layer on the silicon carbide layer according to a preferred embodiment of the present invention. Detailed description of the embodiment

[0024] Formation of silicon carbide layer Figure 1A shows a silicon-based substrate 10 intended for the manufacture of a semiconductor substrate on an insulator or a piezoelectric substrate on an insulator. The electrical resistivity of such a base substrate is advantageous if it exceeds 500 ohms·cm. The base substrate has a back surface 110 and a front surface 130. Typically, in the initial state of the base substrate, a native silicon oxide layer 13 is present on the surface of the base substrate.

[0025] To pre-treat the front surface for subsequent steps, the native silicon oxide layer is first removed. This step is typically performed in an inert atmosphere in an furnace at a temperature between 950°C and 1150°C, preferably close to 1100°C. At the end of this step, the substrate has a silicon front surface 120, referring to Figure 1B.

[0026] Next, a silicon carbide layer 20 is formed on the front surface 120 of the base substrate. The silicon carbide layer is formed in a furnace, which will be described later. It is advantageous to perform the removal of the native oxide layer in the same furnace to avoid a transfer step that would lead to a loss of time and energy for subsequent cooling and heating, as well as the need for additional labor.

[0027] The silicon carbide layer is formed in the gas phase; that is, carbon is present in the furnace in the form of a carbon-containing gas, such as propane (C3H8) gas or acetylene (C2H4) gas. The carbon-containing gas is mixed with a carrier gas, such as argon or a mixture of argon and hydrogen.

[0028] The substrate is heated in a furnace to a temperature suitable for forming a silicon carbide layer. The gaseous phase of carbon is converted to silicon carbide by reacting with silicon on the surface of the substrate. The reaction is self-limiting; that is, the carbonization reaction stops when all the silicon on the front surface of the base substrate is consumed. No additional silicon supply is provided. The final thickness of the silicon carbide layer 20 is between 2 and 5 nm. Referring to Figure 2, a carbon layer 30 is simultaneously formed on the silicon carbide layer 20. At the end of this step, the substrate has a carbon front surface 320.

[0029] Next, referring to Figure 3, the carbon layer is removed. This removal is preferably carried out by supplying oxygen to the front surface of the base substrate.

[0030] In certain embodiments, the removal of the carbon layer is carried out by introducing an oxygen stream into the furnace and reacting the carbon layer with the oxygen stream. In this case, it is advantageous that the removal of the oxygen layer is carried out in the same furnace as the deposition of the silicon carbide layer. This process is therefore performed in situ, and there is no need for a step of cooling in a separate chamber or a step of transferring to a separate chamber. Removal by oxygen stream in the same furnace makes it possible to obtain a surface 220 with sufficiently low roughness for subsequent steps of forming a semiconductor substrate on an insulator or a piezoelectric substrate on an insulator for high-frequency applications.

[0031] In other embodiments, the removal of the carbon layer is performed by an oxygen plasma etching process. While this removal is effective, it requires the step of transferring the substrate to another chamber. In addition, the plasma treatment may degrade the roughness of the front surface 220 of the base substrate, requiring subsequent processing to improve the surface quality.

[0032] Figure 4 shows an example of the temperature profile over time for the process of forming a silicon carbide layer on a silicon substrate in an annealing furnace. In this case, all steps from the removal of the native oxide layer to the removal of the carbon layer are performed in the same furnace.

[0033] The eight steps of the process can be distinguished.

[0034] The first step E1 begins at time t0. The base substrate with the native oxide layer is placed in the furnace at a temperature typically below 500°C. The substrate is placed in the furnace. The base substrate is placed in the furnace at a temperature T to remove the native oxide layer. O The temperature begins to rise to 5°C / min up to 900°C, then 2°C / min up to 1000°C, and 1°C / min up to 1100°C. At time t1, the temperature T is raised to remove native oxides. O It reaches.

[0035] Temperature T for removing native oxides O The temperature is between 1000°C and 1200°C, preferably closer to 1100°C. Typically, this temperature is maintained during step E2, which lasts about 20 minutes until t2. The duration of step E2 may vary depending on the thickness of the native oxide layer.

[0036] Next, during step E3, cooling is performed until the carbon-containing gas reaches a temperature T1 for introduction into the furnace at time t3. Cooling can be performed at a rate of, for example, 5°C / min, and the gas introduction temperature T1 is approximately 750°C.

[0037] After the introduction of the carbon-containing gas and carrier gas, the substrate is heated to a temperature T in step E4 to form a silicon carbide layer. F It is heated to a temperature T for forming the silicon carbide layer 30. F A temperature between 750°C and 1100°C is favorable. Nucleation of silicon carbide on the substrate surface begins during the temperature rise between t3 and t4 in step E4 and stops when the silicon on the base substrate surface is converted to silicon carbide. The SiC formation reaction stops when all the silicon is consumed during the temperature rise. Next, a carbon layer is formed in connection with the high-temperature decomposition of carbon-containing gas. Temperature T F The carbon-containing gas is maintained during step E5, under the flow of carrier gas, for approximately 10 minutes before being discharged from the furnace. Then, the temperature TF The silicon carbide layer is annealed to t5 for, for example, 2 hours as it is.

[0038] Next, cooling E6 is performed until the temperature T for removing the carbon layer R is reached. At time t6, the temperature T R is reached, and T R is between 600 °C and 950 °C. This temperature may be, by way of example and not limitation, about 800 °C. In the removal step E7, the removal temperature T R is maintained and oxygen O2 is introduced into the furnace. When introduced at, for example, 2 to 20 slm, the duration of the removal of the carbon layer is about 5 minutes until t7. Next, in the last step E8, the temperature is lowered to remove the substrate from the furnace.

[0039] Manufacture of a semiconductor-on-insulator substrate or a piezoelectric-on-insulator substrate A base substrate provided with a trap-rich layer made of silicon carbide can here be used for the manufacture of a semiconductor-on-insulator substrate or a piezoelectric-on-insulator substrate for high-frequency applications.

[0040] Here, a step of producing such a substrate will be described, which comprises a base substrate having a trap-rich layer produced according to the process described above, a semiconductor layer on the surface of the trap-rich layer, and an electrical insulating layer disposed at the interface between the trap-rich layer and the semiconductor surface layer.

[0041] Referring to FIG. 5A, in the first step, a semiconductor donor substrate or a piezoelectric donor substrate 500 is prepared, and the semiconductor layer or the piezoelectric layer is to be transferred from the donor substrate to the base substrate and the trap-rich layer. An electrical insulating layer 40 is formed on the surface of the donor substrate 500.

[0042] Referring to FIG. 5B, as schematically shown by the arrows, ion species implantation is performed through the electrical insulating layer 40 using, for example, hydrogen ions and / or helium ions to form a weakened zone 51 in the donor substrate 500. The weakened zone 51 defines the semiconductor layer or the piezoelectric layer 50 to be transferred.

[0043] Referring to Figure 5C, the donor substrate 500 injected in this manner is bonded to the trap-rich layer 20 on the base substrate 10 via the electrical insulating layer 40. The latter then becomes the embedded oxide layer 40.

[0044] Alternatively, the electrical insulating layer (40) may be formed on a trap-rich layer on a base substrate, and the donor substrate 50 having a weakened zone 51 can be bonded to a base substrate 10 having a trap-rich layer 20 and an electrical insulating layer 40.

[0045] Referring to Figure 5D, the donor substrate 500 is peeled along the weakening zone 51, resulting in the transfer of the semiconductor or piezoelectric layer 50 to the carrier substrate 100. The electrical insulating layer 40 is positioned between the trap-rich layer 20 and the semiconductor or piezoelectric layer 50. The transferred layer 50 can then be finished to correct any defects related to the injection and to flatten the free surface of the layer 50. This completes the semiconductor or piezoelectric structure on an insulator, which can then be used to manufacture components for high-frequency applications.

[0046] Furnace Overview To make the process of processing multiple substrates efficient and high-speed, it is preferable to use an annealing furnace that can process as many substrates as possible simultaneously under the same conditions. In the field of microelectronics, such a furnace is conventionally called a batch annealing furnace.

[0047] Figure 6 shows a suitable furnace for accommodating 120 to 150 substrates in the annealing chamber. The substrates 10 are arranged horizontally in the furnace and stacked vertically to process as many substrates as possible with the same high-temperature gas flow 73. Gaps are maintained between each substrate 10 and adjacent substrates 10 to optimize the gas flow and facilitate the formation of the silicon carbide layer.

[0048] Such furnaces employ a "top-flow" structure, meaning that the gas flow is delivered to the furnace through the top 71, passes through the furnace, and is then discharged through an outlet 79 at the bottom of the furnace. Typically, one gas flow carries the carrier gas, and a second gas flow supplies a carbon-containing gas such as propane or acetylene.

[0049] All components of the annealing chamber inside the furnace, excluding external parts such as the outer wall 76 and the end of the gas inlet pipe, namely the inner wall 75, the substrate holders that hold the substrates in a horizontally and vertically stacked position, and the gas contained within the annealing chamber, are at the same temperature during furnace operation. This means that the temperature difference between the upper end 74 of the furnace and the lower end 78 of the furnace is minimal, typically a few degrees Celsius, for example, less than 3 degrees Celsius for furnace temperatures between 800°C and 1200°C.

[0050] The substrate is heated primarily by conduction from the furnace walls. The gas flow is introduced at the same temperature as the inside of the furnace.

[0051] Such a furnace, arranged in a vertically stacked configuration, allows for the simultaneous processing of multiple substrates. Furthermore, the furnace enables the removal of the native oxide layer, the deposition of the silicon carbide layer, and the removal of the carbon layer to be performed in the same chamber, thereby avoiding the risk of contamination during transfer between two different chambers. Transfer steps between different chambers suitable for each step are avoided, thus avoiding the need for cooling between steps, the effort required for transfer, and consequently, the loss of time and efficiency.

Claims

1. A process for forming silicon carbide layers (20) on multiple silicon substrates, wherein the process is performed in order, The step involves placing multiple vertically stacked silicon base substrates (10) into a furnace, creating a vertical space between two adjacent base substrates (10), and the placement step. A step of introducing a flow of carbon-containing gas into the furnace, Temperature (T) for forming the silicon carbide layer (20) Ｆ The step of raising the temperature to ) and simultaneously forming a silicon carbide layer (20) on the surface of each base substrate (10) and a carbon layer (30) on each silicon carbide layer (20) by the reaction of the carbon-containing gas and the silicon, The steps of removing each carbon layer (30) and A process that includes this.

2. The process according to claim 1, wherein the carbon-containing gas is propane or acetylene.

3. The process according to claim 1 or 2, wherein the carbon-containing gas is mixed with argon or a mixture of argon and hydrogen.

4. The temperature (T) for forming the silicon carbide layer (20) Ｆ The process according to any one of claims 1 to 3, wherein the temperature is between 750°C and 1100°C.

5. Temperature (T) for removing the carbon layer Ｒ The process according to any one of claims 1 to 4, wherein the temperature is between 600°C and 950°C.

6. The process according to any one of claims 1 to 5, wherein the silicon substrate has an electrical resistivity of more than 500 ohms / cm.

7. The process according to any one of claims 1 to 6, wherein the thickness of the silicon carbide layer (20) is between 2 and 5 nm.

8. Before the step of taking in the carbon-containing gas stream, The furnace is set to a decomposition temperature (T) of native silicon oxide. Ｏ The step of heating until ) The steps include removing the native silicon oxide layer (13) from the base substrate (100) by thermal decomposition of the oxide, Temperature (T) required to take in the propane flow １ The steps include cooling the furnace down to the specified temperature. The process according to any one of claims 1 to 7, further comprising:

9. The process according to any one of claims 1 to 8, wherein the step of forming the silicon carbide layer (20) and the step of removing the carbon layer (30) are performed in the same furnace (70).

10. The process according to claim 9, wherein the step of removing the carbon layer (30) is performed by introducing an oxygen stream into the furnace and reacting the carbon layer with the oxygen stream.

11. The process according to any one of claims 1 to 9, wherein the step of removing the carbon layer (30) is performed by an oxygen plasma etching process.

12. A process for manufacturing a semiconductor substrate on an insulator or a piezoelectric substrate on an insulator for high-frequency applications, wherein the process comprises: The steps of forming a silicon carbide layer (20) on a silicon substrate according to any one of claims 1 to 11 to form a carrier substrate (100), The steps include forming a weakening zone (51) by injecting atomic species into a donor substrate (500) made of a semiconductor material or piezoelectric material, The step of bonding the donor substrate (500) to the front surface of the carrier substrate (100), wherein the dielectric layer (40) is placed between the silicon carbide layer (20) and the donor substrate (500), The steps include peeling off the donor substrate (500) along the weakened zone (51) and transferring the semiconductor material or piezoelectric material layer (50) to the carrier substrate (100), A process that includes this.

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