Integrated circuit (IC) package and related manufacturing method employing metal posts to thermally bond the die to an interposer substrate in order to dissipate the die's thermal energy.

Abstract

An integrated circuit (IC) package is disclosed that employs metal posts to thermally bond a die to an interposer substrate in order to dissipate the thermal energy of the die. In one embodiment, the IC package includes one or more metal posts thermally bonded to the die. The metal posts are attached to one or more metal interconnects (e.g., metal traces, metal pads, metal wires, metal plates) in the interposer substrate. In this way, when thermal energy is generated in the die, this thermal energy is dissipated into the interposer substrate via the metal posts and the bonded metal interconnects. Therefore, in order to provide heat dissipation to the die in the IC package, metal interconnects, which are features available in the interposer substrate manufacturing process, are deployed to form a base, on which metal posts are manufactured and thermally bonded to the die.

Description

Technical Field

[0001] Priority Application

[0001] This application claims priority to U.S. Patent Application No. 18 / 193,295, filed Mar. 30, 2023, entitled "INTEGRATED CIRCUIT (IC) PACKAGE EMPLOYING METAL POSTS THERMALLY COUPLING A DIE TO AN INTERPOSER SUBSTRATE FOR DISSIPATING THERMAL ENERGY OF THE DIE, AND RELATED FABRICATION METHODS", the entire disclosure of which is incorporated herein by reference.

Background Art

[0002] I. Field of the Disclosure

[0002] The field of the present disclosure relates to integrated circuit (IC) packages, and more particularly to the design and manufacture of IC packages that dissipate thermal energy from semiconductor die(s) within the IC package.

[0003] II. Background

[0003] Integrated circuits (ICs) are the basis of electronic devices. ICs are packaged in IC packages, also called “semiconductor packages” or “chip packages”. An IC package contains, as an IC, one or more semiconductor dies ("dies" or “dice") mounted on a package substrate to provide physical support and an electrical interface to dies(s) or dies(s). The package substrate includes one or more metallization layers containing metal interconnects (e.g., metal traces, metal wires), and vias connect metal interconnects together between adjacent metallization layers to provide an electrical interface between dies(s) or dies(s). The dies(s) or dies(s) are electrically interfaced to metal interconnects exposed in the upper or outer metallization layers of the package substrate to electrically couple the dies(s) or dies(s) to the metal interconnects of the package substrate. For example, the package substrate may include a multilayer or embedded trace substrate (ETS) layer electrically coupled adjacent to the die to provide a signal routing path to the die. Metal interconnects within the outer metallization layer of the package substrate are coupled to other metal interconnects within other lower metallization layers in the package substrate to provide a signal routing path to the coupled die.

[0004]

[0004] Some IC packages are known as “hybrid” IC packages, which include multiple die packages, each having a die for a different purpose or application. For example, a hybrid IC package may have an application die, such as a communication modem or a processor (including a system). A hybrid IC package may also include one or more memory dies to provide memory to support data storage and data access by the application die. Multiple dies may be arranged within a single die layer and adjacent to each other horizontally on the package substrate within the IC package. Multiple dies may also be provided within their own die packages, stacked on top of each other in a three-dimensional (3D) configuration as an overall 3DIC package. Dies within a die layer are typically housed in an epoxy molding compound (EMC) to protect the dies. 3DIC packages may be desirable to reduce the cross-sectional area of ​​the package. In a 3DIC package, a first lower die, directly supported on the package substrate, is electrically coupled to the metallization layer of the package substrate via die interconnects to provide signal routing paths for the dies within the package substrate. Other stacked dies within a 3DIC package that are not directly adjacent to the package substrate can be electrically coupled to the package substrate by wire bonds and / or intermediate interposers to provide die-to-die (D2D) connections between multiple stacked dies. In addition to protecting the dies, EMC provides some thermal dissipation of the heat energy generated by the first bottom die.

[0005]

[0005] Currently, the functionality and operating speed of dies within IC packages are increasing. As the functionality / speed of the die increases, the thermal energy generated within the die typically increases and may exceed the thermal dissipation capacity of the IC package. Increased functionality or speed of the die leads to the need to dissipate the thermal energy generated within the die. Efficient dissipation of thermal energy can be particularly important in 3DIC packages, which include multiple stacked dies, each of which generates heat. [Overview of the project]

[0006]

[0006] Embodiments disclosed in the detailed description include integrated circuit (IC) packages employing metal posts that thermally bond a semiconductor die ("die") to an interposer substrate to dissipate thermal energy within the die. Related manufacturing methods are also disclosed. The IC package includes a die layer containing a die bonded to a package substrate to provide signal routing paths to the die. For example, to facilitate the stacking of additional dies within the IC package as a three-dimensional (3D) IC (3DIC) package, the IC package also includes an interposer substrate adjacent to the die. The interposer substrate supports providing additional signal routing paths to the package substrate for external and / or die-to-die (D2D) connections. In exemplary embodiments, the IC package also includes one or more metal posts thermally bonded to the die and one or more metal interconnects in the interposer substrate (e.g., metal traces, metal pads, metal wires, metal plates). In this way, when thermal energy is generated within the die, this thermal energy is dissipated from the die through metal posts (one or more) and through bonded metal interconnects (one or more) into the interposer substrate. Therefore, in order to provide heat dissipation to the die within the IC package, metal interconnects, which are features available in the interposer substrate manufacturing process, are deployed to form a base, on which metal posts are manufactured and thermally bonded to the die.

[0007]

[0007] In this regard, in one exemplary embodiment, an IC package is provided. The IC package comprises a package substrate and an interposer substrate extending in a first direction. The interposer substrate extending in a first direction comprises a first metal layer. The first metal layer comprises one or more first metal interconnects. The IC package further comprises a first die bonded to the package substrate. The first die is located between the package substrate and the interposer substrate. The IC package further comprises at least one metal post bonded to a first metal interconnect of one or more first metal interconnects in the interposer substrate and thermally bonded adjacent to the first die.

[0008]

[0008] In another embodiment, a method for manufacturing an IC package is provided. The method comprises providing a package substrate. The method also comprises providing an interposer substrate extending in a first direction, the interposer substrate comprising a first metal layer, the first metal layer comprising one or more first metal interconnects. The method also comprises providing at least one metal post, each connected to one of the first metal interconnects. The method also comprises arranging a first die between the package substrate and the interposer substrate, and coupling the first die to the package substrate. The method also comprises thermally coupling the first die to at least one metal post adjacent to the first die. [Brief explanation of the drawing]

[0009] [Figure 1A]

[0009] This is a side view of an IC package, which includes at least one metal post that thermally bonds the first die in the first die layer of the integrated circuit (IC) package to an interposer substrate adjacent to the die, in order to dissipate the thermal energy of the first die. [Figure 1B]

[0010] Figure 1A is an enlarged side view of the IC package, showing an interposer substrate thermally bonded to the first die via metal posts. [Figure 1C]

[0011] Figure 1A is a bottom view of the interposer substrate within the IC package, showing metal posts extending vertically (in the Z-axis direction) between the first die layer and the interposer substrate. [Figure 1D]

[0012] A side view of an IC package, which includes metal posts that thermally bond the first die within the first die layer of the IC package to an interposer substrate adjacent to the die in order to dissipate the thermal energy of the first die, wherein the interposer substrate does not include thermal vias. [Figure 2]

[0013] This flowchart illustrates an exemplary manufacturing process for producing an IC package, including the IC package shown in Figures 1A to 1C, which includes an interposer substrate thermally coupled to a first die via metal posts for dissipating thermal energy within the first die. [Figure 3A]

[0014] Figure 3A is a flowchart illustrating another exemplary manufacturing process for producing an interposer substrate, which includes metal posts constructed on a first metal plate within the interposer substrate. [Figure 3B] Figure 3B is a flowchart illustrating another exemplary manufacturing process for producing an interposer substrate, which includes metal posts constructed on a first metal plate within the interposer substrate. [Figure 4ABC]

[0015] Figures 4A to 4C show exemplary manufacturing stages during the production of an interposer substrate using the manufacturing process shown in Figures 3A and 3B. [Figure 4DEF] Figures 4D to 4F show exemplary manufacturing stages during the production of an interposer substrate using the manufacturing process shown in Figures 3A and 3B. [Figure 5A]

[0016] Figure 5A is a flowchart illustrating another exemplary manufacturing process for producing an interposer substrate, which includes a first metal plate within the interposer substrate and metal posts constructed on a second metal plate thermally bonded to the first metal plate via thermal vias. [Figure 5B]Figure 5B is a flowchart illustrating another exemplary manufacturing process for producing an interposer substrate, which includes a first metal plate within the interposer substrate and metal posts constructed on a second metal plate thermally bonded to the first metal plate via thermal vias. [Figure 6ABC]

[0017] Figures 6A to 6C show exemplary manufacturing stages during the production of an interposer substrate, based on the manufacturing process shown in Figures 5A to 5B. [Figure 6DEF] Figures 6D to 6F show exemplary manufacturing stages during the production of an interposer substrate, based on the manufacturing process shown in Figures 5A to 5B. [Figure 7A]

[0018] Figure 7A is a flowchart illustrating an exemplary assembly process for assembling an IC package that employs metal posts to thermally bond the first die to an interposer substrate in order to dissipate the thermal energy of the first die. [Figure 7B] Figure 7B is a flowchart illustrating an exemplary assembly process for assembling an IC package that employs metal posts to thermally bond the first die to an interposer substrate in order to dissipate the thermal energy of the first die. [Figure 7C] Figure 7C is a flowchart illustrating an exemplary assembly process for assembling an IC package that employs metal posts to thermally bond the first die to an interposer substrate in order to dissipate the thermal energy of the first die. [Figure 8AB]

[0019] Figures 8A to 8B show exemplary assembly stages in the IC package assembly process shown in Figures 7A to 7C. [Figure 8CD] Figures 8C to 8D show exemplary assembly stages in the IC package assembly process shown in Figures 7A to 7C. [Figure 8E] Figure 8E shows an exemplary assembly stage in the IC package assembly process shown in Figures 7A to 7C. [Figure 9]

[0020] A block diagram of an exemplary wireless communication device including, but not limited to, the IC packages of FIGS. 1A-1D and 8A-8E, and employing at least one metal post thermally coupling a first die to an interposer substrate to dissipate thermal energy of the first die by exemplary manufacturing and assembly processes in FIGS. 3A-3B, 5A-5B, and 7A-7C. [Figure 10]

[0021] A block diagram of an exemplary processor-based system that can include components deployed within an IC package that includes, but is not limited to, the IC packages of FIGS. 1A-1D and 8A-8E, and employs at least one metal post thermally coupling a first die to an interposer substrate to dissipate thermal energy of the first die by exemplary manufacturing and assembly processes in FIGS. 3A-3B, 5A-5B, and 7A-7C.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010]

[0022] Next, some exemplary aspects of the present disclosure will be described with reference to the drawings. The term “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” should not necessarily be construed as preferred or advantageous over other aspects.

[0011]

[0023] Embodiments disclosed in the detailed description include integrated circuit (IC) packages employing metal posts that thermally bond a semiconductor die ("die") to an interposer substrate in order to dissipate thermal energy within the die. Related manufacturing methods are also disclosed. The IC package includes a die layer containing a die bonded to a package substrate to provide signal routing paths to the die. For example, to facilitate the stacking of additional dies within the IC package as a three-dimensional (3D) IC (3DIC) package, the IC package also includes an interposer substrate adjacent to the die. The interposer substrate supports providing additional signal routing paths to the package substrate for external and / or die-to-die (D2D) connections. In exemplary embodiments, the IC package also includes one or more metal posts thermally bonded to the die and one or more metal interconnects (e.g., metal traces, metal pads, metal wires, metal plates) within the interposer substrate. In this way, when thermal energy is generated within the die, this thermal energy is dissipated into the interposer substrate via one or more metal posts and connected metal interconnects. Therefore, in order to provide heat dissipation to the die within the IC package, metal interconnects, which are features available in the interposer substrate manufacturing process, are deployed to form a base, on which metal posts are manufactured and thermally bonded to the die.

[0012]

[0024] In this regard, Figure 1A is a side view of an integrated circuit (IC) package 100, which includes thermally bonded metal posts 102 to the first die 104 within the first die layer 114 of the IC package 100 and to an interposer substrate 106 adjacent to the first die 104, in order to dissipate the thermal energy of the first die. "Interposer substrate 106 adjacent to the first die 104" means that the interposer substrate 106 and the first die 104 are spatially adjacent to each other or are adjacent to each other with some intervening space. The metal posts 102 are not limited to a specific number and may include at least one metal post. As will be described in more detail below, when thermal energy is generated in the first die 104, this thermal energy is dissipated through the metal posts 104 and through the interposer substrate 106. The interposer substrate 106 extends in a first horizontal direction (one or more) (X-axis direction and / or Y-axis direction (one or more)). The interposer substrate 106 includes a metallization layer 108, each having routing metal interconnects 110 (e.g., metal traces, metal wires, metal pads) for providing signal routing through the interposer substrate 106. The metallization layer 108 includes a metal layer and an insulating layer. Signal routing between indirectly adjacent metallization layers 108 within the interposer substrate 106 is provided by vias 112, which are vertical metal interconnects extending in a second vertical direction (Z-axis direction). The interposer substrate 106 is coupled to a first die layer 114, which includes a first die 104 coupled to a package substrate 116.

[0013]

[0025] For example, the package substrate 116 can be a laminated substrate or an embedded trace substrate (ETS). In this example, the package substrate 116 includes a plurality of metallization layers 118(1) to 118(3), each of which includes respective metal interconnects 120(1) to 120(3) (e.g., metal traces, metal wires, metal pads) for providing signal routing to the first die 104 in the first die layer 114 bonded to the package substrate 116. The metallization layers 118(1) to 118(3) are parallel to each other, directly adjacent to each other, and extend in a first horizontal direction (one or more) (X-axis direction and / or Y-axis direction (one or more)). The first die 104 is positioned between the package substrate 116 and the interposer substrate 106 in a first horizontal direction (one or more) (X-axis direction and / or Y-axis direction (one or more)), and is electrically coupled to the package substrate 116 by a die interconnect 122 coupled to a metal interconnect 120(1) in the first upper metallization layer 118(1) of the package substrate 116. The package substrate 116 is configured to provide a signal routing path between the first die 104 and the external interconnect 124 for the IC package 100 (e.g., solder ball, ball grid array (BGA) interconnect, etc.) via the coupling of metal interconnects 120(1) to 120(3) in its respective metallization layers 118(1) to 118(3).

[0014]

[0026] As shown in Figure 1A, the external interconnect 124 is located on the land surface 126 of the package substrate 116. The IC package 100 in Figures 1A to 1C is also positioned to provide electrical coupling between the interposer substrate 106 and the package substrate 116. This is to allow, for example, in the IC package 100, signal routing to be provided between a second die (not shown) coupled to the interposer substrate 106 and the package substrate 116 and / or the external interconnect 124. In this regard, vertical interconnects 128 (e.g., metal posts, metal pillars, metal balls) are positioned within the lower first die layer 114, surrounded by a molding compound 130, and coupled to metal vias 112 in the interposer substrate 106 and the package substrate 116, in order to provide electrical connections between the interposer substrate 106 and the package substrate 116.

[0015]

[0027] Continuing to refer to Figure 1A, as will be described in more detail below, the metallization layer 108 of the interposer substrate 106 includes a first metal layer 132(1) and a second metal layer 132(2). The first routing metal interconnects 134(1) (e.g., metal traces, metal wires, metal pads) provided by the specific routing metal interconnects 110 are formed within the first metal layer 132(1). The second routing metal interconnects 134(2) (e.g., metal traces, metal wires, metal pads) provided by the specific routing metal interconnects 110 are formed within the second metal layer 132(2). The first routing metal interconnect 134(1) and the second routing metal interconnect 134(2) are parallel to each other, located on both sides of the insulating layer 136 within the metallization layer 108, and extending in a first horizontal direction (one or more) (X-axis direction and / or Y-axis direction (one or more)). The first routing metal interconnect 134(1) and the second routing metal interconnect 134(2) may be connected to each other using vias 112 to provide a signal routing path within the interposer substrate 106. One or more first metal interconnects 138(1) (e.g., metal traces, metal wires, metal plates) are formed within the first metal layer 132(1). Optionally, the first metal interconnect 138(1) may be formed as a metal plate during the manufacturing of the interposer substrate 106 to provide a larger metal surface area for attracting thermal energy from the first die 104. Similarly, optionally, one or more second metal interconnects 138(2) (e.g., metal traces, metal wires, metal plates) may be included on the insulating layer 136. The insulating layer 136 may optionally include thermal vias 142 that thermally connect one or more first metal interconnects 138(1) to one or more second metal interconnects 138(2). Optionally, the second metal interconnects 138(2) may be formed as metal plates during the manufacturing of the interposer substrate 106. When thermal energy is generated within the first die 104, the metal post 102 draws thermal energy from the first die 104 and conducts it to the first metal interconnects 138(2) via the thermal vias 142.Over time, the thermal energy within the first metal interconnects 138(1), 138(2) and the thermal vias 142 spreads into the insulating layer 136 of the interposer substrate 106. As used herein, the term “thermally coupled” means that thermal energy is drawn from a heat source to a heat sink, or from an intermediate conduit for thermal energy to a heat sink.

[0016]

[0028] The thermal interface material 140 may optionally be bonded to the first die 104 between the first die 104 and the interposer substrate 106 to enhance the thermal coupling of the first die 104 to the metal post 102 and therefore to the interposer substrate 106. The thermal interface material draws heat from the heat source. An example of a thermal interface material is ShinEtsu G-769EL thermal paste.

[0017]

[0029] Figure 1B is an enlarged side view of the IC package 100 in Figure 1A, showing the interposer substrate 106 thermally coupled to the first die 104 via metal posts 102. The first die 104 has a back surface 144 and an active surface 146. The back surface 144 is a surface of the first die 104 formed during the front-end-of-line (FEOL) process. The active surface 146 is a surface of the first die 104 formed during the back-end-of-line (BEOL) process. The active surface 146 is electrically coupled to the package substrate 116 via die interconnects 122. As shown in Figure 1B, the thermal interface material 140 is located on the back surface 144 of the first die 104.

[0018]

[0030] As described above, metal posts 102 are provided within the interposer substrate 106 to provide a thermal coupling between the first die 104 and the interposer substrate 106 for heat dissipation. The metal posts 102 have first ends 148 connected to one or more first metal interconnects 138(1), and each of the metal posts 102 extends in a second vertical direction (Z-axis direction) toward the first die 104. The metal posts 102 have second ends 150 adjacent to and thermally coupled to the first die 104. Optionally, at least one of the second ends 150 of the metal posts 102 may terminate adjacent to the thermal interface material 140, may contact the thermal interface material 140, and / or may also contact the back surface 144 of the first die 104. The length 152 of at least one metal post 102 may be between 30 micrometers (μm) and 100 μm.

[0019]

[0031] As shown in Figure 1B, the molding compound 130 is located between the metal posts 102 and surrounds the top of the first die 104 between the interposer substrate 106 and the package substrate 116. The molding compound 130 insulates the metal posts 102 and other conductive components within the first die layer 114 and protects the first die 104 within the IC package 100.

[0020]

[0032] Furthermore, as shown in Figure 1B, the first metal interconnect portion 138(1) and the second metal interconnect portion 138(2) within the first and second metal layers 132(1) and 132(2) of the interposer substrate 106 are parallel to each other in the first horizontal direction (X and / or Y axis direction (single or multiple)) and are arranged on both sides of the insulating layer 136. The first metal interconnect portion 138(1) and the second metal interconnect portion 138(2) are said to have the same extent because they cover the same area in the second vertical direction (Z axis direction). Therefore, when the first metal interconnect portion 138(1) is formed as the first metal plate and the second metal interconnect portion 138(2) is formed as the second metal plate, the first metal interconnect portion 138(1) and the second metal interconnect portion 138(2) have the same extent and are connected via the thermal via 142.

[0021]

[0033] Figure 1C is a bottom view of the interposer substrate 106 within the IC package 100 of Figure 1A, with the metal posts 102 extending in a second vertical direction (Z-axis direction). The footprint 154 of the first die 104, having length L and a first width W1 in the X and Y directions, is positioned and encompasses the region (L × W1) of the metal posts 102, which are arranged in an array and electrically isolated from the first routing metal interconnect 134(1). In another embodiment, the metal posts 102 may further extend to a second width W2 in the Y direction to define a larger area than the footprint 154 and avoid electrically coupling the first routing metal interconnect 134(1). As the area of ​​the metal posts 102 increases while the footprint 154 remains constant, more thermal energy will be dissipated from the first die 104 into the interposer substrate 106.

[0022]

[0034] Continuing to refer to Figure 1C, the first pitch P1 is the distance (in the X direction) between the center of one of the metal posts 102 and the center of the adjacent metal post (in the X direction) closest to it. The second pitch P2 is the distance (in the Y direction) between the center of one of the metal posts 102 and the center of the adjacent metal post 102 (in the Y direction) closest to it. The pitch P1 and / or P2 between any adjacent metal posts 102 may, for example, be between 100 μm and 200 μm.

[0023]

[0035] As an alternative embodiment to Figure 1A, Figure 1D is a side view of the IC package 158, which includes metal posts 102 that thermally bond the first die 104 within the first die layer 114 of the IC package 158 to an interposer substrate 160 adjacent to the first die 104 in order to dissipate the thermal energy of the first die. "Interposer substrate 160 adjacent to the first die 104" means that the interposer substrate 160 and the first die 104 are spatially adjacent to each other or adjacent to each other with some intervening space. The interposer substrate 160 does not contain thermal vias. Common elements between the elements of the IC package 158 and the elements of the IC package 100 in Figures 1A to 1C are indicated by common element numbers. As shown in Figure 1D, the IC package 158 includes a first metal interconnect 138(1) and a second metal interconnect 138(2) that are not connected to each other. The thermal energy generated within the first die 104 is dissipated through the metal post 102 into the first metal interconnect 138(1) and slowly spreads throughout the interposer 106, including the insulating layer 136. In this embodiment, since the metal interconnect 138(1) to which the post is bonded is not connected to the metal interconnect 138(2) in the interposer substrate, heat is not directly dissipated through additional metal layers. This embodiment may be acceptable if the thermal dissipation requirements can be met by the heat dissipation provided by the bonding of the metal post to a single metal layer for the IC package. The interposer substrate may be designed so that the metal post is thermally bonded through multiple metal layers within the interposer substrate.

[0024]

[0036] Interposer substrates, including but not limited to the interposer substrates 106 and 160 in the associated IC packages 100 and 158 shown in Figures 1A to 1D, which employ at least one metal post thermally bonded to the first die to dissipate thermal energy from the first die, can be manufactured using different manufacturing processes. In this regard, Figure 2 is a flowchart illustrating an exemplary manufacturing process 200 for manufacturing an IC package including, as an example, the interposer substrates 106 and 160 and associated IC packages 100 and 158 shown in Figures 1A to 1D, respectively, but not limited to the interposer substrates 106 and 160 thermally bonded to the first die via at least one metal post to dissipate thermal energy from the first die. Note that the manufacturing process 200 in Figure 2 is described in conjunction with, as an example, the interposer substrate 106 and package substrate 116 in Figures 1A to 1D, but they are not limiting.

[0025]

[0037] In this regard, a first exemplary step in the manufacturing process 200 in Figure 2 may include preparing a package substrate 116 (block 202 in Figure 2). The next step in the manufacturing process 200 may include preparing interposer substrates 106, 160 extending in a first horizontal direction in the X-axis direction and / or Y-axis direction, wherein the interposer substrate 106 comprises a first metal layer 132(1), and the first metal layer 132(1) comprises one or more first metal interconnects 138(1) (block 204 in Figure 2). The next step in the manufacturing process 200 may include preparing a metal post 102 coupled to one or more first metal interconnects 138(1) (block 206 in Figure 2). The next step in the manufacturing process 200 may include placing a first die 104 between the package substrates 116, 160 and the interposer substrate 106 (block 208 in Figure 2). The next step in the manufacturing process 200 may include bonding the first die 104 to the package substrate 116 (block 210 in Figure 2). The next step in the manufacturing process 200 may include thermally bonding the first die 104 to a metal post 102 adjacent to the first die 104 (block 212 in Figure 2).

[0026]

[0038] Other manufacturing processes can also be used to manufacture the interposer substrate, which has at least one metal post that thermally bonds the interposer substrate to a first die, and includes, but is not limited to, the interposer substrates 106, 160 and associated IC packages 100, 158 in Figures 1A and 1D, respectively. In this regard, Figures 3A and 3B are flowcharts showing another exemplary manufacturing process 300 for manufacturing the interposer substrate 160, which includes, but is not limited to, the interposer substrate 160 and associated IC package 158 in Figure 1D, and a metal post 102 built on a first metal plate within the interposer substrate. Figures 4A to 4F show exemplary manufacturing stages in the manufacture of the interposer substrate 160 according to the manufacturing process 300 in Figures 3A and 3B. The manufacturing process 300 shown in manufacturing stages 400A to 400F in Figures 4A to 4F refers to the interposer substrate 160 and associated IC package 158 in Figure 1D, and therefore will be described with reference to the interposer substrate 160 and IC package 158 in Figure 1D.

[0027]

[0039] In this regard, as shown in manufacturing step 400A in Figure 4A, an exemplary step in manufacturing process 300 is to coat the insulating layer 136 with a very thin metal layer 402 to form the beginning portion of the interposer substrate 160 (block 302 in Figure 3A). The next step in manufacturing process 300 may include drilling holes in the interposer substrate 160 to form vias 404 in the interposer substrate 160 (block 304 in Figure 3A, step 400B). The next step in manufacturing process 300 may include drawing a metal pattern on the top and bottom surfaces of the interposer substrate 160, and plating metal on the drawn metal pattern and within the vias 404 to form a first metal interconnect 138(1) and a second metal interconnect 138(2) on the bottom and top surfaces of the interposer substrate 160, respectively (block 306 in Figure 3A, step 400C). The first metal interconnect 138(1) forms the first metal plate 406, and the second metal interconnect 138(2) forms the second metal plate 408. The next step in the manufacturing process 300 may be to plate metal onto the first metal plate 406 to form metal posts 102 (block 308, step 400D in Figure 3B). As shown in Figure 4D, the metal plate is defined as a metal that extends across the metal posts 102 in both the first X and Y directions and has thickness in the second Z direction. The first metal plate 406 has a Z-direction thickness in the range of 10 μm or more and 18 μm or less, and the second metal plate 408 has a Z-direction thickness in the range of 10 μm or more and 18 μm or less. The next step in the manufacturing process 300 may be to apply solder resist to at least the bottom of the interposer substrate 160 (block 310, step 400E in Figure 3B).The next step in manufacturing process 300 may include chemically etching the bottom of the interposer substrate 160 to thin the solder resist, expose the metal posts 102 and metal interconnects, for example, exposing the routing metal interconnect 110 used for routing signals through the interposer substrate 160 via the metal interconnect 138(1) (Block 312, step 400F in Figure 3B). The manufacturing process 300 described above is a modified semi-additive process (MSAP). Similarly, other manufacturing processes, including an embedded trace manufacturing process, can be deployed to manufacture the interposer substrate 160.

[0028]

[0040] Other manufacturing processes can also be used to manufacture the interposer substrate, which includes, but is not limited to, the interposer substrate 106 and associated IC packages 100 and 158 in Figures 1A to 1D, and which has at least one metal post that thermally bonds the interposer substrate to a first die. In this regard, Figures 5A and 5B are flowcharts showing another exemplary manufacturing process 500 for manufacturing an interposer substrate, which includes, but is not limited to, the interposer substrate 106 and associated IC package 100 in Figure 1A, and which includes at least one metal post built on a first metal plate within the interposer substrate and a second metal plate thermally bonded to the first metal plate via thermal vias. Figures 6A to 6F show exemplary manufacturing stages in the manufacture of the interposer substrate 106 according to the manufacturing process 500 in Figures 5A and 5B. The manufacturing process 500 shown in manufacturing stages 600A to 600F in Figures 6A to 6F refers to the interposer substrate 106 and associated IC package 100 in Figure 1A, and therefore will be described with reference to the interposer substrate 106 and IC package 100 in Figure 1.

[0029]

[0041] In this regard, as shown in manufacturing step 600A in Figure 6A, an exemplary step in manufacturing process 500 is to coat the insulating layer 136 with a very thin metal layer 602 to form the beginning portion of the interposer substrate 106 (block 502 in Figure 5A). The next step in manufacturing process 500 may be to drill holes in the interposer substrate 106 to form vias 604 in the interposer substrate 106 (block 504 in Figure 5A, step 600B). As also shown in manufacturing step 600C in Figure 6, the next step in manufacturing process 500 may be to draw a metal pattern on the top and bottom surfaces of the interposer substrate 106, and to plate metal on the drawn metal pattern and within the vias 604 to form thermal vias 142, thereby forming a first metal interconnect 138(1) and a second metal interconnect 138(2) on the bottom and top surfaces of the interposer substrate 106, respectively (block 506 in Figure 5A, step 600C). The first metal interconnect 138(1) forms the first metal plate 606, and the second metal interconnect 138(2) forms the second metal plate 608. The first metal plate 606 has a Z-direction thickness in the range of 10 μm or more and 18 μm or less, and the second metal plate 608 has a Z-direction thickness in the range of 10 μm or more and 18 μm or less. As also shown in manufacturing step 600D in Figure 6, the next step in manufacturing process 500 may be to plate metal onto the first metal plate 606 to form a metal post 102 (block 508, step 600D in Figure 5B). As also shown in manufacturing step 600E in Figure 6, the next step in manufacturing process 500 may be to apply solder resist to at least the bottom of the interposer substrate 106 (block 510, step 600E in Figure 3B).As also shown in manufacturing step 600F of Figure 6, the next step in manufacturing process 500 may include chemically etching the bottom of the interposer substrate 106 to thin the solder resist, exposing the metal posts 102 and the first metal interconnect 138(1), for example, exposing the routing metal interconnect 110 used for routing signals via via 112 through the interposer substrate (block 512, step 600F in Figure 5B). The manufacturing process 500 described above is a modified two-layer modified semi-additive process (MSAP). Similarly, other manufacturing processes, including an embedded trace manufacturing process, can be deployed to manufacture the interposer substrate 106.

[0030]

[0042] IC packages, including but not limited to the IC packages 100 and 158 in Figures 1A to 1D, which employ at least one metal post that thermally bonds the first die to the interposer substrates 106 and 160 in order to dissipate the thermal energy of the first die, can be assembled using different assembly processes. In this regard, Figures 7A to 7C are flowcharts illustrating an exemplary assembly process for assembling an IC package that employs a metal post that thermally bonds the first die to the interposer substrates 106 and 160 in order to dissipate the thermal energy of the first die, including but not limited to the IC packages 100 and 158 in Figures 1A to 1D. The assembly process 700 in Figures 7A to 7C is described, for example, in conjunction with the interposer substrate 106, the first die layer 114, and the package substrate 116 in Figures 1A to 1D.

[0031]

[0043] In this regard, as shown in assembly stage 800A in Figure 8A, an exemplary initial step in the assembly process 700 begins with preparing the first die 104 coupled to the package substrate 116 (block 702 in Figure 7A, stage 800A). As also shown in manufacturing stage 800B in Figure 8, the next step in the assembly process 700 may include applying a thermal interface material 140 to the back surface 144 of the first die 104 (block 704 in Figure 7A, stage 800B). The thermal interface material 140 is available in various forms and can be applied according to those forms. For example, the thermal interface material 140 may be a thermal paste applied to the first die 104 by brushing the paste onto the back surface 144 of the first die 104 (also known as a distribution process). In another example, the thermal interface material 140 may be in the form of a film that is attached to the back surface 144 of the first die 104. As also shown in manufacturing step 800C in Figure 8, the next step in assembly process 700 may include bonding the interposer substrate 106 to the package substrate 116 via thermal compression (block 706 in Figure 7B, step 800C). As also shown in manufacturing step 800D in Figure 8, the next step in assembly process 700 may include inserting a molding compound to fill the space between the interposer substrate 106, the first die 104, and the package substrate 116 (block 708 in Figure 7B, step 800D). As also shown in manufacturing step 800E in Figure 8, the next step in assembly process 700 may optionally include external interconnects, such as attaching solder balls 802 and external capacitors 804 to the land surfaces of the package substrate 116 (block 710 in Figure 7C, step 800E).

[0032]

[0044] As used in this application, “adjacent” objects refer to objects that are adjacent to or next to another object, with a space interposed between them. Adjacent objects may not be physically connected to one another. Directly adjacent objects mean that such objects are directly adjacent to or next to each other, with no other object interposed or positioned between them. Indirectly adjacent objects mean that such objects are not directly adjacent to or next to each other, with no other object interposed or positioned between them.

[0033]

[0045] IC packages employing metal posts that thermally bond a die to an interposer substrate to dissipate the die's thermal energy, including but not limited to IC packages 100 and 158 in Figures 1A-1D, 4A-4F, and 6A-6F, as well as interposer substrates 106 and 160, and according to exemplary manufacturing and assembly processes in Figures 2, 3A-3B, 5A-5B, and 7A-7C, and according to embodiments disclosed herein, may be provided in or incorporated within any processor-based device or wireless device. Examples include, but are not limited to, set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, global positioning system (GPS) devices, mobile phones, cellular phones, smartphones, session initiation protocol (SIP) phones, tablets, phablets, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smartwatches, health trackers or fitness trackers, eyewear, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, and avionics systems.

[0034]

[0046] In this regard, Figure 9 shows an exemplary wireless communication device 900 including radio frequency (RF) components formed from one or more ICs 902, any of which may include an IC package employing metal posts that thermally bond the die to an interposer substrate to dissipate the die's thermal energy, and any form of IC package disclosed herein. The wireless communication device 900 may, for example, include any of the devices referenced above or be provided within any of them. As shown in Figure 9, the wireless communication device 900 includes a transceiver 904 and a data processor 906. The data processor 906 may include memory for storing data and program code. The transceiver 904 includes a transmitter 908 and a receiver 910 that support bidirectional communication. Generally, the wireless communication device 900 may include any number of transmitters 908 and / or receivers 910 for any number of communication systems and frequency bands. All or part of the transceiver 904 may be mounted on one or more analog ICs, RF ICs (RFICs), mixed-signal ICs, etc.

[0035]

[0047] The transmitter 908 or receiver 910 may be implemented using a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal is frequency-converted between RF and baseband in multiple stages; for example, in receiver 910, the frequency is converted from RF to intermediate frequency (IF) in one stage, and then from IF to baseband in another stage. In a direct conversion architecture, the signal is frequency-converted between RF and baseband in one stage. The superheterodyne architecture and the direct conversion architecture may use different circuit blocks and / or have different requirements. In the wireless communication device 900 in Figure 9, the transmitter 908 and receiver 910 are implemented using a direct conversion architecture.

[0036]

[0048] In the transmission path, the data processor 906 processes the data to be transmitted and provides the transmitter 908 with an I analog output signal and a Q analog output signal. In an exemplary wireless communication device 900, the data processor 906 includes digital-to-analog converters (DACs) 912(1), 912(2) for converting the digital signals generated by the data processor 906 into an I analog output signal and a Q analog output signal, such as an I output current and a Q output current, for further processing.

[0037]

[0049] Within transmitter 908, low-pass filters 914(1) and 914(2) filter the I analog output signal and the Q analog output signal, respectively, to remove undesirable signals generated by the preceding digital-to-analog conversion. Amplifiers (AMPs) 916(1) and 916(2) amplify the signals from low-pass filters 914(1) and 914(2), respectively, to provide the I baseband signal and the Q baseband signal. Upconverter 918 upconverts the I baseband signal and the Q baseband signal via mixers 920(1) and 920(2) using the I TX LO signal and the Q TX LO signal from the transmit (TX) local oscillator (LO) signal generator 922, to provide the upconverted signal 924. Filter 926 filters the upconverted signal 924 to remove undesirable signals generated by frequency upconversion, as well as noise in the receiving frequency band. A power amplifier (PA) 928 amplifies the upconverted signal 924 from the filter 926 to obtain a desired output power level and provides a transmit RF signal. The transmit RF signal is routed through a duplexer or switch 930 and transmitted via antenna 932.

[0038]

[0050] In the receiving path, antenna 932 receives signals transmitted by the base station and provides a received RF signal, which is routed through a duplexer or switch 930 and supplied to a low-noise amplifier (LNA) 934. The duplexer or switch 930 is designed to operate with specific RX vs. TX duplexer frequency separation so that the receive (RX) signal is separated from the TX signal. To obtain the desired RF input signal, the received RF signal is amplified by the LNA 934 and filtered by a filter 936. Down-conversion mixers 938(1) and 938(2) mix the output of the filter 936 with the I RX LO signal and Q RX LO signal (i.e., LO_I and LO_Q) from the RX LO signal generator 940 to generate the I baseband signal and the Q baseband signal. The I baseband signal and the Q baseband signal are amplified by AMP942(1) and 942(2), and further filtered by low-pass filters 944(1) and 944(2) to obtain the I analog input signal and the Q analog input signal, which are then provided to the data processor 906. In this example, the data processor 906 includes analog-to-digital converters (ADCs) 946(1) and 946(2) for converting the analog input signals into digital signals that will be further processed by the data processor 906.

[0039]

[0051] In the wireless communication device 900 shown in Figure 9, the TX LO signal generator 922 generates the I TX LO signal and the Q TX LO signal used for frequency upconversion, while the RX LO signal generator 940 generates the I RX LO signal and the Q RX LO signal used for frequency downconversion. Each LO signal is a periodic signal having a specific fundamental frequency. The TX phase-locked loop (PLL) circuit 948 receives timing information from the data processor 906 and generates a control signal used to adjust the frequency and / or phase of the TX LO signal from the TX LO signal generator 922. Similarly, the RX PLL circuit 950 receives timing information from the data processor 906 and generates a control signal used to adjust the frequency and / or phase of the RX LO signal from the RX LO signal generator 940.

[0040]

[0052] Regarding exemplary processor-based devices, Figure 10 shows an example of a processor-based system 1000 including circuits that may be provided within IC packages 1002, 1002(1) to 1002(7). Any of the IC packages 1002, 1002(1) to 1002(7) may include metal posts that thermally bond the die to an interposer substrate for dissipating thermal energy within the die, and include, but are not limited to, the interposer substrates 106, 160 in Figures 1A to 1D, Figures 4A to 4F, and Figures 6A to 6F, and the associated IC packages 100, 158 in Figures 1A to 1D, by exemplary manufacturing and assembly processes in Figures 2, 3A to 3B, and 5A to 5B, and by any embodiment disclosed herein. In this example, the processor-based system 1000 may be formed as IC 1004 within IC package 1002 and as a system-on-a-chip (SoC) 1006. The processor-based system 1000 includes a central processing unit (CPU) 1008, which includes one or more processors 1010, also called CPU cores or processor cores. The CPU 1008 may have a cache memory 1012 coupled to it for quick access to temporarily stored data. The CPU 1008 is coupled to a system bus 1014, which can interconnect master and slave devices contained within the processor-based system 1000. As is well known, the CPU 1008 communicates with these other devices by exchanging address information, control information, and data information via the system bus 1014. For example, the CPU 1008 can communicate bus transaction requests to a memory controller 1016, which is an example of a slave device. Although not shown in Figure 10, it is possible to have multiple system buses 1014, each system bus 1014 constituting a different fabric.

[0041]

[0053] Other master and slave devices can be connected to the system bus 1014. As shown in Figure 10, these devices may include, for example, a memory system 1020, which may be in a separate IC package 1002(4) and include a memory controller 1016 and one or more memory arrays 1018; one or more input devices 1022 (which may be in a separate IC package 1002(6)); one or more output devices 1024 (which may be in a separate IC package 1002(7)); one or more network interface devices 1026 (which may be in a separate IC package 1002(5)); and one or more display controllers 1028 (which may be in a separate IC package 1002(2)). Each of the memory system 1020, one or more input devices 1022, one or more output devices 1024, one or more network interface devices 1026, and one or more display controllers 1028 can be provided in the same or different IC package 1002(5). The input devices (one or more) 1022 may include, but are not limited to, input keys, switches, voice processors, etc., and may include any type of input device. The output devices (one or more) 1024 may include, but are not limited to, audio indicators, video indicators, other visual indicators, etc., and may include any type of output device. The network interface devices (one or more) 1026 may be any device configured to enable data exchange with the network 1030.Network 1030 can be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), Bluetooth® networks, and the Internet. Network interface devices 1026 (one or more) can be configured to support any desired type of communication protocol.

[0042]

[0054] The CPU 1008 may also be configured to access a display controller(s) 1028 via the system bus 1014 to control information sent to one or more displays 1032. The display controller(s) 1028 sends the information to be displayed to the displays(s) 1032 via one or more video processors 1034, and the one or more video processors 1034 process the information to be displayed into a format suitable for the displays(s) 1032. The display controller(s) 1028 and the video processor(s) 1034 may, for example, be included as ICs in the same or different IC package 1002(5) and as ICs in the same or different IC package 1002(1) that includes the CPU 1008. The display(s) 1032 may include, but is not limited to, any type of display, such as a cathode ray tube (CRT), liquid crystal display (LCD), plasma display, or light-emitting diode (LED) display.

[0043]

[0055] Those skilled in the art will further understand that the various exemplary logic blocks, modules, circuits, and algorithms described in relation to the embodiments disclosed herein may be implemented as electronic hardware, or as instructions stored in memory or another computer-readable medium, or a combination of both, and any such instructions may be executed by a processor or other processing device. The memory disclosed herein may be of any type and size and may be configured to store any desired type of information. To clearly demonstrate this compatibility, various exemplary components, blocks, modules, circuits, and steps have been described above in general terms of their functionality. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the system as a whole. Those skilled in the art may implement the described functionality in various ways with respect to each specific application, but such implementation decisions should not be construed as causing a departure from the scope of this disclosure.

[0044]

[0056] Various exemplary logic blocks, modules, and circuits described in relation to the embodiments disclosed herein may be implemented or carried out using processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate logic or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. The processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors working with a DSP core, or any other such configuration).

[0045]

[0057] The embodiments disclosed herein can be embodied in hardware, or in instructions stored in hardware, which may reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable media known in the art. An exemplary storage medium is coupled to a processor so that the processor can read information from and write information to the storage medium. Alternatively, the storage medium may be integrated with the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and storage medium may reside as separate components in a remote station, base station, or server.

[0046]

[0058] Furthermore, it should be noted that the operating steps described in any of the exemplary embodiments of this specification are described for the purpose of providing examples and explanations. The operations described can also be performed in many different orders other than the order shown in the illustrations. Moreover, an operation described in a single operating step can actually be performed in several different steps. Furthermore, one or more operating steps described in the exemplary embodiments can be combined. It should be understood that, as will be readily apparent to those skilled in the art, many different modifications can be made to the operating steps shown in the flowcharts. It will also be understood that information and signals can be represented using a wide variety of techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof.

[0047]

[0059] The above descriptions in this disclosure are provided to enable any person skilled in the art to make or use the disclosure. Various modifications to this disclosure will be readily apparent to a person skilled in the art, and the general principles defined herein may also be applicable to other modifications. Accordingly, this disclosure is not intended to be limited to the examples and designs described herein, but should be given the broadest scope consistent with the principles and novel features disclosed herein.

[0048]

[0060] Implementation examples are described in the following numbered sections. Article 1. Package substrate and An interposer substrate extending in a first direction, A first metal layer comprising one or more first metal interconnectors, At least one metal post coupled to one or more first metal interconnects within the interposer substrate, An interposer substrate comprising, A first die bonded to a package substrate, disposed between the package substrate and the interposer substrate, wherein at least one metal post is adjacent to the first die and thermally bonded to the first die, An integrated circuit (IC) package that includes [the specified features]. Article 2. The IC package according to Clause 1, wherein the first die has a back surface, and at least one metal post is thermally bonded to the back surface adjacent to the back surface. Article 3. The IC package according to Clause 2, further comprising a thermal interface material on its back surface, wherein at least one metal post is thermally bonded to the thermal interface material. Clause 4. The IC package according to Clause 1 or 2, wherein one or more first metal interconnects comprise a first metal plate. Clause 5. The interposer substrate is A second metal layer comprising one or more second metal interconnectors, An insulating layer is placed between the first metal layer and the second metal layer, Furthermore, The IC package according to Clauses 1 to 4, wherein the insulating layer comprises one or more thermal vias, each of which connects a second metal interconnect of one or more second metal interconnects to a first metal interconnect of one or more first metal interconnects. Clause 6. An IC package according to Clauses 3-5, wherein at least one metal post is in contact with a thermal interface material. Clause 7. The IC package according to Clauses 2-6, wherein at least one metal post is in contact with the back surface of the first die. Clause 8. The IC package according to Clauses 1 to 7, wherein the interposer substrate further comprises at least one via that electrically connects a second die to a package substrate via a vertical interconnect. Clause 9. The IC package according to Clauses 1 to 8, wherein the package substrate further comprises external interconnection parts disposed on the land surface of the package substrate. Clause 10. The IC package according to Clauses 1 to 8, wherein the first die further comprises an active surface electrically coupled to a package substrate. Clause 11. An IC package according to Clauses 5 to 10, wherein one or more first metal interconnects comprise a first metal plate, and one or more second metal interconnects comprise a second metal plate. Clause 12. An IC package according to Clauses 1 to 11, wherein at least one metal post has a length of 30 micrometers (μm) or more and 100 μm or less. Clause 13. An IC package according to Clauses 1 to 11, wherein at least one metal post comprises multiple metal posts, and the pitch between each adjacent metal post among the multiple metal posts is 100 micrometers (μm) or more and 200 μm or less. Clause 14. The IC package according to Clauses 1 to 11, wherein at least one metal post comprises multiple metal posts, and the area defined by the multiple metal posts is at least equal to the area of ​​the back surface of the first die. Clause 15. The IC package according to Clauses 1 to 11, wherein at least one metal post comprises a plurality of metal posts, and the IC package further comprises a molding compound disposed between the plurality of metal posts. Article 16. A method for manufacturing an IC package, Prepare a package substrate, To provide an interposer substrate extending in a first direction, comprising a first metal layer, the first metal layer comprising one or more first metal interconnection portions, Provide at least one metal post connected to one or more first metal interconnects, The first die is placed between the package substrate and the interposer substrate. The first die is bonded to the package substrate, Thermally bonding the first die to at least one metal post adjacent to the first die, Methods that include... Clause 17. The interposer substrate shall be provided. Forming one or more second metal interconnections within the second metal layer, An insulating layer is formed between the first metal layer and the second metal layer, Forming thermal vias in the insulating layer to connect one or more second metal interconnects to one or more first metal interconnects, The method described in Article 16, further including the method described in Article 16. Clause 18. The first die is thermally bonded to at least one metal post adjacent to the first die. The method according to clause 16 or 17, further comprising applying a thermal interface material to the back surface of the first die. Clause 19. The first die is bonded to the package substrate and placed between the package substrate and the interposer substrate. The method according to clause 18, further comprising arranging at least one metal post so as to be in contact with the thermal interface material. Clause 20. The first die is bonded to the package substrate and placed between the package substrate and the interposer substrate. The method according to clause 18 or 19, further comprising positioning at least one metal post so as to be in contact with the back surface of the first die. Clause 21. The interposer substrate shall be provided. The method according to clauses 16-20, further comprising forming a plurality of vertical interconnections between an interposer substrate and a package substrate, and electrically coupling a second die to the package substrate via the plurality of vertical interconnections.

Claims

1. Package substrate and An interposer substrate extending in a first direction, A first metal layer comprising one or more first metal interconnecting parts, At least one metal post coupled to the first metal interconnect of the one or more first metal interconnects in the interposer substrate, An interposer substrate comprising, A first die bonded to the package substrate, disposed between the package substrate and the interposer substrate, wherein at least one metal post is adjacent to the first die and thermally bonded to the first die, An integrated circuit (IC) package that includes [the specified features].

2. The IC package according to claim 1, wherein the first die has a back surface, and the at least one metal post is thermally bonded to the back surface adjacent to it.

3. The IC package according to claim 2, further comprising a thermal interface material on the back surface, wherein the at least one metal post is thermally bonded to the thermal interface material.

4. The IC package according to claim 1, wherein one or more of the first metal interconnects comprise a first metal plate.

5. The interposer substrate, A second metal layer comprising one or more second metal interconnecting portions, An insulating layer placed between the first metal layer and the second metal layer, Furthermore, The insulating layer comprises one or more thermal vias, and each of the one or more thermal vias connects a second metal interconnect of the one or more second metal interconnects to a first metal interconnect of the one or more first metal interconnects. The IC package according to claim 1.

6. The IC package according to claim 3, wherein the at least one metal post is in contact with the thermal interface material.

7. The IC package according to claim 2, wherein the at least one metal post is in contact with the back surface of the first die.

8. The IC package according to claim 1, wherein the interposer substrate further comprises at least one via that electrically connects a second die to the package substrate via a vertical interconnection portion.

9. The IC package according to claim 1, wherein the package substrate further comprises an external interconnection portion disposed on the land surface of the package substrate.

10. The IC package according to claim 1, wherein the first die further comprises an active surface electrically coupled to the package substrate.

11. The IC package according to claim 5, wherein one or more first metal interconnects comprises a first metal plate, and one or more second metal interconnects comprises a second metal plate.

12. The IC package according to claim 1, wherein at least one of the metal posts has a length of 30 micrometers (μm) or more and 100 μm or less.

13. The IC package according to claim 1, wherein the at least one metal post comprises a plurality of metal posts, and the pitch between adjacent metal posts among the plurality of metal posts is 100 micrometers (μm) or more and 200 μm or less.

14. The IC package according to claim 1, wherein the at least one metal post comprises a plurality of metal posts, and the area defined by the plurality of metal posts is at least equal to the area of ​​the back surface of the first die.

15. The IC package according to claim 1, wherein the at least one metal post comprises a plurality of metal posts, and the IC package further comprises a molding compound disposed between the plurality of metal posts.

16. A method for manufacturing IC packages, Prepare a package substrate, To provide an interposer substrate extending in a first direction, comprising a first metal layer, wherein the first metal layer comprises one or more first metal interconnection portions, To provide at least one metal post connected to the first metal interconnection part among the one or more first metal interconnection parts, The first die is placed between the package substrate and the interposer substrate, The first die is bonded to the package substrate, The first die is thermally bonded to at least one metal post adjacent to the first die, Methods that include...

17. The interposer substrate mentioned above is provided. Forming one or more second metal interconnections within the second metal layer, An insulating layer is formed between the first metal layer and the second metal layer, Thermal vias are formed in the insulating layer to connect one or more second metal interconnects to one or more first metal interconnects, The method according to claim 16, further comprising:

18. The method according to claim 16, further comprising thermally bonding the first die to the at least one metal post adjacent to the first die, by applying a thermal interface material to the back surface of the first die.

19. The first die is bonded to the package substrate and placed between the package substrate and the interposer substrate. The method according to claim 18, further comprising arranging the at least one metal post so as to be in contact with the thermal interface material.

20. The first die is bonded to the package substrate and placed between the package substrate and the interposer substrate. The method according to claim 18, further comprising arranging the at least one metal post so as to be in contact with the back surface of the first die.

21. The interposer substrate mentioned above is provided. The method according to claim 16, further comprising forming a plurality of vertical interconnection portions between the interposer substrate and the package substrate, and electrically coupling the second die to the package substrate via the plurality of vertical interconnection portions.

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