Switching transducer driver

Abstract

A switching transducer driver capable of operating in: a first mode in which the first and second output stage switches are controlled to produce two levels of output signals, wherein the impedance of the first output stage switch is substantially the same as the impedance of the second output stage switch; and a second mode in which the first and second output stage switches and a third switch are controlled to produce three levels of output signals, wherein the impedance of the third switch is substantially greater than the impedances of the first and second output stage switches.

Description

Technical Field

[0001] The present disclosure relates to a switching transducer driver.

Background Art

[0002] Switching transducer drivers, such as class-D amplifiers, are increasingly being used in electronic devices where power efficiency is important, such as mobile phones, portable media players, laptop and tablet computers, wireless headphones, earphones, and (plug-in type) earbuds. Such transducer drivers are also increasingly being used in automotive applications, such as in-vehicle audio systems.

[0003] A typical switching transducer driver (e.g., a class-D amplifier) includes a modulation stage and an output stage. In low-power applications such as portable audio devices, the output stage is generally implemented as a full-bridge output stage, and a load such as a speaker is coupled in a bridge-connected load configuration between a first half-bridge and a second half-bridge.

[0004] FIG. 1 is a schematic diagram of a full-bridge output stage 100 including a first half-bridge 110 and a second half-bridge 120, which together provide a differential output voltage Vout for driving a bridge-connected load 130 (e.g., a loudspeaker), and the bridge-connected load 130 can be coupled between respective output nodes 112, 122 of the first and second half-bridges 110, 12^{}

[0005] The first half-bridge 110 includes a high-side switch 114 connected in series with a low-side switch 116 between a first supply voltage (VDD) rail 142 and a reference voltage (e.g., GND) rail 144 of the output stage 100. The high-side switch 114 and the low-side switch 116 may be, for example, complementary MOSFET devices.

[0006] Similarly, the second half-bridge 120 includes a high-side switch 124 connected in series with a complementary low-side switch 126 between the first supply voltage (VDD) rail 142 and the reference voltage (e.g., GND) rail 144 of the output stage 100. Again, the high-side switch 124 and the low-side switch 126 may be, for example, complementary MOSFET devices.

[0007] Using the output stage 100, control signals, such as pulse-width modulation (PWM) signals, are supplied to the control terminals (e.g., gate terminals) of the high-side switch 114 and low-side switch 116 of the first half-bridge 110, and to the control terminals (e.g., gate terminals) of the high-side switch 124 and low-side switch 126 of the second half-bridge 120. The control signals are configured such that when the high-side switch 114 is switched on in response to the control signals at its control terminals, the low-side switch 116 is switched off, and vice versa. Thus, during the operation of the first half-bridge 110, the output node 112 becomes either the first supply voltage (VDD) or a reference voltage (e.g., GND), depending on whether the high-side switch 114 or the low-side switch 116 is switched on. Similarly, during the operation of the second half-bridge 120, the output node 122 becomes either the first supply voltage (VDD) or a reference voltage (e.g., GND), depending on whether the high-side switch 124 or the low-side switch 126 is switched on. Thus, the output voltage Vout across the load 130 can take any of three levels: +VDD, -VDD, or 0V (assuming the reference voltage rail 144 is connected to GND).

[0008] In some low-power applications, the output stage 100 can be implemented in an integrated circuit (e.g., a single integrated circuit) that includes switches 114, 116, 124, and 126. In some examples, such an integrated circuit may also include modulation circuits for supplying control signals to switches 114, 116, 124, and 126 of the output stage 100.

[0009] For higher power applications (e.g., automotive audio applications), it may be beneficial to use a single-ended output stage of the type schematically shown in Figure 2.

[0010] As shown in Figure 2, the single-end output stage 200 in this example includes a half-bridge 210 having a high-side switch 212 connected in series with a complementary low-side switch 214 between the first positive (+VDD) supply voltage rail 222 and the second negative (-VDD) supply voltage rail 224 of the single-end output stage 200. The high-side switch 212 and the low-side switch 214 may be, for example, complementary MOSFET devices.

[0011] In the use of a single-ended output stage 200, a load 230, such as a loudspeaker, is coupled between the output node 216 of the half-bridge 210 and the reference voltage (e.g., GND) rail 226 of the single-ended output stage 200. In the example shown in Figure 2, a low-pass filter circuit 240, including an inductor 242 and a capacitor 244, is coupled between the output node 216 and the load 230 to attenuate high-frequency components that may be present in the output signal of the half-bridge 210 due to the switching frequencies of switches 212, 214.

[0012] Unlike the full-bridge output stage 100 in Figure 1, the single-end output stage 200 in Figure 2 requires a negative (-VDD) supply voltage rail 224. As those skilled in the art will understand, this can increase the complexity of the single-end output stage 200 compared to the full-bridge output stage 100 in Figure 1. However, the single-end output stage 200 is more cost-effective than the full-bridge output stage 100. In particular, when multiple channels are required (for example, in applications such as multi-channel audio systems that drive multiple different loads such as speakers), it may be more cost-effective to use one single-end output stage of the type shown in Figure 2 for each channel and share the negative (-VDD) supply voltage rail 224 among all channels than to have multiple full-bridge output stages.

[0013] In the operation of the single-ended output stage 200, a control signal (e.g., a PWM signal) is supplied to the control terminals (e.g., gate terminals) of the high-side switch 112 and low-side switch 114 of the half-bridge 210. The control signal is configured such that when the high-side switch 212 is switched on in response to the control signal at its control terminal, the low-side switch 214 is switched off, and vice versa. Thus, during the operation of the half-bridge 210, the output node 216 will have either a first supply voltage (+VDD) or a second supply voltage (-VDD), depending on whether the high-side switch 212 or the low-side switch 214 is switched on. Therefore, the output voltage Vout across the load 230 can take one of two levels, +VDD or -VDD.

[0014] In some examples, the single-end output stage 200 can be implemented within an integrated circuit (for example, as a single integrated circuit incorporating a high-side switch 212 and a low-side switch 214, and further a modulation circuit for generating control signals supplied to switches 212 and 214), while the low-pass filter circuit 240 is typically implemented using discrete components that are not implemented within an integrated circuit (i.e., the inductor 242 and capacitor 244 of the low-pass filter circuit 240 are typically off-chip devices). However, in other examples, the single-end output stage 200 can be implemented using entirely off-chip devices, particularly in high-power applications where the cost of on-chip switches may be higher than that of off-chip switches.

[0015] The drawback of the single-ended output stage 200 in Figure 2 is that the repeated switching of the output voltage Vout between +VDD and -VDD causes fluctuations in the current flowing through the inductor 242 of the low-pass filter circuit 240, which manifests as a ripple current through the load 230, resulting in a ripple current flowing through the load 230. This load ripple current is due to the power (I 2 This can lead to losses in R), which are particularly noticeable in cases using higher power, such as in automotive applications. [Overview of the Initiative]

[0016] According to a first aspect, the present invention provides a switching transducer driver that can operate in a first mode in which the first and second output stage switches are controlled to produce two levels of output signals, wherein the impedance of the first output stage switch is substantially the same as the impedance of the second output stage switch; and a second mode in which the first and second output stage switches and a third switch are controlled to produce three levels of output signals, wherein the impedance of the third switch is substantially greater than the impedances of the first and second output stage switches.

[0017] The switching transducer driver may be capable of operating at a first frequency in the first mode, and at a second frequency in the second mode.

[0018] The second frequency may be lower than the first frequency.

[0019] The first and second output stage switches may be implemented using wide-bandgap devices or high-electron-mobility transistor (HEMT) devices.

[0020] The impedance of the third switch may be at least twice the impedance of the first output stage switch and / or the second output stage switch.

[0021] The switching transducer driver may include a control circuit configured to select between a first mode and a second mode based on the parameters of the input signal to the switching transducer driver.

[0022] The parameters of the input signal may include the magnitude, level, envelope, or volume of the input signal.

[0023] The control circuit may include a modulation circuit configured to receive an input signal and a carrier signal and generate a modulated output signal based on the input signal and the carrier signal.

[0024] The modulation circuit may include a variable phase shift element configured to generate a phase shift version of the carrier signal, a first comparator configured to generate a first comparison output signal based on a comparison between the input signal and the carrier signal, and a second comparator configured to generate a second comparison output signal based on a comparison between the input signal and the phase shift version of the carrier signal, and the modulated output signal is based on the first comparison output signal and the second comparison output signal.

[0025] The control circuit may operate to generate a control signal for controlling the phase shift applied to the carrier signal by the variable phase shift element to generate the phase shift version of the carrier signal, and the control signal is based on a parameter of the input signal.

[0026] The control signal may represent a variable α that controls the phase shift applied by the variable phase shift element.

[0027] The variable α may be based on a comparison between a parameter of the input signal and a threshold value. When the parameter of the input signal is greater than or equal to a first threshold value, the variable α is equal to 0, and when the parameter of the input signal is less than the first threshold value, the variable α is equal to 1.

[0028] The value of α may be variable over a continuous range based on a parameter of the input signal, and the continuous range is between 0 and an upper limit value of 1 or less.

[0029] The modulation circuit may include an open-loop modulation circuit.

[0030] The switching transducer driver may be operable in a third mode in which the output of the switching transducer driver is clamped to a reference voltage.

[0031] The switching transducer driver may be configured to operate in a third mode when the parameters of the input signal are below a second threshold.

[0032] The third switch may be of a different device type or technology than the first and second output stage switches.

[0033] The third switch may be implemented using one or more MOSFET devices.

[0034] The third switch may be implemented using a wide-bandgap device or a HEMT device, and the characteristics of the third switch are inferior to the corresponding characteristics of the first and second output stage switches.

[0035] The third switch may be implemented as a switch connected in antiparallel.

[0036] According to a second aspect, the present invention provides a module comprising a circuit board on which a third switch and first and second output stage switches of the switching transducer driver of the first aspect are mounted.

[0037] According to a third aspect, the present invention provides a switching transducer driver that can operate in an active mode in which first and second output stage switches are controlled to generate two levels of output signals, and a quiescent mode in which a third switch is controlled to clamp the output of the switching transducer driver to a reference voltage.

[0038] According to a fourth aspect, the present invention provides an integrated circuit comprising a control circuit for supplying control signals to a first output stage switch, a second output stage switch, and a third switch, wherein the impedance of the first output stage switch is substantially the same as that of the second output stage switch, and the impedance of the third switch is greater than that of the first and second output stage switches, and the control circuit is operable to select between a first operating mode in which the first and second output stage switches are controlled to produce two levels of output signals, and a second operating mode in which the first and second output stage switches and the third switch are controlled to produce three levels of output signals.

[0039] The integrated circuit may also include a third switch.

[0040] According to a fifth aspect, the present invention provides a host device equipped with a switching transducer driver according to the first aspect.

[0041] The host device may include laptops, notebooks, netbooks or tablet computers, in-car systems, vehicle audio systems, game devices, game consoles, game console controllers, virtual reality (VR) devices or augmented reality (AR) devices, mobile phones, portable audio players, portable devices, or accessory devices for use with laptops, notebooks, netbooks or tablet computers, game devices, game consoles, VR devices or AR devices, mobile phones, portable audio players or other portable devices.

[0042] According to a sixth aspect, the present invention provides a Class D amplifier circuit configured to receive an input signal and output an output signal, the Class D amplifier circuit comprising a first output stage switch, a second output stage switch, and a third switch, wherein the characteristics of the third switch are inferior to the corresponding characteristics of the first and second output stage switches, and the Class D amplifier circuit is selectively operable in either a first or second operating mode based on parameters of the input signal.

[0043] According to a seventh aspect, the present invention provides a Class D amplifier circuit configured to receive an input signal and output an output signal, the Class D amplifier circuit comprising a first output stage switch, a second output stage switch, a third switch, and a control circuit, the first and second output stage switches being implemented using wide bandgap devices or high electron mobility transistor (HEMT) devices, and the control circuit being configured to select between a first operating mode and a second operating mode of the Class D amplifier circuit based on parameters of the input signal.

[0044] Throughout this specification, it will be understood that the word “prepare,” or variations such as “prepare” or “prepare,” include a predetermined element, integer, or step, or group of elements, groups of integers, or groups of steps, but do not mean to exclude any other element, integer, or step, or group of elements, groups of integers, or groups of steps.

[0045] Embodiments of the present invention will be described with reference to the accompanying drawings, strictly for illustrative purposes only. [Brief explanation of the drawing]

[0046] [Figure 1] This is a schematic diagram of a full-bridge output stage for use as the output stage of a Class D amplifier. [Figure 2] This is a schematic diagram of a half-bridge output stage for use as the output stage of a Class D amplifier. [Figure 3] This is a schematic diagram of the switching transducer driver circuit according to this disclosure. [Figure 4] Figure 3 is a schematic diagram of the control circuit for supplying control signals to the switching transducer driver. [Figure 5] Figure 4 shows the effect of different values ​​of the variable α on the output signal of the modulation circuit in the control circuit. [Figure 6a] Figure 3 illustrates different approaches to switching between the operating modes of the switching transducer driver. [Figure 6b] Figure 3 illustrates different approaches to switching between the operating modes of the switching transducer driver. [Figure 7] Figure 3 is a schematic diagram of an antiparallel switch configuration that can be used with the switching transducer driver. [Modes for carrying out the invention]

[0047] Figure 3 is a schematic diagram of the switching transducer driver according to this disclosure.

[0048] The switching transducer driver in this example is generally implemented as a Class D amplifier circuit, as shown in Figure 300. The Class D amplifier circuit 300 includes a halfbridge 310 with a high-side switch 312 and a low-side switch 314 connected in series between a first positive (+VDD) power rail 322 and a second negative (-VDD) power rail 324, the output node 316 of the halfbridge 310 is coupled to a first terminal of a load 330 via a low-pass filter circuit 340 (with an inductor 342 and a capacitor 344), and the load has a second terminal coupled to a reference voltage (e.g., GND) rail 326.

[0049] The Class D amplifier circuit 300 in Figure 3 further comprises a third switch 350 having an input terminal coupled to a reference voltage (e.g., GND) rail 326 and an output terminal coupled to the output node 316 of the half-bridge 310.

[0050] The Class D amplifier circuit 300 further comprises a control circuit 360 configured to control the operating mode of the Class D amplifier circuit 300. In some examples, the control circuit 360 can control the operating mode of the Class D amplifier circuit 300 based on parameters such as the signal level, magnitude, envelope, or volume of the input signal.

[0051] The Class D amplifier circuit 300 in Figure 3 is configured to operate at relatively high output power. For example, the positive supply voltage +VDD and the negative supply voltage -VDD may each have a magnitude of 50V DC or greater. Therefore, the high-side switch 312 and the low-side switch 314 are configured to operate at such voltages. In some examples, the high-side switch 312 and the low-side switch 314 may be wide-bandgap devices or high-electron-mobility transistor (HEMT) devices based on semiconductor materials such as gallium nitride (GaN), silicon carbide (SiC), gallium oxide (Ga2O3), or other semiconductor materials. Since such devices can typically operate at higher voltages, temperatures, and frequencies than silicon-based switches such as MOSFETs, they can provide a more cost-effective solution than silicon-based devices for high-power applications (e.g., applications with a supply voltage magnitude of 50V DC or greater). The circuit area occupied by switches 312 and 314 in the type of switching transducer driver shown in Figure 3 can be minimized or at least reduced by using switches with higher resistance; however, as the resistance of the switches increases, the supply voltage also increases. For example, if the resistance of switches 312 and 314 is doubled, the required supply voltage also doubles. When switches 312 and 314 are implemented as GaN devices, this trade-off between switch size and supply voltage is manageable and acceptable.

[0052] When the Class D amplifier circuit 300 is in use, the control circuit 360 supplies control signals C1, C2, and C3 to the control terminals of the high-side switch 312, the low-side switch 314, and the third switch 350. Since the control signals C1, C2, and C3 are configured to instantly switch only one of the high-side switch 312, the low-side switch 314, and the third switch 350 to the ON position, the output voltage Vout across the load 330 can take one of three values: +VDD (when the high-side switch 312 is switched ON and both the low-side switch 314 and the third switch 350 are switched OFF), -VDD (when the low-side switch 314 is switched ON and both the high-side switch 312 and the third switch 350 are switched OFF), or 0V (when both the high-side switch 312 and the low-side switch 314 are switched OFF and the third switch 350 is switched ON). These three output voltage values ​​can be used to encode three different values. For example, output voltage +VDD can represent a value of +1, output voltage -VDD can represent a value of -1, and output voltage 0 can represent a value of 0.

[0053] Therefore, the Class D amplifier circuit 300 can operate in a first mode having two output voltage levels when the third switch 350 is held open (i.e., switched off). The Class D amplifier circuit 300 can also operate in a second mode having three output voltage levels. In applications such as audio amplifiers, at high input signal levels (e.g., high-volume audio signals), only +VDD and -VDD output voltages may be required because at high input signal levels, there are relatively few input signal states that require a 0V output stage. Conversely, at low input signal levels (e.g., lower-volume audio signals), a 0V output voltage may also be required because at low input signal levels, there are more input signal states that require a 0V output stage.

[0054] Therefore, the control circuit 360 can operate to control the operating mode of the Class D amplifier circuit 300 based on the level of the input signal level SIn. If the parameters of the input signal (e.g., level, magnitude, envelope, volume, or some other characteristic or parameter) are greater than or equal to a threshold, the control circuit 360 can generate control signals C1, C2, and C3 to cause the Class D amplifier circuit 300 to operate in a first mode having two output signal levels. In this case, the control signal C3 supplied to the third switch 350 causes the third switch 350 to remain open or off, preventing the output node 316 from being coupled to the reference voltage (e.g., GND) rail 326, thereby preventing a 0V output state. Conversely, if the parameters of the input signal are less than a threshold, the control circuit 360 can generate control signals C1, C2, and C3 to cause the Class D amplifier circuit 300 to operate in a second mode having three output signal levels.

[0055] The control circuit 360 may include a pulse width modulation circuit for generating a PWM signal S based on an input signal and one or more carrier signals. The control circuit 360 may further include logic circuits for generating control signals C1, C2, and C3 from the PWM signal generated by the pulse width modulation circuit.

[0056] The advantage of operating in the first mode, which has only two output signal levels, is improved linearity compared to operating in the second mode, which has three output signal levels. Switching between two different voltages is inherently linear, but switching between three voltages may require component matching to produce a linearized output. This is particularly important when switches 312 and 314 are off-chip and when the modulator / amplifier (e.g., the PWM modulation circuit in control circuit 360) is operating in open-loop mode.

[0057] Figure 4 is a schematic diagram of the control circuit of the Class D amplifier circuit 300 shown in Figure 3. Generally, as shown in Figure 400, the control circuit in this example includes an open-loop PWM modulation circuit 410, a logic circuit 440, and a phase shift control circuit 450.

[0058] The PWM modulation circuit 410 in this example includes first and second comparators 412 and 414, a subtractor 416, and a variable phase shift element 418. The input of the variable phase shift element 418 is coupled to the carrier input node 420 of the PWM modulation circuit 410, and the output of the variable phase shift element 418 is coupled to the inverting (-) input of the second comparator 414. The carrier input node 420 is also coupled to the non-inverting (+) input of the first comparator 412. The input signal node 422 is coupled to the inverting (-) input of the first comparator 412 and the non-inverting (+) input of the second comparator 414. The outputs of the first and second comparators 412 and 414 are coupled to the first and second inputs of the subtractor 416, respectively. The output of the subtractor 416 is coupled to the input of the logic circuit 440.

[0059] Using the control circuit 400, a carrier signal SC, which may be, for example, a triangular wave signal, a sawtooth wave signal, or some other periodic reference signal, is supplied to the carrier input node 420 of the PWM modulation circuit 410, thereby transmitted to the non-inverting (+) input of the first comparator 412 and the input of the variable phase shift element 418.

[0060] The variable phase shift element 418 is configured to apply a phase shift Φ between 0 and π (i.e., between 0 and 180°) to the carrier signal SC received at its input, and to output the phase-shifted version SC' of the carrier signal SC to the inverting (-) input of the second comparator 414. As will be understood by those skilled in the art, the variable phase shift element 418 can be implemented in various ways. For example, the variable phase shift element 418 can be implemented by a programmable delay circuit, an all-pass filter circuit with variable phase, a unity-gain amplifier circuit with variable phase, and the like.

[0061] The phase shift Φ applied by the variable phase shift element 418 can be defined as Φ = α·π, where α is a variable having a value between 0 and 1, depending on the parameters of the input signal SIn. For example, α may depend on the magnitude, level, envelope, or volume of the input signal SIn, and thus the phase shift Φ applied by the variable phase shift element depends on the magnitude, level, envelope, or volume of the input signal SIn. The variable phase shift element 418 receives a control signal from the phase shift control circuit 450 indicating the value α, and controls or adjusts the phase shift Φ applied to the received carrier signal SC based on this received control signal.

[0062] For example, an input signal SIn, which may be an audio input signal, is supplied to the input signal node 422, thereby being transmitted to the inverting (-) input of the first comparator 412 and the non-inverting (+) input of the second comparator 414.

[0063] Therefore, the first comparator 412 generates a first comparison output signal VP based on a comparison between the input signal SIn and the carrier signal SC, where the first comparison output signal VP takes a high value (e.g., logic 1) when the magnitude of the carrier signal SC is greater than the magnitude of the input signal SIn, and a low value (e.g., logic 0) when the magnitude of the carrier signal SC is less than the magnitude of the input signal SIn. This can be expressed as VP = SC - SIn > 0.

[0064] Similarly, the second comparator 412 generates a second comparison output signal VN based on a comparison of the input signal SIn with the phase-shifted version SC' of the carrier signal SC, where the second comparison output signal VN takes a high value (e.g., logic 1) if the magnitude of the input signal SIn is greater than the magnitude of the phase-shifted version SC' of the carrier signal SC, and the second comparison output signal VN takes a low value (e.g., logic 0) if the magnitude of the input signal SIn is less than the magnitude of the phase-shifted version SC' of the carrier signal SC. This is given by VN = SIn - SCe - iΦ It can be represented as >0.

[0065] The subtractor 416 subtracts the second comparison output signal VN from the first comparison output signal VP to generate a PWM output signal S, such that S = VP - VN.

[0066] The PWM output signal S is received by a logic circuit 440 configured to generate control signals C1, C2, and C3 for switches 312, 314, and 350 of the Class D amplifier circuit 300 based on the received PWM output signal S.

[0067] Figure 5 shows the effect of different values ​​of α on the output signal S. As is evident from the signal trace shown in Figure 5, when α is equal to 0, the PWM output signal S can take on one of two states, as shown as +1 and -1 in Figure 5 (i.e., the modulation circuit 410 operates as a two-level modulator). Thus, when α is equal to 0, the Class D amplifier circuit 300 operates in its first mode, in which the output signal supplied to the load 330 can take on one of two levels, based on the respective states (on / off) of the high-side switch 312 and the low-side switch 314.

[0068] In contrast, when α is greater than 0, the PWM output signal S can take on any one of three states shown in Figure 5 as +1, -1, and 0 (i.e., the modulation circuit 410 operates as a three-level modulator), and the larger the value of α, the more frequently the 0 state occurs. Therefore, when α is greater than 0, the Class D amplifier circuit 300 operates in its second mode, in which the output signal supplied to the load 330 can take on one of three levels based on the state (on / off) of the high-side switch 312, the low-side switch 314, and the third switch 350, respectively.

[0069] The logic circuit 440 is configured to generate control signals C1, C2, and C3 for switches 312, 314, and 350 of the Class D amplifier circuit 300 based on the received PWM output signal S. For example, the logic circuit 440 can be configured to output a control signal C1 that turns on the high-side switch 312 and control signals C2 and C3 that turn off the low-side switch 314 and the third switch 350 when the PWM output signal S adopts a first state (for example, the +1 state shown in Figure 5), to output a control signal C2 that turns on the low-side switch 314 and control signals C1 and C3 that turn off the high-side switch 312 and the third switch 350 when the PWM output signal S adopts a second state (for example, the -1 state shown in Figure 5), and to output control signals C3 that turns on the low-side switch 314 and the high-side switch 312 and the third switch 350 when the PWM output signal S adopts a third state (for example, the 0 state shown in Figure 5), to output a control signal C3 that turns on the third switch 350 and control signals C1 and C2 that turn off the high-side switch 312 and the low-side switch 314.

[0070] As described above, for relatively large input signals, a zero state in the PWM output signal S is usually not required. Therefore, for such input signals, the phase shift Φ can be set to 0. Conversely, for relatively small input signals, a zero state in the PWM output signal may be required to a greater or lesser extent, depending on the magnitude of the input signal. Therefore, the phase shift Φ can be set to a value greater than 0 for such input signals.

[0071] For this purpose, the phase shift control circuit 450 is configured to generate a control signal indicating a value α based on parameters such as the magnitude, level, envelope, or volume of the input signal SIn. In some examples, the phase shift control circuit 450 is configured to compare the parameters of the input signal SIn with a first predefined threshold parameter value TH1, and if the parameters of the input signal SIn are greater than or equal to the first predefined threshold parameter value TH1, to change the value α from 0 to 1, as shown in Figure 6a. In other examples, as illustrated in Figure 6b, the phase shift control circuit 450 is configured to monitor the parameters of the input signal and adjust the value α over a continuous range between 0 and an upper limit (e.g., 1) as a function of the parameters of the input signal. In both of these examples, the phase shift control circuit 450 is configured to determine the value α based on the parameters of the input signal SIn and generate a control signal indicating the value α to output to the variable phase shift element 418. In some cases, it may be advantageous to set the upper limit of α to less than 1 to prevent the phase shift Φ from becoming π (180°) (for example, the value α may be adjustable over a range of 0 to 0.8, 0.9, or other upper limits less than 1), thereby preventing minute pulses in the output signal S output by the modulation circuit 410.

[0072] The point or threshold at which the modulation circuit 410 switches between 2-level and 3-level modulation of the input signal SIn is a function of the on-resistance of the third switch 350. This point or threshold reduces the ripple current through the load 330 (and the associated distortion of the output of the load 330), thereby reducing the resistance (I) in the load 330. 2 R) Suppressing power consumption of the load due to losses, and resistance (I) that may occur when the third switch 350 is used to provide a state of 0 in the PWM output signal S. 2 R) should be selected to balance the increase in power consumption resulting from the increase in losses, thereby achieving a reduction in the overall power consumption of the Class S amplifier circuit 300.

[0073] In some examples, the Class D amplifier circuit 300 may also be capable of operating in a third mode, in which the input of the Class D amplifier circuit 300 (and possibly the output of the Class D amplifier circuit 300 as well) is clamped to a reference voltage (e.g., GND) rail 326 or some other reference voltage source. The third mode can be entered if the parameters of the input signal Sin (e.g., magnitude, signal level, envelope, or volume) are less than a second predefined threshold parameter value TH2, which indicates that the input signal Sin does not represent a signal being amplified. Thus, if the parameters of the input signal Sin are less than the second predefined threshold parameter value TH2, the control circuit 360 outputs a control signal C3 to the third switch 350, causing the third switch 350 to close, thereby clamping the input of the Class D amplifier circuit 300 to a reference voltage (e.g., GND) rail 326.

[0074] In some examples, the output of the Class D amplifier circuit 300 may be clamped to a reference voltage (e.g., GND) rail 326 or some other reference voltage source in a third operating mode, in addition to clamping the input of the Class D amplifier circuit 300, or instead of clamping the input of the Class D amplifier circuit 300. For this purpose, the Class D amplifier circuit 300 may include a fourth switch 370 coupled between the output of the low-pass filter circuit 340 and the reference voltage (e.g., GND) rail 326. If the parameter of the input signal SIn is less than a second predefined threshold parameter value TH2, the control circuit 360 outputs a control signal C4 to the fourth switch 370 to close the fourth switch 370, thereby clamping the output of the Class D amplifier circuit 360 to the reference voltage (e.g., GND) rail 326.

[0075] In some examples, the Class D amplifier circuit 300 can be made to operate only in the first and third modes described above. In such examples, the first mode may be called the active mode, and the third mode may be called the quiescent mode. In such examples, the control circuit 360 may operate to control the operating mode of the Class D amplifier circuit 300 based on the parameters of the input signal SIn. If the parameters of the input signal SIn (e.g., level, magnitude, envelope, volume, or some other characteristic or parameter) are greater than or equal to a threshold, the control circuit 360 may generate control signals C1, C2, and C3 to cause the Class D amplifier circuit 300 to operate in the first (active) mode having two output signal levels. In this case, the control signal C3 supplied to the third switch 350 causes the third switch 350 to remain open or off, preventing the output node 316 from being coupled to the reference voltage (e.g., GND) rail 326, thereby preventing a 0V output state. In contrast, if the parameters of the input signal are below a threshold, the control circuit 360 can generate a control signal C4 to cause the Class D amplifier circuit 300 to operate in its third (static) mode, and by closing the fourth switch 370, the output of the Class D amplifier circuit 300 can be clamped to a reference voltage (e.g., GND) rail 326. In this mode as well, the control circuit 360 can generate a control signal C3 to clamp the input of the Class D amplifier circuit 300 to a reference voltage (e.g., GND) rail 326.

[0076] In a practical implementation of the Class D amplifier circuit 300 in Figure 3, the high-side switch 312, the low-side switch 314, and the third switch 350 may be of the same device type or technology. However, to minimize or at least reduce costs compared to using devices with the same characteristics for each of the high-side switch 312, the low-side switch 314, and the third switch 350, the characteristics of the third switch 350 may be inferior to the corresponding characteristics of the high-side switch 312 and the low-side switch 314.

[0077] For example, to minimize or reduce the cost of the Class D amplifier circuit 300, the high-side switch 312 and the low-side switch 314 can be implemented using wide-bandgap devices or HEMT devices with impedances of several milliohms or tens of milliohms (e.g., on-resistance such as drain-source resistance Rds), while the third switch 350 can be implemented using a lower-cost wide-bandgap device or HEMT device with a higher on-resistance of tens of milliohms or hundreds of milliohms. The on-resistance of the third switch 350 may be at least twice, and may be significantly greater than twice, the on-resistance of the high-side switch 312 and the low-side switch 314. As an exemplary example, the on-resistance of the high-side switch 312 and the low-side switch may be around 70 milliohms, while the on-resistance of the third switch 350 may be 140 milliohms or more, for example, 500 milliohms.

[0078] In such an embodiment of the Class D amplifier circuit 300, the threshold at which the modulation circuit 410 switches between two-level modulation and three-level modulation should be selected such that the benefit of reduced output ripple current at low input signal levels outweighs the drawback of increased power consumption resulting from using the third switch 350 (and its larger on-resistance) to provide a zero state for the PWM output signal S at low signal levels.

[0079] In other examples, the third switch 350 may consist of a different device type or technology than the high-side switch 312 and the low-side switch 314. For example, the high-side switch 312 and the low-side switch 314 can be implemented using wide-bandgap devices or HEMT devices (e.g., GaN-based devices), while the third switch 350 can be implemented using one or more MOSFET devices or one or more wide-bandgap devices or HEMT devices based on a different semiconductor material, e.g., SiN. In such examples, the threshold at which the modulation circuit 410 switches between two-level modulation and three-level modulation should again be selected to balance the advantage of reduced output ripple current at low input signal levels with the disadvantage of increased power consumption at low signal levels.

[0080] Furthermore, in such examples, the impedance (e.g., on-resistance) of the third switch 350 will not differ significantly from the corresponding impedances (e.g., on-resistance) of the high-side switch 312 and the low-side switch 314, but the third switch 350 may have a lower (perhaps significantly lower) maximum switching speed than the high-side switch 312 and the low-side switch 314. Therefore, in such examples, the maximum switching speed that can be supported by the high-side switch 312 and the low-side switch 314 may be faster than the maximum switching speed that can be supported by the third switch 350, so it may be beneficial to reduce the switching frequency, speed, or edge rate of the control circuit 360 when switching to 3-level modulation. Thus, by reducing the switching speed or edge rate of the control circuit 360, it is ensured that the control signals C1, C2, and C3 output by the control circuit 360 have a switching speed or edge rate that is applicable to all switches 312, 314, and 350. For example, when operating in the first (2-level modulation) mode, the switching frequency, speed, or edge rate can be approximately 1 MHz or higher, and when operating in the second (3-level modulation) mode, the switching frequency, speed, or edge rate can be approximately 100 kHz.

[0081] In some examples, particularly for low-power applications, the high-side switch 312, the low-side switch 314, and the third switch can all be implemented using MOSFET devices. In such examples, the Class D amplifier circuit 300 can be implemented in a single integrated circuit. In such examples, the control circuit 360 can also be implemented in the same integrated circuit as the Class D amplifier circuit. In examples where only the third switch 350 is implemented using a MOSFET device, the third switch 350 can be implemented in an integrated circuit, for example, a single integrated circuit that can also implement the control circuit 360.

[0082] Accordingly, the disclosure extends to an integrated circuit including a control circuit of the kind described herein for supplying control signals to the high-side switch 312, the low-side switch 314, and the third switch 350, the control circuit being operable to select between the first and second operating modes and / or between the first and third operating modes. The integrated circuit may include a drive circuit for driving the control terminals (e.g., gate terminals) of the high-side switch 312 and the low-side switch 314. Additionally or alternatively, the integrated circuit may include the third switch 350.

[0083] The disclosure extends to modules including substrates such as printed circuit boards (PCBs), on which a third switch 350 (either a discrete circuit or an integrated circuit when implemented using a MOSFET device), a high-side switch 312, and a low-side switch 314 are mounted and coupled to appropriate connection circuits such as conductive tracks or traces.

[0084] In the example illustrated in Figure 3, the third switch 350 is shown as a single switch. However, in some examples, the third switch may be implemented as two antiparallel connected switches, as shown in Figure 7, to prevent reverse current flow through the body diode of the third switch 350 when the third switch 350 is switched off. Thus, the third switch 350 may be implemented as a combination of a first MOSFET device 350a and a second MOSFET device 350b, where the source terminals of the first and second MOSFET devices 350a and 350b are coupled to each other, such that the anode of the body diode of the first MOSFET device 350a is coupled to the anode of the body diode of the second MOSFET device 350b. As will be understood by those skilled in the art, in other examples, the first and second MOSFET devices 350a and 350b may be connected such that the direction of the body diodes is reversed compared to the example in Figure 7, according to the structure of the gate driver that drives the switch.

[0085] In the example described above with reference to Figure 4, the operating mode of the switching transducer driver is controlled by adjusting the phase shift applied to the carrier supplied to the second comparator 414 of the PWM modulation circuit 410. However, as will be understood by those skilled in the art, other approaches are possible for controlling the operating mode of the switching transducer (e.g., using a self-oscillating modulator with a coupled quantizer). Therefore, it should be understood that the PWM modulation circuit 410 is merely one example of a possible approach for controlling the operating mode of the switching transducer driver of this disclosure, and alternative approaches can be adopted as well.

[0086] Referring to the attached drawings, the circuits described above may be incorporated into host devices such as laptops, notebooks, netbooks or tablet computers, in-vehicle systems such as audio systems in vehicles, gaming devices such as game consoles or game console controllers, virtual reality (VR) devices or augmented reality (AR) devices, mobile phones, portable audio players or some other portable devices, or they may be incorporated into accessory devices for use with laptops, notebooks, netbooks or tablet computers, gaming devices, VR devices or AR devices, mobile phones, portable audio players or other portable devices.

[0087] Those skilled in the art will recognize that some embodiments of the apparatus and methods described above can be embodied as processor control code in a non-volatile carrier medium such as a disk, CD-ROM or DVD-ROM, programmed memory such as read-only memory (firmware), or data carriers such as optical or electrical signal carriers. In many applications, embodiments of the present invention are implemented in a DSP (Digital Signal Processor), ASIC (Application-Specific Integrated Circuit), or FPGA (Field-Programmable Gate Array). Thus, the code may include conventional program code or microcode, or code for setting up or controlling, for example, an ASIC or FPGA. The code may also include code for dynamically configuring a reconfigurable device, such as a reprogrammable logic gate array. Similarly, the code may include code in a hardware description language such as Verilog® or VHDL (Very High-Speed ​​Integrated Circuit Hardware Description Language). As those skilled in the art will understand, the code may be distributed among multiple coupled components communicating with one another. If necessary, embodiments may also be implemented using code executed on a field (re)programmable analog array or similar device to configure analog hardware.

[0088] It should be noted that, as used herein, the term "module" is used to refer to a functional unit or block that can be at least partially implemented by a dedicated hardware component, such as a custom-defined circuit, and / or by appropriate code that runs on one or more software processors or suitable general-purpose processors. A module may itself contain other modules or functional units. A module may be provided by multiple components or submodules that do not need to be located in the same place, are provided on different integrated circuits, and / or run on different processors.

[0089] Where used herein, if two or more elements are referred to as “joined” together, such term indicates that such two or more elements are in an electronic or mechanical communication relationship, whether indirect or direct, with or without intervening elements, where applicable.

[0090] This disclosure includes all modifications, substitutions, alterations, and modifications to the exemplary embodiments of this specification as understandable to those skilled in the art. Similarly, where appropriate, the appended claims include all modifications, substitutions, alterations, and modifications to the exemplary embodiments of this specification as understandable to those skilled in the art. Furthermore, any reference in the appended claims to a device or system, or a component of a device or system, that is adapted, positioned, enabled, configured, activated, or operable to perform a particular function, includes that device, system, or component, insofar as it is adapted, positioned, enabled, configured, activated, operable, or operable, regardless of whether that device, system, or component, or its particular function, is activated, turned on, or unlocked. Thus, modifications, additions, or omissions can be made to the systems, devices, and methods described herein without departing from the scope of the disclosure. For example, components of systems and devices may be integrated or separated. Furthermore, the operation of the systems and apparatus disclosed herein may be performed by more, fewer, or other components, and the methods described may include more, fewer, or other steps. Furthermore, the steps may be performed in any suitable order. As used in this document, “each” refers to each member of a set, or each member of a subset of a set.

[0091] While exemplary embodiments are illustrated in the drawings and described below, the principles of this disclosure can be carried out using any number of techniques, whether currently known or not. This disclosure should not be limited in any way to the exemplary embodiments and techniques illustrated in the drawings and described above.

[0092] Unless otherwise specified, the items depicted in the drawings are not necessarily drawn to scale.

[0093] All examples and conditional language listed herein are intended for educational purposes to help the reader understand the disclosure and the concepts to which the inventors contribute to advance the art, and are not limited to such specifically listed examples and conditions. While embodiments of the disclosure are described in detail, it should be understood that various changes, substitutions, and modifications are possible without departing from the spirit and scope of the disclosure.

[0094] While certain advantages are listed above, various embodiments may include some, none, or all of the listed advantages. Furthermore, other technical advantages may become readily apparent to those skilled in the art after the overview of the figures and descriptions described above.

[0095] It should be noted that the embodiments described above are illustrative and not limiting to the present invention, and that those skilled in the art can design many alternative embodiments without departing from the scope of the appended claims. The word “equipped with” does not exclude the existence of elements or steps other than those listed in the claims, and “one” or “single” does not exclude multiple, and a single feature or other unit may perform the functions of multiple units described in the claims. No reference numeral or designation in the claims should be construed as limiting its scope.

Claims

1. A switching transducer driver, A first mode in which the first and second output stage switches are controlled to generate two levels of output signals, wherein the impedance of the first output stage switch is substantially the same as the impedance of the second output stage switch, A second mode in which the first and second output stage switches and the third switch are controlled to generate three levels of output signals, wherein the impedance of the third switch is substantially greater than the impedances of the first and second output stage switches, A switching transducer driver that can operate in this environment.

2. The switching transducer driver according to claim 1, wherein the switching transducer driver is capable of operating at a first frequency in the first mode and at a second frequency in the second mode.

3. The switching transducer driver according to claim 2, wherein the second frequency is lower than the first frequency.

4. The switching transducer driver according to any of the prior claims, wherein the first output stage switch and the second output stage switch are implemented using wide bandgap devices or high electron mobility transistor (HEMT) devices.

5. The switching transducer driver according to any of the prior claims, wherein the impedance of the third switch is at least twice the impedance of the first output stage switch and / or the second output stage switch.

6. The switching transducer driver according to any one of the prior claims, comprising a control circuit configured to select between the first mode and the second mode based on the parameters of the input signal to the switching transducer driver.

7. The switching transducer driver according to claim 6, wherein the parameters of the input signal include magnitude, level, envelope, or volume of the input signal.

8. The switching transducer driver according to claim 6 or 7, wherein the control circuit includes a modulation circuit configured to receive the input signal and the carrier signal and generate a modulated output signal based on the input signal and the carrier signal.

9. The modulation circuit described above is A variable phase shift element configured to generate a phase-shifted version of the carrier signal, A first comparator configured to generate a first comparison output signal based on a comparison between the input signal and the carrier signal, A second comparator configured to generate a second comparison output signal based on a comparison between the input signal and a phase-shifted version of the carrier signal, Equipped with, The switching transducer driver according to claim 8, wherein the modulated output signal is based on the first comparison output signal and the second comparison output signal.

10. The control circuit operates to control the phase shift applied to the carrier signal by the variable phase shift element to generate a control signal for generating a phase shifted version of the carrier signal, the control signal being based on the parameters of the input signal, according to claim 9, the switching transducer driver.

11. The switching transducer driver according to claim 10, wherein the control signal represents a variable α that controls the phase shift applied by the variable phase shift element.

12. The switching transducer driver according to claim 11, wherein the variable α is equal to 0 if the parameter of the input signal is greater than or equal to a first threshold, and equal to 1 if the parameter of the input signal is less than the first threshold, based on a comparison between the parameter of the input signal and a threshold.

13. The switching transducer driver according to claim 11 or 12, wherein the value of α is variable over a continuous range based on the parameters of the input signal, and the continuous range is between 0 and an upper limit of 1 or less.

14. The switching transducer driver according to any one of claims 8 to 13, wherein the modulation circuit comprises an open-loop modulation circuit.

15. The switching transducer driver according to any of the prior claims, wherein the switching transducer driver is capable of operating in a third mode in which the output of the switching transducer driver is clamped to a reference voltage.

16. The switching transducer driver according to claim 15, wherein the switching transducer driver is configured to operate in the third mode when the parameters of the input signal are less than a second threshold.

17. The switching transducer driver according to any of the prior claims, wherein the third switch comprises a different device type or different technology from the first and second output stage switches.

18. The switching transducer driver according to claim 17, wherein the third switch is implemented using one or more MOSFET devices.

19. The switching transducer driver according to any one of claims 1 to 17, wherein the third switch is implemented using a wide-bandgap device or a HEMT device, and the characteristics of the third switch are inferior to the corresponding characteristics of the first and second output stage switches.

20. The switching transducer driver according to any one of claims 1 to 18, wherein the third switch is implemented as a switch connected in antiparallel.

21. A module comprising a circuit board on which a third switch of a switching transducer driver according to any of the prior claims and the first and second output stage switches are mounted.

22. A switching transducer driver, The first and second output stage switches are controlled to an active mode that generates two levels of output signals, A third switch is controlled to a quiescent mode in which the output of the switching transducer driver is clamped to a reference voltage, A switching transducer driver that can operate in this environment.

23. It is an integrated circuit, A control circuit for supplying control signals to a first output stage switch, a second output stage switch, and a third switch, wherein the impedance of the first output stage switch is substantially the same as the impedance of the second output stage switch, and the impedance of the third switch is greater than the impedances of the first and second output stage switches. An integrated circuit comprising, The control circuit is an integrated circuit that can be operated to select between a first operating mode in which the first and second output stage switches are controlled to generate two levels of output signals, and a second operating mode in which the first and second output stage switches and the third switch are controlled to generate three levels of output signals.

24. The integrated circuit according to claim 23, wherein the integrated circuit comprises the third switch.

25. A host device comprising a switching transducer driver according to any one of claims 1 to 22.

26. The host device according to claim 25, wherein the host device includes a laptop, notebook, netbook or tablet computer, an in-vehicle system, a vehicle audio system, a game device, a game console, a game console controller, a virtual reality (VR) device or an augmented reality (AR) device, a mobile phone, a portable audio player, a portable device, or an accessory device for use with a laptop, notebook, netbook or tablet computer, a game device, a game console, a VR device or an AR device, a mobile phone, a portable audio player or other portable device.

27. A Class D amplifier circuit configured to receive an input signal and output an output signal, wherein the Class D amplifier circuit is configured The first output stage switch, The second output stage switch, The third switch, Equipped with, The characteristics of the third switch are inferior to the corresponding characteristics of the first and second output stage switches. The Class D amplifier circuit is a Class D amplifier circuit that can be selectively operated in either a first operating mode or a second operating mode based on the parameters of the input signal.

28. A Class D amplifier circuit configured to receive an input signal and output an output signal, wherein the Class D amplifier circuit is configured The first output stage switch, The second output stage switch, The third switch, Control circuit and Equipped with, The first and second output stage switches are implemented using wide-bandgap devices or high-electron-mobility transistor (HEMT) devices. The control circuit is configured to select between a first operating mode and a second operating mode of the Class D amplifier circuit based on the parameters of the input signal, wherein the Class D amplifier circuit is configured to perform a Class D amplifier circuit.

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