Distortion reduction and stop layer in Si / SiGe epistacks
By using n-type dopants, carbon-boron combinations, and tensile silicon layers, the strain and warpage issues in Si/SiGe heteroepitaxial growth are mitigated, enabling stable semiconductor device production.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- APPLIED MATERIALS INC
- Filing Date
- 2024-06-17
- Publication Date
- 2026-05-01
AI Technical Summary
Heteroepitaxial growth of Si/SiGe films induces strain and wafer warpage, particularly in thick layers, which current processes struggle to manage effectively.
Implementing n-type dopants in SiGe layers, adding carbon and/or carbon-boron to selectively etched SiGe layers, and incorporating tensile silicon layers to compensate for lattice mismatches and reduce warpage through controlled etching and layer thickness adjustments.
Reduces wafer warpage and strain by optimizing the etching process and layer composition, ensuring stable and efficient manufacturing of semiconductor devices like DRAMs.
Smart Images
Figure 2026513955000001_ABST
Abstract
Description
Technical Field
[0001] Cross - reference to Related Applications
[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 522,113 to Hao et al., entitled "Reduced Strain and Stop Layer for Si / SiGe epi stacks", filed on June 20, 2023, which is hereby incorporated by reference in its entirety.
[0002]
[0002] This disclosure generally relates to semiconductor devices, and more particularly to semiconductor devices that utilize heteroepitaxial structures and related processes that can reduce strain induced by lattice mismatches of lattice elements.
Background Art
[0003]
[0003] Epitaxial layer growth may refer to crystal growth and / or deposition of materials, by which a new crystal layer can be formed with a predetermined orientation with respect to a crystal seed layer, and the deposited film is called an epitaxial layer. The orientation of the epitaxial layer and the seed layer can be determined using the orientation of the crystal lattice of each material. The epitaxial growth process is used in semiconductor manufacturing, and semiconductor films grow epitaxially on a substrate. Heteroepitaxial growth includes epitaxial growth of different materials with each other. However, during such a heteroepitaxial growth process (e.g., using Si / SiGe films), strain may be induced from the lattice mismatch of lattice elements between the Si lattice and the Ge lattice. As a result, wafer warpage may occur. Regarding the growth of thin layers, wafer warpage may be manageable using various known processes, but not so for thick layers that require warpage compensation.
Summary of the Invention
[0004]
[0004] In some implementations, the subject matter relates to a method for manufacturing a semiconductor device. The method may include providing a substrate, forming at least one silicon layer on top of the substrate, forming at least one silicon-germanium layer on top of the at least one silicon layer, wherein the at least one silicon-germanium layer may contain at least one n-type dopant, and forming a semiconductor device having at least one silicon layer and at least one silicon-germanium layer.
[0005]
[0005] In some implementations, the present subject may include one or more of the following optional features. The method may further include stacking a plurality of at least one silicon-germanium layers formed on top of at least one silicon layer. The semiconductor device may include a plurality of stacked at least one silicon-germanium layers formed on top of at least one silicon layer.
[0006]
[0006] In some implementations, the thickness of at least one silicon layer may be greater than the thickness of at least one silicon germanium layer.
[0007]
[0007] In some implementations, the method may also include forming at least one p-type doped region within at least one silicon layer. The at least one p-type doped region may be located adjacent to at least one silicon-germanium layer. The method may further include stacking a plurality of at least one silicon-germanium layers formed on top of at least one silicon layer. The at least one silicon layer may have at least one p-type doped region formed within the at least one silicon layer. The semiconductor device may include a plurality of stacked at least one silicon-germanium layers formed on top of at least one silicon layer. One or more silicon-germanium layers within the stacked plurality of at least one silicon-germanium layers formed on top of at least one silicon layer may be configured to be adjacent to one or more p-type doped regions formed in silicon layers adjacent to one or more silicon-germanium layers. One or more p-type doped regions may include one or more p-type dopants. One or more p-type dopants may contain at least one of boron, carbon, boron and carbon, or any combination thereof.
[0008]
[0008] In some implementations, the method may also include forming at least one tension layer at the bottom of at least one silicon layer. Forming at least one tension layer may include forming at least one n-type doped silicon layer on top of the substrate, forming at least one p-type stop layer on top of the n-type doped silicon layer, and removing at least a portion of the n-type doped silicon layer. The method may also include reducing the curvature of the substrate by removing the substrate and reducing the germanium concentration in the silicon germanium layer.
[0009]
[0009] In some implementations, the thickness of at least one p-type stop layer may be less than the thickness of at least one n-type doped silicon layer.
[0010]
[0010] In some implementations, the n-type dopant may include at least one of phosphorus, arsenic, antimony, bismuth, lithium, and any combination thereof.
[0011]
[0011] In some implementations, this subject relates to semiconductor devices. The device may include a substrate, at least one silicon layer formed on the top of the substrate, and at least one silicon-germanium layer formed on top of the at least one silicon layer, the at least one silicon-germanium layer may include at least one n-type dopant.
[0012]
[0012] In some implementations, the device may further include a plurality of stacked at least one silicon-germanium layers formed on top of at least one silicon layer. The thickness of the at least one silicon layer may be greater than the thickness of the at least one silicon-germanium layer. The device may further include at least one p-type doped region formed within the at least one silicon layer, the at least one p-type doped region may be located adjacent to the at least one silicon-germanium layer. In some implementations, the device may include a plurality of stacked at least one silicon-germanium layers formed on top of at least one silicon layer, and the at least one silicon layer may have at least one p-type doped region formed within the at least one silicon layer.
[0013]
[0013] In some implementations, in a semiconductor device, one or more silicon-germanium layers in a stacked plurality of at least one silicon-germanium layers formed on top of at least one silicon layer may be adjacent to one or more p-type doped regions formed in a silicon layer adjacent to the one or more silicon-germanium layers. One or more p-type doped regions may contain one or more p-type dopants, one or more p-type dopants containing at least one of boron, carbon, boron and carbon, and any combination thereof.
[0014]
[0014] In some implementations, the semiconductor device may include at least one tension layer formed at the bottom of at least one silicon layer. The at least one tension layer may be formed by forming at least one n-type doped silicon layer on top of the substrate, forming at least one p-type stop layer on top of the n-type doped silicon layer, and removing at least a portion of the n-type doped silicon layer.
[0015]
[0015] In some implementations, the thickness of at least one p-type stop layer in a semiconductor device may be less than the thickness of at least one n-type doped silicon layer. The n-type dopant may include at least one of phosphorus, arsenic, antimony, bismuth, lithium, and any combination thereof.
[0016]
[0016] Details of one or more modifications of the subject matter described herein are shown in the accompanying drawings and the following description. Other features and advantages of the subject matter described herein will be apparent from the description and drawings, as well as from the claims.
[0017]
[0017] The accompanying drawings incorporated herein and constituting part thereof illustrate specific aspects of the subject matter disclosed herein and, together with the description, help to illustrate some of the principles relating to the disclosed implementations. The drawings are essentially schematic and do not represent actual dimensions or aspect ratios. [Brief explanation of the drawing]
[0018] [Figure 1a-c] The following are illustrative semiconductor devices relating to several implementation forms of this subject. [Figure 2a-b] Figures 1a to 1c show exemplary structures used during the formation of tensile layers for inclusion in one or more semiconductor devices, respectively, relating to several implementation forms of this subject. [Figure 3] This document illustrates an exemplary process 300 for forming a tensile layer in several implementation forms of this subject. [Figure 4] This section illustrates an exemplary process using some implementation forms of this subject. [Modes for carrying out the invention]
[0019]
[0022] To address these shortcomings and other potential deficiencies of currently available solutions, one or more implementations of the current subject can provide semiconductor devices using heteroepitaxial structures and associated processes that can reduce distortions that may be induced by mismatches of one or more lattice elements, among other possible advantages.
[0020]
[0023] In some implementations, this subject relates to the ability to compensate for and / or reduce wafer warping in heteroepitaxially grown semiconductor devices, for example, for the purpose of manufacturing dynamic random access memory (DRAM) devices. A typical DRAM device may contain alternating layers of silicon (Si) and silicon germanium (SiGe) that can be epitaxially grown from a crystalline silicon substrate. Lattice mismatches between Si and Ge can occur, causing strain that leads to wafer warping. As mentioned above, in thin layers, such wafer warping is less of a problem than in thick layers. To solve this problem, the compensation and / or reduction of the present subject can be performed either during one or more stages of the heteroepitaxial growth process, and / or after one or more stages and / or after the completion of the entire growth process. Compensation can be performed through one or more of the following: adding an n-type dopant to the SiGe layer, adding carbon and / or carbon-boron to both sides of a selectively etched SiGe layer, and / or adding a tensile Si layer to the front side before memory stack epitaxial processing. Each of these will be explained in more detail below.
[0021]
[0024] The addition of an n-type dopant to the SiGe layer may be beneficial during the selective removal of the SiGe layer. Furthermore, it may cause a decrease in the Ge concentration within the SiGe layer, potentially offering further advantages in reducing wafer warpage. As a non-limiting example, the n-type dopant may be phosphorus with a smaller lattice constant. Therefore, the combination of added phosphorus and the resulting decrease in Ge concentration within the SiGe layer may help reduce wafer warpage. As can be understood, any other n-type dopant material may be used.
[0022]
[0025] Adding carbon and / or a combination of carbon and boron to one or both sides of a selectively etched SiGe layer can be configured to reduce the etching rate of Si that may be exposed during the selective etching process. In particular, the use of carbon and / or a combination of carbon and boron can help increase SiGe layer etching while decreasing Si layer etching. This can also help compensate for wafer warpage. Using carbon with a smaller lattice constant (e.g., smaller than that of silicon) can offset the lattice mismatch with germanium, which has a larger lattice constant. For example, the lattice constant of germanium is about 1.04 times that of silicon, and the lattice constant of carbon is 0.66 times that of silicon. For example, in a layer stack, carbon can be added to a silicon layer, thereby creating a SiC layer. The silicon layer that receives carbon may be, for example, about 15 nanometers (nm) thick, and the added carbon may have a concentration of 0.5%. The addition of carbon to the silicon layer may be performed on one or both sides of a silicon germanium layer doped with an n-type dopant (e.g., phosphorus (SiGe-Phos)), which is sandwiched between silicon layers in the stack. The SiGe-Phos layer may have, for example, a thickness of 10 nm and a germanium concentration of 13%. The resulting combination can be configured to substantially completely compensate for the stress from the presence of germanium and, thus, reduce wafer warpage. Further, as described above, instead of carbon, boron, and / or a combination of carbon and boron, it can be added to the silicon layers surrounding the SiGe-Phos layer. The concentration of the added element can be selected based on the desired reduction in wafer warpage and, for example, specific design specifications of any final product, layer thickness, layer arrangement, etc. As can be understood, the above numerical examples are provided herein for illustrative purposes only and are not intended to limit the scope of the subject matter described herein.
[0023]
[0026] Alternatively or additionally, one or more tensile silicon layers may be added to the front side before the epitaxial treatment of the memory stack. The tensile silicon layers may be doped with carbon, boron, phosphorus, and / or any combination thereof, and may have sufficient thickness to not only provide adequate compensation but also prevent the relaxation of crystal defects. In one embodiment, in a non-limiting implementation, a thin boron-doped epitaxial layer may follow a thick phosphorus-doped silicon epitaxial layer, which may be useful during the back-side silicon removal process in a later stage.
[0024]
[0027] It should be noted that, as used herein, "substrate" may refer to any substrate and / or material surface formed on a substrate on which a film treatment may be performed during the manufacturing process. Substrate materials may include, but are not limited to, silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and / or, for example, metals, metal nitrides, metal alloys, and / or any other conductive materials (which may be specific to a particular mounting configuration, application, use, etc.). A substrate may also include a semiconductor wafer. A substrate may be subjected to one or more pretreatment processes, such as polishing, etching, reduction, oxidation, hydroxylation, annealing, UV curing, electron beam curing, and / or baking of the substrate surface. The substrate surface and / or the substrate may include underlying layers, such as when a film / layer and / or partial film / layer is deposited on the substrate surface, with the exposed surface of the deposited film / layer becoming the substrate surface.
[0025]
[0028] Figures 1a - 1c each show exemplary semiconductor devices 100 - 120 according to some implementations of the present subject matter. Devices 100 - 120 can be used to form dynamic random access memory (DRAM) devices and / or any other type of memory device. Devices 100 - 120 can be configured to include a plurality of stacked layers and / or groups of layers that can be arranged directly above and / or in parallel with each other. For clarity of the figures, Figures 1a - 1c show only a limited number of such layers. As can be understood, any number of layers can be directly stacked on top of each other. As used herein, the term "on" with respect to a film and / or layer of a film can include a film and / or layer that is disposed on a surface and / or directly on one or more underlying layers between the film and / or layer and the surface.
[0026]
[0029] A layer may refer to a single crystal layer of a material and / or a plurality of crystal layers of the same material, which may combine to form a single crystal layer. Devices 100 - 120 may, for example, include a plurality of alternating layers of silicon (Si) and silicon germanium (SiGe), and the thickness or height of each Si layer may be greater than the thickness or height of the SiGe layer. Alternatively, or additionally, at least one Si layer may have a thickness or height that is less than the thickness or height on at least the SiGe layer. As can be understood, any combination of layer thicknesses / heights is possible.
[0027]
[0030] Furthermore, as described herein, one or more SiGe layers and / or Si layers of devices 100-120 may be doped with and / or contain at least one dopant. Some non-limiting examples of dopants may include carbon, boron, phosphorus, oxygen, nitrogen, and / or any other type of dopant, and / or any combination thereof. Furthermore, devices 100-120 may be configured to include any combination of doped Si layers and undoped Si layers, and / or doped SiGe layers. For example, a doped Si layer may be located adjacent to a doped SiGe layer and / or on each side of a doped and / or undoped SiGe layer. Alternatively, or additionally, a doped SiGe layer may be located adjacent to and / or on each side of a doped and / or undoped Si layer. Each doped and / or undoped layer may have its own thickness and / or height, which can be selected according to the design requirements and / or characteristics of device 100-120. Furthermore, each doped layer may have a specific desired doping concentration (e.g., one or more dopants), which can again be selected according to the specific requirements / characteristics of device 100-120. The doping concentration may be configured to be uniform throughout the entire stack of layers. Alternatively, or additionally, the doping concentration may be non-uniform and vary from doped layer to doped layer in the stack. For example, the doping concentration may vary (if desired) from the bottom doped layer in the stack to the top layer in the stack. Such non-uniform doping may help to form uniform recesses in the SiGe layer (depending on recess etching conditions).
[0028]
[0031] Referring to Figure 1a, the device 100 may include silicon layers 102a, 102b, 102c, and one or more silicon-germanium layers 104a, 104b that can be doped with an n-type dopant. As described above, any number of silicon layers 102 and silicon-germanium layers 104 may be used. The silicon-germanium layers 104 may be arranged alternately with the silicon layers 102. For example, the silicon-germanium layer 104a may be placed between silicon layers 102a and silicon layers 102b, the silicon-germanium layer 104a may be placed on top of the silicon layers 102a, and the silicon layer 102b may be placed on top of the silicon-germanium layer 104a. Similarly, the silicon germanium layer 104b may be placed between the silicon layer 102b and the silicon layer 102c, the silicon germanium layer 104b may be placed on top of the silicon layer 102b, and the silicon layer 102c may be placed on top of the silicon germanium layer 104b.
[0029]
[0032] As shown in Figure 1a, the thickness or height of silicon layer 102 may be greater than the thickness or height of silicon germanium layer 104. Alternatively, or additionally, the thickness / height of at least one silicon germanium layer 104 may be greater than the thickness / height of at least one silicon layer 102. Furthermore, while Figure 1a shows a uniform thickness / height for each silicon layer 102, it should be understood that, similarly, the thickness / height of each silicon germanium layer 104 may not be uniform. For example, the thickness / height of layer 102a may be greater than the thickness / height of layer 102b, etc. (and similarly for layer 104). The deposition or growth of each layer 102 and 104 may be carried out according to any existing technique.
[0030]
[0033] In some implementation configurations, one or more silicon-germanium layers 104 may be doped with dopants, such as n-type dopants, not only to reduce wafer warpage but also to enhance the selective etching process. It should be noted that SiGe layers are typically etched more selectively than Si layers. Therefore, adding n-type dopants to the SiGe layers may be configured to increase electron availability, thereby improving the etching rate of the SiGe layers. This improvement in etching rate can lead to a further decrease in germanium concentration within the SiGe layers, thereby reducing the SiGe layer's influence on wafer warpage.
[0031]
[0034] In some embodiments, in non-restrictive implementations, the concentration of the n-type dopant may be about 0.01% or less. The concentration of the n-type dopant may be selected based on the specific dopant and the desired strain reduction effect. For example, a higher doping level of the phosphorus dopant, which has a smaller lattice constant (compared to silicon), may be effective in reducing strain. In contrast, using arsenic and / or antimony dopants may decrease the diffusivity and increase strain, because each has a larger lattice constant (compared to silicon). As can be understood, any type of n-type dopant may be used, and examples of such n-type dopants may include, but are not limited to, phosphorus, arsenic, antimony, bismuth, lithium, and / or any other n-type dopants, and / or any combination thereof. As mentioned above, the doping of the layer may be uniform and / or non-uniform (e.g., fluctuate) within the stack.
[0032]
[0035] Figure 1b shows an exemplary device 110, which may include one or more regions that can be doped with a p-type dopant to further improve the selective etching process and reduce warpage compensation, according to several implementations of the current subject. In non-limiting implementations, doping a p-type dopant and / or carbon to a silicon layer placed adjacent to a silicon-germanium layer may be configured to reduce the etching rate of the silicon layer, which may help in the removal of the SiGe layer relative to the loss of the silicon layer. The use of carbon and the absence of electrons in the silicon layer may be configured to reduce the etching rate of the silicon layer. This may be configured to allow a more aggressive SiGe layer etching process, during which a higher etching rate can be used to reduce the germanium concentration in the SiGe layer, thereby reducing the impact of the SiGe layer on wafer warpage. Although the created p-type and / or carbon-doped silicon layer may not be favorable for DRAM device channels, the thickness of this layer may be kept within the thickness of the silicon layer that can be removed later when the silicon is thinned to form the final thickness of the silicon in the semiconductor device (e.g., a transistor). Furthermore, by adding a gradient and / or thin silicon transition layer, the transition from the compression layer to the tension layer within the epitaxial layer can be buffered, which may help reduce the formation of crystal defects.
[0033]
[0036] As shown in Figure 1b, device 110, like device 100 shown in Figure 1a, may include silicon layers 102a, 102b, 102c, and one or more silicon-germanium layers 104a, 104b that can be doped with an n-type dopant. Here again, any number of silicon layers 102 and silicon-germanium layers 104 can be used. The silicon-germanium layers 104 may be arranged alternately with the silicon layers 102.
[0034]
[0037] In addition to layers 102 and 104, one or more silicon layers 102 may be configured to include one or more doped regions 106 (a, b, c, d). Regions 106 may be doped with p-type dopants. Such p-type dopants may include, but are not limited to, carbon, boron, carbon and boron, and / or any other p-type dopants, and / or any combination thereof. For example, silicon layer 102a may be configured to include doped region 106a, silicon layer 102b may be configured to include doped regions 106b and 106c, and silicon layer 102c may include doped region 106d. As can be understood, silicon layer 102 may include any number of doped regions 106.
[0035]
[0038] Furthermore, the doped regions 106 may be located within each silicon layer 102, adjacent to both sides of each n-type doped layer 104. For example, a doped region 106a located within silicon layer 102a may be located adjacent to the bottom of silicon germanium layer 104a, a doped region 106b located within silicon layer 102b may be located adjacent to the top of silicon germanium layer 104a, and a doped region located within silicon layer 102b and a doped region 106d located within silicon layer 102c may be located adjacent to the top of silicon germanium layer 104b. The thickness, height, and / or density of each doped region 106 may be determined according to the specific characteristics of the device 110, one or more recessed uses of the device 110, and / or specific applications. For example, the thickness and / or height of layer 104 may be equivalent to the thickness and / or height of region 106. Alternatively or additionally, each region 106 may have the same or different thickness and / or height as another region 106 and / or one or more layers 104.
[0036]
[0039] Figure 1c shows an exemplary device 120 that can incorporate one or more layers and regions of devices 100 and 110, as shown in Figures 1a and 1b, respectively, in several implementations of the subject, and includes an additional tensile layer located on the front side of the device. As shown in Figure 1c, device 120 may include a silicon layer 102 having one or more n-type doped regions 106 and one or more n-type dopant-doped silicon-germanium layers 104, similar to devices 100 and 110 shown in Figures 1a and 1b. Here again, any number of silicon layers 102 and silicon-germanium layers 104 can be used. The silicon-germanium layers 104 may be arranged alternately with the silicon layers 102.
[0037]
[0040] In addition to layers 102 and 104, a tensile layer 108 may be added adjacent to the front side of the device 120, for example, to the silicon layer 102a. Layer 108 may be added before memory stack processing. Layer 108 may be a silicon layer doped with a p-type dopant, such as boron. Alternatively or additionally, layer 108 may be one or more layers, a bilayer, and / or any other combination of layers. For example, layer 108 may include a combination of layers such as a thick n-type doped (e.g., phosphorus-doped) silicon layer followed by a thin p-type doped (e.g., boron) silicon layer. Layer 108 may be further configured to assist in the back-side silicon removal process. Furthermore, as described herein, the doping of the layers may be uniform and / or non-uniform between layers in the stack.
[0038]
[0041] Figures 2a and 2b show exemplary structures 200(a, b) used during the formation of a tensile layer, as included in one or more devices 100 to 120 shown in Figures 1a to 1c, respectively, relating to several implementations of this subject. Figure 3 shows an exemplary process 300 for forming a tensile layer, relating to several implementations of this subject.
[0039]
[0042] Referring to Figures 2a-b and 3, the process of forming a tensile layer can be initiated by providing the silicon wafer 202 with 302. In some embodiments, in non-limiting packaging configurations, the silicon wafer 202 may be about 750 micrometers (μm) thick. As background, after processing of memory cells on the front side of the wafer is complete, it is often necessary to remove the back-side silicon to access the memory cells from the back side. Typically, this may involve removing 750 μm or more of silicon remaining in front of the memory cell array, even if the thickness is very small (e.g., less than 0.1 μm). Such removal can be assisted by adding a thin p-type wet etching stop layer on top of a thick n-type silicon wet etching layer. Backside polishing of silicon can be stopped within the n-type region. Wet silicon etching can then be used to easily remove the n-type silicon and stop the etching of the thin p-type silicon. The thin stop layer can be uniformly removed using a conventional etching process.
[0040]
[0043] In 304 (as shown in Figure 3), an n-type doped silicon layer 204a may be grown on top of the silicon wafer 202, as shown in Figure 2a. The n-type (e.g., N+) doped silicon layer 204a may be configured to have a thickness of 10 to 20 μm. The dopant may be phosphorus and / or any other type of dopant material.
[0041]
[0044] In 306 (as shown in Figure 3), a stop layer 206 may be formed on top of the doped silicon layer 204a. The stop layer 206 may have a thickness less than and / or substantially less than the thickness of the doped silicon layer 204a. The stop layer may be p-type (P+) doped. The dopant may be boron and / or any other type of dopant material.
[0042]
[0045] In 308, one or more silicon-silicon germanium layer combinations 208 (e.g., a memory stack) can be formed on top of the stop layer 206. The layer combination 208 may be similar to the combination of layers 102 and / or 104 (whether or not it includes region 106), as shown in one or more of Figures 1a to 1c. The formation of the memory stack (i.e., layer combination 208) can complete the device 202a shown in Figure 2a.
[0043]
[0046] In step 310 (as shown in Figure 3), removal 210 of the silicon wafer 202 and at least a portion of the n-type doped layer 204a may be performed to complete the formation of the memory device. As shown in Figure 2b, the removal of at least a portion of the n-type doped layer 204a forms the n-type doped layer 204b. The removal of the silicon wafer and a portion of the layer 204a can be achieved through any known process, such as back grinding. Removal 210 may be configured to stop once and / or before reaching a thin p-type stop layer 206. The resulting n-type doped layer 204b may have any desired shape, such as the arcuate shape shown in Figure 2b. As can be understood, any desired shape of the layer 204b can be achieved and used in the device 202b.
[0044]
[0047] Furthermore, in some implementations, the remaining stop layers 206 and 204b may be used to reduce the warping of the silicon-germanium layer before the silicon-germanium layer is formed. As can be understood, the stop layer 206 may also be removed using any conventional etching process.
[0045]
[0048] Figure 4 shows an exemplary process 400 for manufacturing a semiconductor device relating to several implementation forms of the subject matter. Process 400 may include any of the components and / or steps described herein with respect to Figures 1a to 3. In 402, a substrate (e.g., a substrate or silicon wafer 202) may be provided. In 404, at least one silicon layer may be formed on top of the substrate. In 406, at least one silicon-germanium layer may be formed on top of the silicon layer. One silicon-germanium layer may contain at least one n-type dopant.
[0046]
[0049] In 408, at least one p-type doped region may be formed within the silicon layer. The p-type doped region may be located adjacent to the silicon germanium layer. In 412, at least one tensile layer may be formed at the bottom of the silicon layer. In 414, a semiconductor device having one or more of the above-described layers may be formed.
[0047]
[0050] In some implementations, the subject may have one or more of the following optional features. For example, process 400 may involve stacking a plurality of silicon-germanium layers formed on top of a silicon layer, and the semiconductor device may include a plurality of stacked silicon-germanium layers formed on top of one or more silicon layers.
[0048]
[0051] In some implementations, the thickness of at least one silicon layer may be greater than the thickness of at least one silicon-germanium layer.
[0049]
[0052] In some implementations, process 400 may include stacking a plurality of silicon-germanium layers formed on top of a silicon layer, the silicon layer may have at least one p-type doped region formed internally. Furthermore, one or more silicon-germanium layers in the stacked plurality of at least one silicon-germanium layers formed on top of at least one silicon layer are configured to be adjacent to one or more p-type doped regions formed in the silicon layer adjacent to the one or more silicon-germanium layers. One or more p-type doped regions may contain one or more p-type dopants. One or more p-type dopants may contain at least one of boron, carbon, boron and carbon, and any combination thereof.
[0050]
[0053] In some implementations, the formation of the tensile layer may include forming at least one n-type doped silicon layer on top of the substrate, forming at least one p-type stop layer on top of the n-type doped silicon layer, and removing at least a portion of the n-type doped silicon layer. In some implementations, process 400 may also include removing the substrate and reducing the curvature of the substrate (e.g., wafer warpage) by reducing the germanium concentration in the silicon germanium layer.
[0051]
[0054] In some implementations, the thickness of at least one p-type stop layer is less than the thickness of at least one n-type doped silicon layer. The n-type dopants may include at least one of phosphorus, arsenic, antimony, bismuth, lithium, and any combination thereof.
[0052]
[0055] It should be understood that the exemplary devices shown in the block diagram above may represent functional examples of many potential implementation forms. Therefore, the division, omission, or inclusion of block functions shown in the attached diagram does not necessarily imply that hardware components, circuits, software, and / or elements for implementing these functions are included in the division, omission, or implementation.
[0053]
[0056] Several implementations may be described using the expression “one implementation” or “implementation” along with their derivatives. These terms mean that a particular feature, structure, or characteristic described in relation to an implementation is included in at least one implementation. Where the phrase “in one implementation” appears in various parts of this specification, it does not necessarily refer to the same implementation every time. Furthermore, unless otherwise specified, the features described above are considered to be usable together in any combination. Thus, any features described separately may be used together in combination, unless it is noted that the features are incompatible with each other.
[0054]
[0057] In one embodiment, a method for manufacturing a semiconductor device may include providing a substrate, forming at least one silicon layer on the top of the substrate, forming at least one silicon-germanium layer on top of the at least one silicon layer, wherein the at least one silicon-germanium layer contains at least one n-type dopant, and forming a semiconductor device having at least one silicon layer and at least one silicon-germanium layer.
[0055]
[0058] The method may also include stacking a plurality of at least one silicon-germanium layers formed on top of at least one silicon layer, so that the semiconductor device includes a plurality of stacked at least one silicon-germanium layers formed on top of at least one silicon layer.
[0056]
[0059] This method may also include cases where the thickness of at least one silicon layer is greater than the thickness of at least one silicon-germanium layer.
[0057]
[0060] The method may also include forming at least one p-type doped region within at least one silicon layer, wherein the at least one p-type doped region is located adjacent to at least one silicon germanium layer.
[0058]
[0061] The method may also include stacking a plurality of at least one silicon-germanium layers formed on top of at least one silicon layer, wherein the at least one silicon layer has at least one p-type doped region formed within the at least one silicon layer, and the semiconductor device includes a plurality of stacked at least one silicon-germanium layers formed on top of the at least one silicon layer.
[0059]
[0062] The method may also include a case in which one or more silicon-germanium layers in a stacked plurality of at least one silicon-germanium layers, formed on top of at least one silicon layer, are configured to be adjacent to one or more p-type doped regions formed in a silicon layer adjacent to the one or more silicon-germanium layers.
[0060]
[0063] The method may also include cases where one or more p-type doped regions comprise one or more p-type dopants, and one or more p-type dopants comprise at least one of boron, carbon, boron and carbon, and any combination thereof.
[0061]
[0064] The method may also include forming at least one tensile layer at the bottom of at least one silicon layer.
[0062]
[0065] The method may also include forming at least one tension layer by forming at least one n-type doped silicon layer on top of the substrate, forming at least one p-type stop layer on top of the n-type doped silicon layer, and removing at least a portion of the n-type doped silicon layer.
[0063]
[0066] This method may also include removing the substrate.
[0064]
[0067] This method may also include reducing the concentration of germanium in the silicon germanium layer, thereby reducing the warping of the substrate.
[0065]
[0068] This method may also include the case where the thickness of at least one p-type stop layer is less than the thickness of at least one n-type doped silicon layer.
[0066]
[0069] The method may also include cases where the n-type dopant contains at least one of phosphorus, arsenic, antimony, bismuth, lithium, and any combination thereof.
[0067]
[0070] In one embodiment, the semiconductor device may include a substrate, at least one silicon layer formed on the top of the substrate, and at least one silicon-germanium layer formed on top of the at least one silicon layer, wherein the at least one silicon-germanium layer includes at least one n-type dopant.
[0068]
[0071] The semiconductor device may also include a plurality of stacked at least one silicon-germanium layers formed on top of at least one silicon layer.
[0069]
[0072] The semiconductor device may also include cases where the thickness of at least one silicon layer is greater than the thickness of at least one silicon-germanium layer.
[0070]
[0073] The semiconductor device may also include at least one p-type doped region formed within at least one silicon layer, the at least one p-type doped region being located adjacent to at least one silicon germanium layer.
[0071]
[0074] The semiconductor device may also include a plurality of stacked at least one silicon-germanium layers formed on top of at least one silicon layer, the at least one silicon layer having at least one p-type doped region formed within the at least one silicon layer.
[0072]
[0075] The semiconductor device may also include a configuration in which one or more silicon-germanium layers in a stacked plurality of at least one silicon-germanium layers, formed on top of at least one silicon layer, are adjacent to one or more p-type doped regions formed in a silicon layer adjacent to the one or more silicon-germanium layers.
[0073]
[0076] A semiconductor device may also include one or more p-type doped regions comprising one or more p-type dopants, where one or more p-type dopants comprising at least one of boron, carbon, boron and carbon, and any combination thereof.
[0074]
[0077] The semiconductor device may also include at least one tensile layer formed at the bottom of at least one silicon layer.
[0075]
[0078] The semiconductor device may also include cases where at least one tension layer is formed by forming at least one n-type doped silicon layer on top of a substrate, forming at least one p-type stop layer on top of the n-type doped silicon layer, and removing at least a portion of the n-type doped silicon layer.
[0076]
[0079] The semiconductor device may also include a case where the thickness of at least one p-type stop layer is less than the thickness of at least one n-type doped silicon layer.
[0077]
[0080] The semiconductor device may also include cases where the n-type dopant contains at least one of phosphorus, arsenic, antimony, bismuth, lithium, and any combination thereof.
[0078]
[0081] It is emphasized that this summary of the disclosure is provided so that readers may quickly confirm the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the claims or their meaning. In addition, it will be found that in the preceding detailed description, various features are grouped together in a single implementation for the purpose of streamlining the disclosure. The method of this disclosure should not be interpreted as reflecting an intention that the implementations of the claims require more features than expressly described in each claim. Rather, as reflected in the following claims, the subject matter of the invention does not fall under all features of a single disclosed implementation. Accordingly, the following claims are incorporated into the detailed description herein, and each claim stands independently as a separate implementation. In the appended claims, the words “including” and “in which” are used as their plain English equivalents to the words “comprising” and “wherein,” respectively. Furthermore, terms such as "first," "second," and "third" are used simply as symbols and are not intended to impose numerical requirements on the objects they refer to.
[0079]
[0082] The foregoing includes examples of disclosed architectures. Naturally, it is impossible to describe all possible combinations of components and / or methods, but those skilled in the art will recognize that many further combinations and substitutions are possible. Therefore, novel architectures are intended to encompass all such changes, modifications, and variations that fall within the spirit and scope of the appended claims.
[0080]
[0083] The foregoing description of exemplary implementations is provided for illustrative and explanatory purposes only. It is not intended to be exhaustive or to limit this disclosure to the exact forms disclosed. Many modifications and variations are possible based on this disclosure. The scope of this disclosure is intended to be limited not by this detailed description, but rather by the claims appended to this specification. Future applications claiming priority to this application may claim subject matter disclosed in different ways and may generally include any set of one or more limitations as disclosed in various ways or otherwise demonstrated herein.
Claims
1. A method for manufacturing semiconductor devices, To provide a substrate, Forming at least one silicon layer on the uppermost part of the substrate, The method involves forming at least one silicon germanium layer on top of the at least one silicon layer, wherein the at least one silicon germanium layer contains at least one n-type dopant. To form the semiconductor device having the at least one silicon layer and the at least one silicon germanium layer, Methods that include...
2. The method according to claim 1, further comprising stacking a plurality of the at least one silicon germanium layers formed on top of the at least one silicon layer, wherein the semiconductor device includes the stacked plurality of the at least one silicon germanium layers formed on top of the at least one silicon layer.
3. The method according to claim 1 or 2, wherein the thickness of the at least one silicon layer is greater than the thickness of the at least one silicon germanium layer.
4. The method according to any one of claims 1 to 3, further comprising forming at least one p-type doped region within the at least one silicon layer, wherein the at least one p-type doped region is located adjacent to the at least one silicon germanium layer.
5. The method according to claim 4, comprising stacking a plurality of the at least one silicon germanium layers formed on top of the at least one silicon layer, wherein the at least one silicon layer has the at least one p-type doped region formed within the at least one silicon layer, and the semiconductor device comprises the stacked plurality of the at least one silicon germanium layers formed on top of the at least one silicon layer.
6. The method according to claim 5, wherein one or more silicon germanium layers in the stacked plurality of at least one silicon germanium layers, formed on the uppermost of the at least one silicon layer, are configured to be adjacent to one or more p-type doped regions formed in a silicon layer adjacent to the one or more silicon germanium layers.
7. The method according to claim 6, wherein the one or more p-type doped regions comprise one or more p-type dopants, and the one or more p-type dopants comprise at least one of boron, carbon, boron and carbon, and any combination thereof.
8. The method according to claim 4, further comprising forming at least one tensile layer at the bottom of the at least one silicon layer.
9. Forming the aforementioned at least one tensile layer is Forming at least one n-type doped silicon layer on the uppermost part of the substrate, Forming at least one p-type stop layer on the uppermost part of the n-type doped silicon layer, Removing at least a portion of the n-type doped silicon layer, The method according to claim 8, including the method described in claim 8.
10. The method according to claim 9, further comprising removing the substrate.
11. The method according to claim 10, further comprising reducing the curvature of the substrate by reducing the concentration of germanium in the silicon germanium layer.
12. The method according to claim 9, wherein the thickness of the at least one p-type stop layer is less than the thickness of the at least one n-type doped silicon layer.
13. The method according to any one of claims 1 to 12, wherein the n-type dopant comprises at least one of phosphorus, arsenic, antimony, bismuth, lithium, and any combination thereof.
14. It is a semiconductor device, circuit board and At least one silicon layer formed on the uppermost part of the substrate, A silicon germanium layer formed on the uppermost part of the at least one silicon layer, comprising at least one n-type dopant, A semiconductor processing chamber, including a semiconductor processing chamber.
15. The semiconductor device according to claim 14, further comprising a plurality of stacked at least one silicon germanium layers formed on the uppermost of the at least one silicon layer.
16. The semiconductor device according to claim 14 or 15, wherein the thickness of the at least one silicon layer is greater than the thickness of the at least one silicon germanium layer.
17. The semiconductor device according to any one of claims 14 to 16, further comprising at least one p-type doped region formed within the at least one silicon layer, wherein the at least one p-type doped region is disposed adjacent to the at least one silicon germanium layer.
18. The semiconductor device according to claim 17, further comprising a plurality of stacked silicon-germanium layers formed on the uppermost of the at least one silicon layer, wherein the at least one silicon layer has the at least one p-type doped region formed within the at least one silicon layer.
19. The semiconductor device according to claim 18, wherein one or more silicon-germanium layers in the stacked plurality of at least one silicon-germanium layers, formed on the uppermost of the at least one silicon layer, are configured to be adjacent to one or more p-type doped regions formed in a silicon layer adjacent to the one or more silicon-germanium layers.
20. The semiconductor device according to claim 19, wherein the one or more p-type doped regions comprise one or more p-type dopants, and the one or more p-type dopants comprise at least one of boron, carbon, boron and carbon, and any combination thereof.
21. The semiconductor device according to claim 17, further comprising at least one tensile layer formed at the bottom of the at least one silicon layer.
22. The at least one tensile layer is Forming at least one n-type doped silicon layer on the uppermost part of the substrate, Forming at least one p-type stop layer on the uppermost part of the n-type doped silicon layer, Removing at least a portion of the n-type doped silicon layer, Methods that include...
23. The semiconductor device according to claim 22, wherein the thickness of the at least one p-type stop layer is less than the thickness of the at least one n-type doped silicon layer.
24. The semiconductor device according to any one of claims 14 to 23, wherein the n-type dopant comprises at least one of phosphorus, arsenic, antimony, bismuth, lithium, and any combination thereof.