Data reading / writing circuits and methods thereof, memory and methods for driving the same, and electronic devices.

Abstract

This disclosure relates to data read / write circuits and methods thereof, memory and methods for driving the same, and electronic devices, and belongs to the field of memory technology, and is used to improve the accuracy of data reading. The data read / write method is applied to a storage unit (U) and includes the following steps: In the pre-charge stage, a data signal line (BL1) supplies a first reference voltage (v1) to a storage transistor (T1), and an auxiliary signal line (BL2) supplies the first reference voltage (v1) simultaneously to the storage transistor (T1) and a write transistor (T2), so that the write transistor (T2) is turned on and the storage node (SN) between the write transistor (T2) and the storage transistor (T1) is pre-charged, where the sum of the maximum data voltage corresponding to the data that the storage unit (U) can store and the threshold voltage of the storage transistor (T1) is the reference voltage, and the first reference voltage (v1) is greater than the reference voltage. During the data writing phase, in response to the write command, the auxiliary signal line (BL2) is floated, the data signal line (BL1) supplies a data voltage to the memory transistor (T1), the memory transistor (T1) turns on, discharges the memory node (SN) to a steady state, and writes the data corresponding to the data voltage.

Description

Technical Field

[0001] This disclosure claims the priority of a Chinese patent application filed with the Chinese Patent Office on April 28, 2023, with an application number of 20231⁃0479255X and an invention title of "Data Reading and Writing Circuit and Its Method, Memory and Its Driving Method, Electronic Device", and incorporates all the contents of this Chinese patent application by reference into this application.

[0002] This disclosure relates to the field of memory technology, and particularly to a data reading and writing circuit and its method, a memory and its driving method, and an electronic device.

Background Art

[0003] With the development of communication technology and digital technology, people have been continuously demanding products with low power consumption, light weight, and excellent performance. Memory is likely to have a higher integration density and a larger storage capacity, and is becoming one of the important research directions in the current storage field. For example, in a three⁃dimensional dynamic random access memory, while the memory cell adopts a 1T1C architecture, by adopting a 2T architecture for the memory cell, it can effectively solve the difficulty of the capacity manufacturing process due to the significant size reduction when the memory cell adopts a 1T1C architecture.

Summary of the Invention

[0004] According to some embodiments, one form of this disclosure provides a data reading and writing method applied to a memory unit. The memory unit is configured to store data and includes a connected memory transistor and a writing transistor. The data reading and writing cycle of the memory unit includes a pre⁃charge stage and a data writing stage. The data reading and writing method includes the following steps.

[0005] During the pre-charge phase, the data signal line supplies a first reference voltage to the memory transistor, and the auxiliary signal line simultaneously supplies the first reference voltage to the memory transistor and the write transistor, turning on the write transistor and recharging the memory node between the write transistor and the memory transistor, where the reference voltage is the sum of the maximum data voltage corresponding to the data that the memory unit can store and the threshold voltage of the memory transistor, and the first reference voltage is greater than the reference voltage.

[0006] During the data writing phase, an auxiliary signal line is floated in response to a write command, and the data signal line supplies a data voltage to the memory transistor. The memory transistor turns on, discharges the memory node to a steady state, and writes the data corresponding to the data voltage.

[0007] According to some embodiments, the data read / write cycle further includes a data hold phase following the data write phase. The data read / write method further includes, in the data hold phase, pulling up the voltage of the data signal line to a first reference voltage, and after the voltage of the data signal line reaches the first reference voltage, turning off the write transistor first, and then pulling up the voltage of the auxiliary signal line to the first reference voltage. Furthermore, after turning off the write transistor, the data read / write method further includes applying a first off-control voltage to the memory transistor.

[0008] According to some embodiments, the data read / write cycle further includes a data hold phase following the data write phase. The data read / write method further includes, in the data hold phase, first turning off the memory transistor, pulling up the voltage of the data signal line to a first reference voltage, then turning off the write transistor, and pulling up the voltage of the auxiliary signal line to a first reference voltage.

[0009] According to some embodiments, the data read / write cycle further includes a data read step. The data read / write method further includes the following steps:

[0010] During the data reading phase, a read control voltage is applied to the memory transistor in accordance with the read command, and a second reference voltage is simultaneously supplied to the memory transistor and the write transistor via an auxiliary signal line. Here, the data signal line is further configured to read data depending on whether the memory transistor is turned on or not.

[0011] According to some embodiments, the data written to the memory node includes either "1" or "0". During the data reading phase, if the data stored in the memory node is "1", the memory transistor is in the ON state, and if the data stored in the memory node is "0", the memory transistor is in the OFF state.

[0012] According to some embodiments, the data read / write cycle further includes a waiting phase prior to the pre-charge phase and / or prior to the data read phase. The data read / write method further includes the following steps:

[0013] In the standby phase, the memory transistor and the write transistor are in the off state, the data signal line supplies the first reference voltage to the memory transistor, and the auxiliary signal line supplies the first reference voltage to both the memory transistor and the write transistor simultaneously.

[0014] According to some embodiments, the data read / write cycle further includes a data hold phase following the data write phase. The data read phase follows the data hold phase. The standby phase includes a first standby phase before the precharge phase and a second standby phase after the data hold phase and before the data read phase.

[0015] According to some embodiments, another embodiment of the present disclosure provides a data read / write circuit comprising a storage unit, data signal lines, and auxiliary signal lines. The storage unit is configured to store data and comprises a connected storage transistor and a write transistor. The data signal lines are connected to the storage transistor and are configured to supply a first reference voltage to the storage transistor in standby and pre-charge phases, to write data to the storage transistor in data write phases, and to read data in data read phases depending on whether the storage transistor is turned on or not. The auxiliary signal lines are connected to the storage transistor and the write transistor and are configured to simultaneously supply a first reference voltage to the storage transistor and the write transistor in standby and pre-charge phases, to be floating in the data write phase, and to supply a second reference voltage to the storage transistor and the write transistor in the data read phase. Here, the sum of the maximum data voltage corresponding to the data that the storage unit can store and the threshold voltage of the storage transistor is the reference voltage, and the first reference voltage is greater than the reference voltage.

[0016] According to some embodiments, the data read / write circuit further comprises a first control signal line and a second control signal line. The first control signal line is connected to a memory transistor and is configured to control the memory transistor to be turned off during the standby phase, to apply a first write control voltage to the memory transistor during the precharge phase and the data write phase, and to apply a read control voltage to the memory transistor during the data read phase. The second control signal line is connected to a write transistor and is configured to control the write transistor to be turned off during the standby phase and the data read phase, and to control the write transistor to be turned on during the data write phase.

[0017] In some embodiments, the data signal line is further configured to supply a first reference voltage to the memory transistor during the data retention phase. The second control signal line is further configured to control the write transistor to turn off after the voltage of the data signal line becomes the first reference voltage during the data retention phase. The auxiliary signal line is further configured to supply the first reference voltage to both the memory transistor and the write transistor simultaneously after the write transistor has been turned off during the data retention phase. The first control signal line is also further configured to apply a first off control voltage to the memory transistor after the write transistor has been turned off during the data retention phase.

[0018] According to some embodiments, the first control signal line is further configured to control the memory transistor to turn off earlier than the write transistor during the data hold phase. The data signal line is further configured to supply a first reference voltage to the memory transistor after it has been turned off during the data hold phase. The second control signal line is further configured to control the write transistor to turn off after the data signal line has supplied the first reference voltage during the data hold phase. The auxiliary signal line is further configured to supply the first reference voltage to both the memory transistor and the write transistor simultaneously after it has been turned off during the data hold phase.

[0019] According to some embodiments, a memory transistor comprises a memory gate, a first gate, a first pole, and a second pole. A write transistor comprises a second gate, a first pole, and a second pole. The first gate is connected to a first control signal line. The second gate is connected to a second control signal line. The first pole of the memory transistor is connected to a data signal line. The first pole of the write transistor is connected to the memory gate, and the intersection of the first pole of the write transistor and the memory gate is a memory node. The second pole of the memory transistor and the second pole of the write transistor are each connected to auxiliary signal lines.

[0020] In some embodiments, there are multiple storage units. These multiple storage units are arranged in rows along a first direction and in columns along a second direction, with the first and second directions intersecting. Here, each column of storage units shares one data signal line and one auxiliary signal line. Each row of storage units shares one first control signal line and one second control signal line.

[0021] In some embodiments, the data read / write circuit further includes a first reference voltage terminal and a second reference voltage terminal. The first reference voltage terminal is connected to a data signal line via a first gate circuit and to an auxiliary signal line via a second gate circuit. The first reference voltage terminal is configured to supply a first reference voltage. The first gate circuit is configured to selectively connect the first reference voltage terminal and the data signal line during the standby and precharge phases. The second gate circuit is configured to selectively connect the first reference voltage terminal and the auxiliary signal line during the standby and precharge phases. The second reference voltage terminal is connected to an auxiliary signal line via a third gate circuit. The second reference voltage terminal is configured to supply a second reference voltage. The third gate circuit is configured to selectively connect the second reference voltage terminal and the auxiliary signal line during the data read phase.

[0022] According to some embodiments, another embodiment of the present disclosure provides a memory comprising at least one storage unit, a first bit line, a second bit line, a first word line, and a second word line connected to the storage unit, wherein the storage unit comprises a storage transistor and a write transistor. The storage transistor comprises a storage gate, a first gate, a first pole, and a second pole. The write transistor comprises a second gate, a first pole, and a second pole. The storage gate is connected to the first pole of the write transistor, and the intersection of the storage gate and the first pole of the write transistor is a storage node. The first word line is connected to the first gate, and the second word line is connected to the second gate. The first bit line is connected to the first pole of the storage transistor, and the second bit line is simultaneously connected to the second pole of the storage transistor and the second pole of the write transistor. Here, the first bit line is configured to supply a data voltage to the data to be written during the data writing phase, and to read the data written to the storage node during the data reading phase, depending on whether the storage transistor is turned on or not.

[0023] According to some embodiments, another embodiment of the present disclosure provides a method for driving memory applicable to the memory described above. The method includes the following steps:

[0024] During the pre-charge phase, the first bit line supplies a first reference voltage to the first pole of the memory transistor, the second bit line simultaneously supplies the first reference voltage to the second pole of the memory transistor and the second pole of the write transistor, the first word line applies a first write control voltage to the first gate, and the second word line applies a second write control voltage to the second gate, thereby controlling the write transistor to turn on and pre-charging the memory node.

[0025] During the data writing phase, the second bit line is floated, and the first bit line supplies the data voltage to the first pole of the memory transistor, turning on the memory transistor, discharging the memory node to a steady state, and writing the data corresponding to the data voltage.

[0026] In the data reading stage, the second word line applies a second off control voltage to the second gate, the write transistor is in an off state, the first word line applies a read control voltage to the first gate, the second bit line simultaneously supplies a second reference voltage to the second pole of the memory transistor and the second pole of the write transistor, and the first bit line reads the data written into the memory node according to whether the memory transistor is turned on or not. Here, the first reference voltage is the sum of the maximum data voltage to be written in the memory unit and the threshold voltage of the memory transistor.

[0027] According to some embodiments, another form of the present disclosure provides an electronic device including the data reading and writing circuit described in some of the above embodiments or the memory described in some of the above embodiments.

[0028] One or more embodiments of the present disclosure will be described in more detail with reference to the following drawings and description. Other features, objects, and advantages of the present disclosure will become apparent from the specification, drawings, and claims.

Brief Description of the Drawings

[0029] [Figure 1] It is a circuit schematic diagram of a 2T0C architecture memory unit related to the related art. [Figure 2] It is a circuit schematic diagram of another 2T0C architecture memory unit related to the related art. [Figure 3] It is a circuit schematic diagram of a data reading and writing circuit or a memory according to some embodiments of the present disclosure. [Figure 4] It is a block diagram of a data reading and writing circuit or a memory according to some embodiments of the present disclosure. [Figure 5] It is an equivalent circuit diagram of the data reading and writing circuit or the memory shown in FIG. 4. [Figure 6] It is a timing chart of a data reading and writing method or a driving method of a memory according to some embodiments of the present disclosure. [Figure 7]This is a timing chart of other data reading / writing methods or other memory driving methods according to some embodiments of the present disclosure. [Figure 8] This is a timing chart for a data reading / writing method or a memory driving method according to some embodiments of the present disclosure. [Figure 9] This is a graph of the current-voltage characteristics of a memory transistor during the data reading stage according to some embodiments of this disclosure. [Modes for carrying out the invention]

[0030] To more clearly explain the technical concepts of the embodiments of this disclosure, the drawings necessary for describing the embodiments are briefly introduced below. The drawings described below represent only a portion of the embodiments of this disclosure, and it is clear to those skilled in the art that drawings of other embodiments can be obtained from these drawings without any special ingenuity.

[0031] To facilitate understanding of this disclosure, the disclosure will be described in more detail below with reference to the drawings. The drawings illustrate embodiments of this disclosure. However, this disclosure can be realized in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the content of this disclosure more complete.

[0032] Unless otherwise defined, all technical and scientific terms used in this disclosure have the same meaning as those generally understood by those skilled in the art. Terms used in the specification of this disclosure are used solely for the purpose of describing specific embodiments and are not intended to limit this disclosure.

[0033] As used in the specification, “Examples” means that certain features, structures, or properties described in relation to the Examples may be included in at least one embodiment of the present disclosure. Phrases appearing in different parts of the specification do not necessarily all mean the same Example, nor are they mutually exclusive, independent, or alternative examples. Those skilled in the art will understand, both explicitly and implicitly, that the Examples described herein can be combined with other Examples.

[0034] The terms “first,” “second,” “third,” and “fourth” used in this application may be used to describe various elements herein, but these elements are not limited to these terms. These terms are used solely to distinguish between the first element and other elements.

[0035] In the following embodiments, "connection" should be understood as "electrical connection," "communicative connection," etc., when connected circuits, modules, units, etc., have the transmission of electrical signals or data to each other.

[0036] In this application, the singular forms “one,” “one,” and “the said / the said” may also include the plural form unless the context explicitly specifies another form. Furthermore, terms such as “equip / include” or “have” should be understood to specify the presence of the described feature, whole, step, operation, component, part, or combination thereof, but not to exclude the possibility of the presence or addition of one or more other features, whole, step, operation, component, part, or combination thereof. At the same time, the term “and / or” as used herein includes any and all combinations of such items.

[0037] Figures 1 and 2 show schematic circuit diagrams of two 2T0C architecture memory units commonly found in related technologies.

[0038] In some embodiments, as shown in Figure 1, the storage unit comprises a connected read transistor T_r and a write transistor T_w, where the gate of the write transistor T_w is connected to the write word line Write-WL, the first pole of the write transistor T_w is connected to the write bit line Write-BL, the second pole of the write transistor T_w is connected to the gate of the read transistor T_r and is connected to the storage node SN, the first pole of the read transistor T_r is connected to the read word line Read-WL, and the second pole of the read transistor T_r is connected to the read bit line Read-BL.

[0039] In some other embodiments, as shown in Figure 2, the memory unit comprises a connected read transistor T_r and a write transistor T_w, where the gate of the write transistor T_w is connected to the write word line Write-WL, the first pole of the write transistor T_w is connected to the write bit line Write-BL, the second pole of the write transistor T_w is connected to the memory gate of the read transistor T_r and is connected to the memory node SN, the control gate of the read transistor T_r is connected to the read word line Read-WL, the first pole of the read transistor T_r is connected to the read word line Read-WL, and the second pole of the read transistor T_r is connected to the ground voltage terminal.

[0040] The two types of storage units described in the above embodiment both use a 2T0C architecture, and furthermore, the read transistor T_r and write transistor T_w of the storage unit operate relatively independently when writing and reading data. That is, data is written depending on whether the write transistor T_w is turned on, while the read transistor T_r is kept off. Data is read depending on whether the read transistor T_r is turned on or off, while the write transistor T_w is kept off. However, due to limitations in the manufacturing process and the usage time of the transistors, the threshold voltage of each transistor (especially the read transistor T_r) is prone to change, which negatively affects data reading and impacts the accuracy of data reading.

[0041] In a novel memory unit circuit design and driving method according to some embodiments of the present disclosure, the memory unit has 2T and 1C, where 2T simultaneously participates in precharging and writing data, and provides compensation for the read transistor Vth during the write phase.

[0042] Some embodiments of this disclosure provide a data read / write circuit and method therefor, a memory and a method for driving the same, and electronic equipment. By using a data signal line (first bit line) and an auxiliary signal line (second bit line), different electrical signals are supplied to the memory transistor at different stages of the data read / write cycle, and the control voltages of both the memory transistor and the write transistor are controlled. This allows data to be written to the memory node during the data write phase while simultaneously maintaining the threshold compensation voltage of the memory transistor in the memory node. In this way, it becomes easier to read data unaffected by the memory transistor threshold voltage via the data signal line (first bit line) during the data read phase, and further improves memory performance by ensuring the accuracy of storing the data read. Here, the data signal line (or first bit line) not only supplies the data voltage for the data to be written during the data write phase, but can also read the written data depending on whether the memory transistor is turned on or not during the data read phase.

[0043] In at least some embodiments of this application, the memory transistor can be understood as a read transistor having the function of reading data, and the read transistor or memory transistor simultaneously participates in both precharging and writing data during the data writing phase and is used to read data during the reading phase.

[0044] Memory can generally be understood to comprise multiple storage units, each of which may be distributed in a two-dimensional single layer or a three-dimensional multilayer configuration. For ease of explanation and understanding, the data read / write circuits and data read / write methods in some of the following embodiments will be described using a single storage unit and its corresponding drive as an example. When describing the technical proposals relating to embodiments of this disclosure, the data read / write circuits relating to embodiments of this disclosure mainly refer to circuits within the storage unit matrix and do not include peripheral circuits (e.g., row address drive circuits, column address drive circuits, etc.). The data read / write circuit comprises components of at least one storage unit and drive leads connected to the storage unit.

[0045] As shown in Figure 3, a data read / write circuit according to some embodiments of the present disclosure comprises a storage unit U, a data signal line BL1, and an auxiliary signal line BL2.

[0046] The memory unit U is configured to store data and includes a connected memory transistor T1 and a write transistor T2.

[0047] As shown in Figure 3, the memory transistor T1 comprises a memory gate G0, a first gate G1, a first pole S / D11, and a second pole S / D12. The write transistor T2 comprises a second gate G2, a first pole S / D21, and a second pole S / D22. Here, the first gate G1 is connected to the first control signal line WL. The second gate G2 is connected to the second control signal line WWL. The first pole S / D11 of the memory transistor T1 is connected to the data signal line BL1. The first pole S / D21 of the write transistor T2 is connected to the memory gate G0. The second pole S / D12 of the memory transistor T1 and the second pole S / D22 of the write transistor T2 are each connected to the auxiliary signal line BL2. Here, the intersection where the first pole S / D21 of the write transistor T2 and the memory gate G0 are connected is the memory node SN.

[0048] The data read / write timing of the storage unit U includes a data write phase, a data read phase, and a standby phase (which may be understood as a stand-by phase) before writing or reading data, where, in the embodiments of this application, a precharge phase is further included before the data write phase, and a data hold phase is further included after the data write phase.

[0049] The data signal line BL1 is connected to the memory transistor T1 and is configured to supply a first reference voltage to the memory transistor T1 during the standby and pre-charge phases, write data to the memory transistor T1 during the data writing phase, and read data during the data reading phase depending on whether the memory transistor T1 is turned on or not.

[0050] The auxiliary signal line BL2 is connected to the memory transistor T1 and the write transistor T2, and is configured to simultaneously supply a first reference voltage to the memory transistor T1 and the write transistor T2 during the standby and pre-charge phases, to float during the data writing phase, and to simultaneously supply a second reference voltage to the memory transistor T1 and the write transistor T2 during the data reading phase.

[0051] In the embodiments of this disclosure, the sum of the maximum data voltage corresponding to the data that the storage unit U can store and the threshold voltage of the storage transistor T1 is a reference voltage, and the first reference voltage supplied by the data signal line BL1 and the auxiliary signal line BL2 is greater than the reference voltage.

[0052] Here, the maximum data voltage corresponding to the data that the memory unit U can store means the voltage corresponding to the voltage at which the absolute value of the data voltage is maximized among the data that the memory unit U can store (for example, data "1" or data "0"). For example, the data that the memory unit U can store includes data "0" and data "1", where the data voltage Vdata1 corresponding to data "1" and the data voltage Vdata0 corresponding to data "0" may be the same positive voltage or the same negative voltage. The absolute value of the data voltage Vdata1 corresponding to data "1" is greater than the absolute value of the data voltage Vdata0 corresponding to data "0". Based on this, the data voltage corresponding to data "1" may be the maximum data voltage of the data that the memory unit U can store. The reverse is also true.

[0053] If the data voltage Vdata1 corresponding to data "1" is set as the maximum data voltage that the storage unit U can store, then the sum of this maximum data voltage and the threshold voltage Vth of the storage transistor T1 is the reference voltage, i.e., the reference voltage is Vdata1 + Vth. Here, for the sake of explanation, the reference voltage is defined as the sum of the maximum data voltage and the threshold voltage Vth of the storage transistor T1, and is merely used to indicate the range of values ​​for the first reference voltage when the reference voltage is used as the reference. For example, the first reference voltage is greater than the reference voltage (i.e., greater than Vdata1 + Vth). The difference between the first reference voltage and the reference voltage can be set reasonably according to the needs.

[0054] For example, the second reference voltage is smaller than the first reference voltage. As an example, if memory transistor T1 and writing transistor T2 are both N-type transistors, the first reference voltage terminal supplies the first reference voltage, and the second reference voltage terminal supplies the second reference voltage. The first reference voltage terminal is, for example, a power supply voltage terminal that can supply a rated high-level voltage, and the second reference voltage terminal is, for example, a common voltage terminal that can supply a rated low-level voltage.

[0055] For example, the second reference voltage is greater than the minimum data voltage of data that the storage unit U can store, and less than the maximum data voltage of data that the storage unit U can store. For instance, Vdata1 > second reference voltage > Vdata0.

[0056] In the actual application of the data read / write circuit, considering the coupling effect between the data signal line BL1 and the auxiliary signal line BL2, it can be understood that in order to clearly distinguish between the voltage or current changes caused by data "1" and data "0" during the data read stage, the second reference voltage V2 can be made greater than the sum of the minimum data voltage and the voltage variable (vector) due to the coupling effect, and less than the sum of the maximum data voltage and the voltage variable (vector) due to the coupling effect. Furthermore, since different timings and / or different control voltages have different coupling effects on the data read / write circuit, the above voltage variables (vectors) can be specifically determined according to the actual situation.

[0057] In some embodiments, as shown in Figure 3, the data read / write circuit further includes a first control signal line WL and a second control signal line WWL. The memory transistor T1 includes a memory gate G0, a first gate G1, a first pole S / D11, and a second pole S / D12. The write transistor T2 includes a second gate G2, a first pole S / D21, and a second pole S / D22. Here, the first gate G0 is connected to the first control signal line WL. The second gate G2 is connected to the second control signal line WWL. The first pole S / D11 of the memory transistor T1 is connected to the data signal line BL1. The first pole S / D21 of the write transistor T2 is connected to the memory gate G0, and the intersection of the first pole S / D21 of the write transistor T2 and the memory gate G0 is the memory node SN. The second pole S / D12 of the memory transistor T1 and the second pole S / D22 of the write transistor T2 are each connected to the auxiliary signal line BL2.

[0058] Here, if the direction of current transmission is matched, and the first pole S / D11 and second pole S / D12 of the memory transistor T1, one may become the source and the other the drain. If the first pole S / D21 and second pole S / D22 of the write transistor T2, one may become the source and the other the drain.

[0059] Furthermore, it can be understood that the memory transistor T1 employs a double-gate structure. The first gate G1 is the control gate of memory transistor T1 and is used to control the on and off states of memory transistor T1. The memory gate G0 is a floating gate and is used to capture charge and store data. Accordingly, the memory gate G0 of memory transistor T1 can be equivalently depicted as a capacitor in other equivalent circuit diagrams as well.

[0060] In some of the embodiments described above, the threshold voltage of the memory transistor T1 is defined as the threshold voltage Vth corresponding to the memory gate G0 stored in the memory transistor T1 when the first control signal line WL supplies a preset voltage to the first gate G1.

[0061] For example, the memory transistor T1 is an N-type transistor, and the preset voltage supplied by the first control signal line WL to the first gate G1 is a fixed high-level voltage. However, this is not limited to this; for example, the memory transistor T1 could be a P-type transistor, which would allow for adaptive adjustment of the voltage signals of the first gate G1 and other components connected to the memory transistor T1 to enable data reading. Similarly, the write transistor T2 could be an N-type or P-type transistor.

[0062] Based on the above, if the data voltage Vdata1 corresponding to data "1" is set as the maximum data voltage that the storage unit U can store, the reference voltage is Vdata1 + Vth, and the first reference voltage is greater than Vdata1 + Vth. The difference between the first reference voltage and the reference voltage can be set reasonably according to the needs.

[0063] In the embodiments of this disclosure, by connecting the data signal line BL1 to the storage transistor T1 in the storage unit U, and connecting the auxiliary signal line BL2 to the storage transistor T1 and the write transistor T2 in the storage unit U, different electrical signals can be supplied to the storage transistor T1 at different stages of the data read / write cycle using the data signal line BL1 and the auxiliary signal line BL2. Furthermore, by controlling the control voltages of both the storage transistor T1 and the write transistor T2, data can be written to the storage node SN during the data write stage, while simultaneously maintaining the threshold compensation voltage of the storage transistor T1 in the storage node SN. This makes it easier to read data that is not affected by the threshold voltage of the storage transistor T1 via the data signal line BL1 during the data read stage, ensuring accuracy in storing data reads and further improving memory performance. In addition, the data read / write circuit according to the embodiments of this disclosure does not require a ground terminal in the storage unit U, which is advantageous for further realizing high-density integration of the storage unit U.

[0064] In some embodiments, the first control signal line WL is connected to the first gate G1 of the memory transistor T1 and is configured to control the memory transistor T1 to be off during the standby phase, apply a first write control voltage to the memory transistor T1 during the precharge phase and data writing phase, and apply a read control voltage to the memory transistor T1 during the data reading phase. The second control signal line WWL is connected to the second gate G2 of the write transistor T2 and is configured to control the write transistor T2 to be off during the standby phase and data reading phase, and to control the write transistor T2 to be on during the data writing phase. Here, the control voltage at which the second control signal line WWL controls the write transistor T2 to be on is the second write control voltage.

[0065] Here, it can be understood that turning off the memory transistor T1 can be achieved by controlling it with the first off-control voltage applied by the first control signal line WL to the first gate G1. Turning off the write transistor T2 can be achieved by controlling it with the second off-control voltage applied by the second control signal line WWL to the second gate G2.

[0066] For example, the first off-control voltage and the second off-control voltage are the same.

[0067] For example, both the memory transistor T1 and the write transistor T2 are N-type transistors. Correspondingly, both the first write control voltage and the second write control voltage are high-level voltages. Both the first off-control voltage and the second off-control voltage are low-level voltages. Furthermore, the first write control voltage may be smaller than the second write control voltage, and the first write control voltage can be set rationally according to the needs.

[0068] In some other embodiments, the write cycle further includes a data retention phase that follows the data writing phase.

[0069] In some examples, the data signal line BL1 is further configured to supply a first reference voltage to the memory transistor T1 during the data retention phase. The second control signal line WWL is further configured to control the write transistor T2 to turn off after the voltage of the data signal line BL1 reaches the first reference voltage during the data retention phase. The auxiliary signal line BL2 is further configured to supply the first reference voltage to both the memory transistor T1 and the write transistor T2 simultaneously after the write transistor T2 has been turned off during the data retention phase.

[0070] Furthermore, the first control signal line WL is configured to apply a first off-control voltage to the memory transistor T1 after turning off the write transistor T2 during the data holding phase.

[0071] In the embodiments of this disclosure, during the data retention phase after writing data to the storage node SN, the voltage of the data signal line BL1 is pulled up to the first reference voltage V1, and the storage transistor T1 can be turned off by the voltage difference between the first pole S / D11 of the storage transistor T1 and the storage node SN. In this case, the write transistor T2, which connects the storage node SN and the auxiliary signal line BL2, is turned on, and the voltage stability of the storage node SN can be ensured based on the coupling effect between the data signal line BL1 and the auxiliary signal line BL2. Subsequently, by turning off the write transistor T2 first, and then having the auxiliary signal line BL2 simultaneously supply the first reference voltage to the storage transistor T1 and the write transistor T2, leakage current in the write transistor T2 can be avoided, and the data can be retained in the storage node SN.

[0072] In the data reading phase, the data signal line BL1 reads data depending on whether the memory transistor T1 is turned on or not, and it can be understood that the data is read by the change in current or voltage transmitted on the data signal line BL1. Therefore, in the data holding phase, after turning off the write transistor T2, a first off control voltage can be applied to the memory transistor T1 using the first control signal line WL. In this way, the off state of the memory transistor T1 can be further ensured, preventing leakage current from occurring in the memory transistor T1, and also facilitating the implementation of data reading scan control by applying a read control voltage to the memory transistor T1 with the first control signal line WL, as described later.

[0073] In some other examples, the first control signal line WL is further configured to turn off the memory transistor T1 earlier than the write transistor T2 during the data hold phase. The data signal line BL1 is further configured to supply a first reference voltage to the memory transistor T1 after it has been turned off during the data hold phase. The second control signal line WWL is further configured to turn off the write transistor T2 after the data signal line BL1 has supplied the first reference voltage during the data hold phase. The auxiliary signal line BL2 is further configured to supply the first reference voltage to both the memory transistor T1 and the write transistor T2 simultaneously after it has been turned off during the data hold phase.

[0074] In the embodiments of this disclosure, after writing data to the storage node SN, the storage transistor T1 is first turned off, and then the voltage of the data signal line BL1 is pulled up to the first reference voltage V1. In this case, the write transistor T2, which connects the storage node SN and the auxiliary signal line BL2, remains on, ensuring the stability of the voltage at the storage node SN. Subsequently, after turning off the write transistor T2, the auxiliary signal line BL2 simultaneously supplies the first reference voltage to the storage transistor T1 and the write transistor T2, thereby preventing leakage current from occurring at the write transistor T2 and stabilizing the data at the storage node SN.

[0075] For details regarding the control of the memory transistor T1 by the first control signal line WL and the control of the write transistor T2 by the second control signal line WWL, please refer to the data reading and writing method described later. Here, only the connection relationship and basic functions of the first control signal line WL and the second control signal line WWL will be explained.

[0076] In some embodiments, the write control voltage supplied by the first control signal line WL and the second control signal line WWL is a pulse voltage.

[0077] In some embodiments, the first write control voltage supplied by the first control signal line WL during the write cycle and the read control voltage supplied during the read cycle may be the same or different.

[0078] For example, the first write control voltage is the same as the read control voltage. Taking the example that both the memory transistor T1 and the write transistor T2 are N-type transistors, both the first write control voltage and the read control voltage may be high-level voltages. Taking the example that both the memory transistor T1 and the write transistor T2 are P-type transistors, both the first write control voltage and the read control voltage may be low-level voltages.

[0079] For example, the first write control voltage is smaller than the read control voltage. For instance, the absolute value of the first write control voltage is smaller than the absolute value of the read control voltage.

[0080] The memory unit and the driving method of the memory unit according to the embodiment of this application have been described above. The memory matrix of the memory unit will now be described below.

[0081] In some embodiments, as shown in Figures 4 and 5, there are multiple storage units U. The multiple storage units U are arranged in rows along a first direction and in columns along a second direction, with the first and second directions intersecting. Here, the first direction is, for example, the direction of extension of a first control signal line WL and / or a second control signal line WWL, and the second direction is, for example, the direction of extension of a data signal line BL1 and / or an auxiliary signal line BL2, with the first and second directions being, for example, orthogonal.

[0082] For example, multiple memory units U can be distributed according to an m × n matrix.

[0083] For example, as shown in Figures 4 and 5, a single row of storage units U shares one data signal line BL1 and one auxiliary signal line BL2. A single row of storage units U shares one first control signal line WL and one second control signal line WWL.

[0084] For example, the coupling capacitance between data signal line BL1 and memory gate G0 (which can be equivalent to memory node SN) is less than the first target threshold. The coupling capacitance between auxiliary signal line BL2 and memory gate G0 (which can be equivalent to memory node SN) is less than the second target threshold. Here, the first and second target thresholds may be the same or different.

[0085] Furthermore, both the first and second target thresholds can take small values.

[0086] For example, let the coupling capacitance between data signal line BL1 and memory gate G0 (which can be equivalent to memory node SN) be the first coupling capacitance. Let the coupling capacitance between data signal line BL1 and auxiliary signal line BL2 be the second coupling capacitance. The ratio of the first coupling capacitance to the second coupling capacitance is smaller than the target value. Furthermore, the smaller the target value, the better.

[0087] In some embodiments, as shown in Figures 4 and 5, the data read / write circuit further comprises a first reference voltage terminal v1 and a second reference voltage terminal v2.

[0088] The first reference voltage terminal v1 is connected to the data signal line BL1 via the first gate circuit 10 and to the auxiliary signal line BL2 via the second gate circuit 20. The first reference voltage terminal v1 is configured to provide the first reference voltage. The first gate circuit 10 is further configured to selectively connect the first reference voltage terminal v1 and the data signal line BL1 during the standby and pre-charge phases. The second gate circuit 20 is further configured to selectively connect the first reference voltage terminal v1 and the auxiliary signal line BL2 during the standby and pre-charge phases.

[0089] The second reference voltage terminal v2 is connected to the auxiliary signal line BL2 via the third gate circuit 30. The second reference voltage terminal v2 is configured to provide the second reference voltage. The third gate circuit 30 is configured to selectively connect the second reference voltage terminal v2 and the auxiliary signal line BL2 during the data reading phase.

[0090] For example, the first reference voltage terminal v1 connecting data signal line BL1 and the first reference voltage terminal v1 connecting auxiliary signal line BL2 may be the same voltage terminal or may be different voltage terminals providing the same voltage.

[0091] Furthermore, the first reference voltage terminal v1 connecting the data signal line BL1 and the first reference voltage terminal v1 connecting the auxiliary signal line BL2 are different voltage terminals that provide the same voltage, and these different voltage terminals may be provided in separate areas, for example, on opposite sides of the matrix of the memory unit U.

[0092] In some embodiments, as shown in Figure 5, the first gate circuit 10 includes first selection transistors TC1, one for each data signal line BL1, where the gate of each first selection transistor TC1 is connected to the first gate signal line CTL1, the first pole of each first selection transistor TC1 is connected to the corresponding data signal line BL1, and the second pole of each first selection transistor TC1 is connected to the first reference voltage terminal v1.

[0093] The second gate circuit 20 includes a second selection transistor TC2 connected to each auxiliary signal line BL2, where the gate of each second selection transistor TC2 is connected to the second gate signal line CTL2, the first pole of each second selection transistor TC2 is connected to the corresponding auxiliary signal line BL2, and the second pole of each second selection transistor TC2 is connected to the first reference voltage terminal v1.

[0094] The third gate circuit 30 includes a third selection transistor TC3, one for each auxiliary signal line BL2, where the gate of each third selection transistor TC3 is connected to the read gate signal line CTL-R, the first pole of each third selection transistor TC3 is connected to the corresponding auxiliary signal line BL2, and the second pole of each third selection transistor TC3 is connected to the second reference voltage terminal v2.

[0095] In some of the embodiments described above, the first and second poles of each selection transistor may be either a source or a drain. Each selection transistor is switched on selectively according to the gate signal on the corresponding gate signal line to realize read / write control for each memory unit U.

[0096] In some embodiments, as shown in Figures 4 and 5, the data read / write circuit may further include one or more sense amplifier circuits 40. For example, the data read / write circuit may include multiple sense amplifier circuits 40, one for each data signal line BL1. The end of each data signal line BL1 furthest from the first reference voltage terminal v1 is connected to the corresponding sense amplifier circuit 40 to read the data.

[0097] Here, the sense amplification circuit 40 can be either a current sense amplification circuit or a voltage sense amplification circuit, depending on the method by which the data read / write circuit reads the data.

[0098] For example, the sense amplifier circuit 40 is a current sense amplifier circuit. In this way, during the data reading stage, the data signal line BL1 continues to supply the first reference voltage, and the sense amplifier circuit 40 can read the data by detecting the change in current transmitted through the data signal line BL1, depending on whether or not the memory transistor T1 is turned on.

[0099] For example, the sense amplifier circuit 40 is a voltage sense amplifier circuit. During the data reading stage, the first reference voltage supplied in advance by the data signal line BL1 may or may not be changed depending on whether the memory transistor T1 is turned on or not, and the sense amplifier circuit 40 can read the data by detecting the change in voltage transmitted on the data signal line BL1.

[0100] Furthermore, the embodiments of this disclosure do not limit the circuit structure of the sense amplifier circuit 40. In some examples, if the sense amplifier circuit 40 is a voltage sense amplifier circuit such as a comparator amplifier circuit, the sense amplifier circuit 40 is connected to a third reference voltage terminal v3, and data can be read by comparing the difference between the third reference voltage supplied by the third reference voltage terminal v3 and the voltage transmitted on the data signal line BL.

[0101] In some of the embodiments described above, as shown in Figures 4 and 5, the first write control voltage supplied by the first control signal line WL and the third write control voltage supplied by the second control signal line WWL are both control voltages supplied when the storage unit U performs data writing. Based on this, it can be understood that, in addition to supplying the aforementioned first and second write control voltages to the row where the storage unit U performing data writing is located in the matrix of the storage unit U, the first control signal line WL and the second control signal line WWL corresponding to the other storage units U in other rows only need to supply off control voltages, thereby realizing scan writing to the rows of the matrix of the storage unit U.

[0102] Some embodiments of this disclosure provide a data reading and writing method for implementing the data reading and writing process of the data reading and writing circuit described above. The data reading and writing method can be applied to any storage unit configured to store data, the structure of which can be found in the relevant descriptions of the above embodiments. The technical advantages of the data reading and writing circuit are also found in the data reading and writing method.

[0103] As shown in Figures 3, 6, 7, and 8, in a data read / write method according to some embodiments of the present disclosure, the data read / write cycle t of the storage unit U includes a write cycle tW, a read cycle tR, and standby stages (e.g., a first standby stage tD1 and a second standby stage tD2).

[0104] In some embodiments, as shown in Figure 6, the write cycle tW includes a pre-charge stage tW1 and a data write stage tW2. The data read / write method includes steps S100 and S200.

[0105] In S100, during the pre-charge stage tW1, the data signal line BL1 supplies a first reference voltage V1 to the memory transistor T1, and the auxiliary signal line BL2 simultaneously supplies the first reference voltage V1 to the memory transistor T1 and the write transistor T2, turning on the write transistor T2 and pre-charging the memory node SN. Here, the sum of the maximum data voltage corresponding to the data that the memory unit U can store and the threshold voltage Vth of the memory transistor T1 is the reference voltage, and the first reference voltage V1 is greater than the reference voltage.

[0106] At this point, after the pre-charging of memory node SN is complete, the voltage of memory node SN becomes the first reference voltage V1.

[0107] For example, the data that memory unit U can store includes data "0" and data "1", where the data voltage Vdata1 corresponding to data "1" is greater than the data voltage Vdata0 corresponding to data "0". Based on this, the data voltage Vdata1 corresponding to data "1" becomes the maximum data voltage that memory unit U can store. The reverse is also true.

[0108] Based on this, if the data voltage Vdata1 corresponding to data "1" is set as the maximum data voltage that the storage unit U can store, then the reference voltage is Vdata1 + Vth, and the first reference voltage is greater than Vdata1 + Vth. The difference between the first reference voltage and the reference voltage can be set reasonably according to the needs.

[0109] For the sake of explanation, the reference voltage is defined here as the sum of the maximum data voltage and the threshold voltage Vth of the memory transistor T1, and is merely used to indicate the range of values ​​for the first reference voltage when the reference voltage is used as the reference.

[0110] In some embodiments, the memory transistor T1 employs a double-gate structure comprising a first gate G1 and a memory gate G0. The first gate G1 is connected to the first control signal line WL and is the control gate of the memory transistor T1, used to control the on and off states of the memory transistor T1. The memory gate G0 is a floating gate and is connected to the write transistor T2, used to capture charge and store data. The threshold voltage Vth of the memory transistor T1 is defined as the threshold voltage Vth corresponding to the memory gate G0 stored in the memory transistor T1 when the first control signal line WL supplies a preset voltage to the first gate G1.

[0111] For example, the memory transistor T1 is an N-type transistor, and the preset voltage supplied by the first control signal line WL to the first gate G1 is a fixed high-level voltage. However, this is not limited to this; for example, the memory transistor T1 could be a P-type transistor, which would allow for adaptive adjustment of the voltage signals of the first gate G1 and other components connected to the memory transistor T1 to enable data reading. Similarly, the write transistor T2 could be an N-type or P-type transistor.

[0112] Furthermore, the second gate G2 of the write transistor T2 is connected to the second control signal line WWL, and can be turned on or off in response to the control signal supplied by the second control signal line WWL. For the sake of explanation, some of the following embodiments will be described using the example that the memory transistor T1 and the write transistor T2 are N-type transistors.

[0113] In some embodiments, as shown in Figures 3, 6, 7, and 8, during the pre-charge stage tW1, the first control signal line WL supplies a first write control voltage VCW1 to the first gate G1 of the memory transistor T1. The second control signal line WWL supplies a second write control voltage VCW2 to the second gate G2 of the write transistor T2. In this case, the data signal line BL1 supplies a first reference voltage V1 to the first pole of the memory transistor T1, and the auxiliary signal line BL2 supplies a first reference voltage V1 to the second pole of the memory transistor T1, and the memory transistor T1 is in an ON state. Illustratively, both the first write control voltage VCW1 and the second write control voltage VCW2 are high-level voltages.

[0114] For example, the first write control voltage VCW1 is smaller than the second write control voltage VCW2, and the first write control voltage VCW1 can be reasonably set according to the needs.

[0115] In S200, during the data writing stage tW2, in response to the write command, the auxiliary signal line BL2 is floated, and the data signal line BL1 supplies the data voltage Vdata to the memory transistor T1. The memory transistor T1 turns on, discharges the memory node SN to a steady state, and writes the data data corresponding to the data voltage Vdata.

[0116] Here, discharging memory node SN to a steady state means that the voltage change across memory node SN tends to become zero. After discharging memory node SN to a steady state, the voltage across memory node SN will be Vdata + Vth (including being approximately equal).

[0117] Then, as shown in Figures 6, 7, and 8, during the data writing stage tW2, the first control signal line WL continues to supply the first write control voltage VCW1 to the first gate G1 of the memory transistor T1. The second control signal line WWL continues to supply the second write control voltage VCW2 to the second gate G2 of the write transistor T2. In this case, the data signal line BL1 supplies the data voltage Vdata to the first pole of the memory transistor T1, the auxiliary signal line BL2 is floating, and the memory transistor T1 is in the ON state.

[0118] Furthermore, the data voltage Vdata supplied by the data signal line BL1 is associated with the data to be written. For example, if the data to be written is "1", the data voltage supplied by the data signal line BL1 at the data writing stage tW2 is Vdata1. Also, for example, if the data to be written is "0", the data voltage supplied by the data signal line BL1 at the data writing stage tW2 is Vdata0.

[0119] In some embodiments, as shown in Figures 4 and 5, the auxiliary signal line BL2 is connected to the first reference voltage terminal v1 via the second gate circuit 20 and to the second reference voltage terminal v2 via the third gate circuit 30. The floating of the auxiliary signal line BL2 means that both the second gate circuit 20 and the third gate circuit 30 connected to the auxiliary signal line BL2 are in the off state, and there is no signal input at the end of the auxiliary signal line BL2 connecting the second gate circuit 20 and the third gate circuit 30.

[0120] In some embodiments, the write cycle tW further includes a data retention phase tW3 that follows the data writing phase tW2.

[0121] In some examples, as shown in Figure 7, the data reading and writing method further includes step S300.

[0122] In S300, during the data holding stage tW3, the voltage of the data signal line BL1 is pulled up to the first reference voltage V1. After the voltage of the data signal line BL1 reaches the first reference voltage V1, the write transistor T2 is turned off first, and then the voltage of the auxiliary signal line BL2 is pulled up to the first reference voltage V1.

[0123] Furthermore, as shown in Figure 7, after turning off the write transistor T2, the data read / write method further includes applying a first off-control voltage VCG1 to the storage transistor T1.

[0124] In the embodiments of this disclosure, during the data retention stage tW3 after writing data to the storage node SN, the voltage of the data signal line BL1 is pulled up to the first reference voltage V1, and the storage transistor T1 can be turned off by the voltage difference between the first pole S / D11 of the storage transistor T1 and the storage node SN. In this case, the write transistor T2 connecting the storage node SN and the auxiliary signal line BL2 is turned on, and the voltage stability of the storage node SN can be maintained (for example, held at Vdata+Vth) based on the coupling effect between the data signal line BL1 and the auxiliary signal line BL2. Subsequently, the write transistor T2 is turned off first, and then the auxiliary signal line BL2 simultaneously supplies the first reference voltage V1 to the storage transistor T1 and the write transistor T2, thereby allowing the data to be retained in the storage node SN (where the voltage of the storage node SN includes Vdata+Vth).

[0125] In the data reading stage tR, the data signal line BL1 reads the data data depending on whether the memory transistor T1 is turned on or not, and it can be understood that the data data is read by the change in current or voltage transmitted on the data signal line BL1. Therefore, in the data holding stage tW3, after turning off the write transistor T2, a first off control voltage VCG1 can also be applied to the memory transistor T1 using the first control signal line WL. In this way, not only can the off state of the memory transistor T1 be further ensured and leakage current can be prevented, but it is also possible to easily implement data reading scan control by applying a read control voltage VCR to the memory transistor T1 with the first control signal line WL, as described later.

[0126] Here, as shown in Figure 7, in the data holding stage tW3, after turning off the write transistor T2, the voltage of the auxiliary signal line BL2 may be pulled up to the first reference voltage V1 first, or the first off control voltage VCG1 may be applied to the storage transistor T1 via the first control signal line WL, or both may be done simultaneously.

[0127] Then, after the write transistor T2 is turned off, the first control signal line WL applies the first off-control voltage VCG1 to the memory transistor T1, and the voltage of the memory node SN changes accordingly. For example, if the first off-control voltage VCG1 is a low-level voltage, and the data written to the memory node SN is data "1", the voltage of the memory node SN can change as Vdata1 + Vth - ΔV, and if the data written to the memory node SN is data "0", the voltage of the memory node SN can change as Vdata0 + Vth - ΔV.

[0128] Correspondingly, in the subsequent data reading step tR, when the first control signal line WL applies the read control voltage VCR to the memory transistor T1, the voltage of the memory node SN changes accordingly. For example, if the read control voltage VCR is a high-level voltage, and the data written to the memory node SN is data "1", the voltage of the memory node SN can change as follows: Vdata1 + Vth - △V + △V', and if the data written to the memory node SN is data "0", the voltage of the memory node SN can change as follows: Vdata0 + Vth - △V + △V'.

[0129] In the embodiments of this disclosure, the voltage of the storage node SN changes after the first control signal line WL applies a first off-control voltage VCG1 or a read control voltage VCR to the storage transistor T1, but the voltage of the storage node SN always includes the data voltage Vdata corresponding to writing data and the threshold voltage Vth of the storage transistor T1, and the voltage of the storage node SN is the same even when corresponding to different data voltages (e.g., Vdata1 and Vdata0), and does not affect the correct reading of data in the data reading stage tR.

[0130] In some other examples, as shown in Figure 8, the data reading and writing method further includes step S300'.

[0131] In S300', during the data holding stage tW3, the voltage of the data signal line BL1 is first pulled up to the first reference voltage V1, the memory transistor T1 is turned off, then the write transistor T2 is turned off, and the voltage of the auxiliary signal line BL2 is pulled up to the first reference voltage V1.

[0132] Here, it can be understood that turning off the memory transistor T1 can be achieved by controlling it with the first off-control voltage VCG1 applied to the first gate G1 by the first control signal line WL. Turning off the write transistor T2 can be achieved by controlling it with the second off-control voltage VCG2 applied to the second gate G2 by the second control signal line WWL.

[0133] For example, the first off-control voltage VCG1 is the same as the second off-control voltage VCG2.

[0134] For example, memory transistor T1 and writing transistor T2 are both N-type transistors. Correspondingly, the first off-control voltage VCG1 and the second off-control voltage VCG2 are both low-level voltages.

[0135] In the embodiments of this disclosure, after writing data to the storage node SN, the storage transistor T1 is first turned off, and then the voltage of the data signal line BL1 is pulled up to the first reference voltage V1. In this case, the write transistor T2 connecting the storage node SN and the auxiliary signal line BL2 remains on, maintaining the stability of the voltage of the storage node SN (for example, held at Vdata + Vth). Subsequently, the write transistor T2 is turned off, and then the auxiliary signal line BL2 simultaneously supplies the first reference voltage to the storage transistor T1 and the write transistor T2, thereby preventing leakage current from occurring in the write transistor T2 and stabilizing the data in the storage node SN (for example, the voltage of the storage node SN being Vdata + Vth).

[0136] In some embodiments, as shown in Figures 6, 7, and 8, the reading period tR includes a data reading step tR. The data reading and writing method further includes step S400.

[0137] In S400, during the data reading stage tR, a read control voltage VCR is applied to the memory transistor T1 in accordance with the read command, and a second reference voltage V2 is simultaneously supplied to the memory transistor T1 and the write transistor T2 via the auxiliary signal line BL2. Here, the data signal line BL1 is further configured to read data depending on whether the memory transistor is turned on or not.

[0138] For example, the second reference voltage V2 is smaller than the first reference voltage V1.

[0139] For example, the second reference voltage V2 is greater than the minimum data voltage of data that the storage unit U can store, and less than the maximum data voltage of data that the storage unit U can store. For instance, Vdata1 > V2 > Vdata0.

[0140] In the actual application of the data read / write circuit, considering the coupling effect between the data signal line BL1 and the auxiliary signal line BL2, the second reference voltage V2 can be made greater than the sum of the minimum data voltage and the voltage variable (vector) due to the coupling effect, and less than the sum of the maximum data voltage and the voltage variable (vector) due to the coupling effect. For example, in the data reading stage tR, the first control signal line WL applies a read control voltage VCR to the first gate G1 of the memory transistor T1. The read control voltage VCR and the first write control voltage VCW1 supplied by the first control signal line WL during the write period tW may be the same or different.

[0141] For example, the read control voltage VCR is the same as the first write control voltage VCW1.

[0142] For example, the read control voltage VCR is higher than the first write control voltage VCW1.

[0143] Here, the read control voltage VCR applied to the memory transistor T1 in response to a read command means that, by an appropriate voltage applied by the first control signal line WL, it is possible to ensure that the memory transistor T1 corresponds to different states when storing different data in the memory node SN.

[0144] As an example, as shown in Figures 6, 7, 8, and 9, the data written to the memory node SN includes "1" or "0". In the data reading stage tR, after applying the read control voltage VCR to the memory transistor T1,

[0145] If the data stored in memory node SN is "1", the gate-source voltage VGS of memory transistor T1 (i.e., the voltage difference between the memory gate G0 and its second pole S / D12) is large and greater than the threshold voltage Vth of memory transistor T1, and memory transistor T1 is in the ON state;

[0146] If the data stored in memory node SN is "0", the gate-source voltage VGS of memory transistor T1 (i.e., the voltage difference between memory gate G0 and its second pole S / D12) is small, and is smaller than the threshold voltage Vth of memory transistor T1, so memory transistor T1 is in the off state.

[0147] To more clearly explain the data reading process in the data reading stage tR, the data reading methods shown in Figures 6 and 8 are illustrated below, and the data reading method shown in Figure 7 can be understood adaptively.

[0148] In the data reading stage tR, the voltage at the memory gate G0 of memory transistor T1 is the voltage after writing the data "1" to memory node SN, i.e., = Vdata1 + Vth. The voltage at the second pole S / D12 of memory transistor T1 is the second reference voltage V2 supplied by the auxiliary signal line BL2. The gate-source voltage VGS of memory transistor T1 becomes Vdata1 + Vth - V2. Since V2 is smaller than Vdata1, the gate-source voltage VGS of memory transistor T1 is greater than Vth.

[0149] In the data reading stage tR, the voltage at the memory gate G0 of memory transistor T1 is the voltage after writing the data "0" to memory node SN, i.e., = Vdata0 + Vth. The voltage at the second pole S / D12 of memory transistor T1 is the second reference voltage V2 supplied by the auxiliary signal line BL2. The gate-source voltage VGS of memory transistor T1 becomes Vdata0 + Vth - V2. Since V2 is greater than Vdata0, the gate-source voltage VGS of memory transistor T1 is less than Vth.

[0150] Furthermore, as shown in Figures 4, 5, 6, 7, and 8, the method by which the data read / write circuit reads data, depending on whether the data signal line BL1 is turned on or off when the memory transistor is turned on, can be described as current-sensing reading or voltage-sensing reading.

[0151] For example, in the data reading stage tR, the data signal line BL1 continues to provide a first reference voltage V1, and depending on whether the memory transistor T1 is turned on or not, the sense amplifier circuit 40 connected to the data signal line BL1 can read the data by detecting the change in current transmitted through the data signal line BL1.

[0152] For example, in the data reading stage tR, the first reference voltage V1 supplied in advance by the data signal line BL1 may or may not be changed depending on whether the memory transistor T1 is turned on or not, and the sense amplifier circuit 40 can read the data by detecting the change in voltage transmitted on the data signal line BL1.

[0153] In particular, in some embodiments, as shown in Figures 6, 7, and 8, the data read / write cycle t further includes a standby phase (i.e., a Standby phase) that precedes the precharge phase tW1 and / or the data read phase tR.

[0154] Exemplary, as shown in Figure 7, the data read / write cycle t further includes a data hold phase tW3 following the data write phase tW2. The data read phase tR follows the data hold phase tW3. The standby phase includes a first standby phase tD2 prior to the precharge phase tW1, and a second standby phase tD2 following the data hold phase tW3 and prior to the data read phase tR.

[0155] Accordingly, the data reading and writing method according to the embodiments of this disclosure further includes the following steps:

[0156] During the standby phase (including the first standby phase tD1 and the second standby phase tD2), the memory transistor T1 and the write transistor T2 are in the off state, the data signal line BL1 supplies the first reference voltage V1 to the memory transistor T1, and the auxiliary signal line BL2 simultaneously supplies the first reference voltage V1 to the memory transistor T1 and the write transistor T2.

[0157] In the embodiments of this disclosure, during the standby phase, a first reference voltage V1 is supplied to the first pole of the memory transistor T1 using the data signal line BL1, and the first reference voltage V1 is supplied to the second pole of the memory transistor T2 using the auxiliary signal line BL2. This ensures that there is no large differential voltage between the first and second poles of the memory transistor T1, and effectively reduces the risk of leakage current generation. This is especially true when the first reference voltage V1 is a high-level voltage.

[0158] Furthermore, the first standby stage tD1 and the second standby stage tD2 in some of the above embodiments can be understood as standby stages related to the data read / write circuit described above. Combining the above, the first standby stage tD1 is independent of the write cycle tw, and the second standby stage tD2 is independent of the read cycle tR. In some examples, the first standby stage tD1 and the second standby stage tD2 can be considered the same standby stage based on the fact that the voltage signals supplied by the data signal line BL1, auxiliary signal line BL2, first control signal line WL, and second control signal line WWL are the same during the first and second standby stages tD1 and tD2, and enter different read / write cycles depending on the difference in the received command. For example, in response to receiving a write command, the system enters the write cycle, or in response to receiving a read command, the system enters the read cycle.

[0159] In the first standby stage tD1 and the second standby stage tD2, the first control signal line WL applies a first off-control voltage VCG1 to the first gate G1 of the memory transistor T1, and the second control signal line WWL applies a second off-control voltage VCG2 to the second gate G2 of the write transistor T2.

[0160] For example, the first off-control voltage VCG1 is the same as the second off-control voltage VCG2.

[0161] For example, memory transistor T1 and writing transistor T2 are both N-type transistors. The first off-control voltage VCG1 and the second off-control voltage VCG2 are both low-level voltages.

[0162] In embodiments of the present disclosure, the storage unit U is configured to store data and comprises a connected storage transistor T1 and a write transistor T2. In embodiments of the present disclosure, by connecting a data signal line BL2 to the storage transistor T1 in the storage unit U, and connecting an auxiliary signal line BL2 to the storage transistor T1 and the write transistor T2 in the storage unit U, in the pre-charge stage tW1, the data signal line BL1 supplies a first reference voltage V1 to the storage transistor T1, and the auxiliary signal line BL2 simultaneously supplies the first reference voltage V1 to the storage transistor T1 and the write transistor T2, and after turning on the write transistor T2, the storage node SN of the storage unit U can be pre-charged. Based on the first reference voltage V1 being greater than a reference voltage (i.e., the sum of the maximum data voltage corresponding to the data that the storage unit U can store and the threshold voltage of the first transistor T1, for example, Vdata1 + Vth), i.e., V1 > (Vdata1 + Vth), the voltage of the storage node SN of the storage unit U can be pre-charged. TIFF2026514171000002.tif8167 may be greater than the reference voltage, for example, greater than (Vdata1 + Vth). In this way, during the data writing stage tW2, the auxiliary signal line BL2 is floated in accordance with the write command, and after the data signal line BL1 supplies the data voltage Vdata to the memory transistor T1, the memory transistor T1 is turned on, allowing the memory node SN to naturally discharge to a steady state, and the data data corresponding to the aforementioned data voltage Vdata can be written.

[0163] In the embodiments of this disclosure, the voltage of the storage node SN after precharging is greater than the reference voltage (for example, greater than (Vdata1 + Vth)), that is, the voltage of the storage node SN is greater than the data voltage Vdata supplied by the data signal line BL1, and the difference between the voltage of the storage node SN and the aforementioned data voltage Vdata is greater than the threshold voltage Vth of the storage transistor T1. Therefore, after the storage node SN is discharged to a steady state, the voltage of the storage node SN corresponds to the sum of the aforementioned data voltage Vdata and the threshold voltage Vth of the storage transistor T1. The file is TIFF2026514171000003.tif8167, and when the data is written, the threshold compensation voltage of the memory transistor T1 is also calculated. The file TIFF2026514171000004.tif8167 can be stored in the memory node SN.

[0164] Based on this, after writing the data, some embodiments of this disclosure can turn off the storage transistor T1 and the write transistor T2 (see the description of the data holding stage tW3 for details). Then, in the second standby stage tD2, the first reference voltage V1 can be supplied to the storage transistor T1 using the data signal line BL1 and the auxiliary signal line BL2, respectively, and the first reference voltage V1 can be supplied to the write transistor T2 using the auxiliary signal line BL2. In this case, both the first transistor T1 and the write transistor T2 are in the off state, and the voltage stability of the storage node SN can be ensured.

[0165] Subsequently, in the data reading stage tR, a read control voltage VCR is applied to the memory transistor T1 according to the read command, and a second reference voltage V2 can be simultaneously supplied to the memory transistor T1 and the write transistor T2 via the auxiliary signal line BL2. After the data signal line BL1 supplies the first reference voltage V1, the auxiliary signal line BL1 supplies the second reference voltage V2, and the read control voltage VCR is applied to the memory transistor T1, the magnitude of the voltage stored in the memory node SN affects the presence or absence of conduction between the first and second poles of the memory transistor T1, and the data signal line BL1 can read the data depending on whether the memory transistor T1 is turned on or not. The threshold compensation voltage of the memory transistor T1 is applied to the voltage stored in the memory node SN. Because TIFF2026514171000005.tif8167 is included, the data read by the data signal line BL1 depending on whether the memory transistor T1 is turned on or not is not affected by the threshold voltage Vth of the memory transistor T1, ensuring the accuracy of data reading and further improving memory performance.

[0166] Another embodiment of some of the embodiments of the present disclosure provides a memory. As shown in Figures 3, 4 and 5, it comprises at least one storage unit U, a first bit line BL1, a second bit line BL2, a first word line WL, and a second word line WWL connected to the storage unit U. Here, the storage unit U comprises a storage transistor T1 and a write transistor T2. The storage transistor T1 comprises a storage gate G0, a first gate G1, a first pole S / D11, and a second pole S / D12. The write transistor T2 comprises a second gate G2, a first pole S / D21, and a second pole S / D22. The storage gate G0 is connected to the first pole S / D21 of the write transistor T2, and the intersection of the storage gate G0 and the first pole S / D21 of the write transistor T2 is a storage node SN. The first word line WL is connected to the first gate G1, and the second word line WWL is connected to the second gate G2. The first bit line BL1 is connected to the first pole S / D11 of the memory transistor T1, and the second bit line BL2 is simultaneously connected to the second pole S / D12 of the memory transistor T1 and the second pole S / D22 of the write transistor T2. Here, the first bit line BL1 is configured to supply a data voltage to the data to be written during the data writing phase, and to read the data written to the memory node during the data reading phase depending on whether the memory transistor T1 is turned on or not.

[0167] Here, if the current transmission direction is matched, and the first pole S / D11 and second pole S / D12 of the memory transistor T1, one may be the source and the other the drain. If the first pole S / D21 and second pole S / D22 of the write transistor T2, one may be the source and the other the drain. In Figure 3, the memory transistor T1 and the write transistor T2 are explained as examples where both are N-type transistors, but in actual applications, the type of transistor is not limited.

[0168] Furthermore, combining the descriptions of the data read / write circuits in some of the embodiments described above, the function of the first bit line BL1 in the memory is the same as the function of the data signal line described above, the function of the second bit line BL2 is the same as the function of the auxiliary signal line described above, the function of the first word line WL is the same as the function of the first control signal line described above, and the function of the second word line WWL is the same as the function of the second control signal line described above. The structure and use of the first bit line BL1, the second bit line BL2, the first word line WL, and the second word line WWL in the memory can be referred to in correspondence with the data read / write circuits in the embodiments described above, and will not be described in detail here.

[0169] Some embodiments of this disclosure further provide a method for driving the above-mentioned memory. As shown in Figures 3, 6, 7, and 8, the method includes the following steps.

[0170] In the pre-charge stage tW1, the first bit line BL1 supplies the first reference voltage V1 to the first pole S / D11 of the memory transistor T1. The second bit line BL2 simultaneously supplies the first reference voltage V1 to the second pole S / D12 of the memory transistor T1 and the second pole S / D22 of the write transistor T1. The first word line WL applies the first write control voltage VCW1 to the first gate G1. The second word line WWL applies the third write control voltage VCW3 to the second gate G2, controlling the write transistor T2 to turn on and pre-charge the memory node SN. Here, the first reference voltage V1 is greater than the sum of the maximum data voltage to be written in the memory unit U and the threshold voltage VTH of the memory transistor T1.

[0171] During the data writing stage tW2, the second bit line BL2 is floated, and the first bit line BL1 supplies the data voltage Vdata to the first pole S / D11 of the memory transistor T1. The memory transistor T1 is turned on, discharges the memory node SN to a steady state, and writes the data data corresponding to the data voltage.

[0172] In the data reading stage tR, the second word line WWL applies the second off control voltage VCG2 to the second gate G2, and the write transistor T2 is in the off state. The first word line WL applies the read control voltage VCR to the first gate G1. The second bit line BL2 simultaneously supplies the second reference voltage V2 to the second pole S / D12 of the memory transistor T1 and the second pole S / D22 of the write transistor T2. The first bit line BL1 reads the data written to the memory node SN depending on whether the memory transistor T1 is turned on or not.

[0173] In some embodiments, as shown in Figure 7, the method further includes pulling up the voltage of the first bit line BL1 to the first reference voltage V1 during the data holding stage tW3, and after the voltage of the first bit line BL1 reaches the first reference voltage, turning off the write transistor T2 first, and then pulling up the voltage of the second bit line BL2 to the first reference voltage V1.

[0174] Furthermore, as shown in Figure 7, after turning off the write transistor T2, the method further includes applying a first off-control voltage VCG1 to the first gate G1 via the first word line WL.

[0175] For example, the first off-control voltage VCG1 is the same as the second off-control voltage VCG2.

[0176] For example, both the memory transistor T1 and the write transistor T2 are N-type transistors. Correspondingly, both the first write control voltage VCW1 and the second write control voltage VCW2 are high-level voltages. Both the first off-control voltage VCG1 and the second off-control voltage VCG2 are low-level voltages. Furthermore, the first write control voltage VCW1 may be smaller than the second write control voltage VCW2, and the first write control voltage VCW1 can be set rationally according to the needs.

[0177] In some examples, as shown in Figure 7, during the data holding stage tW3, after turning off the write transistor T2, the voltage of the second bit line BL2 may be pulled up to the first reference voltage V1 first, or the first off control voltage VCG1 may be applied to the first gate G1 via the first word line WL, or both may be done simultaneously.

[0178] In some other embodiments, as shown in Figure 8, the method further includes, during the data holding stage tW3, first applying a first off-control voltage VCG1 to the first gate G1 via the first word line WL, pulling up the voltage of the first bit line BL1 to the first reference voltage V1, then turning off the write transistor T2, and pulling up the voltage of the second bit line BL2 to the first reference voltage V1.

[0179] Here, it can be understood that turning off the write transistor T2 can be achieved by applying a second off-control voltage VCG2 to the second gate G2 via the second word line WWL.

[0180] In particular, in some embodiments, as shown in Figures 6, 7, and 8, the method further includes the following: in a first standby stage tD1 prior to the precharge stage tW1, and in a second standby stage tD2 after the data holding stage tW3 and before the data reading stage tR, the first word line WL applies a first off-control voltage VCG1 to the first gate G1, the second word line WWL applies a second off-control voltage VCG2 to the second gate G2, the first bit line BL1 supplies a first reference voltage V1 to the first pole S / D11 of the memory transistor T1, and the second bit line BL2 simultaneously supplies the first reference voltage V1 to the second pole S / D12 of the memory transistor T1 and the second pole S / D22 of the writing transistor T2.

[0181] The technical principles of the driving method according to some of the above embodiments can be adaptively understood by referring to the technical principles of the data reading and writing method described above, but they will not be explained in detail here.

[0182] Some embodiments of this disclosure further provide electronic devices, such as data storage devices, photocopiers, network devices, home appliances, instruments, mobile phones, and computers, which have data storage capabilities. These electronic devices comprise a housing, a circuit board located within the housing, and a memory or data read / write circuit integrated on the circuit board. The structure of the memory or data read / write circuit can be described by referring to the relevant descriptions in the above embodiments. The electronic devices may further comprise other necessary elements or components, and the embodiments of this disclosure are not limited thereto.

[0183] In some embodiments, the memory may be coupled to an external control device such as a processor or actuator. The processor is coupled to the memory, and the processor can control the memory read operations.

[0184] In some embodiments, the memory is a three-dimensional dynamic random access memory.

[0185] The technical features of the embodiments described above can be combined in any way; for the sake of brevity, not all possible combinations of the constituent elements of the above embodiments have been described, but as long as these combinations of constituent elements are consistent, they should be considered to fall within the scope described herein.

[0186] The embodiments described above illustrate some of the embodiments of the present disclosure, and while the description is more specific and detailed, this should not be understood as limiting the scope of the claims. Those skilled in the art can make several modifications and improvements, provided they do not deviate from the concepts of the present disclosure, and these fall within the scope of the present disclosure. Therefore, the scope of the present disclosure should be based on the claims.

Claims

1. A method for reading and writing data, The data reading and writing method described above is applied to a storage unit, which is configured to store data and comprises connected storage transistors and write transistors, and the data reading and writing cycle of the storage unit includes a pre-charge stage and a data writing stage. The aforementioned data reading and writing method is: In the pre-charge stage, the data signal line supplies a first reference voltage to the memory transistor, and the auxiliary signal line simultaneously supplies the first reference voltage to the memory transistor and the write transistor, causing the write transistor to turn on and pre-charge the memory node between the write transistor and the memory transistor. In the data writing stage, in response to the write command, the auxiliary signal line is floated, the data signal line supplies a data voltage to the storage transistor, the storage transistor turns on, the storage node is discharged to a steady state, and data corresponding to the data voltage is written. Includes, The sum of the maximum data voltage corresponding to the aforementioned data and the threshold voltage of the memory transistor is the reference voltage, and the first reference voltage is greater than the reference voltage. Data reading and writing methods.

2. The aforementioned data read / write cycle further includes a data holding stage that follows the data writing stage, The aforementioned data reading and writing method is: The data holding stage further includes pulling up the voltage of the data signal line to the first reference voltage, and after the voltage of the data signal line reaches the first reference voltage, turning off the write transistor first, and then pulling up the voltage of the auxiliary signal line to the first reference voltage. After turning off the write transistor, the data read / write method further includes applying a first off-control voltage to the storage transistor. The data reading and writing method according to claim 1.

3. The aforementioned data read / write cycle further includes a data holding stage that follows the data writing stage, The aforementioned data reading and writing method is: The data retention stage further includes first turning off the memory transistor, pulling up the voltage of the data signal line to the first reference voltage, then turning off the write transistor, and pulling up the voltage of the auxiliary signal line to the first reference voltage. The data reading and writing method according to claim 1 or 2.

4. The aforementioned data read / write cycle further includes a data read step, The aforementioned data reading and writing method is: The data reading step further includes applying a read control voltage to the storage transistor in response to a read command, and simultaneously supplying a second reference voltage to the storage transistor and the write transistor via the auxiliary signal line. The data signal line is further configured to read data depending on whether the memory transistor is turned on or not. A data reading and writing method according to any one of claims 1 to 3.

5. The data written to the memory node includes "1" or "0", and in the data reading stage, if the data stored in the memory node is "1", the memory transistor is in the ON state, and if the data stored in the memory node is "0", the memory transistor is in the OFF state. A data reading and writing method according to any one of claims 1 to 4.

6. The data read / write cycle further includes a standby phase that precedes the precharge phase and / or the data read phase, The aforementioned data reading and writing method is: The standby phase further includes the following: the memory transistor and the write transistor are in an off state, the data signal line supplies the first reference voltage to the memory transistor, and the auxiliary signal line simultaneously supplies the first reference voltage to the memory transistor and the write transistor. A data reading and writing method according to any one of claims 1 to 5.

7. The data read / write cycle further includes a data holding stage that follows the data writing stage, and the data read stage follows the data holding stage. The standby stage includes a first standby stage prior to the pre-charge stage, and a second standby stage after the data holding stage and before the data reading stage. The data reading and writing method according to claim 6.

8. A data read / write circuit, A storage unit configured to store data, comprising connected storage transistors and write transistors, A data signal line connected to the memory transistor, configured to supply a first reference voltage to the memory transistor during the standby and pre-charge phases, write data to the memory transistor during the data writing phase, and read data during the data reading phase depending on whether the memory transistor is turned on or not. An auxiliary signal line connected to the memory transistor and the write transistor, configured to simultaneously supply the first reference voltage to the memory transistor and the write transistor during the standby and pre-charge phases, to be floating during the data writing phase, and to simultaneously supply the second reference voltage to the memory transistor and the write transistor during the data reading phase, Equipped with, The sum of the maximum data voltage corresponding to the aforementioned data and the threshold voltage of the memory transistor is the reference voltage, and the first reference voltage is greater than the reference voltage. Data read / write circuit.

9. A first control signal line connected to the memory transistor, configured to control the memory transistor to turn off during the standby phase, apply a first write control voltage to the memory transistor during the precharge phase and the data write phase, and apply a read control voltage to the memory transistor during the data read phase, A second control signal line connected to the write transistor, configured to control the write transistor to turn off during the standby phase and the data reading phase, and to control the write transistor to turn on during the pre-charge phase and the data writing phase, It also has, The data read / write circuit according to claim 8.

10. The data signal line is further configured to supply the first reference voltage to the memory transistor during the data retention phase. The second control signal line is further configured to control the write transistor to turn off after the voltage of the data signal line becomes the first reference voltage during the data holding stage. The auxiliary signal line is further configured to simultaneously supply the first reference voltage to the storage transistor and the write transistor after turning off the write transistor during the data holding stage. The first control signal line is further configured to apply a first off-control voltage to the storage transistor after turning off the write transistor during the data holding stage. The data read / write circuit according to claim 9.

11. The first control signal line is further configured to turn off the memory transistor earlier than the write transistor during the data holding phase. The data signal line is further configured to supply the first reference voltage to the storage transistor after turning off the storage transistor during the data holding stage. The second control signal line is further configured to control the write transistor to turn off after the data signal line has supplied the first reference voltage during the data holding stage. The auxiliary signal line is further configured to simultaneously supply the first reference voltage to the storage transistor and the write transistor after turning off the write transistor during the data holding stage. The data read / write circuit according to claim 9 or 10.

12. The memory transistor comprises a memory gate, a first gate, a first pole, and a second pole, and the writing transistor comprises a second gate, a first pole, and a second pole. The first gate is connected to the first control signal line, The second gate is connected to the second control signal line, The first pole of the memory transistor is connected to the data signal line, The first pole of the write transistor is connected to the memory gate, and the intersection of the first pole of the write transistor and the memory gate is a memory node. The second pole of the memory transistor and the second pole of the writing transistor are each connected to the auxiliary signal line. A data read / write circuit according to any one of claims 9 to 11.

13. The number of the aforementioned storage units is multiple, and the multiple storage units are arranged in rows along a first direction and in columns along a second direction, and the first direction intersects with the second direction. The single row of storage units shares one data signal line and one auxiliary signal line. Each of the memory units in a row shares one of the first control signal lines and one of the second control signal lines. A data read / write circuit according to any one of claims 9 to 12.

14. A first reference voltage terminal is connected via a first gate circuit to correspond to the data signal line and via a second gate circuit to correspond to the auxiliary signal line, A second reference voltage terminal connected via a third gate circuit to the auxiliary signal line, Furthermore, The first reference voltage terminal is configured to supply the first reference voltage, the first gate circuit is configured to selectively connect the first reference voltage terminal and the data signal line during the standby phase and the precharge phase, and the second gate circuit is configured to selectively connect the first reference voltage terminal and the auxiliary signal line during the standby phase and the precharge phase. The second reference voltage terminal is configured to supply the second reference voltage, and the third gate circuit is configured to selectively connect the second reference voltage terminal and the auxiliary signal line during the data reading stage. A data read / write circuit according to any one of claims 8 to 13.

15. It is memory, The memory comprises at least one storage unit, a first bit line, a second bit line, a first word line, and a second word line connected to the storage unit, The memory unit comprises a memory transistor and a write transistor, the memory transistor comprising a memory gate, a first gate, a first pole and a second pole, and the write transistor comprising a second gate, a first pole and a second pole. The memory gate is connected to the first pole of the write transistor, and the intersection of the memory gate and the first pole of the write transistor is a memory node. The first word line is connected to the first gate, and the second word line is connected to the second gate. The first bit line is connected to the first pole of the memory transistor, and the second bit line is simultaneously connected to the second pole of the memory transistor and the second pole of the write transistor. The first bit line is configured to supply a first reference voltage to the first pole of the memory transistor during the pre-charge phase, supply a data voltage of data awaiting writing to the memory transistor during the data writing phase, and read the data written to the memory node during the data reading phase depending on whether the memory transistor has been turned on or not. The second bit line is configured to simultaneously supply the first reference voltage to the second pole of the memory transistor and the second pole of the write transistor during the pre-charge phase, to be loaded during the data writing phase, and to simultaneously supply the second reference voltage to the memory transistor and the write transistor during the data reading phase. The first reference voltage is greater than the sum of the maximum data voltage to be written in the memory unit and the threshold voltage of the memory transistor. Memory.

16. A method of driving memory, Applicable to the memory described in claim 15, the method is In the pre-charge phase, the first bit line supplies a first reference voltage to the first pole of the memory transistor, the second bit line supplies the first reference voltage to the second pole of the memory transistor and the second pole of the write transistor, the first word line applies a first write control voltage to the first gate, the second word line applies a second write control voltage to the second gate, and the write transistor is controlled to turn on to pre-charge the memory node. During the data writing phase, the second bit line is floated, the first bit line supplies a data voltage to the first pole of the memory transistor, the memory transistor turns on, the memory node is discharged to a steady state, and data corresponding to the data voltage is written. In the data reading stage, the second word line applies a second off control voltage to the second gate, the write transistor is in the off state, the first word line applies a read control voltage to the first gate, the second bit line simultaneously supplies a second reference voltage to the second pole of the memory transistor and the second pole of the write transistor, and the first bit line reads the data written to the memory node depending on whether the memory transistor has been turned on or not. Includes, The first reference voltage is greater than the sum of the maximum data voltage to be written in the memory unit and the threshold voltage of the memory transistor. The method of driving memory.

17. It is an electronic device, A data read / write circuit according to any one of claims 8 to 14, or a memory according to claim 15, electronic equipment.

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