3D DRAM access transistor

Abstract

This specification discloses a method for forming a three-dimensional dynamic random access memory device with reduced floating body effects. In one embodiment, the method may include forming a plurality of layers stacked in a first direction, the plurality of layers including a gate layer formed on a first oxide layer and source / drain (S / D) layers between the series of gate oxide layers. The series of gate oxide layers may be formed on top of the gate layer, and the S / D layers may include a source and a drain located on opposite sides of the body. The method may further include forming doped layers on top of the source and drain.

Description

Technical Field

[0001] Related Applications

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 499,888, filed May 3, 2023, entitled "3D Dram Access Transistor", the entire contents of which are hereby incorporated by reference.

[0002]

[0002] This disclosure relates to semiconductor structures, and more particularly to three-dimensional dynamic random access memory (DRAM) transistors having thinned sources and drains for reducing the floating body effect.

Background Art

[0003]

[0003] The manufacture of dynamic random access memory (DRAM) cells involves forming transistors, capacitors, and contacts to lines for bit lines, word lines, and reference voltages. In DRAM manufacturing, there is a continuing goal of improving the memory capacity present on a single memory chip by reducing the individual cell size and increasing the memory cell density, particularly at densities greater than 256 megabits.

[0004]

[0004] As the dimensions of DRAM devices are scaled down, patterning of three-dimensional structures including trenches for storage nodes and access transistors is becoming increasingly important. However, since there is no body contact in the access transistor, for example, when the bit line voltage changes, holes accumulate and a "floating body effect" occurs in which the transient leakage current increases. This is also seen when a selected bit cell is detected, when the bit line voltage toggles, and / or when an unselected victim bit cell on the same bit line loses charge due to the transient current of the floating body effect. Such accumulation of charge loss can degrade the detection of victim bit cells or even cause inversion of bit data.

[0005]

[0005] One of the current methods for suppressing the floating body effect involves adding body contacts to the 3D DRAM structure. However, this method significantly increases the complexity of processing such as additional doping, wiring, spacing, and line contacts. This disclosure addresses these and other problems of the current technology. [Overview of the project]

[0006]

[0006] This summary is provided in a simplified manner to introduce the selection of concepts that will be further described below in modes for carrying out the invention. This summary is not intended to identify any important or essential features of the claimed subject matter, nor is it intended to be an aid in determining the scope of the claimed subject matter.

[0007]

[0007] In one embodiment, a method for forming a three-dimensional memory device may include forming a plurality of layers stacked in a first direction, wherein the plurality of layers include a gate layer formed on a first oxide layer and source / drain (S / D) layers between the series of gate oxide layers. The series of gate oxide layers may be formed on top of the gate layer, and the S / D layer may include a source and a drain located on opposite sides of the body. The method may further include forming a doped layer on top of the source.

[0008]

[0008] In another embodiment, a method for forming a three-dimensional dynamic random access memory device may include forming a plurality of layers stacked in a first direction, the plurality of layers including a source / drain (S / D) layer between a series of gate oxide layers, the series of gate oxide layers being formed on top of the gate layers, and the S / D layer including a source and drain located on opposite sides of the body. The method may further include etching the source and drain to form a thinned portion having a first thickness, the first thickness in the first direction being less than a second thickness of the body in the first direction. The method may further include forming doped layers on top of the source and on top of the drain.

[0009]

[0009] In yet another embodiment, the memory device may include a plurality of layers stacked in a first direction, the plurality of layers including a gate layer formed on a first oxide layer and a source / drain (S / D) layer between the series of gate oxide layers, the series of gate oxide layers being formed on the gate layer, and the S / D layer including a source and a drain located on opposite sides of the body, and the first thickness of each of the source and drain in the first direction is less than the second thickness of the body in the first direction. The memory device may further include doped layers formed on the source and on the drain.

[0010]

[0010] The accompanying drawings illustrate exemplary methods of the Disclosure, including practical applications of the principles of the Disclosure, as shown below. [Brief explanation of the drawing]

[0011] [Figure 1] This is a side view showing a device such as a three-dimensional DRAM device according to the embodiment of this disclosure. [Figure 2] This is a side view showing a device in a doping process according to an embodiment of the present disclosure. [Figure 3] This is a side view showing a device after doping of a doped layer according to an embodiment of the present disclosure. [Figure 4] This is a side view showing an alternative device after doping layer formation according to an embodiment of the present disclosure. [Figure 5] This is a side view showing a device after heat treatment according to an embodiment of the present disclosure. [Figure 6] This is a side view showing a device according to an embodiment of the present disclosure. [Figure 7] This is an exemplary flowchart according to an embodiment of the present disclosure. [Figure 8] This figure shows a system or processing apparatus according to an embodiment of the present disclosure. [Modes for carrying out the invention]

[0012]

[0019] The drawings are not necessarily to scale. The drawings are for illustrative purposes only and are not intended to depict any particular parameter of the disclosure. The drawings are intended to depict exemplary embodiments of the disclosure and should therefore not be considered limiting. In the drawings, similar numbering represents similar elements.

[0013]

[0020] Furthermore, certain elements in some drawings may be omitted or shown at a non-scale for illustrative clarity. Sectional views may take the form of "fragments" or "myopic" sectional views, omitting certain background lines that would otherwise be visible in a "true" sectional view, for illustrative clarity.

[0014]

[0021] The devices, 3D DRAM transistors, and methods relating to this disclosure will be described in more detail below with reference to the accompanying drawings illustrating various embodiments. These devices, 3D DRAM transistors, and methods can be embodied in many different forms and should not be considered as being limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure thorough and complete and to fully convey the scope of the methods to those skilled in the art.

[0015]

[0022] To address the shortcomings of the prior art described above, embodiments of this specification design the source and / or drain of the access device to reduce the current gain of the parasitic bipolar transistor in the 3D DRAM. By designing the band, the emitter bandgap of the source-body-drain npn parasitic bipolar transistor can be narrowed, thereby reducing the current gain. As a result, floating bodies can be reduced when the source-body junction is forward-biased. Advantageously, this procedure can be integrated into existing 3D DRAM process flows and therefore does not require body contacts. Thus, embodiments of this disclosure can avoid the need for precise contact doping of the body, additional metal lines for connecting body contacts, extra line contacts for wiring to power supplies, or spacers between the gate / source electrodes and metal wiring.

[0016]

[0023] In some methods, a three-dimensional memory stack can include a gate layer formed on a first oxide layer and source / drain (S / D) layers between a series of gate oxide layers, where the series of gate oxide layers are formed on top of the gate layer. The S / D layers may include a source (i.e., bit line contact) and a drain located on opposite sides of the body. During processing, the source and / or drain are thinned (e.g., etched) and then doped (e.g., with germanium) to change the band gap. In some embodiments, an N-type dopant (e.g., As and / or P) is also doped into the exposed Si of the source and / or drain. SiGe has a narrower band gap compared to Si, making it easier to integrate into Si DRAM flows. Further optimization is possible by adjusting the Ge concentration during doping.

[0017]

[0024] Thereafter, by epitaxially growing SiGe along the thinned Si of the source and drain, a doped layer can be formed and a series of junctions can be formed. In some embodiments, the SiGe is doped in situ during formation. Thereafter, dopant activation and junction penetration processes can be performed, in which the position of the junction can be adjusted by changing the processing temperature and time to control the dopant diffusion depth.

[0018]

[0025] FIG. 1 is a side view showing a transistor or a part of a device 100 such as a 3D DRAM device. As shown, the device 100 can include a plurality of layers stacked perpendicular to a first direction (e.g., the y direction), and the plurality of layers can represent a first stage 112 and a second stage 114 of one or more lateral access devices. The first stage 112 of the device 100 can include a first oxide layer 101 and a second oxide layer 102, and the second stage 114 can include a third oxide layer 103. A first gate layer 104 (e.g., a metal gate) may be formed on the first oxide layer 101, and a second gate layer 105 may be formed below the second oxide layer 102. A source / drain (S / D) layer 106 can be provided between a series of gate oxide layers 108A and 108B. One or more spacer layers 110 (e.g., nitride) may be formed between the first oxide layer 101 and the second oxide layer 102. More specifically, the spacer layer 110 may be formed on both sides of the S / D layer 106.

[0019]

[0026] Although not described in more detail herein, the second stage 114 can have the same or similar layer structure and processing techniques as the first stage 112. For example, the second stage 114 can also have a gate layer (e.g., a metal gate) and an S / D layer between a series of gate oxide layers. One or more spacer layers (e.g., nitride) may be formed between the oxide layers.

[0020]

[0027] In some embodiments, the S / D layer 106 can include a source 116 and a drain 118 on both sides of the body 120. In the illustrated embodiment, the S / D layer 106 can be silicon (Si) such as doped silicon, amorphous silicon, or polysilicon. The source 116 can correspond to a bit line contact, and the drain 118 can correspond to a SN contact. As shown, the source 116 and the drain 118 can be thinned (e.g., etched) to form a thinned portion 121 with a reduced thickness in the y direction. In some embodiments, the source 116 and the drain 118 are also partially recessed in the x direction, and gaps 122 can be formed between the source 116 and the spacer layer 110 and between the drain 118 and the spacer layer 110. In various embodiments, isotropic etching can be performed on the source 116 and the drain 118 to reduce the source / drain thickness relative to the thickness of the body 120. In this embodiment, the thickness of the source 116 and the thickness of the drain 118 can be the same. In other embodiments, the thickness of the body 120 can be the same as or similar to the thickness of the drain 118, and the thickness of the source 116 can be reduced.

[0021]

[0028] As shown in FIG. 2, a narrow bandgap dopant material 124 (e.g., germanium) can be implanted into the exposed surfaces 123 of the source 116 and the exposed surfaces 126 of the drain 118 for bandgap modification, for example, using a plasma immersion or plasma doping (PLAD) process. In some embodiments, the exposed Si of the source 116 and the drain 118 can also be doped with an N-type dopant (e.g., As and / or P) by PLAD.

[0022]

[0029] As shown in Figure 3, a doped layer 125 may then be formed on the source 116 and the drain 118. More specifically, SiGe can be epitaxially grown on the exposed surface 123 of the thinned portion 121 of the source 116 and on the exposed surface 126 of the drain 118. As illustrated, the doped layer 125 may be partially formed between the spacer layer 110 and the thinned portion 121 of the source 116 and the thinned portion 121 of the drain 118. It will be understood that the ratio of Ge to Si can be changed to adjust the band gap. In some embodiments, an N-type dopant may be insitu-doped into the doped layer 125 during formation. In other embodiments, the doped layer 125 is formed by chemical vapor deposition (CVD), plasma CVD, atomic layer deposition, physical vapor deposition (PVD), ion implantation, etc.

[0023]

[0030] Figure 4 shows a device 100A according to an alternative embodiment. Device 100A may be the same as or similar to device 100 described above in many aspects. Therefore, for brevity, only specific aspects of device 100A will be described below. Narrow bandgap dopant material (e.g., Ge) may be injected into the exposed surface 123A of source 116A and the exposed surface 126A of drain 118A to change the bandgap, for example, by a plasma immersion or plasma doping (PLAD) process. In some embodiments, N-type dopants (e.g., As and / or P) may also be doped into the exposed Si of source 116A and the exposed Si of drain 118A by PLAD. In this case, the Si body 120A may be extremely thin (e.g., 10 nm or less) so as to avoid thinning of source 116A and / or drain 118A. As illustrated, the doped layer 125A may be formed on the source 116A and the drain 118A, rather than being formed between the spacer layer 110A and the S / D layer 106A. Alternatively, the doped layer 125A may be partially formed along the sidewall of the spacer layer 110A. In some embodiments, the doped layer 125A may be epitaxially grown SiGe on the exposed surfaces of the source 116A and the drain 118A.

[0024]

[0031] Next, as shown in Figure 5, the device 100 (see Figure 3) may undergo a heat treatment 130, such as rapid thermal annealing, to activate the dopant in the dope layer 125 and allow it to penetrate the source 116 and drain 118. In some cases, small portions 132 of the Si pn junction may exist between the body 120 and the source 116, and between the body 120 and the drain 118, but the floating body effect is still improved. In the heat treatment 130, the source 116 and drain 118 may be exposed to temperatures between 950°C and 1050°C, but not limited to these. The location of the junction may be adjustable by controlling the dopant diffusion depth (for example, using the treatment temperature and time).

[0025]

[0032] Figure 6 shows one or more additional structures of device 100. Though not exhaustive, device 100 may further include a bit line 134 formed around the doped layer 125 of source 116, and a capacitor 136 formed around the doped layer 125 of drain 118. Thus, source 116 may be electrically connected to bit line 134, and drain 118 may be electrically connected to capacitor 136. Bit line 134 may include bit line metal deposited in one or more bit line openings. In various embodiments, the bit line metal may include one or more of WSi, WN, or W, and can be deposited by any suitable technique.

[0026]

[0033] Figure 7 shows a method 200 for forming a three-dimensional DRAM device according to an embodiment of the present disclosure. In block 201, the method 200 may include forming a plurality of layers, including S / D layers, between a series of gate oxide layers, the series of gate oxide layers being formed on top of the gate layers, and the S / D layers including source and drain located on opposite sides of the body. In some embodiments, the S / D layers are silicon.

[0027]

[0034] In block 202, method 200 may include etching the source and drain to a first thickness, where the first thickness in a first direction is less than a second thickness of the body in the first direction. Etching can form thinned portions of the source and drain. In some embodiments, isotropic etching may be performed in a suitable etching chamber, such as a plasma etching chamber. In some cases, for example, if the S / D layer is very thin (e.g., less than 10 nm), it is not necessary to reduce the thickness of the source. In some embodiments, the source and drain are symmetrical, and the thinned portions of the source and drain have the same or similar thicknesses. In some embodiments, only the source is thinned.

[0028]

[0035] In block 203, method 200 may include doping the exposed surfaces of the source and drain with a dopant (e.g., Ge) for band gap modification, for example, using a PLAD process. In some embodiments, an N-type dopant (e.g., As and / or P) may be additionally doped onto the exposed Si of the source and / or drain during and / or after Ge doping.

[0029]

[0036] In block 204, method 200 may include forming doped layers on the source and on the drain. In some embodiments, forming doped layers includes doping the thinned portions of the source and drain, and then epitaxially growing SiGe on the thinned portions of the source and on the thinned portions of the drain.

[0030]

[0037] In block 205, method 200 may further include heat-treating multiple layers to activate the dopants in the dope layers and allow them to penetrate into the source and drain. In some embodiments, the heat treatment may be a rapid heat process, such as rapid heat annealing.

[0031]

[0038] The above method can be performed using a tool such as an integrated tool or cluster tool 300, as shown in Figure 8. The tool 300 may include a suitable process chamber configured for one or more of epitaxial growth, dopant feeding, and plasma etching. Exemplary processing systems available for performing the methods of the present invention disclosed herein may include, but are not limited to, the ENDURA®, CENTURA®, CENTURA® PRIME® EPI, or PRODUCER® series processing systems, which are commercially available from Applied Materials, Inc. of Santa Clara, California. Other process chambers, including those from other manufacturers, may also be used appropriately in connection with the teachings provided herein.

[0032]

[0039] In some embodiments, the tool 300 facilitates the process of the method described herein by limiting or eliminating vacuum interruptions between processes. Reducing vacuum interruptions can limit or prevent contamination, and further improve throughput by shortening the time between processes and reducing or eliminating certain processes that would be required, for example, when the processes are executed sequentially in a single process chamber, such as pre-cleaning or other steps.

[0033]

[0040] The tool 300 may include a processing platform 301, a factory interface 304, and a system controller 302. The processing platform 301 may include a plurality of process chambers 314A, 314B, 314C, and 314D operably connected to the transfer chamber 303. The factory interface 304 is operably connected to the transfer chamber 303 by one or more load lock chambers, for example, 306A and 306B.

[0034]

[0041] In some embodiments, the factory interface 304 includes at least one docking station 307 and at least one factory interface robot 338 to facilitate the transfer of one or more semiconductor substrates 321 (e.g., wafers). The docking station 307 is configured to receive one or more forward-opening unified pods (FOUPs) 305A, 305B, 305C, and 305D. The factory interface robot 338 is configured to transfer the substrates 321 from the factory interface 304 to the processing platform 301 through load lock chambers 306A and 306B. Each load lock chamber 306A and 306B has a first port connected to the factory interface 304 and a second port connected to the transfer chamber 303. The load lock chambers 306A and 306B are connected to a pressure control system (not shown) that pumps down and evacuates the load lock chambers 306A and 306B to facilitate the passage of the substrate 321 between the vacuum environment of the transfer chamber 303 and the substantial ambient (e.g., atmospheric) environment of the factory interface 304. The transfer chamber 303 may have a vacuum robot 342 positioned within the transfer chamber 303, which can transfer the substrate 321 between the load lock chambers 306A and 306B and the process chambers 314A, 314B, 314C, and 314D.

[0035]

[0042] In some embodiments, process chambers 314A, 314B, 314C, and 314D are connected to a transfer chamber 303. Process chambers 314A, 314B, 314C, and 314D include at least an epitaxial deposition / forming chamber, a plasma doping chamber, and an etching chamber. In some embodiments, at least one deposition chamber is configured to deposit a plurality of layers stacked in a first direction, the plurality of layers including a gate layer formed on a first oxide layer and a source / drain (S / D) layer between the series of gate oxide layers. The series of gate oxide layers may be formed on top of the gate layer. The S / D layer may include a source and a drain located on opposite sides of the body.

[0036]

[0043] In some embodiments, at least one of the process chambers is an etching chamber configured to etch the source and / or drain to a first thickness, where the first thickness in a first direction is less than a second thickness of the body in the first direction. In some embodiments, at least one of the chambers is a plasma doping chamber configured to dope the exposed surfaces of the source and / or drain. In some embodiments, at least one of the process chambers is an epitaxial deposition / forming chamber configured to epitaxially grow a layer on top of the source and / or drain.

[0037]

[0044] In some embodiments, one or more optional service chambers (shown as 316A and 316B) may be connected to the transfer chamber 303. Service chambers 316A and 316B may be configured to perform other substrate processes such as degassing, bonding, chemical mechanical polishing (CMP), wafer splitting, etching, plasma dicing, orientation, substrate measurement, and cooling.

[0038]

[0045] The system controller 302 controls the operation of the tool 300 by direct control of the process chambers 314A, 314B, 314C, and 314D, or by controlling the computer (or controller) associated with the process chambers 314A, 314B, 314C, and 314D and the tool 300. During the process, the system controller 302 enables data collection and feedback from each chamber and system to optimize the performance of the tool 300. The system controller 302 generally includes a central processing unit (CPU) 330, memory 334, and support circuits 332. The CPU 330 may be any form of general-purpose computer processor available for use in an industrial environment. The support circuits 332 are conventionally connected to the CPU 330 and may include a cache, clock circuit, input / output subsystem, power supply, etc. Software routines such as the processing methods described above are stored in memory 334 (e.g., a non-transient computer-readable storage medium) and, when executed by the CPU 330, can be converted into a purpose-specific computer (system controller 302). The software routines may also be stored and / or executed by a second controller (not shown) located remotely from the tool 300.

[0039]

[0046] For convenience and clarity, please understand that terms such as "top," "bottom," "upper," "downward," "vertical," "horizontal," "sideways," and "vertical" describe the constituent elements shown in the diagram and the relative arrangement and orientation of their components. Furthermore, the terminology includes the specifically mentioned words, their derivatives, and words with similar meanings.

[0040]

[0047] As used herein, any element or action referred to in the singular form and preceded by the word "a" or "an" shall be understood to include multiple elements or actions unless an exclusion is expressly stated. Furthermore, references to “one embodiment” in this disclosure are not limiting. Additional embodiments may also incorporate the features mentioned.

[0041]

[0048] Furthermore, the terms “substantial” or “effectively,” and the terms “approximately” or “about,” can be used interchangeably in several embodiments and can be described using any relative measure acceptable to those skilled in the art. For example, these terms may serve as a comparison to a reference parameter to indicate a deviation that can provide the intended function. Although not limiting, the deviation from the reference parameter may be a quantity such as less than 1%, less than 3%, less than 5%, less than 10%, less than 15%, less than 20%, etc.

[0042]

[0049] Furthermore, those skilled in the art will understand that when it is stated that an element such as a layer, region, or substrate is formed, deposited, or placed "on top of" or "on the surface of" another element, that element may be directly on top of the other element, or there may be an intervening element. In contrast, when it is stated that an element is "directly on top of" or "directly on the surface of" another element, there is no intervening element.

[0043]

[0050] While this specification has described specific embodiments of the Disclosure, the Disclosure is not limited thereto and is as broad as possible in the Art, and this specification can be interpreted in that manner. Therefore, the above description should not be construed as limiting. Rather, the above description is merely an example of a specific embodiment. Those skilled in the art will envision other modifications within the claims and spirit appended to this specification.

Claims

1. A method for forming a three-dimensional memory device, To form a plurality of layers stacked in a first direction, wherein the plurality of layers are A gate layer formed on the first oxide layer, A source / drain (S / D) layer between a series of gate oxide layers, wherein the series of gate oxide layers are formed on the gate layers, and the source / drain (S / D) layer includes a source and a drain located on opposite sides of the body. Forming a plurality of layers stacked in a first direction, including, Forming a doped layer on top of the aforementioned source A method that includes this.

2. The method according to claim 1, further comprising forming the source to a first thickness in the first direction, wherein the first thickness is less than a second thickness of the body in the first direction.

3. The method according to claim 1, wherein forming the doped layer on the source comprises epitaxially growing the doped layer along the source.

4. The method according to claim 3, further comprising doping the source before epitaxially growing the doped layer along the source.

5. The method according to claim 4, wherein doping the source includes supplying an N-type dopant to the exposed surface of the source.

6. The method according to claim 1, further comprising forming a spacer layer between the first oxide layer and the second oxide layer.

7. The method according to claim 1, further comprising heat-treating the plurality of layers in order to activate the dopants in the dope layer and allow them to penetrate into the source.

8. The method according to claim 7, wherein the heat treatment of the plurality of layers includes performing rapid thermal annealing.

9. A method for forming a three-dimensional dynamic random access memory device, To form a plurality of layers stacked in a first direction, wherein the plurality of layers include source / drain (S / D) layers between a series of gate oxide layers, the series of gate oxide layers are formed on top of the gate layers, and the source / drain (S / D) layers include a source and a drain located on opposite sides of the body, thereby forming a plurality of layers stacked in a first direction. Etching the source and the drain to form a thinned portion, each having a first thickness, wherein the first thickness in the first direction is less than the second thickness of the body in the first direction, and Forming a dope layer on the thinned portions of the source and the drain. A method that includes this.

10. The method according to claim 9, wherein forming the dope layer on the thinned portions of the source and the drain comprises epitaxially growing a silicon germanium layer along the exposed surface of the source and along the exposed surface of the drain.

11. The method according to claim 9, further comprising doping the thinned portions of the source and the drain with a narrow bandgap material before forming the doped layer.

12. The method according to claim 9, further comprising doping the source and the drain by injecting an N-type dopant into the exposed surface of the source and the exposed surface of the drain after the source and the drain have been etched.

13. The method according to claim 9, further comprising forming a spacer layer between the first oxide layer and the second oxide layer.

14. The method according to claim 9, further comprising heat-treating the plurality of layers in order to activate the dopants in the dope layers and allow them to penetrate into the source and the drain.

15. A memory device, A plurality of layers stacked in a first direction, A gate layer formed on the first oxide layer, A source / drain (S / D) layer between a series of gate oxide layers, wherein the series of gate oxide layers are formed on the gate layers, and the source / drain (S / D) layer includes a source and a drain located on opposite sides of the body, and the first thickness of each of the source and the drain in the first direction is less than the second thickness of the body in the first direction. A doped layer formed on the source and the drain Multiple layers, including A memory device comprising the above features.

16. The memory device according to claim 15, wherein the plurality of layers further include a spacer layer extending between the first oxide layer and the second oxide layer.

17. The memory device according to claim 15, wherein the doped layer is an epitaxially grown silicon-germanium layer and the S / D layer is silicon.

18. The memory device according to claim 15, wherein the source and the drain are doped with a narrow bandgap dopant material.

19. The memory device according to claim 15, further comprising a bit line electrically connected to the doped layer of the source.

20. The memory device according to claim 15, further comprising a capacitor electrically connected to the drain.

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