Source / drain contact replacement method in complementary field-effect transistor (CFET) devices

Abstract

The semiconductor structure forming the complementary field-effect transistor (CFET) includes a metal gate, a bottom field-effect transistor (FET) module comprising a plurality of channel layers extending through the metal gate in a first direction, and bottom source / drain (S / D) contacts electrically connected to the plurality of channel layers via a bottom epitaxial (epi) S / D and a bottom interface, and an upper FET module stacked on the bottom FET module in a second direction orthogonal to the first direction, comprising a plurality of channel layers extending through the metal gate in the first direction, and upper source / drain (S / D) contacts electrically connected to the plurality of channel layers via an upper epitaxial (epi) S / D and an upper interface, wherein the bottom S / D contact and the upper S / D contact each comprise cobalt (Co) or tungsten (W).

Description

[Technical Field]

[0001] Cross-reference with related applications

[0001] This application claims priority to U.S. Provisional Application No. 63 / 456,435 filed on 31 March 2023, the contents of which are incorporated herein by reference in their entirety.

[0002]

[0002] The embodiments described herein relate in general to semiconductor device manufacturing, and more specifically to methods for forming complementary field-effect transistor (CFET) devices. [Background technology]

[0003]

[0003] To continue scaling beyond the physical limits of planar metal oxide semiconductor field-effect transistors (MOSFETs), three-dimensional FinFETs, multilayer nanosheet gate all-around FETs (GAA FETs), and complementary FETs (CFETs) have been proposed. In CFET architectures, n-devices and p-devices are stacked vertically on top of each other, eliminating the np spacing from the standard cell height. In currently proposed process flows, the contact trenches of the bottom device are filled with silicide and metal contact plugs before the top device is formed. As a result, silicides and contact plugs formed from currently known materials such as titanium silicide, cobalt, or tungsten may not withstand the high-temperature process for forming the top device and may degrade during the high-temperature process. Using materials that can withstand such high-temperature processes may result in higher resistance, leading to increased complexity in the deposition and etching processes.

[0004]

[0004] Therefore, an improved method is needed for fabricating silicide and metal contact plugs in the bottom device of the CFET architecture. [Overview of the project]

[0005]

[0005] Embodiments of the present disclosure provide a semiconductor structure for forming a complementary field-effect transistor (CFET). The semiconductor structure includes a metal gate, a bottom field-effect transistor (FET) module, a bottom FET module including a plurality of channel layers extending through the metal gate in a first direction, and bottom source / drain (S / D) contacts electrically connected to the plurality of channel layers via a bottom epitaxial (epi) S / D and a bottom interface, and an upper FET module stacked on the bottom FET module in a second direction orthogonal to the first direction, including a plurality of channel layers extending through the metal gate in a first direction, and upper source / drain (S / D) contacts electrically connected to the plurality of channel layers via an upper epitaxial (epi) S / D and an upper interface, wherein the bottom S / D contact and the upper S / D contact each include cobalt (Co) or tungsten (W).

[0006]

[0006] Embodiments of the present disclosure provide a method for forming a complementary field-effect transistor (CFET). The method comprises: performing an upper cover spacer formation process to deposit an upper cover spacer covering the exposed surface of an upper nanosheet and a spacer around the upper nanosheet along a first plane perpendicular to a first direction, wherein the upper nanosheet is laminated on a bottom nanosheet in a second direction perpendicular to the first direction, and the upper nanosheet and bottom nanosheet each include a plurality of channel layers extending in the first direction through a dummy gate; performing a bottom epitaxial (epi)source / drain (S / D) formation process to form a bottom epi S / D on the exposed surface of the bottom nanosheet along the first plane; and depositing a bottom interlayer insulator (ILD) on the spacer surface around the bottom epi S / D, patterning the bottom ILD, forming a dummy contact, and removing the upper cover spacer by performing a bottom contact process. The process includes performing a turning and sacrificial filling process; performing an upper epitaxial S / D formation process to form upper epitaxial S / Ds on the exposed surfaces of the upper nanosheets along a first plane and upper intraluminal S / Ds around the upper epitaxial S / Ds; performing a metal gate replacement (RMG) process to replace dummy gates with metal gates; performing an upper contact patterning and metal filling process to pattern the upper ILDs and form upper S / D contacts; performing a dummy contact stripping process following the bottom epitaxial S / D formation process, the upper epitaxial S / D formation process, and the RMG process to selectively etch the dummy contacts; and performing a replacement bottom S / D contact formation process to form bottom S / D contacts in the portions etched by the dummy contact stripping process.

[0007]

[0007] Embodiments of the present disclosure provide a semiconductor structure for forming a complementary field-effect transistor (CFET). The semiconductor structure includes a metal gate and a bottom field-effect transistor (FET) module, which includes a plurality of channel layers extending through the metal gate in a first direction and dummy contacts connected to the plurality of channel layers via a bottom epitaxial (epi) S / D and a bottom interface, and an upper FET module stacked on the bottom FET module in a second direction orthogonal to the first direction, which includes a plurality of channel layers extending through the metal gate in a first direction and upper source / drain (S / D) contacts electrically connected to the plurality of channel layers via an upper epitaxial (epi) S / D and an upper interface, wherein the dummy contacts include silicon oxide (SiO2), silicon nitride (Si3N4), silicon carbide (SiC), or a combination thereof, and the upper S / D contacts include cobalt (Co) or tungsten (W).

[0008]

[0008] In order to understand the features of the present disclosure described above in detail, the present disclosure summarized above will be described more specifically with reference to embodiments illustrated in part in the accompanying drawings. However, it should be noted that the accompanying drawings are merely illustrative embodiments and should not be considered to limit the scope of the present disclosure, and that the present disclosure may also permit other equally valid embodiments. [Brief explanation of the drawing]

[0009] [Figure 1] This is a schematic top view of a multi-chamber processing system according to one or more embodiments of the present disclosure. [Figure 2] A is an isometric view of a portion of a semiconductor structure that can form a complementary field-effect transistor (CFET) according to one or more embodiments of the present disclosure, and B is a view of the semiconductor structure of Figure 2A cut along the ZX plane including the line 2B-2B shown in Figure 2A. [Figure 3A] This is a process flow diagram showing a method for forming a cell transistor in a semiconductor structure according to one embodiment. [Figure 3B] It is a process flow diagram showing a method of forming a cell transistor in a semiconductor structure according to an embodiment. [Figure 4A] It is an isometric view of a part of a semiconductor structure corresponding to various states of the method of FIGS. 3A and 3B. [Figure 4B] It is an isometric view of a part of a semiconductor structure corresponding to various states of the method of FIGS. 3A and 3B. [Figure 4C] It is an isometric view of a part of a semiconductor structure corresponding to various states of the method of FIGS. 3A and 3B. [Figure 4D] It is an isometric view of a part of a semiconductor structure corresponding to various states of the method of FIGS. 3A and 3B. [Figure 4E] It is an isometric view of a part of a semiconductor structure corresponding to various states of the method of FIGS. 3A and 3B. [Figure 4F] It is an isometric view of a part of a semiconductor structure corresponding to various states of the method of FIGS. 3A and 3B. [Figure 4G] It is an isometric view of a part of a semiconductor structure corresponding to various states of the method of FIGS. 3A and 3B. [Figure 4H] It is an isometric view of a part of a semiconductor structure corresponding to various states of the method of FIGS. 3A and 3B. [Figure 4I] It is an isometric view of a part of a semiconductor structure corresponding to various states of the method of FIGS. 3A and 3B. [Figure 4J] It is an isometric view of a part of a semiconductor structure corresponding to various states of the method of FIGS. 3A and 3B. [Figure 4J-1] It is an isometric view of a part of a semiconductor structure corresponding to various states of the method of FIGS. 3A and 3B. [Figure 4K] It is an isometric view of a part of a semiconductor structure corresponding to various states of the method of FIGS. 3A and 3B. [Figure 4L] It is an isometric view of a part of a semiconductor structure corresponding to various states of the method of FIGS. 3A and 3B. [Figure 4M] It is an isometric view of a part of a semiconductor structure corresponding to various states of the method of FIGS. 3A and 3B. [Figure 4N]Figures 3A and 3B are isometric views of some of the semiconductor structures corresponding to various states of the method shown in Figures 3A and 3B. [Figure 4O] Figures 3A and 3B are isometric views of some of the semiconductor structures corresponding to various states of the method shown in Figures 3A and 3B. [Modes for carrying out the invention]

[0010]

[0013] For ease of understanding, the same reference numerals are used to indicate identical elements common to the drawings whenever possible. Elements and features of one embodiment are considered to be usefully incorporated into other embodiments without further detail. In the figures and the following description, a Cartesian coordinate system including the X, Y, and Z axes is used. Directions indicated by arrows in the drawings are assumed to be positive for convenience. Elements disclosed in some embodiments are expected to be usefully used in other embodiments without specific description.

[0011]

[0014] The embodiments described herein provide a method for complementary FET (CFET) devices. In the method described herein, dummy contacts are deposited in place of the source / drain (S / D) contacts of the bottom device of the CFET before the top device of the CFET is formed. The dummy contacts are replaced with S / D contacts after the formation of the top device, which includes a high-temperature process. This replacement with S / D contacts makes it possible to use materials best optimized for S / D contacts for the bottom device without any thermal balance constraints.

[0012]

[0015] Figure 1 is a schematic top view of a multi-chamber processing system 100 according to one or more embodiments of the present disclosure. The processing system 100 generally includes a factory interface 102, load lock chambers 104, 106, transfer chambers 108, 110 having transfer robots 112, 114 respectively, holding chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130. As detailed herein, substrates within the processing system 100 can be processed in various chambers and transferred between various chambers without exposing the substrates to the ambient environment outside the processing system 100 (e.g., atmospheric ambient environment that may be present in a manufacturing facility). For example, substrates can be processed in various chambers maintained at low pressure (e.g., about 300 Torr or less) or in a vacuum environment without breaking the low-pressure or vacuum environment between the various processes performed on the substrates within the processing system 100 and transferred between various chambers. Thus, the processing system 100 can provide a unified solution for processing a subset of substrates.

[0013]

[0016] Examples of processing systems that may be suitably modified in accordance with the teachings provided herein include the Endura®, Producer®, or Centura® integrated processing systems, or other suitable processing systems, commercially available from Applied Materials, Inc., Santa Clara, California. It is assumed that other processing systems (including those from other manufacturers) may also be adapted to benefit from the embodiments described herein.

[0014]

[0017] In the embodiment illustrated in Figure 1, the factory interface 102 includes a docking station 132 and a factory interface robot 134 for facilitating substrate transfer. The docking station 132 is adapted to receive one or more forward-opening unified pods (FOUPs) 136. In some embodiments, each factory interface robot 134 generally includes a blade 138 located at one end of the factory interface robot 134, adapted to transfer substrates from the factory interface 102 to the load lock chambers 104, 106.

[0015]

[0018] The load lock chambers 104 and 106 each have ports 140 and 142 connected to the factory interface 102, and ports 144 and 146 connected to the transfer chamber 108. The transfer chamber 108 further has ports 148 and 150 connected to the holding chambers 116 and 118, and ports 152 and 154 connected to the processing chambers 120 and 122. Similarly, the transfer chamber 110 has ports 156 and 158 connected to the holding chambers 116 and 118, and ports 160, 162, 164, and 166 connected to the processing chambers 124, 126, 128, and 130. Ports 144, 146, 148, 150, 152, 154, 156, 158, 160, 162, 164, and 166 may be slit valve openings having slit valves, for example, for transfer robots 112 and 114 to pass substrates through them, and for providing a seal between each chamber to prevent gas from passing between each chamber. Normally, one of the ports is open to transfer substrates through it; otherwise, the port is closed.

[0016]

[0019] The load lock chambers 104, 106, transfer chambers 108, 110, holding chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130 may be fluidically connected to a gas and pressure control system (not shown). The gas and pressure control system may include one or more gas pumps (e.g., turbopumps, cryopumps, roughing pumps), gas sources, various valves, and conduits fluidly connected to the various chambers. During operation, the factory interface robot 134 transfers the substrate from the FOUP 136 through port 140 or 142 to the load lock chamber 104 or 106. The gas and pressure control system then pumps down the load lock chamber 104 or 106. The gas and pressure control system further maintains the transfer chambers 108, 110 and the holding chambers 116, 118 in an internal low-pressure or vacuum environment (which may include an inert gas). Therefore, by pumping down the load lock chamber 104 or 106, it becomes easier to pass the substrate between, for example, the atmospheric environment of the factory interface 102 and the low-pressure or vacuum environment of the transfer chamber 108.

[0017]

[0020] For substrates in the pumped-down load lock chamber 104 or 106, the transfer robot 112 transfers the substrates from the load lock chamber 104 or 106 to the transfer chamber 108 through port 144 or 146. The transfer robot 112 can then transfer the substrates to and / or between the processing chambers 120, 122 through their respective ports 152, 154 for processing, and to and / or between the holding chambers 116, 118 through their respective ports 148, 150 to hold and await further transfer. Similarly, the transfer robot 114 can access the substrates in the holding chamber 116 or 118 through port 156 or 158, and can transfer the substrates to and / or between any of the processing chambers 124, 126, 128, 130 for processing through their respective ports 160, 162, 164, 166, and to any of the holding chambers 116, 118, and / or between them through their respective ports 156, 158, to hold and await further transfer. Transfer and holding of substrates within and between the various chambers can be performed in a low-pressure or vacuum environment provided by a gas and pressure control system.

[0018]

[0021] Processing chambers 120, 122, 124, 126, 128, and 130 may be any suitable chamber for processing the substrate. In some embodiments, processing chamber 120 may be capable of performing an etching process, processing chamber 122 may be capable of performing a cleaning process, processing chamber 124 may be capable of performing a selective removal process, processing chamber 126 may be capable of performing a chemical vapor deposition (CVD) process, and processing chambers 128 and 130 may be capable of performing their respective epitaxial growth processes. Processing chamber 120 may be a Selectra® Etch chamber available from Applied Materials, Inc., Santa Clara, California. Processing chamber 122 may be a SiCoNi® Preclean chamber available from Applied Materials, Inc., Santa Clara, California. Processing chamber 126 may be a W×Z® chamber available from Applied Materials, Inc., Santa Clara, California. The processing chamber 128 or 130 may be a Centura® Epi chamber, available from Applied Materials, Inc. in Santa Clara, California.

[0019]

[0022] The system controller 168 is connected to the processing system 100 to control the processing system 100 or its components. For example, the system controller 168 can control the operation of the processing system 100 by using direct control of the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, and 130 of the processing system 100, or by controlling controllers associated with the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, and 130. In the process, the system controller 168 enables data collection and feedback from each chamber to adjust the performance of the processing system 100.

[0020]

[0023] The system controller 168 generally includes a central processing unit (CPU) 170, memory 172, and support circuitry 174. The CPU 170 may be one of any form of general-purpose processor available for use in an industrial environment. Memory 172, or non-transient computer-readable medium, is accessible by the CPU 170 and may be one or more of the following: random access memory (RAM), read-only memory (ROM), floppy disk, hard disk, or any other form of local or remote digital storage. Support circuitry 174 is connected to the CPU 170 and may include a cache, clock circuitry, input / output subsystems, power supply, etc. Various methods disclosed herein are generally carried out under the control of the CPU 170 by the CPU 170 executing computer instruction code stored in memory 172 (or memory of a particular processing chamber), for example, as software routines. Once the computer instruction code is executed by the CPU 170, the CPU 170 controls the chamber to execute the process according to various methods.

[0021]

[0024] Other processing systems may have different configurations. For example, more or fewer processing chambers may be connected to the transfer device. In the illustrated example, the transfer device includes transfer chambers 108, 110 and holding chambers 116, 118. In other embodiments, the transfer device in the processing system may consist of more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chambers).

[0022]

[0025] Figure 2A is an isometric view of a portion of a semiconductor structure 200 that can form a complementary field-effect transistor (CFET) according to one or more embodiments of the present disclosure. Figure 2B is a view of the semiconductor structure of Figure 2A cut along the ZX plane including the line 2B-2B shown in Figure 2A. The semiconductor structure 200 is a bottom field-effect transistor (FET) module TR B And, the bottom FET module TR B The upper FET module TR is stacked in the Z direction on top. Tincluding a bottom FET module TR B and a top FET module TR T each include a channel layer 202 extending in the Y direction through a metal gate 204. The channel layer 202 may be encapsulated by a liner 206. The surface of the metal gate 204 along the ZX plane is covered by a spacer 208. The channel layer 202 of the bottom FET module TR B is electrically isolated from the channel layer 202 of the top FET module TR T by a middle dielectric isolation (MDI) 210 and is electrically connected to a bottom S / D contact 212 through a bottom epitaxial (epi) S / D 214 and a bottom interface 216 embedded in a bottom interlayer dielectric (ILD) 218. In some embodiments, the bottom FET module TR B is p-type, the top FET module TR T is n-type, the bottom epi S / D 214 is p-type doped, and the top epi S / D 222 is n-type doped. In some embodiments, the bottom FET module TR B is n-type, the top FET module TR T is p-type, the bottom epi S / D 214 is n-type doped, and the top epi S / D 222 is p-type doped. The channel layer 202 of the top FET module TR T is electrically connected to a top S / D contact 220 through a top epi S / D 222 and a top interface 224 embedded in a top ILD 226. The bottom S / D contact 212, the top S / D contact 220, and the metal gate 204 are connected to a metal layer 228 formed in dielectric layers 230, 232, and 234 through contact plugs 236.

[0023]

[0026] The channel layer 202 may be formed of silicon (Si), germanium (Ge), silicon germanium (SiGe), or indium gallium zinc oxide (IGZO). The metal gate 204, bottom S / D contact 212, top S / D contact 220, metal layer 228, and contact plug 236 may be formed of cobalt (Co), tungsten (W), ruthenium (Ru), copper (Cu), molybdenum (Mo), titanium (Ti), nickel (Ni), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), platinum (Pt), conductive oxides or nitrides thereof, or any combination thereof. In the embodiments described herein, the bottom S / D contact 212 is formed by an S / D contact replacement method in which a dummy contact formed of a material that can withstand high-temperature processes (such as epitaxial deposition processes and metal gate replacement processes) is replaced with metal after the high-temperature process, as will be described in more detail below. Therefore, the bottom S / D contact 212 may be made of the above metal material which may not be able to withstand the above high-temperature process. The spacers 208 and MDI 210 are made of silicon oxycarbide (SiO2). x C yThe liner 206 may be formed from a dielectric material such as titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum carbide (TiAlC), or tungsten (W). The bottom epi S / D 214 and top epi S / D 222 may be formed from epitaxially grown silicon (Si) or silicon germanium (SiGe). The bottom interface 216 and top interface 224 may be formed from metal silicides such as titanium silicide (TiSi2), molybdenum silicide (MoSi2), cobalt silicide (CoSi2), nickel silicide (Ni2Si), tantalum silicide (TaSi2), or any combination thereof. The dielectric layers 230, 232, and 234 may be formed of silicon oxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), or any combination thereof doped with carbon, such as silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), or silicon carbide nitride (SiCN). The bottom ILD 218 and the top ILD 226 may be formed of silicon oxide (SiO2), silicon oxynitride (SiON), aluminum oxide (Al2O3), or any combination thereof.

[0024]

[0027] Figures 3A and 3B are process flow diagrams showing a method 300 for forming a semiconductor structure 400, which may be a semiconductor structure 200 forming part of a complementary field-effect transistor (CFET) according to one or more embodiments of the present disclosure. Figures 4A, 4B, 4C, 4D, 4E, 4F, 4G, 4H, 4I, 4J, 4J', 4K, 4L, 4M, 4N, and 4O are isometric views of parts of the semiconductor structure 400 corresponding to various states of the method 300. Figures 4A, 4B, 4C, 4D, 4E, 4F, 4G, 4H, 4I, 4J, 4J', 4K, 4L, 4M, 4N, and 4O show only partial schematic diagrams of the semiconductor structure 400, and it should be understood that the semiconductor structure 400 may include any number of transistor sections and additional materials having embodiments as illustrated in the figures. Furthermore, while the methods illustrated in Figures 3A and 3B will be described sequentially, please note that other process sequences, including one or more steps that are omitted and / or added, and / or rearranged in a different preferred order, also fall within the scope of the embodiments of the present disclosure provided herein.

[0025]

[0028] Method 300 begins in block 302, where a double superlattice deposition process is performed, as shown in Figure 4A, in which a bottom superlattice 402 is deposited on a substrate 404, an interstitial sacrificial layer 406 is deposited on the bottom superlattice 402, and an upper superlattice 408 is deposited on the interstitial sacrificial layer 406. The bottom superlattice 402 and the upper superlattice 408 each contain alternating channel layers 202 and sacrificial layers 410 stacked in the Z direction. The channel layers 202 may be formed of a first material. The sacrificial layer 410 may be formed of a second material. The etching selectivity of the second material (i.e., the ratio of the etching rate of the second material to the etching rate of the first material) is about 10:1 to 500:1. Examples of the first material include pure silicon (Si), germanium (Ge), and silicon germanium (SiGe). An example of a second material is silicon germanium (SiGe) having a germanium (Ge) concentration of about 10% to about 30%. The interstitial sacrificial layer 406 may be formed of a material having etching selectivity from the first and second materials, for example, silicon germanium (SiGe) having a high germanium (Ge) concentration of about 35% to about 60%. The bottom superlattice 402 and the upper superlattice 408 may each contain about 2 to about 10 pairs of channel layers 202 and sacrificial layers 410. Each channel layer 202 has a thickness of about 5 nm to about 40 nm. Each sacrificial layer 410 has a thickness of about 5 nm to about 40 nm. The interstitial sacrificial layer 406 may have a thickness of about 20 nm to about 100 nm.

[0026]

[0029] As used herein, the term “substrate” refers to a layer of material that forms the basis for subsequent processing steps and includes a surface to be cleaned. The substrate 404 may be a silicon-based material, or any suitable insulating or conductive material as needed. The substrate 404 may be crystalline silicon (e.g., Si <100> or Si <111> ), may include materials such as silicon oxide, strained silicon, silicon germanium, doped or undoped polycrystalline silicon, doped or undoped silicon wafers and patterned or unpatterned wafers, silicon-on-insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, or sapphire.

[0027]

[0030] The double superlattice deposition process in block 302 may include any suitable deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or epitaxial deposition, performed in a processing chamber such as processing chambers 126, 128, or 130 shown in Figure 1.

[0028]

[0031] In block 304, as shown in Figure 4B, a nanosheet patterning process is performed to form a nanosheet 412 and a shallow trench isolation (STI) 414. The nanosheet patterning process includes etching the upper superlattice 408, the interstitial sacrificial layer 406, and the bottom superlattice 402 onto the substrate 404. The nanosheet 412, having a bottom nanosheet 416 etched from the bottom superlattice 402 and an upper nanosheet 418 etched from the upper superlattice 408, has a width in the X direction of about 5 nm to about 60 nm and an aspect ratio of about 1:10 to about 1:80. The etched portion of the substrate 404 is filled with a dielectric material such as silicon dioxide (SiO2) up to the top surface of the remaining substrate 404 to form a shallow trench isolation (STI) 414.

[0029]

[0032] The nanosheet patterning process in block 304 may include any suitable lithography and etching processes, such as photolithography, performed in a processing chamber such as processing chamber 120 shown in Figure 1, as well as any suitable deposition processes, such as chemical vapor deposition (CVD) and physical vapor deposition (PVD), performed in a processing chamber such as processing chambers 126, 128, or 130 shown in Figure 1.

[0030]

[0033] In block 306, as shown in Figure 4C, a gate and spacer formation process is performed in which a dummy gate 420 is formed around the nanosheet 412, and spacers 208 are formed on the surface of the dummy gate 420 along the ZX plane. A gate cap layer 422 may be formed on the dummy gate 420 between the spacers 208. The dummy gate 420 may be made of polysilicon. The spacers 208 are made of silicon oxycarbide (SiO2). x C y The gate cap layer 422 may be formed of a dielectric material such as silicon nitride (Si3N4).

[0031]

[0034] The gate and spacer formation process in block 306 may include any suitable deposition process performed in a processing chamber such as processing chambers 126, 128, or 130 shown in Figure 1, including chemical vapor deposition (CVD), physical vapor deposition (PVD), and epitaxial deposition processes.

[0032]

[0035] In block 308, as shown in Figure 4D, a middle-dielectric isolation (MDI) formation process is performed in which the superlattice sacrificial layer 406 within the nanosheet 412 is selectively etched, and a dielectric material is filled into the etched portion to form an MDI 210. The MDI 210 may be formed from the same or similar dielectric material as the spacer 208.

[0033]

[0036] The MDI formation process in block 308 may include any suitable etching process performed in a processing chamber such as processing chamber 120 shown in Figure 1, and any suitable deposition process such as chemical vapor deposition (CVD) or physical vapor deposition (PVD) performed in a processing chamber such as processing chambers 126, 128, or 130 shown in Figure 1.

[0034]

[0037] In block 310, as shown in Figure 4E, an internal spacer formation process is performed in which the sacrificial layer 410 in the bottom nanosheet 416 and the upper nanosheet 418 is selectively etched, and a dielectric material is filled into the etched portion to form an internal spacer 424. The internal spacer 424 may be formed of the same or similar dielectric material as the spacer 208, which has a composition of silicon (Si), oxygen (O), carbon (C), nitrogen (N), and boron (B).

[0035]

[0038] The internal spacer formation process in block 310 may include any suitable etching process performed in a processing chamber such as processing chamber 120 shown in Figure 1, and any suitable deposition process such as chemical vapor deposition (CVD) or physical vapor deposition (PVD) performed in a processing chamber such as processing chambers 126, 128, or 130 shown in Figure 1.

[0036]

[0039] In block 312, as shown in Figure 4F, an upper cover spacer formation process is performed to deposit an upper cover spacer 426 on top of the semiconductor structure 400. The upper cover spacer 426 is deposited along the ZX plane on the exposed surfaces of the upper nanosheet 418 and the spacer 208 around the upper nanosheet 418, so as to cover the exposed surfaces of the upper nanosheet 418. The bottom nanosheet 416 and the spacer 208 around the bottom nanosheet 416 remain exposed along the ZX plane. The upper cover spacer 426 may be formed of the same or similar dielectric material as the spacer 208.

[0037]

[0040] The upper cover spacer formation process in block 312 may include any suitable deposition process, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD), performed in a processing chamber such as processing chambers 126, 128, or 130 shown in Figure 1.

[0038]

[0041] In block 314, as shown in Figure 4G, a bottom epitaxial (epi)source / drain (S / D) formation process is performed to form a bottom epitaxial S / D214. The bottom epitaxial S / D214 is epitaxially grown on the exposed surface of the bottom nanosheet 416 along the ZX plane. The bottom epitaxial S / D214 bonds between the channel layer 202 within the bottom nanosheet 416 and the S / D contact formed at the bottom of the semiconductor structure 400, minimizing parasitic resistance. The bottom epitaxial S / D214 may be formed of silicon (Si) or silicon germanium (SiGe).

[0039]

[0042] The bottom epitaxial S / D214 is approximately 10 depending on the desired conductivity characteristics of the bottom epitaxial S / D214. 20 cm -3 From 5x10 21 cm -3 The bottom epitaxial S / D214 may be doped with a p-type dopant such as boron (B) or gallium (Ga) at a concentration of 10. In some embodiments, the bottom epitaxial S / D214 is doped with a concentration of about 10 depending on the desired conductivity characteristics of the bottom epitaxial S / D214. 20 cm -3 From 5x10 21 cm -3 The device is doped with an n-type dopant such as phosphorus (P), arsenic (As), or antimony (Sb) at a certain concentration.

[0040]

[0043] The bottom epi-S / D formation process in block 314 may include an epitaxial deposition process performed in a processing chamber such as processing chamber 128 or 130 shown in Figure 1, in which the semiconductor structure 400 is exposed to a deposition gas. In some embodiments, the deposition gas includes a silicon-containing precursor, a germanium-containing precursor, and a dopant source. The silicon-containing precursor is silane (SiH4), disilane (Si2H6), tetrasilane (Si4H10 ), or combinations thereof may be included. Germanium-containing precursors may include germanium (GeH4), germanium tetrachloride (GeCl4), and digermane (Ge2H6). The dopant source may include precursor diborane (B2H6) or trimethylgallium Ga(CH3)3, which contain a p-type dopant such as boron (B) or gallium (Ga). In embodiments in which the bottom epi S / D214 is doped with n-type dopants, the dopant source may include precursor phosphine (PH3), phosphorus trichloride (PCl3), triisobutylphosphine ([(CH3)3C]3P), arsine (AsH3), arsenic trichloride (AsCl3), tertiary butylarsine (AsC4H 11 ), contains antimony trichloride (SbCl3), or Sb(C2H5)5.

[0041]

[0044] The epitaxial deposition process can be carried out at temperatures ranging from approximately 400°C to approximately 800°C. The dopants in the bottom epi-S / D214 can be activated by a subsequent annealing process carried out at temperatures ranging from approximately 850°C to approximately 1200°C.

[0042]

[0045] In block 316, as shown in Figure 4H, a bottom interlayer dielectric (ILD) 218 ​​is deposited on the uncovered surface of the spacer 208 around the bottom epi S / D 214 at the bottom of the semiconductor structure 400, and a bottom contact patterning and sacrificial filling process is performed to pattern the bottom ILD 218 and form a dummy contact 428. The bottom ILD 218 may be formed of a dielectric material such as silicon oxide (SiO2). The dummy contact 428 may be formed of a dielectric material such as silicon oxide (SiO2), silicon nitride (Si3N4), silicon carbide (SiC), or a combination thereof, which has etching selectivity from the bottom ILD 218 and can withstand subsequent high-temperature processes. Following the formation of the dummy contact 428, the upper cover spacer 426 is removed to expose the surface of the upper nanosheet 418 (shown in Figure 4E) and the spacer 208 around the upper nanosheet 418 along the ZX plane.

[0043]

[0046] The bottom contact patterning and sacrificial filling process in block 316 may include any suitable lithography and etching processes, such as photolithography, performed in a processing chamber such as processing chamber 120 shown in Figure 1, as well as any suitable deposition processes, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD), performed in a processing chamber such as processing chambers 126, 128, or 130 shown in Figure 1.

[0044]

[0047] In block 318, an upper epitaxial S / D formation process is performed to form upper epitaxial S / D222, as shown in Figure 4I. The upper epitaxial S / D222 is epitaxially grown on the exposed surface of the upper nanosheet 418 along the ZX plane. The upper epitaxial S / D222 bonds between the channel layer 202 in the upper nanosheet 418 and the S / D contact formed on top of the semiconductor structure 400, minimizing parasitic resistance. The upper epitaxial S / D222 may be formed of silicon (Si) or silicon germanium (SiGe). Following the formation of the upper epitaxial S / D222, upper ILD226 is formed on the exposed surface of the spacer 208 and around the upper epitaxial S / D222 between the spacers 208. The upper ILD226 may be formed of a dielectric material such as silicon oxide (SiO2).

[0045]

[0048] The upper epitaxial S / D222 is approximately 10 depending on the desired conductivity characteristics of the upper epitaxial S / D222. 20 cm -3 From 5x10 21 cm -3 The n-type dopant such as phosphorus (P), arsenic (As), or antimony (Sb) may be doped at a concentration of . In an embodiment in which the bottom epitaxial S / D214 is doped with a p-type dopant, the upper epitaxial S / D222 is doped with approximately 10 depending on the desired conductivity characteristics of the upper epitaxial S / D222. 20 cm -3 From 5x10 21 cm -3 The device is doped with a p-type dopant such as boron (B) or gallium (Ga) at a concentration of [value missing].

[0046]

[0049] The upper epitaxial S / D formation process in block 318 may include an epitaxial deposition process performed in a processing chamber such as processing chamber 128 or 130 shown in Figure 1, in which the semiconductor structure 400 is exposed to a deposition gas. In some embodiments, the deposition gas includes a silicon-containing precursor, a germanium-containing precursor, and a dopant source. The silicon-containing precursor is silane (SiH4), disilane (Si2H6), tetrasilane (Si4H 10 ), or combinations thereof may be included. Germanium-containing precursors may include germanium (GeH4), germanium tetrachloride (GeCl4), and digermane (Ge2H6). Dopant sources may include n-type dopants such as phosphorus (P), arsenic (As), or antimony (Sb), such as precursor phosphine (PH3), phosphorus trichloride (PCl3), triisobutylphosphine ([(CH3)3C]3P), arsine (AsH3), arsenic trichloride (AsCl3), and tertiary butylarsine (AsC4H 11 ), antimony trichloride (SbCl3), or Sb(C2H5)5 may be included. In embodiments in which the upper epi S / D222 is doped with a p-type dopant, the dopant source may include precursor diborane (B2H6) or trimethylgallium Ga(CH3)3, which contain a p-type dopant such as boron (B) or gallium (Ga).

[0047]

[0050] The epitaxial deposition process can be carried out at temperatures ranging from approximately 400°C to approximately 800°C. The dopants in the upper epi-S / D222 can be activated by a subsequent annealing process carried out at temperatures ranging from approximately 850°C to approximately 1200°C.

[0048]

[0051] In block 320, a metal gate replacement (RMG) process is performed to replace the dummy gate 420 with a metal gate 204, as shown in Figures 4J and 4J'. Figure 4J' is a cutaway of the semiconductor structure 400 along the ZX plane containing the line J'-J' shown in Figure 4J. The metal gate 204 may be formed of a metal-filling material such as cobalt (Co) and tungsten (W). The metal gate 204 may be bonded to the channel layer 202 and MDI 210 via a liner 206. The liner 206 may be formed of titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum carbide (TiAlC), or tungsten (W).

[0049]

[0052] The RMG process in block 320 may include any suitable etching process performed in a processing chamber such as processing chamber 120 shown in Figure 1, and any suitable deposition process such as chemical vapor deposition (CVD) or physical vapor deposition (PVD) performed in a processing chamber such as processing chambers 126, 128, or 130 shown in Figure 1.

[0050]

[0053] The metal filling process can be carried out at temperatures ranging from approximately 150°C to approximately 400°C. Following the metal filling process, various annealing steps, such as high dielectric constant annealing and reliability annealing, can be performed at temperatures ranging from approximately 700°C to approximately 950°C.

[0051]

[0054] In block 322, as shown in Figure 4K, an upper contact patterning and metal filling process is performed to pattern the upper ILD 226 to form the upper S / D contact 220. An upper interface 224 is formed between the upper epi S / D 222 and the upper S / D contact 220, providing an ohmic contact.

[0052]

[0055] The upper S / D contact 220 may be formed of cobalt (Co) or tungsten (W) and may include a liner (not shown) made of titanium nitride (TiN) or tungsten (W) around it. The upper interface 224 may be formed of a metal silicide such as titanium silicide (TiSi2), molybdenum silicide (MoSi2), cobalt silicide (CoSi2), nickel (Ni2Si), tantalum silicide (TaSi2), or any combination thereof. An optional contact epitaxial layer (not shown) may be formed between the upper epitaxial S / D 222 and the upper interface 224 by low-temperature epitaxial deposition at temperatures ranging from approximately 400°C to approximately 900°C. The contact epitaxial layer and the upper interface 224 can be formed in a cluster tool without breaking the vacuum.

[0053]

[0056] The upper contact patterning and metal filling process in block 322 may include any suitable lithography and etching processes, such as photolithography, performed in a processing chamber such as processing chamber 120 shown in Figure 1, as well as any suitable deposition processes, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), and epitaxial deposition processes, performed in a processing chamber such as processing chambers 126, 128, or 130 shown in Figure 1. The low-temperature epitaxial deposition process in block 322 can be performed in a processing chamber such as processing chambers 126, 128, or 130 shown in Figure 1. The upper contact patterning and metal filling process and the low-temperature epitaxial deposition process in block 322 can be performed in a cluster tool such as processing system 100 without breaking the vacuum.

[0054]

[0057] In block 324, as shown in Figure 4L, a via contact (VCT) and via contact to gate (VCG) patterning process is performed to form a bottom VCT 430, an upper VCT 432, and a VCG 434. Dielectric layers 232 and 234 are deposited on the semiconductor structure 400. The bottom VCT 430 is formed by etching through the dielectric layers 232 and 234, the upper ILD 226, and the bottom ILD 218 to the dummy contact 428. The upper VCT 432 is formed by etching through the dielectric layers 232 and 234 to the upper S / D contact 220. The VCG 434 is formed by etching through the dielectric layers 232 and 234 to the metal gate 204.

[0055]

[0058] The dielectric layers 232 and 234 may be formed of silicon oxide (SiO2), silicon nitride (Si3N4), or aluminum oxide (Al2O3). The dielectric layers 232 and 234 may be formed of different materials.

[0056]

[0059] The VCT and VCG patterning processes in block 324 may include any suitable lithography and etching processes, such as photolithography, performed in a processing chamber such as processing chamber 120 shown in Figure 1, as well as any suitable deposition processes, such as chemical vapor deposition (CVD) and physical vapor deposition (PVD), performed in a processing chamber such as processing chambers 126, 128, or 130 shown in Figure 1.

[0057]

[0060] In block 326, as shown in Figure 4M, a dummy contact stripping process is performed to selectively etch the dummy contact 428 to form the etched portion 436.

[0058]

[0061] The dummy contact strip process in block 324 may include any suitable etching process, such as photolithography, performed in a processing chamber, such as the processing chamber 120 shown in Figure 1.

[0059]

[0062] In block 328, a replacement bottom S / D contact formation process is performed to form a bottom S / D contact 212, as shown in Figure 4N. The bottom S / D contact 212 is formed by filling the portion 436 etched in the dummy contact strip process in block 324 with a metal filler material such as cobalt (Co) and tungsten (W). The metal filler material is filled into the bottom VCT 430 up to the top surface of the upper ILD 226 to form a contact plug 438. The bottom S / D contact 212 can be joined to the bottom epi S / D 214 via the bottom interface 216. The bottom S / D contact 212 may include a liner (not shown) made of titanium nitride (TiN) or tungsten (W) around it. The bottom interface 216 may be formed of a metal silicide such as titanium silicide (TiSi2), molybdenum silicide (MoSi2), cobalt silicide (CoSi2), nickel (Ni2Si), tantalum silicide (TaSi2), or any combination thereof. An optional contact epitaxial layer (not shown) can be formed between the bottom epitaxial layer S / D214 and the bottom interface 216 by low-temperature epitaxial deposition at temperatures ranging from approximately 400°C to approximately 900°C. The contact epitaxial layer and the bottom interface 216 can be formed using a cluster tool without breaking the vacuum.

[0060]

[0063] The replacement bottom S / D contact formation process in block 328 may include any suitable deposition process such as chemical vapor deposition (CVD) or physical vapor deposition (PVD) performed in a processing chamber such as processing chambers 126, 128, or 130 shown in Figure 1. The low-temperature epitaxial deposition process in block 328 can be performed in a processing chamber such as processing chambers 126, 128, or 130 shown in Figure 1. The replacement bottom S / D contact formation process and the low-temperature epitaxial deposition process in block 328 can be performed using a cluster tool such as processing system 100 without breaking the vacuum. The cluster tool may be the same as the cluster tool used to perform the upper contact patterning and metal filling process and the low-temperature epitaxial deposition process in block 322.

[0061]

[0064] In block 330, as shown in Figure 4O, a VCT and VCG filling process is performed to fill the bottom VCT 430, upper VCT 432, and VCG 434 within the dielectric layers 232 and 234 with metal filler materials such as cobalt (Co) and tungsten (W) to form a contact plug 236.

[0062]

[0065] The VCT and VCG filling process in block 330 may include any suitable deposition process, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD), performed in a processing chamber such as processing chambers 126, 128, or 130 shown in Figure 1.

[0063]

[0066] In block 332, as shown in Figure 2A, a metal layer formation process is performed in which a metal layer 228 is formed on dielectric layers 232 and 234 and embedded in dielectric layer 230. The metal layer 228 may be formed of cobalt (Co) or tungsten (W). The dielectric layer 230 may be formed of silicon oxide (SiO2), silicon nitride (Si3N4), or aluminum oxide (Al2O3).

[0064]

[0067] The metal layer formation process in block 332 may include any suitable lithography and etching processes, such as photolithography, performed in a processing chamber such as processing chamber 120 shown in Figure 1, as well as any suitable deposition processes, such as chemical vapor deposition (CVD) and physical vapor deposition (PVD), performed in a processing chamber such as processing chambers 126, 128, or 130 shown in Figure 1.

[0065]

[0068] The embodiments described herein provide a method for complementary FET (CFET) devices. In the method described herein, dummy contacts are deposited in place of the bottom source / drain (S / D) contacts of the bottom FET module of the CFET before high-temperature processes such as epitaxial deposition processes and metal gate replacement processes, and are subsequently replaced with bottom S / D contacts formed of metal. By replacing with these S / D contacts, it becomes possible to use materials optimized for the bottom S / D contacts of the bottom FET module without any thermal balance constraints.

[0066]

[0069] While the foregoing applies to embodiments of the present disclosure, it is possible to devise other further embodiments of the present disclosure without departing from its basic scope as defined by the following claims.

Claims

1. A semiconductor structure that forms a complementary field-effect transistor (CFET), Metal gate and This is a bottom field-effect transistor (FET) module, Multiple channel layers extending in a first direction through the metal gate, Bottom epitaxial (epi) S / D and bottom source / drain (S / D) contacts electrically connected to the plurality of channel layers via bottom interface Includes a bottom FET module, An upper FET module stacked on the bottom FET module in a second direction perpendicular to the first direction, A plurality of channel layers extending in the first direction through the metal gate, Upper epitaxial (epi) S / D and upper source / drain (S / D) contacts electrically connected to the plurality of channel layers via the upper interface Includes the upper FET module and Equipped with, The bottom S / D contact and the upper S / D contact each have a semiconductor structure containing cobalt (Co) or tungsten (W).

2. The semiconductor structure according to claim 1, wherein the metal gate comprises cobalt (Co) or tungsten (W).

3. The semiconductor structure according to claim 1, wherein each of the plurality of channel layers in the upper FET module and the plurality of channel layers in the bottom FET module contains silicon.

4. The semiconductor structure according to claim 1, wherein the bottom epitaxial S / D is doped with p-type material and the upper epitaxial S / D is doped with n-type material.

5. The semiconductor structure according to claim 1, wherein the bottom epitaxial S / D is doped with n-type, and the upper epitaxial S / D is doped with p-type.

6. The semiconductor structure according to claim 1, wherein the upper interface and the bottom interface each include a metal silicide.

7. A method for forming a complementary field-effect transistor (CFET), An upper cover spacer formation process is performed to deposit an upper cover spacer that covers the exposed surface of the upper nanosheet and a spacer around the upper nanosheet along a first plane perpendicular to the first direction, The upper nanosheet is laminated on the bottom nanosheet in a second direction perpendicular to the first direction. The upper nanosheet and the lower nanosheet each include a plurality of channel layers extending in the first direction through the dummy gate. Perform the upper cover spacer formation process, To form a bottom epi-S / D on the exposed surface of the bottom nanosheet along the first plane, a bottom epitaxial (epi)source / drain (S / D) formation process is performed, The process involves depositing a bottom interlayer insulator (ILD) on the spacer surface around the bottom epi S / D, patterning the bottom ILD to form a dummy contact, and then performing a bottom contact patterning and sacrificial filling process to remove the upper cover spacer. The process involves performing an upper epi S / D formation process to form an upper epi S / D on the exposed surface of the upper nanosheet along the first plane, and to form an upper ILD around the upper epi S / D. In order to replace the dummy gate with a metal gate, a metal gate replacement (RMG) process is performed. To pattern the upper ILD and form the upper S / D contact, an upper contact patterning and metal filling process is performed. In order to selectively etch the dummy contact, a dummy contact stripping process is performed following the bottom epitaxial S / D formation process, the top epitaxial S / D formation process, and the RMG process. In order to form a bottom S / D contact in the portion etched by the dummy contact strip process, a replacement bottom S / D contact formation process is performed. A method that includes this.

8. The method according to claim 7, wherein the bottom S / D contact, the upper S / D contact, and the metal gate each contain cobalt (Co) or tungsten (W).

9. The dummy contact is made of silicon dioxide (SiO ２ ), silicon nitride (Si ３ N ４ The method according to claim 7, comprising ), silicon carbide (SiC), or a combination thereof.

10. The bottom ILD and the upper ILD are each made of silicon dioxide (SiO ２ The method according to claim 7, including )

11. The method according to claim 7, wherein the bottom epi S / D is doped with p-type and the upper epi S / D is doped with n-type.

12. The method according to claim 11, further comprising performing an annealing process to activate dopants in the bottom epi S / D and the upper epi S / D before the dummy contact strip process.

13. The method according to claim 7, wherein the bottom epitaxial S / D formation process and the top epitaxial S / D formation process are carried out at a temperature of 400°C to 1200°C.

14. The method according to claim 7, wherein the RMG process is carried out at a temperature of 150°C to 950°C.

15. A semiconductor structure that forms a complementary field-effect transistor (CFET), Metal gate and This is a bottom field-effect transistor (FET) module, Multiple channel layers extending in a first direction through the metal gate, Dummy contacts connected to the multiple channel layers via bottom epitaxial (epi) S / D and bottom interface Includes a bottom FET module, An upper FET module stacked on the bottom FET module in a second direction perpendicular to the first direction, A plurality of channel layers extending in the first direction through the metal gate, Upper epitaxial (epi) S / D and upper source / drain (S / D) contacts electrically connected to the plurality of channel layers via the upper interface Includes the upper FET module and Equipped with, The dummy contact is made of silicon dioxide (SiO ２ ), silicon nitride (Si ３ N ４ A semiconductor structure comprising silicon carbide (SiC), or a combination thereof, wherein the upper S / D contact comprises cobalt (Co) or tungsten (W).

16. The semiconductor structure according to claim 15, wherein the metal gate comprises cobalt (Co) or tungsten (W).

17. The semiconductor structure according to claim 15, wherein each of the plurality of channel layers in the upper FET module and the plurality of channel layers in the bottom FET module contains silicon.

18. The semiconductor structure according to claim 15, wherein the bottom epitaxial S / D is doped with p-type material and the upper epitaxial S / D is doped with n-type material.

19. The semiconductor structure according to claim 15, wherein the bottom epitaxial S / D is doped with n-type material and the upper epitaxial S / D is doped with p-type material.

20. The semiconductor structure according to claim 15, wherein the upper interface and the bottom interface each include a metal silicide.

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