Package substrate with embedded electronic components in the core of the package substrate

Abstract

In one embodiment, an electronic device is disclosed, comprising: a core having an upper plane and an inner plane; a cavity extending at least partially through the upper plane of the core into the inner plane of the core; an electronic component mounted within the cavity, the electronic component having an upper plane having one or more electronic component terminals, and the electronic component being supported by the inner plane of the core such that the upper plane of the electronic component is at the same height as the upper plane of the core; and an upper metallization structure configured to provide one or more conductive paths from one or more electronic component terminals to one or more upper metal terminals of the upper metallization structure.

Description

Technical Field

[0001] The present disclosure generally relates to substrates, and more particularly to a package substrate having embedded electronic components implemented within a core of the package substrate, and a method of fabricating the package substrate.

Background Art

[0002] Integrated circuit (IC) technology has achieved great progress in improving computing power by miniaturizing electrical components. An IC can be realized in the form of an IC chip having a set of circuits integrated thereon. In some implementation forms, one or more IC chips can be physically carried and protected by an IC package, and various power and signal nodes of the one or more IC chips can be electrically coupled to respective conductive terminals of the IC package via electrical paths formed within the package substrate of the IC package. Various packaging technologies can be found in many electronic devices, including processors, servers, radio frequency (RF) integrated circuits, etc. Advanced packaging and processing techniques can be used to realize composite devices, such as multi-electronic component devices and system-on-a-chip (SOC) devices, which can include a plurality of functional blocks, where each functional block is designed to perform a specific function, such as a microprocessor function, a graphics processing unit (GPU) function, a communication function (e.g., Wi-Fi, Bluetooth (registered trademark), and other communications), and the like.

[0003] In some implementations, embedded electronic components, such as deep trench capacitors, are incorporated into IC packaging to improve performance and reduce package size. One factor driving the use of such embedded electronic components is the demand for small form factor products that have electrical performance equivalent to or better than their larger counterparts. Depending on the size and / or thickness of the package substrate, and the size and / or process node of the IC chip supported thereon, a process for embedding electronic components in a package substrate for one packaging task may not be suitable for another packaging task.

[0004] Therefore, there is a need for improved methods for embedding electronic components into substrates such as package substrates, which can be suitable for a wider range of packaging tasks. [Overview of the project] [Means for solving the problem]

[0005] The following provides a simplified overview of one or more embodiments disclosed herein. Therefore, this overview should not be considered a broad overview of all intended embodiments, nor should it be considered to identify the main or important elements of all intended embodiments, or to define the scope relevant to any particular embodiment. Accordingly, the sole purpose of this overview is to provide, in a simplified form, certain concepts relating to one or more embodiments of the mechanisms disclosed herein, prior to the detailed descriptions presented below.

[0006] In one embodiment, the substrate includes a core having an upper plane and an inner plane; a cavity extending at least partially through the upper plane of the core into the inner plane of the core; an electronic component mounted within the cavity, the electronic component having an upper plane having one or more electronic component terminals, and the electronic component being supported by the inner plane of the core such that the upper plane of the electronic component is at the same height as the upper plane of the core; and an upper metallization structure configured to provide one or more conductive paths from one or more electronic component terminals to one or more upper metal terminals of the upper metallization structure.

[0007] In one embodiment, the electronic device includes a substrate comprising: a core having an upper plane and an inner plane; a cavity extending at least partially through the upper plane of the core into the inner plane of the core; an electronic component within the cavity, the electronic component having an upper plane having one or more electronic component terminals, the electronic component being supported by the inner plane of the core such that the upper plane of the electronic component is at the same height as the upper plane of the core; and an upper metallization structure configured to provide one or more conductive paths from one or more electronic component terminals to one or more upper metal terminals of the upper metallization structure.

[0008] In one embodiment, a method for forming a substrate includes forming a cavity extending from the upper plane of a core to the inner plane of a core; inserting an electronic component, which is supported by the inner plane of a core such that the upper plane of the electronic component is at the same height as the upper plane of the core, into the cavity such that the upper plane of the electronic component having one or more electronic component terminals is supported by the inner plane of the core; and forming an upper metallization structure on the upper plane of a core, which is configured to provide one or more conductive paths from one or more electronic component terminals to one or more upper metal terminals of the upper metallization structure.

[0009] Other purposes and advantages associated with the embodiments disclosed herein will become apparent to those skilled in the art based on the accompanying drawings and detailed description.

[0010] A more complete understanding of many aspects of this disclosure and their associated advantages will be easier to obtain, as they will be better understood when considered together with the accompanying drawings, which are presented merely for illustrative purposes and not to limit this disclosure, by referring to the detailed description below. [Brief explanation of the drawing]

[0011] [Figure 1] This is a cross-sectional view of a first exemplary substrate having embedded electronic components according to an aspect of the present disclosure. [Figure 2] This is a cross-sectional view of a second exemplary substrate having embedded electronic components according to an aspect of the present disclosure. [Figure 3] This is a cross-sectional view of an exemplary deep trench capacitor according to an aspect of the present disclosure. [Figure 4] This is a cross-sectional view of an exemplary substrate according to an aspect of the present disclosure. [Figure 5] This is a cross-sectional view of an exemplary substrate according to an aspect of the present disclosure. [Figure 6A] The following are exemplary steps taken when manufacturing a substrate according to an aspect of this disclosure. [Figure 6B] The following are exemplary steps taken when manufacturing a substrate according to an aspect of this disclosure. [Figure 6C] The following are exemplary steps taken when manufacturing a substrate according to an aspect of this disclosure. [Figure 6D] The following are exemplary steps taken when manufacturing a substrate according to an aspect of this disclosure. [Figure 6E] The following are exemplary steps taken when manufacturing a substrate according to an aspect of this disclosure. [Figure 6F] The following are exemplary steps taken when manufacturing a substrate according to an aspect of this disclosure. [Figure 6G]The following are exemplary steps taken when manufacturing a substrate according to an aspect of this disclosure. [Figure 7] This flowchart shows an exemplary method for manufacturing a substrate according to an aspect of the present disclosure. [Figure 8] A side view of a package including a surface mount substrate, an integrated device, and an integrated passive device according to an aspect of this disclosure is shown. [Figure 9] This diagram illustrates an exemplary flow chart of a method for manufacturing a package including a substrate, integrated devices, and integrated passive devices. [Figure 10] This specification describes various electronic devices capable of integrating the electronic components, electronic circuits, integrated devices, integrated passive devices, passive components, packages, and / or device packages described herein. [Modes for carrying out the invention]

[0012] By convention, features depicted in the drawings may not be drawn to scale. Therefore, the dimensions of depicted features may be enlarged or reduced as appropriate for clarity. By convention, some of the drawings are simplified for clarity. Therefore, the drawings may not depict all parts of a particular apparatus or method. Furthermore, similar reference numerals indicate similar features throughout this specification and the drawings.

[0013] Aspects of the Disclosure are shown in the following description and related drawings, which cover specific embodiments. Alternative embodiments or designs may be devised without departing from the scope of the teachings herein. In addition, well-known elements of the exemplary embodiments herein may not be described in detail or may be omitted so as not to obscure the relevant details of the teachings herein.

[0014] In some of the exemplary implementations described, cases are identified where some of the structures and operations of various components are incorporated from known prior art techniques and can then be configured according to one or more exemplary embodiments. In such cases, in order to help avoid obscuring the concepts illustrated in the exemplary embodiments disclosed herein, details inside of some of the structures and / or operations of the known prior art components may be omitted.

[0015] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are to be construed to include the plural forms as well, unless the context clearly dictates otherwise. The terms "comprises", "comprising", "includes" and / or "including" when used herein specify the presence of the stated feature, integer, step, operation, element, and / or component, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0016] FIG. 1 is a cross-sectional view of a first exemplary substrate 100 having an embedded electronic component according to an aspect of the present disclosure. In this example, substrate 100 includes a core portion 102 having a cavity 104 that extends completely through core portion 102. An electronic component 106 is disposed within cavity 104. Electronic component 106 has an upper surface 108 having metal terminals 110 that provide electrical connections to electronic component 106. According to various aspects of the present disclosure, electronic component 106 can be one or more of an active electronic component, a passive electronic component (e.g., a deep trench capacitor (DTC)), a die, etc.

[0017] According to various aspects of the present disclosure, the substrate (e.g., substrate 100) described herein that includes a core and embedded electronic components is targeted at a package substrate. The package substrate is a part of an integrated circuit package that gives the board its mechanical strength and enables it to connect to external devices. Such a package substrate should be distinguished from other substrates, such as a substrate that may be included within the embedded electronic component itself, a die that includes a substrate (e.g., a silicon substrate or other similar electronic device).

[0018] Substrate 100 further includes a plurality of dielectric layers 112 lying on top surface 116 of core 102 and corresponding patterned metallization layers 114. A patterned metallization layer 118 is disposed on top surface 116 of core 102 to provide an electrical connection between metal terminals 110 of electronic component 106 and the patterned metallization layer 114. In one aspect, the same dielectric resin material used to form the plurality of dielectric layers 112 can be used within region 109 of cavity 104 between the sidewalls of electronic component 106 and the sidewalls of cavity 104. Dispensing the dielectric resin over electronic component 106 and within region 109 helps to fix electronic component 106 within cavity 104, such that after the dielectric resin is cured, metal terminals 110 remain in electrical connection with corresponding portions of patterned metallization layer 118.

[0019] In one aspect, the uppermost patterned metallization layer 114 on top surface 120 of substrate 100 is connected to a plurality of metal terminals 122. The patterned metallization layer 114 provides a conductive path between metal terminals 110 of electronic component 106 and metal terminals 122. In one aspect, the plurality of metal terminals 122 can be configured for connection to an electronic package of a surface mount device (not shown in FIG. 1).

[0020] In one embodiment, a further plurality of dielectric layers 132 and corresponding patterned metallization layers 134 lie on the bottom surface 136 of the core 102. Here, a patterned metallization layer 138 is disposed on the bottom surface 136 of the core 102. The bottommost patterned metallization layer 134 on the bottom surface 140 of the substrate 100 is connected to a plurality of metal terminals 142. The patterned metallization layer 134 provides a conductive path to the metal terminals 142. In one embodiment, the plurality of metal terminals 142 may be configured for connection to an electronic package of a further surface mount device (not shown in Figure 1) or to a circuit board for connection to other devices.

[0021] In Figure 1, the electronic component 106 has a height H1 that is substantially the same as the thickness H2 of the core 102. During the fabrication of the substrate 100, the electronic component 106 is inserted into the cavity 104 before dielectric resin is injected to fill the region 109 between the cavity 104 and the electronic component 106. During insertion, the electronic component 106 is carefully aligned within the cavity 104 to ensure that the metal terminals 110 make proper contact with the corresponding portions of the patterned metallization layer 118 and electrically couple. In addition, the injection of dielectric resin into region 109 must be carried out carefully so as not to disturb the initial alignment of the electronic component 106. In one embodiment, once the dielectric resin has cured, it fixes the electronic component 106 in its proper place within the cavity 104.

[0022] In a scenario where the height H1 of the electronic component 106 and the thickness H2 of the core 102 are substantially the same, the insertion of the electronic component 106 into the cavity 104 and the subsequent injection and curing of the dielectric resin can be carried out using the processing techniques described with reference to Figure 1. In one example, the height H1 of the electronic component and the thickness H2 of the core 102 in Figure 1 may each be about 760 micrometers or less.

[0023] The structure of substrate 100 shown in Figure 1 was suitable for use in many high-performance applications (e.g., computational and automotive applications), but current trends are moving towards applications requiring substrates with larger body sizes. However, substrates with larger body sizes present unique design and fabrication challenges that must be addressed (e.g., substrate warpage, the need for larger cavity sizes, the need for larger keep-out zones, etc.). These challenges can be addressed, at least in part, by employing a thicker core in the design and fabrication of such substrates. For example, warpage control is more easily achieved with a thicker core than with a thin core. In addition, the need for larger cavity sizes and keep-out zones can be met by employing such a thicker core.

[0024] However, substrates employing thick cores may be difficult to fabricate using the same packaging techniques used to manufacture substrates with thin cores of the type described in relation to Figure 1. When using thick cores, a large gap exists between the electronic component and the cavity, resulting from the increased cavity depth compared to the height of the electronic component (for example, a thick core has a thickness greater than the height of the electronic component). In such thick core scenarios, it may be difficult or impossible to fill the gap surrounding the electronic component with dielectric resin in a manner that maintains the proper initial alignment of the electronic component within the cavity during resin injection. Furthermore, it may be difficult or impossible to inject a sufficient amount of dielectric resin into the gap to fix the electronic component in its desired position after the dielectric resin has cured.

[0025] Figure 2 is a cross-sectional view of an exemplary substrate 200 having embedded electronic components according to an aspect of the present disclosure. In this example, it is assumed that the substrate 200 was manufactured using the same processing operations used to manufacture the substrate 100 shown in Figure 1. For simplicity, some of the reference numerals used in Figure 1 are also used to indicate similar elements in Figure 2.

[0026] In the example shown in Figure 2, the substrate 200 differs from the substrate 100 in Figure 1 in that the substrate 200 employs a thick core 202 having a thickness H3 greater than the height H1 of the electronic component 106. According to some aspects of this disclosure, the thickness H3 is greater than approximately 760 micrometers and is therefore thicker than the electronic component 106 and its thin core 102 counterpart. In some scenarios, the thick core may have a thickness considerably greater than 760 micrometers (e.g., 820 micrometers, 1240 micrometers, etc.).

[0027] The substrate 200 has a cavity 204 that is considerably deeper than the cavity 104 of the substrate 100. Therefore, it becomes more difficult to align the metal terminals 110 with the corresponding portions of the patterned metallization layer 118 during the initial placement of the electronic component 106 into the cavity 204. Initial misalignment of the electronic component 106 may result in failure to establish an electrical connection between the metal terminals 110 and the corresponding portions of the patterned metallization layer 118. In addition, once the cavity 209 (e.g., particularly the enlarged region of the cavity 209) is cured, it becomes difficult to accurately fill it with enough dielectric resin to properly surround the electronic component 106 and secure it in place within the cavity 204. Insufficient filling of the cavity 204 with dielectric resin can lead to the subsequent delamination of electronic components 106 from electrical contact with the corresponding portion of the patterned metallization layer 118 when the substrate 200 is incorporated into a larger electronic system (e.g., an automotive sensor / computer, a mobile device, or any other type of electronic device as described herein). Figure 2 shows an example of delamination in region 208, where a portion of the metal terminals 110 has detached from the corresponding portion of the patterned metallization layer 118.

[0028] Some aspects of this disclosure are implemented with recognition of the problems associated with using existing fabrication techniques to manufacture substrates having certain types of cores (e.g., thick cores) and / or certain types of electronic components (e.g., deep trench capacitors). According to some aspects of this disclosure, electronic components may be embedded in a substrate within a cavity formed from the upper plane of the core to the inner plane of the core. In one aspect, the electronic component is supported by the inner plane of the core such that the upper plane of the electronic component, on which the electronic component contacts are located, is at the same height as the upper plane of the core. This architecture allows for the same top-surface routing of electronic component contacts (e.g., as shown in Figure 1) without the challenges of supporting and detaching embedded electronic components associated with cavities that extend completely through the core (e.g., as shown in Figure 2). In one aspect, the cavity may be filled with a filler material, such as a dielectric resin, to fix the electronic component within the cavity. The filler material may be deposited within the cavity without creating voids that could otherwise cause substrate failure. According to certain aspects of this disclosure, core thickness is no longer a limiting factor that must be considered when embedding electronic components in a substrate.

[0029] According to certain aspects of this disclosure, the electronic component may be a DTC. Figure 3 is a cross-sectional view of an exemplary DTC 300 according to an aspect of this disclosure. In Figure 3, a capacitor 310 is deposited in trenches 320 of an insulator 304 on a substrate 302. The capacitor 310 may include a metal layer 312, a dielectric layer 314, and a metal layer 316. The dielectric layer 314 separates the metal layer 312 from the metal layer 316. The metal layers 312, 316 form the electrodes of the capacitor 310 and may be connected to terminals on a surface, for example (see, for example, the top surface 108 having metal terminals 110 of the electronic component 106 shown in Figure 1). In some scenarios, the capacitor is formed from an array of deep trenches in the substrate and filled with an electrical insulator (e.g., a dielectric) between the layers of electrodes. In some scenarios, the capacitor is mounted on the land side under the shadow of the integrated circuit die (land-side capacitor, LSC), or mounted on the die side adjacent to the die (die-side capacitor, DSC).

[0030] Figure 4 is a cross-sectional view of an exemplary substrate 400 according to an aspect of the present disclosure. In this example, the substrate 400 includes an electronic component 402 having a lower plane 404 and an upper plane 406. The upper plane 406 of the electronic component 402 includes one or more electronic component terminals 408 that provide electrical connections to the electronic component 402.

[0031] The substrate 400 further includes a core 410 having a lower plane 412 (e.g., a first plane), an upper plane 414 (e.g., a second plane), and an internal plane 418. A cavity 416 is formed within the upper plane 414 of the core 410 and extends through at least a portion of the core 410 to the internal plane 418 of the core 410. The internal plane 418 of the core 410 may be an internal portion of the core 410. The lower plane 404 of the electronic component 402 faces the internal plane 418, either directly supporting the electronic component 402 or indirectly supporting the electronic component 402 via an intermediate layer 420 (e.g., an adhesive layer). The depth of the H1 cavity 416 is substantially the same dimension as the height H2 of the electronic component 402 as measured between the upper plane 406 and the lower plane 404 of the electronic component 402. Therefore, the upper plane 406 of the electronic component 402 is substantially the same height as the upper plane 414 of the core 410, as shown by the dashed line 422. In one embodiment, the cavity 416 is dimensioned so that it can be filled with a filler material 424, such as a dielectric resin, without creating voids. This configuration allows the electronic component 402 to be mounted in a fixed position within the cavity 416, while also being connected using the same top-connection configuration as shown in Figure 1, and at the same time, to reduce the opportunity for the electronic component 402 to detach from connections with other layers of the substrate 400. If an intermediate layer 420 (e.g., an adhesive layer) is used, the thickness of the intermediate layer 420 must be such that the upper plane of the electronic component 402 remains at the same height as the upper plane of the core 410.

[0032] In one embodiment, the core 410 may include a patterned metallization layer 426 on the upper plane 414. In the example shown in Figure 4, the patterned metallization layer 426 may be connected to one or more electronic component terminals 408. A patterned metallization layer 428 may also be provided on the lower plane 412 of the core 410.

[0033] According to certain aspects of this disclosure, the substrate 400 may include an upper metallization structure 430 configured to provide one or more conductive paths from one or more electronic component terminals 408 to one or more upper metal terminals 432 of the upper metallization structure 430. In the example shown in Figure 4, the upper metallization structure 430 includes one or more dielectric layers 434 disposed on the upper plane 414 of the core 410. Although the dielectric layers 434 are shown as separate layers in Figure 4, it will be understood that multiple dielectric layers may be fused during the fabrication process so that they appear and function as a single dielectric structure. Furthermore, it will be understood that different layers of dielectric layers 434 may be formed from different dielectric materials during the fabrication process. In one aspect, different dielectric materials may be used for different dielectric layers when one or more of the dielectric layers 434 are to have a different dielectric constant than other dielectric layers 434.

[0034] According to certain aspects of this disclosure, each of the dielectric layers 434 is associated with a corresponding patterned metallization layer 436. One or more metal via structures may be formed through the dielectric layers 434. The metal via structures provide a conductive path between one or more electronic component terminals 408 of the electronic component 402 and metal terminals 432 formed by the upper metallization layer of the upper metallization structure 430. According to certain aspects of this disclosure, the metal terminals 444 may be configured for connection to an electronic circuit package (not shown in Figure 4) mounted on the upper surface of the substrate 400.

[0035] As described above, the cavity 416 may be filled with filler material 424 to mount the electronic component 402 within the cavity 416. In one embodiment, the filler material 424 may completely fill the cavity 416 such that the entire electronic component 402 is surrounded by the filler material 424. In one embodiment, the filler material 424 may consist of the same dielectric material used to form the dielectric layer 434. In this case as well, it will be understood that the filler material 424 within the cavity 416 may merge with the dielectric layer 434 to appear and function as a single dielectric structure surrounding the electronic component 402. Furthermore, it will be understood that the filler material 424 may include materials other than the dielectric material used to form the dielectric layer 434.

[0036] In one embodiment, the substrate 400 may include a lower metallization structure 437 having one or more dielectric layers 438 and a corresponding set of patterned metallization layers 440 disposed on the lower plane 412 of the core 410. As shown, the dielectric layers 438 may separate the patterned metallization layers 440 from each other. One or more metal via structures may extend between the patterned metallization layers 440 and connect to metal terminals 444 in the bottommost patterned metallization layer 442 on the lower surface of the substrate 400. According to various embodiments of the present disclosure, the metal terminals 444 may be configured to mount the substrate 400 onto another substrate and / or into an electrical device package (not shown in Figure 4).

[0037] Figure 5 is a cross-sectional view of an exemplary substrate 500 according to an aspect of the present disclosure. In this example, the substrate 500 is similar in most respects to the substrate 400 shown in Figure 4. Therefore, similar reference numerals are used to refer to similar elements. Unlike the substrate 400, the substrate 500 includes a non-conductive paste 502 disposed between the lower plane 404 of the electronic component 402 and the inner plane 418 of the cavity 416 to facilitate the fixation of the electronic component 402 within the cavity 416. In one embodiment, the non-conductive paste 502 surrounds at least partially one or more sidewalls of the electronic component 402. In addition to facilitating the fixation of the electronic component 402 in place within the finished substrate 500, the non-conductive paste 502 may also serve to hold the electronic component 402 in place during manufacturing (e.g., filling the cavity 416).

[0038] Figures 6A to 6H illustrate exemplary steps taken when manufacturing a substrate according to an embodiment of the present disclosure. As shown in Figure 6A, a first intermediate structure 600 is formed having a patterned metallization layer 602 disposed on the upper plane 604 of the core 606. In addition, a further patterned metallization layer 608 is formed on the lower surface 610 of the core 606.

[0039] As shown in Figure 6B, a cavity 612 is formed within the upper plane 604 of the first intermediate structure 600 to form a second intermediate structure 615. The cavity 612 is bounded by the side walls 616 of the core 606 and the internal plane 614 of the core 606. In one embodiment, the depth H1 of the cavity 612 corresponds to the height of the electronic components to be mounted within the cavity 612.

[0040] As shown in Figure 6C, a third intermediate structure 618 is formed when the adhesive layer 620 (and / or a layer of non-conductive paste) is placed on the internal plane 614 of the core 606. In one embodiment, the amount of adhesive (or non-conductive paste) dispensed for the adhesive layer 620 depends on the extent to which the adhesive layer should engage with the electronic component mounted in the cavity 612. A larger amount of adhesive may be used when the electronic component should be at least partially embedded in the adhesive layer (for example, when the adhesive layer extends into the region between the side wall 616 of the core 606 and the peripheral side wall of the electronic component).

[0041] As shown in Figure 6D, a fourth intermediate structure 622 is formed when the electronic component 624 is inserted into the cavity 612 such that its upper surface 626, which has the electronic component terminals 628, faces upward and its lower surface 630 faces the internal surface 614 of the core 606. In this example, the lower surface 630 of the electronic component 624 is bonded to the internal surface 614 by the adhesive layer 620. As described above in this specification, the depth of the cavity 612 is substantially the same dimension as the height of the electronic component 624, so that when the electronic component 624 is installed in the cavity 612, the upper surface 626 of the electronic component 624 is at the same height as the upper surface 604 of the core 606 (as shown, for example, by the dotted line 632). Based on the teachings of this disclosure, it will be understood that the depth of the cavity 612 may take into account the amount that the electronic component 624 is lifted by the adhesive layer 620. Therefore, the depth of the cavity 612 may depend on the amount of material used to form the adhesive layer 620, or any other thin layer lying on top of the internal plane 614.

[0042] Figure 6E shows a fifth intermediate structure 634 in which the cavity 612 is filled with a filler material 636 that helps to secure the electronic component 624 within the cavity 612. In one embodiment, the filler material 636 may be formed from a dielectric resin or other non-conductive viscous material. The fifth intermediate structure 634 undergoes a layer build-up process in which a further layer 638, including a dielectric layer 640 and a patterned metallization layer 642, is formed on the upper surface of the fourth intermediate structure 622. In one embodiment, the filler material 636 may be formed from the same dielectric material as the dielectric layer 640 and deposited during the same layer build-up operation. In addition, a layer 644, including a dielectric layer 646 and a patterned metallization layer 648, is formed on the lower surface of the fourth intermediate structure 622 during the layer build-up process.

[0043] In Figure 6F, the sixth intermediate structure 650 is formed by subjecting the fifth intermediate structure 634 to a further layer build-up process to form layers 652 and 654. It will be understood that metal via structures may be formed during the layer build-up process to establish conductive paths between the layers.

[0044] Figure 6G shows a completed substrate 656 according to an aspect of the present disclosure, where a plurality of metal terminals 658 may be formed on the upper surface 660 of the substrate to provide electrical connections to a patterned metallization layer 662. The patterned metallization layer 662 may be connected to the electronic component terminals 628 of an electronic component 624 through conductive paths formed by metal vias deposited during the layer build-up process. As described above in this specification, the metal terminals 658 may be configured for connection to the electronic package of a surface mount device.

[0045] As shown in Figure 6G, an additional number of metal terminals 664 are formed on the underside 666 of the substrate and electrically connected to the bottom patterned metallization layer 668. As described above in this specification, the metal terminals 664 may be configured for connection to another electronic package of the surface mount device, connection to another substrate, or the like.

[0046] Figure 7 is a flowchart illustrating an exemplary method 700 for manufacturing a substrate according to an aspect of the present disclosure. In operation 702, a cavity is formed within the core, extending from the upper plane of the core to the inner plane of the core. In operation 704, an electronic component is inserted into the cavity such that the upper plane of the electronic component, having one or more electronic component terminals, is supported by the inner plane of the core. The electronic component is supported by the inner plane of the core such that the upper plane of the electronic component is at the same height as the upper plane of the core. In operation 706, an upper metallization structure is formed and configured to provide one or more conductive paths from one or more electronic component terminals to one or more upper metal terminals of the upper metallization structure.

[0047] The technical advantage of Method 700 is that it can be used to form substrates having embedded electronic components (e.g., deep trench capacitors) and cores, and the manufacturing process is independent of the core thickness.

[0048] Figure 8 shows a side view of a package 800 according to an aspect of the present disclosure, including a surface mount substrate 802, an integrated device 803, and an integrated passive device 805 (e.g., a substrate having embedded electronic components and a core). The package 800 may be coupled to a printed circuit board (PCB) 806 via a plurality of solder interconnects 810. The PCB 806 may include at least one board dielectric layer 860 and a plurality of board interconnects 862.

[0049] The surface mount substrate 802 includes at least one dielectric layer 820 (e.g., a substrate dielectric layer), a plurality of interconnection parts 822 (e.g., substrate interconnection parts), a solder resist layer 840, and a solder resist layer 842. The integrated device 803 may be coupled to the surface mount substrate 802 via a plurality of solder interconnection parts 830. The integrated device 803 may be coupled to the surface mount substrate 802 via a plurality of pillar interconnection parts 832 and a plurality of solder interconnection parts 830. The integrated passive device 805 may be coupled to the surface mount substrate 802 via a plurality of solder interconnection parts 850. The integrated passive device 805 may be coupled to the surface mount substrate 802 via a plurality of pillar interconnection parts 852 and a plurality of solder interconnection parts 850.

[0050] The package (e.g., 800) may be implemented within a radio frequency (RF) package. The RF package may be a radio frequency front end (RFFE) package. The package (e.g., 800) may be configured to provide Wireless Fidelity (WiFi) communications and / or cellular communications (e.g., 2G, 3G, 4G, 5G). The package (e.g., 800) may be configured to support Global System for Mobile (GSM) communications, Universal Mobile Telecommunications System (UMTS), and / or Long-Term Evolution (LTE). The package (e.g., 800) may be configured to transmit and receive signals with different frequencies and / or different communication protocols.

[0051] Figure 9 shows an exemplary method 900 for providing or manufacturing a package including an integrated device having electronic components mounted in a core, according to an aspect of the present disclosure. In some implementations, the method 900 of Figure 9 can be used to provide or manufacture the package 800 of Figure 8 described herein. However, the method 900 can also be used to provide or manufacture any of the packages described herein.

[0052] It should be noted that the method in Figure 9 may combine one or more processes to simplify and / or clarify a method for providing or manufacturing a package including an integrated device having electronic components mounted in a core, according to aspects of this disclosure. In some implementations, the order of the processes may be changed or modified.

[0053] This method provides a substrate (e.g., 802) (in 905). The substrate 802 may be provided by a supplier or manufactured by the supplier. The substrate 802 includes at least one dielectric layer 820 and a plurality of interconnection portions 822. The substrate 802 may include an embedded trace substrate (ETS). In some mounting configurations, at least one dielectric layer 820 may include a prepreg layer.

[0054] This method (in 910) bonds at least one integrated device (e.g., 803) to a first surface of a substrate (e.g., 802). For example, the integrated device 803 may be bonded to the substrate 802 via a plurality of pillar interconnects 832 and a plurality of solder interconnects 830. The plurality of pillar interconnects 832 can be optional. The plurality of solder interconnects 830 are bonded to a plurality of interconnects 822. A solder reflow process may be used to bond the integrated device 803 to the plurality of interconnects via the plurality of solder interconnects 830.

[0055] The method also involves bonding at least one integrated passive device (e.g., 805) to a first surface of a substrate (e.g., 802) (in 910). For example, the integrated passive device 805 may be bonded to the substrate 802 via a plurality of pillar interconnects 852 and a plurality of solder interconnects 850. The plurality of pillar interconnects 852 can be optional. The plurality of solder interconnects 850 are bonded to a plurality of interconnects 822. A solder reflow process may be used to bond the integrated passive device 805 to the plurality of interconnects via the plurality of solder interconnects 850.

[0056] This method bonds a plurality of solder interconnects (e.g., 810) (in 915) to a second surface of a substrate (e.g., 802). A solder reflow process may be used to bond the plurality of solder interconnects 810 to the substrate.

[0057] Figure 10 shows various electronic devices that can be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, electronic components, interposer packages, package-on-package (PoP), system-in-package (SiP), or system-on-chip (SoC). For example, a mobile phone device 1002, a laptop computer device 1004, a stationary terminal device 1006, a wearable device 1008, or a motor vehicle 1010 may include device 1000 as described herein. Device 1000 can be, for example, any of the devices and / or integrated circuit (IC) packages described herein. Devices 1002, 1004, 1006, and 1008, and vehicle 1010 shown in Figure 10 are merely examples. Device 1000 may also feature a group of devices (e.g., electronic devices) including, but not limited to, mobile devices, handheld personal communication systems (PCS) units, portable data units such as personal information terminals, global positioning system (GPS) devices, navigation devices, set-top boxes, music players, video players, entertainment units, meter reading devices, communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in automobiles (e.g., autonomous vehicles), or any other devices that store or take in data or computer instructions, or any combination thereof.

[0058] Implementation examples will be described in the following numbered embodiments.

[0059] Embodiment 1. A substrate comprising: a core having an upper plane and an inner plane; a cavity extending into the inner plane of the core, at least partially penetrating the upper plane of the core; an electronic component mounted within the cavity, the electronic component including an upper plane having one or more electronic component terminals, the electronic component being supported by the inner plane of the core such that the upper plane of the electronic component is at the same height as the upper plane of the core; and an upper metallization structure configured to provide one or more conductive paths from one or more electronic component terminals to one or more upper metal terminals of the upper metallization structure.

[0060] Embodiment 2. The substrate according to Embodiment 1, wherein the cavity has a stepped cross-section.

[0061] Embodiment 3. The substrate according to Embodiment 1 or 2, further comprising an adhesive layer disposed between the internal plane of the core and the lower plane of an electronic component, wherein the adhesive layer has a thickness such that the upper plane of the electronic component is at the same height as the upper plane of the core.

[0062] Embodiment 4. A substrate according to any one of Embodiments 1 to 3, wherein an electronic component is at least partially surrounded by a filler material disposed in the region between the side wall of the core and the side wall of the electronic component.

[0063] Embodiment 5. The substrate according to Embodiment 4, wherein the filler material includes a dielectric material.

[0064] Embodiment 6. The substrate according to Embodiment 5, wherein the dielectric material of the filler includes the same dielectric material as one or more dielectric layers of the upper metallization structure.

[0065] Embodiment 7. A substrate according to any one of Embodiments 1 to 6, wherein the upper metal terminals of the upper metallization structure are further configured to provide electrical connections to an electronic package mounted on the substrate.

[0066] Embodiment 8. A substrate according to any one of Embodiments 1 to 7, comprising one or more conductive paths, a first patterned metallization layer disposed on the upper plane of a core, wherein the first patterned metallization layer is electrically connected to one or more electronic component terminals, and a plurality of further patterned metallization layers disposed through one or more dielectric layers, each containing metal vias configured to connect the first patterned metallization layer to upper metal terminals of an upper metallization structure.

[0067] Embodiment 9. A substrate according to any one of Embodiments 1 to 8, wherein the core has a thickness greater than approximately 760 micrometers.

[0068] Embodiment 10. A substrate according to any one of Embodiments 1 to 9, wherein the core has a thickness greater than approximately 820 micrometers.

[0069] Embodiment 11. A substrate according to any one of Embodiments 1 to 10, wherein the core has a thickness greater than approximately 1240 micrometers.

[0070] Embodiment 12. A substrate according to any one of Embodiments 1 to 11, wherein the core has a thickness greater than the height of the electronic components.

[0071] Embodiment 13. A substrate according to any one of Embodiments 1 to 12, wherein the upper metallization structure comprises one or more dielectric layers, each having a patterned metallization layer disposed on each of the dielectric layers.

[0072] Embodiment 14. A substrate according to any one of Embodiments 1 to 13, wherein the electronic component includes at least one deep trench capacitor.

[0073] Embodiment 15. An electronic device comprising a substrate, the substrate comprising: a core having an upper plane and an inner plane; a cavity extending at least partially through the upper plane of the core into the inner plane of the core; an electronic component within the cavity, the electronic component having an upper plane having one or more electronic component terminals, and the electronic component being supported by the inner plane of the core such that the upper plane of the electronic component is at the same height as the upper plane of the core; and an upper metallization structure configured to provide one or more conductive paths from one or more electronic component terminals to one or more upper metal terminals of the upper metallization structure.

[0074] Embodiment 16. The electronic device according to Embodiment 15, further comprising an electronic circuit package mounted on a substrate and electrically connected to one or more upper metal terminals of an upper metallization structure.

[0075] Embodiment 17. The electronic device according to Embodiment 15 or 16, wherein the electronic device includes at least one of the following: a music player, video player, entertainment unit, navigation device, communication device, mobile device, mobile phone, smartphone, personal digital assistant, stationary terminal, tablet computer, computer, wearable device, laptop computer, server, Internet of Things (IoT) device, or device in a motor vehicle.

[0076] Embodiment 18. A method for forming a substrate, comprising: forming a cavity extending from the upper plane of a core to the inner plane of a core; inserting an electronic component into the cavity such that the upper plane of the electronic component having one or more electronic component terminals is supported by the inner plane of the core, wherein the electronic component is supported by the inner plane of the core such that the upper plane of the electronic component is at the same height as the upper plane of the core; and forming an upper metallization structure on the upper plane of a core, wherein the upper metallization structure is configured to provide one or more conductive paths from one or more electronic component terminals to one or more upper metal terminals of the upper metallization structure.

[0077] Embodiment 19. The method according to Embodiment 18, further comprising forming the cavity to have a stepped cross-section.

[0078] Embodiment 20. The method according to Embodiment 18 or 19, further comprising forming an adhesive layer between the inner plane of the core and the lower plane of the electronic component, wherein the adhesive layer has a thickness such that the upper plane of the electronic component is at the same height as the upper plane of the core.

[0079] Embodiment 21. The method according to any one of Embodiments 18 to 20, further comprising forming a filler in the region between the side wall of the core and the side wall of the electronic component.

[0080] Embodiment 22. The method according to Embodiment 21, wherein the filler includes a dielectric material.

[0081] Embodiment 23. The method according to Embodiment 22, wherein the dielectric material of the filler includes the same dielectric material as one or more dielectric layers of the upper metallization structure.

[0082] Embodiment 24. The method according to any one of embodiments 18 to 23, wherein forming an upper metallization structure comprises configuring the upper metal terminals of the upper metallization structure for electrical connection to an electronic package.

[0083] Embodiment 25. The method according to any one of Embodiments 18 to 24, wherein forming an upper metallization structure includes forming a first patterned metallization layer on the upper plane of a core, wherein the first patterned metallization layer is electrically connected to one or more electronic component terminals; forming a plurality of further patterned metallization layers that form metal vias penetrating one or more dielectric layers; and connecting the first patterned metallization layer to the upper metal terminals of the upper metallization structure.

[0084] Embodiment 26. The method according to any one of Embodiments 18 to 25, wherein the core has a thickness greater than about 760 micrometers.

[0085] Embodiment 27. The method according to any one of Embodiments 18 to 26, wherein the core has a thickness greater than approximately 820 micrometers.

[0086] Embodiment 28. The method according to any one of Embodiments 18 to 27, wherein the core has a thickness greater than approximately 1240 micrometers.

[0087] Embodiment 29. The method according to any one of Embodiments 18 to 28, wherein the core has a thickness greater than the height of the electronic component.

[0088] Embodiment 30. The method according to any one of Embodiments 18 to 29, wherein the electronic component includes at least one deep trench capacitor.

[0089] It should be noted that the figures in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some cases, the figures may not be to exact scale. In some cases, not all components and / or parts may be shown for clarity. In some cases, the position, location, size, and / or shape of various parts and / or components in the figures may be illustrative. In some implementations, various components and / or parts in the figures may be optional.

[0090] The term “exemplary” is used herein to mean “to serve as an example, case, or illustration.” No implementation or aspect described herein as “exemplary” should necessarily be construed as being preferable or advantageous to any other aspect of the Disclosure. Similarly, the term “aspect” does not require that all aspects of the Disclosure include the features, advantages, or modes of operation described herein. The term “coupled” is used herein to mean a direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A is in physical contact with object B, and object B is in contact with object C, then objects A and C can still be considered coupled to each other, even though they are not in direct physical contact with each other. The term “electrically coupled” may mean that two objects are directly or indirectly coupled together so that an electric current (e.g., signal, power, ground) can propagate between them. Two electrically coupled objects may or may not transmit an electric current between them. The use of the terms “first,” “second,” “third,” and “fourth” (and / or above fourth) is arbitrary. Any of the components described may be the first, second, third, or fourth component. For example, a component referred to as the second component may also be the first, second, third, or fourth component. The term “encapsulating” means that one object may partially or completely encapsulate another object. The terms “top” and “bottom” are arbitrary. A component located at the top may be located on top of a component located at the bottom. A top component may be considered a bottom component, and vice versa.As described in this disclosure, a first component positioned "over" a second component may mean that the first component is positioned above or below the second component, depending on how the bottom or top is arbitrarily defined. In another example, the first component may be positioned on (e.g., above) a first surface of the second component, and the third component may be positioned on (e.g., below) a second surface of the second component, in which case the second surface is on the opposite side of the first surface. It should be further noted that, in the context of one component being positioned on another, the term “on” as used in this application may be used to mean a component that is on and / or inside another component (e.g., on the surface of the component or embedded within the component). Therefore, for example, a first component on a second component may mean (1) the first component is on the second component but does not directly contact the second component, (2) the first component is on the second component (e.g., on the surface of the second component), and / or (3) the first component is inside the second component (e.g., embedded within the second component). A first component located "in" a second component may be partially located within the second component or completely located within the second component. As used in this disclosure, the terms "about 'value X'" or "approximately value X" mean a range of 10 percent of "value X". For example, a value of "about 1" or "approximately 1" means a value in the range of 0.9 to 1.1.

[0091] In some implementations, an interconnect is an element or component of a device or package that enables or facilitates an electrical connection between two points, elements, and / or components. In some implementations, an interconnect may include traces, vias, pads, pillars, metallization layers, redistribution layers, and / or underbump metallization (UBM) layers / interconnects. In some implementations, an interconnect may include conductive material that can be configured to provide electrical paths for signals (e.g., data signals), ground, and / or power. An interconnect may include two or more elements or components. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metallization layers. An interconnect may be part of a circuit. Different implementations may use different processes and / or sequences to form an interconnect. In some implementations, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, spray coating, and / or plating processes can be used to form interconnects.

[0092] Furthermore, note that various disclosures contained herein may be described as processes shown as flowcharts, flow diagrams, structural diagrams, or block diagrams. While flowcharts can describe operations as sequential processes, many of these operations can also be performed in parallel or simultaneously. Moreover, the order of operations can be rearranged. A process terminates when its operations are completed.

[0093] In the detailed description above, it will be seen that in the examples, different features are grouped together. This manner of disclosure should not be understood as an intention that exemplary embodiments have more features than are explicitly stated within each embodiment. Rather, the various embodiments of this disclosure may contain fewer features than all the features of the individual exemplary embodiments disclosed. Accordingly, the following embodiments should be considered incorporated into the description, and each embodiment may be valid on its own as a distinct example. Each dependent embodiment may refer within the embodiment to a specific combination with one of the other embodiments, but the embodiments (singular or plural) of that dependent embodiment are not limited to that specific combination. It will be understood that other exemplary embodiments may also include combinations of dependent embodiments (singular or plural) with the subject matter of any other dependent embodiment or independent embodiment, or any combination of features with other dependent embodiments and independent embodiments. The various embodiments disclosed herein explicitly include certain combinations (e.g., contradictory embodiments such as defining an element as both an electrical insulator and an electrical conductor) unless it is explicitly stated or easily inferred that such combinations are not intended. Furthermore, even if an aspect is not directly dependent on an independent aspect, it is intended that aspects of that aspect may be included in any other independent aspect.

[0094] While the above disclosures represent exemplary aspects of the Disclosure, it should be noted that various changes and modifications can be made to this Specified without departing from the scope of the Disclosure as defined by the appended claims. The functions, steps, and / or actions of the method claims in the aspects of the Disclosure described herein do not need to be performed in any particular order. Furthermore, elements of the Disclosure may be described or claimed in the singular, but the plural is intended unless a limitation to the singular is explicitly stated. [Explanation of Symbols]

[0095] 400 circuit boards 402 Electronic Components 404 Lower plane 406 Upper plane 408 Electronic component terminals 410 cores 412 Lower plane 414 Upper plane 416 Cavity 418 Internal plane 420 Intermediate layer, adhesive layer 426 Patterned metallization layers 430 Upper metallization structure 432 Upper metal terminal 434 Dielectric layer 436 Patterned metallization layers

Claims

1. It is a substrate, A core having an upper plane, A cavity extending into the internal plane of the core, at least partially penetrating the upper plane of the core, An electronic component mounted within the cavity, wherein the electronic component includes an upper plane having one or more electronic component terminals, and the electronic component is supported by the internal plane of the core such that the upper plane of the electronic component is at the same height as the upper plane of the core, An upper metallization structure, configured to provide one or more conductive paths from one or more electronic component terminals to one or more upper metal terminals of the upper metallization structure, A substrate comprising the above.

2. The substrate according to claim 1, wherein the cavity has a stepped cross-section.

3. The substrate according to claim 1, further comprising an adhesive layer disposed between the internal plane of the core and the lower plane of the electronic component, wherein the adhesive layer has a thickness such that the upper plane of the electronic component is at the same height as the upper plane of the core.

4. The substrate according to claim 1, wherein the electronic component is at least partially surrounded by a filler material disposed in the region between the side wall of the core and the side wall of the electronic component.

5. The substrate according to claim 4, wherein the filler material includes a dielectric material.

6. The substrate according to claim 5, wherein the dielectric material of the filler includes the same dielectric material as one or more dielectric layers of the upper metallization structure.

7. The substrate according to claim 1, wherein the upper metal terminals of the upper metallization structure are further configured to provide electrical connections to an electronic package mounted on the substrate.

8. The one or more conductive paths described above are A first patterned metallization layer disposed on the upper plane of the core, wherein the first patterned metallization layer is electrically connected to one or more electronic component terminals, and A plurality of further patterned metallization layers, each comprising metal vias disposed through one or more dielectric layers and configured to bond the first patterned metallization layer to the upper metal terminal of the upper metallization structure, A substrate according to claim 1, including the above.

9. The substrate according to claim 1, wherein the core has a thickness greater than approximately 760 micrometers.

10. The substrate according to claim 1, wherein the core has a thickness greater than approximately 820 micrometers.

11. The substrate according to claim 1, wherein the core has a thickness greater than approximately 1240 micrometers.

12. The substrate according to claim 1, wherein the core has a thickness greater than the height of the electronic component.

13. The substrate according to claim 1, wherein the upper metallization structure includes one or more dielectric layers, each having a patterned metallization layer disposed on each of the one or more dielectric layers.

14. The substrate according to claim 1, wherein the electronic component includes at least one deep trench capacitor.

15. It is a substrate, A core having an upper plane, A cavity extending into the internal plane of the core, at least partially penetrating the upper plane of the core, An electronic component in the cavity, wherein the electronic component includes an upper plane having one or more electronic component terminals, and the electronic component is supported by the internal plane of the core such that the upper plane of the electronic component is at the same height as the upper plane of the core, An upper metallization structure, configured to provide one or more conductive paths from one or more electronic component terminals to one or more upper metal terminals of the upper metallization structure, An electronic device comprising a substrate.

16. The electronic device according to claim 15, further comprising an electronic circuit package mounted on the substrate and electrically connected to one or more upper metal terminals of the upper metallization structure.

17. The aforementioned electronic device The electronic device according to claim 15, comprising at least one of the following: a music player, video player, entertainment unit, navigation device, communication device, mobile device, mobile phone, smartphone, personal digital assistant, stationary terminal, tablet computer, computer, wearable device, laptop computer, server, Internet of Things (IoT) device, or device in a motor vehicle.

18. A method for forming a substrate, To form a cavity extending from the upper plane of the core to the inner plane of the core, Inserting an electronic component into the cavity such that the upper plane of the electronic component having one or more electronic component terminals is supported by the internal plane of the core, wherein the electronic component is inserted such that the upper plane of the electronic component is at the same height as the upper plane of the core, and is supported by the internal plane of the core. The upper metallization structure is formed on the upper plane of the core, wherein the upper metallization structure is configured to provide one or more conductive paths from one or more electronic component terminals to one or more upper metal terminals of the upper metallization structure. Methods that include...

19. The method according to claim 18, further comprising forming the cavity to have a stepped cross-section.

20. The method according to claim 18, further comprising forming an adhesive layer between the inner plane of the core and the lower plane of the electronic component, wherein the adhesive layer has a thickness such that the upper plane of the electronic component is at the same height as the upper plane of the core.

21. The method according to claim 18, further comprising forming a filler in the region between the side wall of the core and the side wall of the electronic component.

22. The method according to claim 21, wherein the filler includes a dielectric material.

23. The method according to claim 22, wherein the dielectric material of the filler includes the same dielectric material as one or more dielectric layers of the upper metallization structure.

24. Forming the aforementioned upper metallization structure The method according to claim 18, further comprising configuring the upper metal terminals of the upper metallization structure for electrical connection to an electronic package.

25. Forming the aforementioned upper metallization structure Forming a first patterned metallization layer on the upper plane of the core, wherein the first patterned metallization layer is electrically connected to one or more electronic component terminals. Forming multiple further patterned metallization layers that form metal vias penetrating one or more dielectric layers, and Connecting the first patterned metallization layer to the upper metal terminal of the upper metallization structure, The method according to claim 18, including the method described in claim 18.

26. The method according to claim 18, wherein the core has a thickness greater than about 760 micrometers.

27. The method according to claim 18, wherein the core has a thickness greater than about 820 micrometers.

28. The method according to claim 18, wherein the core has a thickness greater than about 1240 micrometers.

29. The method according to claim 18, wherein the core has a thickness greater than the height of the electronic component.

30. The method according to claim 18, wherein the electronic component includes at least one deep trench capacitor.

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