Defect classification of processed wafers

Abstract

A method and apparatus for training a machine learning model for automatic defect detection and classification of at least a portion of a processed wafer includes: receiving labeled images having defect classification types and features for several portions of a post-processed wafer; creating a first training set containing the received labeled images; training a machine learning model using the first training set to automatically classify the wafer portions based on at least one detected defect in each wafer portion; receiving labeled wafer profiles containing respective downstream yield data; creating a second training set containing the labeled wafer profiles; and training a machine learning model using the second training set to automatically determine the respective downstream yield of the wafer based on each wafer profile. The machine learning model can be applied to at least one unlabeled wafer image to determine at least one defect classification for at least one portion of the wafer.

Description

Technical Field

[0001] Embodiments of the present principle generally relate to classifying defects on a wafer, and more particularly to automatic defect detection and classification of at least a portion of a processed wafer using machine learning techniques.

Background Art

[0002] Wafer defects can be caused by the processes by which the wafer is manipulated. Currently, many manual processes exist for detecting and classifying wafer defects. For example, confocal scanning ultrasonic microscopy (cSAM) is a rapid non-destructive analysis technique that uses ultrasound to detect changes in acoustic impedance in integrated circuits (ICs) and other similar materials. The cSam technique can be used, for example, to manually detect defects within a wafer after a hybrid bonding process.

[0003] Manual cSAM defect classification and other such manual defect classification processes are redundant and may not provide an accurate correlation to downstream bonding performance.

[0004] There is a need for a process to automate the detection and classification of post-process wafer defects that occur on a wafer by various processes associated with wafer processing, such as hybrid bonding of the wafer, that accurately and efficiently correlate to downstream bonding performance.

Summary of the Invention

[0005] Methods and apparatuses for automatic defect detection and classification of at least a portion of a processed wafer are provided herein.

[0006] In some embodiments, a method for training a machine learning (ML) model for automated defect detection and classification of at least a portion of a processed wafer includes: receiving labeled images having multiple defect classification types and their respective features for at least a portion of a post-processed wafer; creating a first training set containing the received labeled images having multiple defect classification types and their respective features for those portions of the wafer; training the machine learning model to automatically classify the wafer portions based on at least one detected defect in each wafer portion, using the first training set in a first step; receiving labeled wafer profiles having respective downstream yield data; creating a second training set containing the labeled wafer profiles having respective downstream yield data; and training the machine learning model to automatically determine the respective downstream yield of the wafer based on each wafer profile, using the second training set.

[0007] In some embodiments, a method for automated defect detection and classification of at least a portion of a processed wafer using a trained machine learning (ML) model includes: receiving at least one unlabeled image of at least a portion of the processed wafer; processing at least a portion of the processed wafer to separate image pixels that depict image objects from image pixels that depict the image background; determining features for the image pixels that depict image objects; applying a trained ML model to the determined features for the image pixels that depict image objects, wherein the machine learning model has been trained using a first set of labeled images containing features associated with and identifying each wafer defect classification type; and using the trained machine learning model to determine a defect classification for at least one portion of at least one unlabeled wafer image.

[0008] In some embodiments, the method may further include determining a wafer profile for at least one wafer depicted in an unlabeled wafer image by compiling determined defect classification types for at least some of the portions of at least one portion of at least one unlabeled wafer image.

[0009] In some embodiments, the method may further include using a trained machine learning model to determine the downstream yield of at least one wafer depicted in an unlabeled image, the machine learning model being further trained with a second set of labeled wafer profiles having respective downstream yield data for the imaged wafers, so that the machine learning model can automatically determine the respective downstream yield of each wafer based on each determined wafer profile.

[0010] In some embodiments, the downstream yield of a wafer is determined based on the compilation of the conductivity of each pixel in at least that portion of the wafer.

[0011] In some embodiments, the method may further include determining from at least one determined wafer profile whether the wafer contains a fatal defect.

[0012] In some embodiments, an apparatus for training a machine learning (ML) model for automated defect detection and classification of at least a portion of a processed wafer includes a processor and memory. The memory stores at least one program, which, when executed by the processor, includes instructions causing the apparatus to perform a method, the method comprising: receiving labeled images having a plurality of defect classification types and their respective characteristics for at least a portion of a post-processed wafer; creating a first training set containing the received labeled images having a plurality of defect classification types and their respective characteristics for those portions of the wafer; in a first step, using the first training set, training a machine learning model to automatically classify the wafer portions based on at least one detected defect in each wafer portion; receiving labeled wafer profiles having respective downstream yield data; creating a second training set containing the labeled wafer profiles having respective downstream yield data; and using the second training set, training a machine learning model to automatically determine the respective downstream yield of the wafer based on the respective wafer profile.

[0013] In some embodiments, an apparatus for automated defect detection and classification of at least a portion of a processed wafer using a trained machine learning (ML) model includes a processor and memory. The memory stores at least one program which, when executed by the processor, includes instructions causing the apparatus to perform a method, the method comprising: receiving at least one unlabeled image of at least a portion of a processed wafer; processing at least a portion of the processed wafer to separate image pixels that depict image objects from image pixels that depict the image background; determining features for the image pixels that depict image objects; applying a trained ML model to the determined features for the image pixels that depict image objects, wherein the machine learning model has been trained using a first set of labeled images which include features associated with and identifying each wafer defect classification type; and using the trained machine learning model to determine a defect classification for at least one portion of at least one unlabeled wafer image.

[0014] In some embodiments, the method implemented by the apparatus further includes determining a wafer profile for at least one wafer depicted in an unlabeled wafer image by compiling determined defect classification types for at least some of the portions of at least one portion of at least one unlabeled wafer image.

[0015] In some embodiments, the method implemented by the apparatus further includes using a trained machine learning model to determine the downstream yield of at least one wafer depicted in an unlabeled image, the machine learning model being further trained using a second set of labeled wafer profiles having respective downstream yield data for the imaged wafers, to automatically determine the respective downstream yield of each wafer based on each determined wafer profile.

[0016] In some embodiments, the method performed by the apparatus further includes determining from at least one determined wafer profile whether the wafer contains a fatal defect.

[0017] Further embodiments of this disclosure are described below.

[0018] The embodiments of this disclosure, briefly summarized above and discussed in more detail below, can be understood by referring to the explanatory embodiments of this disclosure shown in the accompanying drawings. However, the accompanying drawings only show typical embodiments of this disclosure and should not be considered limiting in scope, as this disclosure may also permit other equally valid embodiments. [Brief explanation of the drawing]

[0019] [Figure 1] This is a high-level block diagram of a post-processing wafer defect detection and classification system according to one embodiment of this principle. [Figure 2] This is a graph of the functional architecture of an image processing module according to one embodiment of this principle. [Figure 3] This is a graph of the functional architecture of a feature extraction module according to one embodiment of this principle. [Figure 4] This is a graph of the functional architecture of the training and defect detection / classification module according to one embodiment of this principle. [Figure 5] This is a flowchart illustrating a method for training a machine learning model for the automatic classification of at least each portion of a post-processed wafer according to one embodiment of the present principle. [Figure 6] This is a flowchart illustrating a method for automatically classifying at least each portion of a post-processed wafer according to one embodiment of the present principle. [Figure 7] This is a high-level block diagram of a computing device suitable for use with an embodiment of a post-processing wafer defect detection and classification system according to one embodiment of the present principle. [Figure 8]FIG. 0 is a high-level block diagram of a network to which an embodiment of a post-processing wafer defect detection and classification system according to one embodiment can be applied. DETAILED DESCRIPTION OF THE INVENTION

[0020] For ease of understanding, wherever possible, the same reference numbers are used to refer to the same elements common to these figures. These figures are not drawn to scale and may be simplified for clarity. Without further recitation, elements and features of one embodiment may be beneficially incorporated in other embodiments.

[0021] The following detailed description describes techniques (e.g., methods, apparatuses, and systems) for automatically classifying at least respective portions of a wafer after various processes, such as a hybrid bonding process, have been applied to the wafer. In some embodiments, such techniques can include compiling at least some or all of the post-processed wafer portions to determine respective downstream device performance and yield (DPY) of the wafer. The concepts of the present principles are capable of various modifications and alternative forms, and specific embodiments thereof are shown by way of example in the drawings and will be described in detail below. It should be understood that there is no intention to limit the concepts of the present principles to the specific forms disclosed. On the contrary, the intention is to cover all modifications, equivalents, and alternatives consistent with the present principles and the appended claims. For example, embodiments of the present principles are described herein with respect to specific wafer defects and specific classification types / categories related to defects that may occur during a hybrid bonding process, but embodiments of the present principles can be applied to automatically detect substantially any wafer portion having defects occurring during substantially any process involving a wafer and classify it into substantially any classification type / category.

[0022] Throughout this disclosure, the terms learning model, machine learning (ML) model, ML algorithm, and ML classifier are used interchangeably to describe an ML process that can be trained to recognize / detect and distinguish various types of defects occurring on a wafer and classify those defects into categories. Additionally, throughout this disclosure, the terms classification and categorization, and any derivatives thereof, can be used interchangeably.

[0023] Embodiments of the present principles enable automatic defect detection and categorization of wafer portions after wafer processing, such as a bonding process. In some embodiments of the present principles, the AI / ML algorithms of the present principles are trained to identify defects and classify wafer portions based on the identified defects, using, for example, the cSAM technique. In some embodiments, the AI / ML algorithms of the present principles can be further trained to provide cSAM defect classification types and to provide correlations to downstream device performance and yield (DPY) based on the detected defects and classified wafer portions.

[0024] FIG. 1 shows a high-level block diagram of a post-processing wafer defect detection and classification system 100 according to an embodiment of the present principles. In the embodiment of FIG. 1, the post-processing wafer defect detection and classification system 100 includes, illustratively, an image processing module 110, a feature extraction module 115, and a training and defect detection / classification module 120. In the embodiment of FIG. 1, the training and defect detection / classification module 120 includes a learning model 122 (described in more detail below). The post-processing wafer defect detection and classification system 100 of FIG. 1 further includes, illustratively, an optional memory device 130.

[0025] As shown in FIG. 1, embodiments of the post-processing wafer defect detection and classification system of the present principles, such as the post-processing wafer defect detection and classification system 100, can be implemented via a computing device 700 (described in more detail below) according to the present principles.

[0026] In the post-processing wafer defect detection and classification system 100 of Figure 1, the training and defect detection / classification module 120 can receive data including labeled images and their respective features of at least several portions of a processed wafer. The labeled images and their respective features identify to the training model 122 categories of wafer sections that may contain defects, such as wafer defects after bonding, and such categories may include, but are not limited to, at least several defect categories, including good quality, voids, or delamination. In some embodiments, labeled image data can be received / retrieved from an optional storage device 130. Alternatively, or in addition, the training and defect detection / classification module 120 can receive labeled image data and associated features from a user of a post-processing wafer defect detection and classification system of this principle, such as the post-processing wafer defect detection and classification system 100 of Figure 1. The training model 122 can be trained using the labeled image data and features received by the training and defect detection / classification module 120. For example, in some embodiments, the training data received by the training and defect detection / classification module 120 may include labeled cSAM images and associated features of wafer sections having each defect category, as well as associated features for each wafer section. The training and defect detection / classification module 120 uses the received training data (e.g., labeled cSAMs) to train the learning model 122 to recognize / detect and distinguish various types of defects that occur on the wafer after processing, and to classify those wafer sections into categories including, but not limited to, good quality, voids, or delamination.

[0027] In some embodiments, the learning model / algorithm of this principle, such as learning model / algorithm 122, may include a multilayer neural network containing nodes trained to have specific weights and biases. In some embodiments, the learning model / algorithm 122 uses artificial intelligence or machine learning techniques to analyze received data images containing wafer defects in at least a portion of the processed wafer. In some embodiments of this principle, a suitable machine learning technique can be applied to learn commonalities in sequential application programs, and from the machine learning technique, it can be determined to what level the sequential application programs can be standardized. In some embodiments, machine learning techniques that can be applied to learn commonalities in sequential application programs may include, but are not limited to, regression methods, ensemble methods, or neural networks and deep learning, such as "Seq2Seq" regressive neural networks (RNNs) / long-term memory (LSTM) networks, convolutional neural networks (CNNs), and graph neural networks applied to abstract syntax trees corresponding to sequential program applications. In some embodiments, but are not limited to, supervised machine learning (ML) classifiers / algorithms such as multilayer perceptrons, random forests, naive Bayes, support vector machines, and logistic regression may also be used. In addition, in some embodiments, the ML classifier / algorithm of this principle can analyze the data by implementing at least one of the following techniques: sliding window or sequence-based techniques.

[0028] As described above, the learning model / algorithm 122 can be trained using multiple instances (e.g., hundreds, thousands, etc.) of labeled image data, the training data including multiple labeled images of post-processed wafer portions and their respective features, and the learning model / algorithm of this principle can be trained to recognize / detect and distinguish various types of defects in at least a portion of the wafer and classify those portions into categories.

[0029] In some embodiments, in a second stage, a learning model / algorithm of the present principle, such as the learning model / algorithm 122 in Figure 1, can be trained to provide a correlation with downstream device performance and yield (DPY) based on detected defects and classified wafer portions. That is, in some embodiments, the learning model 122 can be trained using multiple instances (e.g., hundreds, thousands, etc.) of the generated labeled wafer maps (described in more detail below), where the wafer maps are correlated with the final throughput and / or efficiency of each wafer, and the learning model / algorithm of the present principle can be trained to provide a correlation between the generated wafer maps and downstream device performance and yield (DPY). In some embodiments, the learning model of the present principle can be trained to recognize fatal failures in a processed wafer, for example, using the wafer maps.

[0030] After training a learning model of the present principle, such as the learning model 122 of the training and defect detection / classification module 120 in Figure 1, a post-processing wafer defect detection and classification system of the present principle, such as the post-processing wafer defect detection and classification system 100 in Figure 1, can be used to detect defects and classify sections of the post-processed wafer into categories, including, but not limited to, good products, voids, or delamination, using the received wafer image. For example, referring again to Figure 1, the image processing module 110 of the post-processing wafer defect detection and classification system 100 can receive an image of the post-processed wafer. As described above, in some embodiments, such an image may include a cSAM image of the processed wafer. According to the present principle, the image processing module 110 processes the received image to prepare an image of the processed wafer for classification.

[0031] For example, Figure 2 shows a graph 200 of the functional architecture of an image processing module of the present principle according to one embodiment. As shown in Figure 2, in some embodiments, an image processing module of the present principle, such as the image processing module 110 of a post-processing wafer defect detection and classification system 100, can apply a binarization process 204 to a received post-processed wafer image 202 to separate, for example, objects in the image data from background data. For example, in some embodiments, each pixel of the received post-processed wafer image 202 can be labeled as a background pixel or an image object pixel.

[0032] Next, an image processing module based on this principle, such as the image processing module 110 in Figure 1, can apply a contour detection process 208 to the segmented image 206 to detect, for example, the boundaries of image objects in each pixel and localize the image objects in the received post-processed wafer image. Then, the image processing module based on this principle can apply a patching process 212 to the contoured image segment 210 to index the value of each pixel.

[0033] In the embodiments of Figure 2 described above and in the following description, at least a portion of the wafer is divided into pixels, and the processing technique is described as being applied to each pixel of several portions of the wafer depicted in the wafer image. Alternatively, or in addition, in some embodiments, pixels can be combined to represent dies in at least a portion of the wafer. In such embodiments, dies in at least that portion of the wafer can be identified using the technique described in at least the embodiment of Figure 2. Thus, in some embodiments of the principle described throughout this disclosure, a process / referencing a pixel described as being applied to a pixel can be applied to / referencing pixels combined to represent dies of the wafer. For example, in some embodiments, as described in the following disclosure, the electrical efficiency / conductivity of specific dies (not pixels) in at least several portions of the wafer can be determined based on each identified defect of the die (not pixels), and thus the downstream yield of the wafer can be determined based on a compilation (i.e., wafer profile / map) of the electrical efficiency / conductivity of each die (not pixels) in at least a portion of the wafer.

[0034] The indexed patches generated from the post-processed wafer images received by the image processing module of this principle can be communicated to feature extraction modules of this principle, such as the feature extraction module 115 of the post-processed wafer defect detection and classification system 100 in Figure 1. The feature extraction modules of this principle apply feature extraction techniques to the indexed patches to reduce the amount of abstract / redundant data from the data of the indexed patches, enabling model construction with less mechanical effort and helping to increase the speed of the learning and generalization steps in the machine learning process applied to the features extracted by the training and defect detection / classification modules of this principle, such as the training and defect detection / classification module 120 of the post-processed wafer defect detection and classification system 100 in Figure 1.

[0035] For example, Figure 3 shows a graph 300 of the functional architecture of a feature extraction module of the present principle according to one embodiment. In the embodiment of Figure 3, a feature extraction module of the present principle, such as the feature extraction module 115 of Figure 1, applies a local binary pattern feature extraction technique 304 to a patch image 302 received from an image processing module of the present principle, such as the image processing module 110 of the post-processing wafer defect detection and classification system 100 of Figure 1, to determine a feature vector 306 from the received patch image 302. For example, in some embodiments, the local binary pattern feature extraction technique 304 analyzes the texture of the defect image, and the defect class may vary based on the luminosity effect, and the feature representation of the image can use this correlation to capture key defect class information. The texture operator labels the pixels of the image by thresholding the neighborhood of each pixel, and the result can be considered as a binary number, which is a weighted sum of powers of 2. The resulting final normalized histogram information of the image can be used as a feature vector.

[0036] The determined feature vector 306 can be communicated to a training and defect detection / classification module of the present principle, such as the training and defect detection / classification module 120 of the post-processing wafer defect detection and classification system 100 in Figure 1. For example, Figure 4 shows a graph 400 of the functional architecture of a training and defect detection / classification module of the present principle according to one embodiment. In the embodiment of Figure 4, a training and defect detection / classification module of the present principle, such as the training and defect detection / classification module 120 of the post-processing wafer defect detection and classification system 100 in Figure 1, receives the feature vector 402 determined by the feature extraction module of the present principle and uses the learning model 122 to classify the feature vector into at least the delamination category 404, the void category 406, and the good product category 408.

[0037] Using the techniques described above, a post-processing wafer defect detection and classification system of this principle, such as the post-processing wafer defect detection and classification system 100 in Figure 1, can determine a profile (e.g., wafer map) of the image of a post-processed wafer by compiling at least some of the classified wafer sections. Using the determined wafer profile having at least some or all of the classified portions of the image of the post-processed wafer, the defect detection / classification module 120 of the post-processing wafer defect detection and classification system 100 can use the learned model 122 to determine the final throughput and / or efficiency of each post-processed wafer. That is, as described above, in at least some embodiments, the learned model 122 can be trained using multiple instances (e.g., hundreds, thousands, etc.) of the generated labeled wafer maps, where the wafer maps are correlated with the final throughput and / or efficiency of each wafer, and the learned model / algorithm of this principle can be trained to provide a correlation between the generated wafer maps and downstream device performance and yield (DPY). Similarly, according to embodiments of the principle, a learning model of the principle can be trained to determine whether multiple classified defects on a wafer that exceed a determined threshold are fatal, and whether a wafer having a certain number of classified defects should be discarded or removed from the wafer processing system.

[0038] Figure 5 shows a flowchart of method 500 for training a machine learning model for automated defect detection and classification of at least a portion of a processed wafer according to one embodiment of the present principle. The method can begin at 502, during which labeled images and features of the post-processed wafer portion having multiple defect classification types are received. Method 500 can then proceed to 504.

[0039] In step 504, a first training set is created containing received labeled images of wafer portions having multiple defect classification types and their respective features. Method 500 can then proceed to step 506.

[0040] In 506, in the first stage, a machine learning model is trained using the first training set to automatically classify wafer portions based on at least one detected defect in each wafer portion. Method 500 can then proceed to 508.

[0041] In step 508, labeled wafer profiles / maps containing the respective downstream yield data are received. Method 500 can then proceed to step 510.

[0042] In step 510, a second training set is created containing the received wafer profiles / maps, each with downstream yield data. Method 500 can then proceed to step 512.

[0043] In step 512, a machine learning model is trained using a second training set to automatically determine the respective downstream yield of each wafer based on its respective wafer profile. Method 500 can then be exited.

[0044] Figure 6 shows a flowchart of method 600 for automated defect detection and classification of at least a portion of a processed wafer using a trained machine learning model according to one embodiment of the present principle. The method can begin at 602, during which at least one unlabeled image of at least a portion of the processed wafer is received. Method 600 can then proceed to 604.

[0045] In 604, at least a portion of the processed wafer is processed to separate the image pixels that depict the image object from the image pixels that depict the image background. As described above, in some embodiments of this principle, instead of separating the processed wafer into pixels, the wafer can be separated into, for example, a group of pixels including at least one die on the wafer. Method 600 can proceed to 606.

[0046] In step 606, the features of the image pixels that depict the image object are determined (the features of the identified die can be determined). Method 600 can then proceed to step 608.

[0047] In 608, a machine learning model is applied to the determined features (dies) for image pixels that depict an image object, and the machine learning model is trained using a first set of labeled images that include features associated with and identifying each wafer defect classification type. Method 600 can proceed to 610.

[0048] In method 610, a trained machine learning model is used to determine the defect classification for at least one portion of at least one unlabeled wafer image. Method 600 can then be exited.

[0049] In some embodiments, this method 600 may further include using a trained machine learning model to determine the downstream yield of at least one wafer depicted in an unlabeled image, the machine learning model being further trained using a second set of labeled wafer profiles having respective downstream yield data for the imaged wafers, so that the machine learning model can automatically determine the respective downstream yield of each wafer based on each wafer profile.

[0050] As shown in Figure 1, embodiments of the post-processing wafer defect detection and classification system based on this principle, such as the post-processing wafer defect detection and classification system 100 in Figure 1, can be implemented using a computing device 700 based on this principle. That is, in some embodiments, the computing device 700 can be used to communicate wafer image data and other data to the post-processing wafer defect detection and classification system based on this principle, for example, via any input / output means associated with the computing device 700. The output device of the computing device 700, such as a display, printer, or any other form of output device, can be used to present the classification data and downstream yield data determined by the post-processing wafer defect detection and classification system based on this principle to the user.

[0051] For example, Figure 7 shows a high-level block diagram of a computing device 700 suitable for use with embodiments of post-processing wafer defect detection and classification systems based on this principle, such as the post-processing wafer defect detection and classification system 100 of Figure 1. In some embodiments, the computing device 700 can be configured to implement the method of this principle of processor-executable program instructions 722 (for example, program instructions executable by processor 710) in various embodiments.

[0052] In the embodiment shown in Figure 7, the computing device 700 includes one or more processors 710a to 710n coupled to system memory 720 via an input / output (I / O) interface 730. The computing device 700 further includes a network interface 740 coupled to the I / O interface 730, and one or more input / output devices 750 such as a cursor control device 760, a keyboard 770, and a display 780. In various embodiments, a user interface can be generated and displayed on the display 780. In some cases, the embodiment can be implemented using a single instance of the computing device 700, but in other embodiments, it is intended that multiple such systems, or multiple nodes constituting the computing device 700, can be configured to host different parts or instances of various embodiments. For example, in one embodiment, some elements can be implemented through one or more nodes of the computing device 700 that are separate from the nodes implementing other elements. In another example, multiple nodes can implement the computing device 700 in a distributed manner.

[0053] In different embodiments, the computing device 700 may be any of a variety of devices, including, but is not limited to, personal computer systems, desktop computers, laptops, notebooks, tablets, or netbook computers, mainframe computer systems, handheld computers, workstations, network computers, cameras, set-top boxes, mobile devices, consumer devices, video game consoles, handheld video game devices, application servers, storage devices, peripheral devices such as switches, modems, routers, or any type of computing or electronic device as a whole.

[0054] In various embodiments, the computing device 700 may be a uniprocessor system including one processor 710, or a multiprocessor system including several processors 710 (e.g., two, four, eight, or another preferred number). The processors 710 may be any preferred processor capable of executing instructions. For example, in various embodiments, the processors 710 may be general-purpose or embedded processors implementing any of various instruction set architectures (ISAs). In a multiprocessor system, each of the processors 710 may, but not necessarily, generally implement the same ISA.

[0055] The system memory 720 can be configured to store program instructions 722 and / or data 732 accessible by the processor 710. In various embodiments, the system memory 720 can be implemented using any suitable memory technology, such as static random access memory (SRAM), synchronous dynamic RAM (SDRAM), non-volatile / flash memory, or any other type of memory. In the embodiments shown, program instructions and data that implement any of the elements of the embodiments described above can be stored in the system memory 720. In other embodiments, program instructions and / or data can be received, transmitted, or stored on a different type of computer-accessible medium, or on a similar medium separate from the system memory 720 or the computing device 700.

[0056] In one embodiment, the I / O interface 730 can be configured to coordinate I / O traffic between the processor 710, the system memory 720, and any peripheral devices in the device, including the network interface 740 or other peripheral interfaces, such as the input / output device 750. In some embodiments, the I / O interface 730 can perform any necessary protocols, timing, or other data conversions to convert data signals from one component (e.g., the system memory 720) into a format suitable for use by another component (e.g., the processor 710). In some embodiments, the I / O interface 730 can include support for devices attached via various types of peripheral buses, such as variations of the Peripheral Interconnect (PCI) bus standard or the Universal Serial Bus (USB) standard. In some embodiments, the functionality of the I / O interface 730 can be divided into two or more separate components, such as a northbridge and a southbridge. Also, in some embodiments, some or all of the functionality of the I / O interface 730, such as the interface to the system memory 720, can be directly incorporated into the processor 710.

[0057] The network interface 740 can be configured to enable data exchange between the computing device 700 and other devices attached to a network (e.g., network 790), such as one or more external systems, or between nodes of the computing device 700. In various embodiments, network 790 may include, but is not limited to, one or more networks, including a local area network (LAN) (e.g., Ethernet or a corporate network), a wide area network (WAN) (e.g., the Internet), a wireless data network, any other electronic data network, or any combination thereof. In various embodiments, the network interface 740 may support communication via wired or wireless general-purpose data networks, such as any preferred type of Ethernet network, digital fiber optic communication networks, storage area networks, such as Fibre Channel SANs, or any other preferred type of network and / or protocol.

[0058] In some embodiments, the input / output device 750 may include one or more display terminals, keyboards, keypads, touchpads, scanning devices, voice or optical recognition devices, or any other devices suitable for data input or access by one or more computer systems. Multiple input / output devices 750 may reside in a computer system or be distributed across various nodes of the computing device 700. In some embodiments, similar input / output devices may be separate from the computing device 700 and may interact with one or more nodes of the computing device 700 via wired or wireless connections, for example, via a network interface 740.

[0059] Those skilled in the art will understand that the computing device 700 is merely illustrative and not intended to limit the scope of the embodiments. In particular, computer systems and devices may include any combination of hardware or software capable of performing the functions shown in various embodiments, including computers, network devices, internet equipment, PDAs, wireless telephones, pagers, and the like. The computing device 700 may also be connected to other devices not shown, or it may instead operate as a standalone system. In addition, in some embodiments, the functions provided by the shown components may be combined within fewer components or distributed within additional components. Similarly, in some embodiments, some functions of the shown components may not be provided, and / or other additional functions may be made available.

[0060] Computing device 700 can communicate with other computing devices based on various computer communication protocols, including Wi-Fi, Bluetooth, RTM (and / or other standards for exchanging data over short distances, including protocols using short-wavelength radio transmission), USB, Ethernet, cellular, and ultrasonic local area communication protocols. Computing device 700 may further include a web browser.

[0061] Although the computing device 700 is shown as a general-purpose computer, the computing device 700 may be programmed to perform various specialized control functions and configured to act as a specific computer specialized by this principle, and embodiments may be implemented in hardware, for example, as an application-specific integrated circuit (ASIC). Accordingly, the process steps described herein are intended to be broadly interpreted as being equivalently implemented by software, hardware, or a combination thereof.

[0062] Figure 8 shows a high-level block diagram of a network to which embodiments of the post-processing wafer defect detection and classification system of the present principle, such as the post-processing wafer defect detection and classification system 100 of Figure 1, can be applied. The network environment 800 in Figure 8 descriptively includes a user domain 802, which includes a user domain server / computing device 804. The network environment 800 in Figure 8 further includes a computer network 806 and a cloud environment 810, which includes a cloud server / computing device 812.

[0063] In the network environment 800 of Figure 8, a post-processing wafer defect detection and classification system based on this principle, such as the post-processing wafer defect detection and classification system of Figure 1, can be included in at least one of the user domain server / computing device 804, the computer network 806, and the cloud server / computing device 812. That is, in some embodiments, a user can use a local server / computing device (e.g., user domain server / computing device 804) to detect and classify defects on at least a portion of a wafer processed by this principle.

[0064] In some embodiments, a user can implement a system for detecting and classifying defects in at least a portion of processed wafers within a computer network 806 based on the present principle. Alternatively, or in addition, in some embodiments, a user can implement a system for detecting and classifying defects in at least a portion of processed wafers within a cloud server / computing device 812 in a cloud environment 810, and in some embodiments, for providing downstream yield data of processed wafers based on the present principle. For example, in some embodiments, it may be advantageous to implement the processing functions of the present principle within the cloud environment 810 in order to utilize the processing and storage capabilities of the cloud environment 810. In some embodiments of the present principle, a system for detecting and classifying defects in at least a portion of processed wafers can be located in one and / or more locations / servers / computers to perform all or some of the functions of the system based on the present principle described herein. For example, a post-processing wafer defect detection and classification system based on the present principle can be located in one or more of the user domain 802, the computer network environment 806, and the cloud environment 810 to detect and classify wafer defects by the present principle.

[0065] While various items are shown as being stored in memory or storage during use, it will be understood by those skilled in the art that, for the purposes of memory management and data integrity, these items or some parts thereof can be transferred between memory and other storage devices. Alternatively, in other embodiments, some or all of the software components may be executed in memory on another device and communicate with the computer system shown via intercomputer communication. Some or all of the system components or data structures may also be stored (for example, as instructions or structured data) on a computer-accessible medium or portable article so as to be read by a suitable drive, various examples of which have been described above. In some embodiments, instructions stored on a computer-accessible medium separately from the computing device 600 may be transmitted to the computing device 600 via a transmission medium or signal such as electrical, electromagnetic, or digital signals carried over a communication medium such as a network and / or wireless link. Various embodiments may further include receiving, transmitting, or storing instructions and / or data implemented in accordance with the above description on a computer-accessible medium or via a communication medium. Generally, computer-accessible media may include magnetic or optical media, such as disks or DVD / CD-ROMs; volatile or non-volatile media, such as RAM (e.g., SDRAM, DDR, RDRAM, SRAM, etc.); and storage or memory media such as ROM.

[0066] The methods and processes described herein can be implemented in various embodiments using software, hardware, or a combination thereof. In addition, the order of the methods can be changed, and various elements can be added, rearranged, combined, omitted, or otherwise modified. All examples described herein are presented non-limitingly. Various modifications and changes can be made, as will be apparent to those skilled in the art who are interested in this disclosure. Implementations by embodiment are described in the context of a particular embodiment. These embodiments are described as descriptive, not limiting. Many changes, modifications, additions, and improvements are possible. Thus, multiple things can be provided for a component described herein as a single thing. The boundaries between various components, operations, and data stores are arbitrary to some extent, and certain operations are shown in the context of a specific descriptive configuration. Other assignments of functions are also conceivable and may fall within the scope of the appended claims. Structures and functions presented as individual components in exemplary configurations may also be implemented as combined structures or components. The above and other changes, modifications, additions, and improvements may fall within the scope of embodiments defined in the appended claims.

[0067] The above description includes numerous specific details, examples, and scenarios to provide a more thorough understanding of the disclosure. However, it will be understood that embodiments of the disclosure can be implemented without such specific details. Furthermore, such examples and scenarios are provided for illustrative purposes only and are not intended to limit the disclosure in any way. Those skilled in the art should be able to implement the appropriate functions without unnecessary experimentation based on the descriptions provided.

[0068] References such as “one embodiment” in this specification indicate that the embodiments described may include certain features, structures, or characteristics, but not all embodiments necessarily include those features, structures, or characteristics. Such phrases do not necessarily refer to the same embodiment. Furthermore, when certain features, structures, or characteristics are described in relation to one embodiment, it is considered within the knowledge of those skilled in the art that they may affect such features, structures, or characteristics in relation to other embodiments, whether explicitly indicated or not.

[0069] Embodiments provided in this disclosure can be implemented in hardware, firmware, software, or any combination thereof. Embodiments can also be implemented as instructions stored using one or more machine-readable media that can be read and executed by one or more processors. The machine-readable media can include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computing device, or a “virtual machine” running on one or more computing devices). For example, the machine-readable media can include any preferred form of volatile or non-volatile memory.

[0070] The modules, data structures, etc., as defined herein are defined in this manner for the sake of facilitating discussion and are not intended to imply that any specific implementation details are required. For example, any of the modules and / or data structures described may be combined or divided into submodules, subprocesses, or other units of computer code or data, as may be required by a particular design or implementation.

[0071] In the drawings, specific arrangements or orders of schematic elements may be shown for the sake of clarity. However, such specific arrangements or orders of elements are not meant to imply that a particular order or sequence of operations, or separation of processes, is required in all embodiments. Generally, schematic elements used to represent instruction blocks or modules can be implemented using any preferred form of machine-readable instruction, each such instruction can be implemented using any preferred programming language, library, application programming interface (API), and / or other software development tools or frameworks. Similarly, schematic elements used to represent data or information can be implemented using any preferred electronic arrangement or data structure. Furthermore, in the drawings, some connections, relationships, or associations between elements may be simplified or omitted in order to avoid obscuring this disclosure.

[0072] While the above applies to embodiments of the present disclosure, other further embodiments of the present disclosure can be devised without departing from the fundamental scope of the present disclosure.

Claims

1. A method for training a machine learning (ML) model for automated defect detection and classification of at least a portion of a processed wafer, Receiving labeled images of multiple defect classification types and their respective characteristics for at least a portion of a post-processed wafer, Creating a first training set including the received labeled image having the plurality of defect classification types and their respective characteristics for the portion of the wafer, In the first stage, the machine learning model is trained using the first training set to automatically classify wafer portions based on at least one detected defect in each wafer portion. Receiving labeled wafer profiles with respective downstream yield data, Creating a second training set that includes the labeled wafer profile having the respective downstream yield data, A method comprising training the machine learning model to automatically determine the respective downstream yield of each wafer based on each wafer profile using the second training set.

2. The method according to claim 1, wherein the plurality of defect classification types include at least one of good product category, void category, or delamination category.

3. The method according to claim 1, wherein the ML model includes at least one of a convolutional neural network model or a recurrent neural network model.

4. A method for automated defect detection and classification of at least a portion of a processed wafer using a trained machine learning (ML) model as described in claim 1, Receiving at least one unlabeled image of at least a portion of the processed wafer, Processing at least a portion of the processed wafer to separate image pixels that depict image objects from image pixels that depict the image background, Determining the characteristics of the image pixels that depict the image object, The application involves applying the trained ML model to the features determined for the image pixels that depict the image object, wherein the machine learning model is trained using a first set of labeled images that include features associated with and identifying each wafer defect classification type. A method comprising using the trained machine learning model to determine the defect classification for at least one portion of the at least one unlabeled wafer image.

5. The method according to claim 4, further comprising determining a wafer profile for at least one wafer depicted in the unlabeled wafer image by compiling determined defect classification types for at least some of the portions of the at least one portion of the at least one wafer image.

6. The process further includes using the trained machine learning model to determine the downstream yield of at least one wafer depicted in the unlabeled image, wherein the machine learning model is further trained using a second set of labeled wafer profiles having respective downstream yield data for the imaged wafers, so that it can automatically determine the respective downstream yield of each wafer based on the determined wafer profile. The method according to claim 4 or 5.

7. The method according to claim 6, wherein the downstream yield of the wafer is determined based on the compilation of the conductivity of each of the pixels in at least the portion of the wafer.

8. Determining whether the wafer contains a fatal defect from the at least one determined wafer profile. The method according to any one of claims 4 to 7, further comprising:

9. The method according to any one of claims 4 to 8, wherein the wafer defect classification type includes at least one of the good product category, void category, or delamination category.

10. The method according to any one of claims 4 to 9, wherein the trained ML model includes at least one of a convolutional neural network model or a recurrent neural network model.

11. Apparatus for training a machine learning (ML) model for automated defect detection and classification of at least a portion of a processed wafer, Processor and The device comprises a memory storing at least one program, the at least one program including instructions that cause the device to perform a method when executed by the processor, and the method is Receiving labeled images of multiple defect classification types and their respective characteristics for at least a portion of a post-processed wafer, Creating a first training set including the received labeled image having the plurality of defect classification types and their respective characteristics for the portion of the wafer, In the first stage, the machine learning model is trained using the first training set to automatically classify wafer portions based on at least one detected defect in each wafer portion. Receiving labeled wafer profiles with respective downstream yield data, Creating a second training set that includes the labeled wafer profile having the respective downstream yield data, Apparatus comprising training the machine learning model to automatically determine the respective downstream yield of each wafer based on each wafer profile using the second training set described above.

12. The apparatus according to claim 11, wherein the plurality of defect classification types include at least one of good product category, void category, or delamination category.

13. The apparatus according to claim 12, wherein the ML model includes at least one of a convolutional neural network model or a recurrent neural network model.

14. An apparatus for automated defect detection and classification of at least a portion of a processed wafer using a trained machine learning (ML) model, Processor and The device comprises a memory storing at least one program, the at least one program including instructions that cause the device to perform a method when executed by the processor, and the method is Receiving at least one unlabeled image of at least a portion of the processed wafer, Processing at least a portion of the processed wafer to separate image pixels that depict image objects from image pixels that depict the image background, Determining the characteristics of the image pixels that depict the image object, The application involves applying the trained ML model to the features determined for the image pixels that depict the image object, wherein the machine learning model is trained using a first set of labeled images that include features associated with and identifying each wafer defect classification type. Apparatus comprising determining a defect classification for at least one portion of the at least one unlabeled wafer image using the trained machine learning model.

15. The apparatus according to claim 14, further comprising determining a wafer profile for at least one wafer depicted in the unlabeled wafer image by compiling determined defect classification types for at least some of the portions of the at least one portion of the at least one wafer image.

16. The process further includes using the trained machine learning model to determine the downstream yield of at least one wafer depicted in the unlabeled image, wherein the machine learning model is further trained using a second set of labeled wafer profiles having respective downstream yield data for the imaged wafers, so that it can automatically determine the respective downstream yield of each wafer based on the determined wafer profile. The apparatus according to claim 14 or 15.

17. The apparatus according to any one of claims 14 to 16, wherein the downstream yield of the wafer is determined based on the compilation of the conductivity of each of the pixels in at least the portion of the wafer.

18. Determining whether the wafer contains a fatal defect from the at least one determined wafer profile. The apparatus according to any one of claims 14 to 17, further comprising:

19. The apparatus according to any one of claims 14 to 18, wherein the wafer defect classification type includes at least one of the good product category, void category, or delamination category.

20. The apparatus according to any one of claims 14 to 19, wherein the trained ML model includes at least one of a convolutional neural network model or a recurrent neural network model.

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