High-speed tuning of radio frequency (RF) matched networks

Abstract

Some embodiments relate to tuning circuits. A tuning circuit generally includes a transformer having a first impedance, a second impedance coupled to the first impedance, a primary winding and a secondary winding magnetically coupled to the primary winding, wherein the primary winding is coupled to the control input of the tuning circuit, and a signal path coupled in parallel to the first impedance or the second impedance, wherein the secondary winding is part of the signal path coupled in parallel to the first impedance or the second impedance.

Description

Technical Field

[0001]

[0001] Embodiments of the present invention generally relate to systems and methods used in semiconductor device manufacturing. More specifically, embodiments of the present disclosure relate to a plasma processing system used to process a substrate.

Background Art

[0002] Description of Related Art

[0002] Ensuring the reliable manufacture of high aspect ratio features is one of the important technical challenges for next-generation semiconductor devices. One way to form high aspect ratio features is to use a plasma-assisted etching process (e.g., a reactive ion etching (RIE) plasma process) to form high aspect ratio openings in a material layer of a substrate (e.g., a dielectric layer). In a typical RIE plasma process, a plasma is formed within a processing chamber, and ions from the plasma are accelerated toward the substrate surface to form openings in a material layer disposed beneath a mask layer formed on the substrate surface.

[0003]

[0003] A typical RIE plasma processing chamber includes a radio frequency (RF) bias generator that supplies an RF voltage to a power electrode. In a capacitively coupled gas discharge, the plasma is generated by using an RF generator coupled to a power electrode disposed within an electrostatic chuck (ESC) assembly or another part of the processing chamber. Typically, an RF matching network (the "RF matcher") adjusts the RF waveform supplied from the RF generator to supply RF power to a 50Ω apparent load, minimize the reflected power, and maximize the power supply efficiency. If the impedance of the load does not properly match the impedance of the source (e.g., the RF generator), a portion of the RF waveform supplied in the forward direction can reflect back in the opposite direction along the same transmission line.

[0004]

[0004] In some plasma processes, a DC voltage pulse scheme is used to control the plasma sheath placed on the substrate being processed. During operation, the DC voltage pulse toggles the generated plasma sheath between a state containing a thick plasma sheath and a state where no plasma sheath is present. Typical DC pulsing techniques are configured to supply voltage pulses at frequencies above 100 kHz (e.g., 400 kHz). The toggling of the plasma sheath caused by the supplied DC pulsed voltage waveform results in the plasma load having different impedance values ​​over time. It has been found that the interaction between the RF waveform and the DC pulsed voltage waveform supplied simultaneously during plasma processing can result in significantly different plasma processing outcomes because the RF matching portion of the RF power supply system cannot adjust the RF matching point to account for the rapidly changing plasma load impedance values ​​over time.

[0005]

[0005] Conventional impedance matching components and matching processes cannot keep up with the rapid changes in the amplitude (magnitude) of the plasma load impedance, and therefore, RF matchers typically generate a fluctuating amount of RF power, which is undesirable high reflected RF power found in the harmonics of the driven RF frequency, 1) intermodulation distortion (IMD) of the RF signal, and 2) harmonics of the driven RF frequency. Intermodulation distortion resulting from the interaction between the RF pulsed voltage waveform and the DC pulsed voltage waveform causes at least the amplitude of the RF signal to change over time. Interaction or intermodulation between the RF pulsed voltage waveform and the DC pulsed voltage waveform creates additional undesirable waveform components at frequencies other than the harmonic frequencies (i.e., integer multiples) of the interacting signals, such as either the RF waveform or the DC pulsed waveform. Generating IMD components within the power supply system reduces the actual forward RF power supplied to the plasma load. Because differences in power supply configurations and power supply components are unavoidable in processing chambers, rapidly changing plasma load impedance values ​​in semiconductor manufacturing environments lead to undesirable differences in plasma processing results, whether in a single plasma processing chamber, multiple similarly configured processing chambers within a single processing system, or multiple similarly configured processing chambers within separate plasma processing systems. Furthermore, the generated IMD components are also not readily considered in most power supply systems due to the wide range of frequencies that can occur during plasma processing in the same or different processing chambers, thus causing unexpected fluctuations in the power actually supplied to the plasma load during plasma processing.

[0006]

[0006] Therefore, in the art, there is a need for a plasma processing device and a biasing method that can at least solve the problem outlined above. [Overview of the Initiative]

[0007]

[0007] Embodiments provided herein generally include apparatus, plasma processing systems, and methods for adjusting impedance tuning in high-frequency (RF) plasma processing systems for high-speed impedance matching.

[0008]

[0008] Some embodiments relate to tuning circuits. A tuning circuit generally includes a transformer having a first impedance, a second impedance coupled to the first impedance, a primary winding and a secondary winding magnetically coupled to the primary winding, wherein the primary winding is coupled to a control input for the tuning circuit, and a signal path coupled in parallel to the first impedance or the second impedance, wherein the secondary winding is part of the signal path coupled in parallel to the first impedance or the second impedance.

[0009]

[0009] Some embodiments relate to methods for processing a substrate in a plasma processing system. The method generally includes generating a control signal based on a pulse voltage (PV) waveform supplied to electrodes in a processing chamber and supplying the control signal to a primary winding of a transformer in a tuning circuit, wherein the transformer further includes a secondary winding magnetically coupled to the primary winding, and the tuning circuit includes a first impedance and a second impedance coupled to the first impedance, the secondary winding being part of a signal path coupled in parallel with the first impedance or the second impedance, and the primary winding being coupled to the control input of the tuning circuit.

[0010]

[0010] Some embodiments relate to apparatus for processing substrates in a plasma processing system. The apparatus generally includes a PV waveform generator configured to generate a PV waveform supplied to electrodes in a processing chamber; a tuning circuit including a transformer having a secondary winding magnetically coupled to a primary winding, which includes a first impedance and a second impedance coupled to the first impedance, the secondary winding being part of a signal path coupled in parallel with the first or second impedance; and a generator configured to generate a control signal based on the PV waveform and supply the control signal to the primary winding.

[0011]

[0011] To enable a detailed understanding of the above-described features of the Disclosure, a more specific description of the Disclosure, which has been briefly summarized above, can be obtained by referring to embodiments. Some of these embodiments are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings only show exemplary embodiments and should not be considered to limit the scope of the Disclosure, and other equally valid embodiments are also permissible. [Brief explanation of the drawing]

[0012] [Figure 1A] This is a schematic diagram of a plasma processing system according to a particular aspect of this disclosure. [Figure 1B] This is a schematic detailed cross-sectional view of a plasma processing system relating to a particular aspect of this disclosure. [Figure 2] The voltage waveform established on the substrate by the voltage waveform applied to the electrodes of the processing chamber according to a specific embodiment of this disclosure is shown. [Figure 3] This is a schematic diagram of a radio frequency (RF) matching network according to a specific embodiment of the present disclosure. [Figure 4] The graphs show the real part of the impedance associated with the processing chamber and the imaginary part of the impedance associated with the processing chamber. [Figure 5A]This is a schematic diagram of an active RF matching network according to a specific embodiment of the present disclosure. [Figure 5B] This is a schematic diagram of a tuning circuit according to a specific embodiment of the present disclosure. [Figure 6] This is a process flow diagram illustrating a method for processing a substrate in a plasma processing system according to a particular aspect of this disclosure. [Modes for carrying out the invention]

[0013]

[0020] For ease of understanding, the same reference numerals have been used to indicate identical elements common to the figures where possible. It is intended that elements and features of one embodiment can be advantageously incorporated into other embodiments without further description.

[0014]

[0021] Embodiments of this disclosure generally relate to systems used in semiconductor device manufacturing processes. More specifically, embodiments provided herein generally include apparatus and methods for impedance tuning in high-frequency (RF) plasma processing systems for high-speed impedance matching (e.g., matching the impedance of a plasma load to the impedance of an RF source such as an RF generator).

[0015]

[0022] In RF plasma processing systems, the plasma load impedance varies depending on the state of the plasma chamber. For example, a pulsed voltage (PV) waveform may be supplied to the chamber electrodes. The impedance associated with plasma formation within the chamber may vary depending on the state of the PV waveform (e.g., whether the waveform is in the sheath collapse stage or the ion current stage). While RF matching networks may typically be implemented to match individual impedances, conventional RF matching networks cannot match two or more individual impedances within a cycle of the PV waveform. Therefore, the impedance matching stage is incomplete, potentially leading to periodic reflected power spikes. These periodic reflected power spikes can cause unexpected fluctuations in the RF power supplied to the plasma load during plasma processing.

[0016]

[0023] The techniques described herein can be used to provide impedance matching in response to rapid impedance changes associated with plasma formation in a chamber. For example, rapid impedance changes occurring within a PV waveform cycle can be matched using a tuning circuit having a transformer driven by a generator based on the PV waveform. Thus, the tuning circuit can be matched to a high impedance state when the PV waveform generator is in an "off" stage (e.g., sheath collapse stage) and to a low impedance stage when the PV waveform generator is in an "on" stage (e.g., ion current stage). The techniques described herein offer several advantages. For example, the techniques provide a fast tuning speed to match impedance changes during PV waveform cycling, reduce reflected power, increase power supply efficiency, and increase etching rate.

[0017] Examples of plasma treatment systems

[0024] FIG. 1A is a schematic diagram of a plasma processing system. The plasma processing system 10 is configured for plasma-assisted etching processes such as reactive ion etching (RIE) plasma processing. The plasma processing apparatus 10 can also be used for other plasma-assisted processes such as plasma enhanced deposition processes (e.g., plasma-enhanced chemical vapor deposition (PECVD) process, plasma-enhanced physical vapor deposition (PEPVD) process, plasma-enhanced atomic layer deposition (PEALD) process, plasma processing process, plasma-based ion implantation process, or plasma doping (PLAD) process). In one configuration, as shown in FIG. 1A, the plasma processing system 10 is configured to form capacitively coupled plasma (CPP). However, in some embodiments, plasma may be alternately generated by an inductively coupled source disposed above the processing region of the plasma processing system 10.

[0018]

[0025] The plasma processing system 10 includes a processing chamber 100, a substrate support assembly 136, a gas supply system 182, a high DC voltage source 173, a radio frequency (RF) generator 171, and an RF matcher 172 (e.g., an RF impedance matching network). The chamber lid 123 includes one or more sidewalls and a chamber base, and the one or more sidewalls and the chamber base are configured to withstand the pressure and energy applied thereto while plasma 101 is generated within the processing space 129 of the processing chamber 100 during processing in a vacuum environment maintained therein.

[0019]

[0026] The gas supply system 182 coupled to the processing space 129 of the processing chamber 100 is configured to supply at least one processing gas from at least one gas processing source 119 to the processing space 129 of the processing chamber 100. The gas supply system 182 includes a processing gas source 119 and one or more gas inlets 128 disposed through the chamber lid 123. The gas inlets 128 are configured to supply one or more processing gases to the processing space 129 of the processing chamber 100.

[0020]

[0027] The processing chamber 100 includes an upper electrode (e.g., chamber lid 123) and a lower electrode (e.g., substrate support assembly 136) positioned within the processing space 129 of the processing chamber 100. The upper electrode and the lower electrode face each other. In one embodiment, the RF generator 171 is electrically coupled to the lower electrode. The RF generator 171 is configured to supply an RF signal for igniting and maintaining a plasma 101 between the upper electrode and the lower electrode. In some alternative configurations, the RF generator 171 may be electrically coupled to the upper electrode. For example, the RF generator 171 may supply RF source power to an RF base plate within the cathode assembly (e.g., within the substrate support assembly 136) for plasma generation, while the upper electrode is grounded. The center frequency of the RF source power can range from 13.56 MHz to a very high frequency band such as 60 MHz, 120 MHz, or 162 MHz. In some embodiments, the RF source power may also be supplied through the upper electrode. The RF source power can operate in continuous mode or pulse mode. The pulse frequency of the RF power can be from 100 to 10 kHz, and the duty cycle can range from 5% to 95%. The RF generator 171 has frequency tuning capabilities and can adjust its RF power frequency, for example, within a range of ±5% or ±10%. In some embodiments, the RF generator 171 switches the RF power frequency at a predetermined speed (e.g., 2 nanoseconds, 50 nanoseconds, etc.).

[0021]

[0028] The substrate support assembly 136 may be coupled to a high-voltage DC power source 173 that supplies a chucking voltage. The high-voltage DC power source 173 may be coupled to a filter assembly 178 positioned between the high-voltage DC power source 173 and the substrate support assembly 136.

[0022]

[0029] The filter assembly 178 is configured to electronically isolate the DC voltage source 173 during plasma processing. In one configuration, the static DV voltage is between approximately -5000V and approximately 5000V and is supplied using an electrical conductor (such as a coaxial power supply line). The filter assembly 178 may include multiple filtering components or a single common filter.

[0023]

[0030] The substrate support assembly 136 is coupled to a pulse voltage (PV) waveform generator 175 configured to supply PV to bias the substrate support assembly 136. The PV waveform generator 175 is coupled to a filter assembly 178. The filter assembly 178 is positioned between the PV waveform generator 175 and the substrate support assembly 136. The filter assembly 178 is configured to electronically isolate the PV waveform generator 175 during plasma processing.

[0024]

[0031] The substrate support assembly 136 is coupled to an RF generator 171 configured to supply an RF signal to the processing space 129 of the processing chamber 100. The RF generator 171 is electronically coupled to an RF matcher 172 located between the RF generator 171 and the processing space 129 of the processing chamber 100. For example, the RF matcher 172 is an electrical circuit used between the RF generator 171 and the plasma reactor (e.g., the processing space 129 of the processing chamber 100) to optimize power supply efficiency. One or more RF filters (e.g., within the RF matcher 172) are designed to allow only power within a selected frequency range and to isolate the RF power supplies from each other. In some cases, the bandwidth of the RF filters must be greater than the frequency tuning range of the RF generator 171.

[0025]

[0032] During plasma processing, the RF generator 171 supplies an RF signal to the substrate support assembly 136 via the RF matcher 172. For example, the RF signal is applied to a load (e.g., gas) in the processing space 129 of the processing chamber 100. If the impedance of the load does not properly match the impedance of the source (e.g., the RF generator 171), a portion of the waveform may be reflected back in the opposite direction. Therefore, to prevent substantial portions of the waveform from being reflected, it is necessary to find a matched impedance (e.g., a match point) by adjusting one or more components of the RF matcher 172 as the source and load impedances change.

[0026]

[0033] The RF matcher 172 is electrically coupled to the RF generator 171, the substrate support assembly 136, and the PV waveform generator 175. The RF matcher 172 is configured to receive synchronization signals from either or both of the RF generator 171 and the PV waveform generator 175.

[0027]

[0034] The RF generator 171 and the PV waveform generator 175 are directly coupled to the system controller 126, respectively. The system controller 126 synchronizes the generated RF signal and PV waveform.

[0028]

[0035] Voltage and current sensors may be placed at the input and / or output of the RF matcher 172 to measure impedance and other parameters. These sensors can be synchronized by determining their timing internally using an external transistor-to-transistor logic (TTL) synchronization signal from a high-performance waveform generator and / or RF generator, or using measured voltage and current data. For example, the output sensor 117 is configured to measure the impedance of the plasma processing chamber 100, and other characteristics such as voltage, current, harmonics, and phase. The input sensor 116 is configured to measure the impedance of the RF generator 171, and / or other characteristics such as voltage, current, harmonics, and phase. Based on either the synchronization signal or the characteristics of the plasma processing chamber 100, the RF matcher 172 can capture rapid impedance changes and optimize impedance matching.

[0029]

[0036] The PV waveform generator 175 is used to supply the PV waveform and / or a tuned voltage waveform, which is the sum of the harmonic frequencies associated with the waveform. The PV waveform generator 175 may output a synchronous TTL signal to the RF matcher 172. The voltage waveform is coupled to a bias electrode (e.g., bias electrode 104 shown in Figure 1B) via a filter assembly 178. A high DC voltage source 173 is applied to chuck the wafer during the process for thermal control. In some cases, a third electrode may be present at the edge of the cathode assembly for edge uniformity control.

[0030]

[0037] Figure 1B is a schematic detail cross-sectional view of the plasma processing system 10. As shown in Figure 1B, the plasma processing system 10 is configured to form a capacitively coupled plasma (CCP). However, in some embodiments, the plasma 101 may instead be generated by an inductively coupled source located above the processing area of ​​the plasma processing system 10. In this configuration, the coil may be located above the ceramic lid (e.g., vacuum boundary) of the plasma processing chamber 100.

[0031]

[0038] The plasma processing system 10 includes a processing chamber 100, a substrate support assembly 136, a gas supply system 182, a DC power system 183, an RF power system 189, and a system controller 126. The processing chamber 100 includes a chamber body 113 which includes a chamber lid 123, one or more side walls 122, and a chamber base 124. Collectively, the chamber lid 123, one or more side walls 122, and the chamber base 124 define the processing space 129 of the processing chamber 100. The one or more side walls 122 and the chamber base 124 are sized and shaped to form structural supports for the elements of the processing chamber 100 and include materials (such as aluminum, aluminum alloy, etc.) configured to withstand the pressure and additional energy applied to them while plasma 101 is generated in a vacuum environment maintained within the processing space 129 of the processing chamber 100 during processing. The substrate 103 is loaded into the processing space 129 of the processing chamber 100 through one of the openings (not shown) in the side wall 122 and removed from there. The opening is sealed by a slit valve (not shown) during the plasma processing of the substrate 103.

[0032]

[0039] The gas supply system 182, coupled to the processing space 129 of the processing chamber 100, includes a processing gas source 119 and a gas inlet 128 located through the chamber lid 123. The gas inlet 128 is configured to supply one or more processing gases from the processing gas source 119 to the processing space 129 of the processing chamber 100.

[0033]

[0040] As described above, the processing chamber 100 includes an upper electrode (e.g., a chamber lid 123) and a lower electrode (e.g., a substrate support assembly 136) located within the processing space 129 of the processing chamber 100. The upper and lower electrodes are positioned facing each other. As shown in Figure 1B, the RF generator 171 is electrically coupled to the lower electrode. The RF generator 171 is configured to supply an RF signal for igniting and maintaining the plasma 101 between the upper and lower electrodes. In some alternative configurations, the RF generator 171 may be electrically coupled to the upper electrode.

[0034]

[0041] The substrate support assembly 136 includes a substrate support 105, a substrate support base 107, an insulating plate 111, a grounding plate 112, a plurality of lift pins 186, one or more substrate potential sensing assemblies 184 (including, for example, a signal detection assembly 188), and a bias electrode 104. Each lift pin 186 is positioned through a through hole 185 formed in the substrate support assembly 136 and is used to facilitate the transfer of the substrate 103 between the substrate support 105 and the substrate receiving surface 105A. The substrate support 105 is formed of a dielectric material. The dielectric material may include bulk sintered ceramic materials, corrosion-resistant metal oxides (e.g., aluminum oxide (Al2O3), titanium oxide (TiO), yttrium oxide (Y2O3)), metal nitride materials (e.g., aluminum nitride (AIN), titanium nitride (TiN)), mixtures thereof, or combinations thereof.

[0035]

[0042] The substrate support base 107 is formed from a conductive material (e.g., aluminum, an aluminum alloy, or a stainless steel alloy). The substrate support base 107 is electrically insulated from the chamber base 124 by an insulating plate 111 and a grounding plate 112 interposed between the insulating plate 111 and the chamber base 124. The substrate support base 107 is configured to regulate the temperature of both the substrate support 105 and the substrate 103 placed on the substrate support 105 during substrate processing. The substrate support base 107 includes one or more cooling channels (not shown) located therein, which are fluidly coupled to and in fluid communication with a coolant source (not shown), such as a refrigerant source or substrate source having relatively high electrical resistance. The substrate support 105 includes a heater (not shown) for heating the substrate support 105 and the substrate 103 placed on the substrate support 105.

[0036]

[0043] The bias electrode 104 is embedded in the dielectric material of the substrate support 105. The bias electrode 104 is formed of one or more conductive components. The conductive components include mesh, foil, plate, or a combination thereof. The bias electrode 104 functions as a chuck electrode (i.e., an electrostatic chuck electrode) used to fix the substrate 103 to the substrate receiving surface 105A of the substrate support 105 (e.g., electrostatic chuck). A parallel plate-like structure is formed by the bias electrode 104 and a layer of dielectric material placed between the bias electrode 104 and the substrate receiving surface 105A. The dielectric material has an effective capacitance C between approximately 5 nF and approximately 50 nF. EThe dielectric material layer (e.g., aluminum nitride (AlN), aluminum oxide (Al2O3), etc.) may have a thickness of about 0.03 mm to about 5 mm, for example, between about 0.1 mm and about 3 mm, for example, between about 0.1 mm and about 1 mm, or even between about 0.1 mm and 0.5 mm. The bias electrode 104 is electrically coupled to a clamp network that supplies the chuck voltage. The clamp network includes a DC voltage source 173 (e.g., a high-voltage DC source) coupled to a filter 178A of a filter assembly 178 positioned between the DC voltage source 173 and the bias electrode 104. The filter 178A is a low-pass filter and is configured to prevent RF frequency and PV waveform signals provided by other bias components found within the processing chamber 100 from reaching the DC voltage source 173 during plasma processing. The static DV voltage is between about -5000V and about 5000V and is supplied using an electrical conductor (e.g., a coaxial power supply line 106). The bias electrode 104 can bias the substrate 103 to the plasma 101 using one or more of the PV bias schemes.

[0037]

[0044] The substrate support assembly 136 includes an edge control electrode 115. The edge control electrode 115 is formed from one or more conductive components. The conductive components include mesh, foil, plate, or a combination thereof. The edge control electrode 115 is positioned below the edge ring 114, surrounding the bias electrode 104, and / or at a certain distance from the center of the bias electrode 104. In the case of a processing chamber 100 configured to process a circular substrate, the edge control electrode 115 is annular in shape, made from a conductive material, and configured to surround at least a portion of the bias electrode 104. As shown in Figure 1B, the edge control electrode 115 is positioned within the region of the substrate support 105 and is biased by the use of a PV waveform generator 175. The edge control electrode 115 is biased using a different PV waveform generator than the one used for the bias electrode 104. The edge control electrode 115 is biased by splitting a portion of the signal supplied from the PV waveform generator 175 to the bias electrode 104.

[0038]

[0045] The DC power system 183 includes a DC voltage source 173, a PV waveform generator 175, and a current source 177. The RF power system 189 includes an RF waveform generator 171, an RF matching circuit 172, and an RF filter 174. As shown in Figure 1B, the power supply line 163 electrically connects the output of the RF generator 171 to the RF matching circuit 172, the RF filter 174, and the substrate support base 107. As described above, during plasma processing, the DC voltage source 173 supplies a constant chucking voltage, while the RF generator 171 supplies an RF signal to the processing area, and the PV waveform generator 175 establishes a PV waveform at the bias electrode 104. For example, a sufficient amount of RF power is applied to the RF bias voltage signal (also referred to herein as the RF waveform), and the RF waveform is supplied to the electrode (e.g., the substrate support base 107) to form plasma 101 in the processing space 129 of the processing chamber 100. The RF waveform has a frequency range between approximately 1 MHz and approximately 200 MHz, for example, between 2 MHz and 40 MHz.

[0039]

[0046] The DC power system 183 includes a filter assembly 178 for electrically isolating one or more of the components contained within the DC power system 183. Power supply line 160 electrically connects the output of the DC voltage source 173 to the filter assembly 178. Power supply line 161 electrically connects the output of the PV waveform generator 175 to the filter assembly 178. Power supply line 162 connects the output of the current source 177 to the filter assembly 178.

[0040]

[0047] The current source 177 is selectively coupled to the bias electrode 104 using a switch (not shown) located within the power supply line 162, allowing the current source 177 to supply a desired current to the bias electrode 104 during one or more stages (e.g., an ion current stage) of the voltage waveform generated by the PV waveform generator 175.

[0041]

[0048] The filter assembly 178 includes a number of separate filtering components (i.e., separate filters 178A to 178C) each electrically connected to the output node via the power supply line 164. The filter assembly 178 may include one common filter electrically coupled to the output node via the power supply line 164. The power supply lines 160 to 164 include conductors, including combinations of coaxial cables such as rigid coaxial cables and flexible coaxial cables connected in series, insulated high-voltage corona-resistant hookup wires, bare wires, metal rods, electrical connectors, and any combination of the above.

[0042]

[0049] The system controller 126, also referred to herein as the processing chamber controller, includes a central processing unit (CPU) 133, memory 134, and support circuitry 135. The system controller 126 is used to control the process sequence used to process the substrate 103. The CPU is a computer processor configured for use in an industrial environment to control the processing chamber and its associated subprocessors. The memory 134 described herein, which is generally non-volatile memory, may include random access memory, read-inline memory, a hard disk drive, or other suitable form of local or remote digital storage. The support circuitry 135 is connected to the CPU 133 and includes a cache, clock circuitry, input / output subsystems, power supply, etc., and combinations thereof. Software instructions (programs) and data may be coded and stored in the memory 134 to instruct the processor in the CPU 133. Software programs (or computer instructions) readable by the CPU 133 in the system controller 126 determine which tasks can be performed by the components in the plasma processing system 10.

[0043]

[0050] A program readable by the CPU 133 in the system controller 126, when executed by the CPU 133, includes code that performs tasks related to the plasma processing scheme described herein. The program may include instructions used to control various hardware and electrical components within the plasma processing system 10 for performing various process tasks and various process sequences used to perform the method described herein. The program includes instructions used to perform one or more of the steps described herein.

[0044]

[0051] Figure 2 shows two distinct voltage waveforms established on a substrate 103 placed on the substrate receiving surface 105A of the substrate support assembly 136 of the processing chamber 100 by supplying a PV waveform to the bias electrode 104 of the processing chamber 100. The first waveform (e.g., waveform 225) is an example of an uncompensated PV waveform established on the substrate 103 during plasma processing. The second waveform (e.g., waveform 230) is an example of a compensated PV waveform established on the substrate 103 by applying a negative slope waveform to the bias electrode 104 of the processing chamber 100 during the "ion current stage" portion of the PV waveform cycle using a current source 177. The compensated PV waveform can alternatively be established by applying a negative voltage ramp during the ion current stage of the PV waveform generated by the PV waveform generator 175.

[0045]

[0052] Waveforms 225 and 230 include two main stages, namely the ion current stage and the sheath collapse stage. Both portions of waveforms 225 and 230 (e.g., the ion current stage and the sheath collapse stage) can be established alternately and / or separately on the substrate 103 during plasma processing. At the start of the ion current stage, the supply of the negative portion (e.g., the ion current portion) of the PV waveform supplied to the bias electrode 104 by the PV waveform generator 175 causes a voltage drop on the substrate 103, creating a high-voltage sheath on the substrate 103. The high-voltage sheath allows plasma-generated positive ions to be accelerated toward the biased substrate 103 during the ion current stage, and thus, in the case of the RIE process, controls the amount and characteristics of the etching process that occurs on the surface of the substrate 103 during plasma processing. In some embodiments, it is desirable that the ion current stage includes a region of the PV waveform that achieves a voltage on the substrate 103 that is stable or minimally fluctuating throughout the stage, as shown in Figure 2 by waveform 230. It should be noted that significant fluctuations in the voltage established on the substrate 103 during the ion current stage, for example as indicated by the positive slope of waveform 225, undesirably cause fluctuations in the ion energy distribution (IED), resulting in the formation of undesirable characteristics of the etched features on the substrate 103 during the RIE process.

[0046]

[0053] The impedance of the plasma sheath changes depending on the supplied PV waveform voltage. The RF matcher 172 can sample the impedance at various processing stages using one or both of the synchronization signals and / or its internal sensors. In one embodiment, the synchronization signal or characteristic determined by the input sensor 116 or the output sensor 117 is used to trigger the RF matcher 172 to determine at least two different impedances at different processing stages. The RF matcher 172 then updates its matching point based on at least two different impedances.

[0047]

[0054] Figure 3 is a schematic diagram of the RF matcher 172. The RF matcher 172 includes a controller 302, an input sensor 116, an output sensor 117, a first RF filter 308, a second RF filter 310, a tuning circuit 312, an interlock 314, and a memory 316. The two RF filter circuits (e.g., the first RF filter 308 and the second RF filter 310) are located near both the input and output of the RF matcher 172. In some cases, only one RF filter may be used near the output of the RF matcher 172.

[0048]

[0055] The RF matcher 172 is connected to the RF generator 171 via a 50Ω transmission line. The RF generator 171 can supply power at frequencies between 100kHz and 200MHz. The RF generator 171 has frequency tuning capability and can adjust its RF power frequency within, for example, a range of ±5% or ±10%. The RF generator 171 transmits TTL signals directly to the input sensor 116 and output sensor 117 for rapid response and better synchronization. The RF matcher 172 is configured to receive the RF waveform from the RF generator 171, adjust the RF waveform to minimize reflected power and maximize power supply efficiency, and supply the adjusted RF waveform to the plasma chamber 100. Simultaneously, as described above, the PV waveform generator 175 is configured to provide the PV waveform to the processing chamber 100. Both the RF generator 171 and the PV waveform generator 175 are coupled to and synchronized by the controller 302.

[0049]

[0056] The controller 302 can work with various communication protocols, such as RS-232, RS-485, USB, Ethernet, or ECAT (Ethernet for Control Automation Technology). The controller 302 can function as a local EtherCAT master. Other components (e.g., input sensor 116, output sensor 117, motor) are EtherCAT slave devices controlled by the controller 302.

[0050]

[0057] The controller 302 may be coupled to the interlock 314, memory 316, tuning circuit 312, input sensor 116, output sensor 117, and system controller 126. The controller 302 includes a CPU. The controller 302 is configured to control the tuning circuit 312 to change the impedance parameters of the RF matcher 172. In one embodiment, the tuning circuit 312 is a T-network tuning circuit. In another example, the tuning circuit 312 is a Pi-network tuning circuit. In yet another example, the tuning circuit 312 is an L-network tuning circuit. The tuning circuit 312 may include one or more capacitors and inductors that can be adjusted by the controller 302 to change the impedance of the RF waveform supplied to the processing chamber 100.

[0051]

[0058] The system controller 126 can communicate with the RF matcher 172, the RF generator 171, and / or other chamber components. Controller 302 can communicate with the system controller 126 using EtherCAT. Controller 302 can perform master-slave conversion, which enables communication with the EtherCAT master of the system controller 126. Controller 302 receives requests from the system controller 126 and provides feedback. The system controller 126 also receives forward and reflected power information from the RF generator 171 and acquires data from all internal devices of the RF matcher 172. The RF generator 171 can also be controlled by the system controller 126 for cooperative and intelligent real-time control and tuning.

[0052]

[0059] Memory 316 may be programmed for long-term or short-term memory storage. The memory 316 described herein is generally non-volatile memory and may include random-access memory, read-only memory, hard disk drives, or other suitable forms of local or remote digital storage. Software instructions (programs) and data can be coded and stored in memory 316 to instruct the processor in controller 302. A software program (or computer instruction) readable by controller 302 determines which tasks are executable by the components in the plasma processing system 10. The program readable by controller 302 includes code, which, when executed, performs tasks relating to the plasma processing scheme described herein. The program may include instructions used to control the RF matcher 172 using the method described herein. The program includes instructions used to perform one or more of the steps described herein.

[0053]

[0060] Interlock 314 is implemented for safety purposes to control temperature switches, cable-in-place switches, and match-in-place switches, etc. Interlock 314 is released in the event of a failure, and an interlock signal is sent from the local microcontroller to both the user laptop and the system controller 126 to shut down the system.

[0054]

[0061] The RF matcher 172 may include a serial control port for algorithm uploading and external match control (e.g., by using external software and an application programming interface (API)). Automatic impedance tuning algorithms and preset variable capacitor positions are stored in memory 316. Sensor data and tuning algorithms can be accessed from an external user laptop, providing the RF matcher 172 with significant flexibility. Furthermore, advanced process-related control algorithms can be deployed in real time. The RF matcher 172 can operate fully autonomously, in cooperation with the system controller 126, or manually controlled by an external user laptop.

[0055]

[0062] The output sensor 117 may include a voltage sensor and / or current sensor configured to measure the impedance or characteristics of the plasma processing system 10 described above. The input sensor 116 may include a voltage sensor and / or current sensor configured to measure the characteristics of an RF waveform such as voltage, current, phase, or harmonics. In some cases, only one sensor may be used at the input of the RF matcher 172. Sensor readings can be used in feedback and feedforward algorithms for impedance matching.

[0056]

[0063] The output sensor 117 is configured to sample a first set of impedances of the plasma processing system 10 over a first period and report them to the controller 302. The output sensor 117 is also configured to sample a second set of impedances of the plasma processing system 10 over a second period and report them to the controller 302. The first period may begin after a first portion of the waveform pulse of the synchronization signal, or after a first delay that is internally triggered (i.e., measured) by a sensor that detects a change in the characteristics of the PV waveform or RF waveform. The second period may begin after a second delay that is triggered simultaneously with the first delay. The second delay is longer than the first delay.

[0057]

[0064] The controller 302 determines the first and second impedances and uses both sets of impedances to combine them into a combined impedance. The controller 302 then adjusts one or more capacitors in the tuning circuit 312 based on the combined impedance parameter to change the matching point of the RF matcher 172 so that the impedance of the generated RF waveform matches the impedance of the plasma processing system 100. The controller 302 then may further fine-tune the tuning circuit 312 based on the impedance of the RF waveform sampled by the input sensor 116, after adjusting the tuning circuit 312 based on the combined impedance parameter.

[0058] An exemplary technique for high-speed tuning of RF-matched networks

[0065] Conventional RF matching networks may use variable capacitors for impedance matching. The tuning of the variable capacitor within the RF matching network may not be fast enough to track impedance changes within a single PV waveform cycle. For example, an RF matching network may only be able to tune to one selected impedance. As a result, high reflected power can occur due to impedance mismatches in other impedance states during plasma processing. Furthermore, frequency tuning of an RF matching circuit may only be possible with respect to the imaginary part of the impedance (e.g., not the real part of the impedance).

[0059]

[0066] Specific embodiments of this disclosure relate to active RF matching and tuning techniques that provide high-speed impedance tuning. The tuning techniques described herein can provide impedance matching that can track changes in impedance during each cycle of a PV waveform (e.g., the PV waveform described with respect to Figure 2). Plasma impedance changes rapidly (e.g., on a microsecond scale) within a PV waveform cycle. Implementing an impedance matching network that can track impedance changes associated with the PV waveform via a high-speed impedance matching network results in reduced reflected power, improved power delivery efficiency, and faster etching rates.

[0060]

[0067] Figure 4 shows graph 400, which shows the real portion of the impedance associated with the processing chamber, and graph 450, which shows the imaginary portion of the impedance associated with the processing chamber. As shown, during stage 402 (e.g., related to the sheath collapse stage described with respect to Figure 2), the real impedance of the processing chamber may be Z2, as shown in Smith chart 410. During stage 404 (e.g., related to the ion current stage described with respect to Figure 2), the real impedance of the processing chamber may be Z1, which is lower than Z2. Similarly, the processing chamber may have different virtual impedances between stages 402 and 404, as shown in graph 450. Specific embodiments of this disclosure concern impedance matching and tuning techniques that enable impedance matching to track such changes in impedance, as shown by graphs 400 and 450.

[0061]

[0068] Figure 5A is a schematic diagram of an active RF matcher 572 (corresponding to, for example, an RF matcher 172) according to a particular embodiment of the present disclosure. As shown, the RF matcher 572 may include a tuning circuit 312. Figure 5B is a schematic diagram of the tuning circuit 312 according to a particular embodiment of the present disclosure. Some of the elements shown in Figure 5A are omitted from the schematic diagram shown in Figure 5B. As shown, the tuning circuit 312 may include a capacitive element 510 (labeled "VC1") coupled to a shunt between terminal 594 of the tuning circuit 312 and a reference potential node (e.g., electrical ground). The tuning circuit 312 also includes a capacitive element 514 (labeled "VC2") coupled between terminal 594 and terminal 596 (e.g., the output of the tuning circuit 312 or the input of the filter 310).

[0062]

[0069] In some embodiments of this disclosure, the signal path 590 may be coupled in parallel with the capacitive element 510. The signal path 590 may include the capacitive element 512. In some embodiments, the tuning circuit 312 may include a transformer having a primary winding 504 and a secondary winding 506. The secondary winding 506 may be part of the signal path 590 in parallel with the capacitive element 510. The capacitive element 512 and the secondary winding 506 may be coupled between terminal 594 and a reference potential node (e.g., electrical ground). For example, the first terminal of the secondary winding 506 may be coupled to the capacitive element 512, as shown, and the second terminal of the secondary winding 506 may be coupled to the reference potential node. In some embodiments, the capacitive element 508 may be coupled in parallel with the secondary winding 506.

[0063]

[0070] In some embodiments, the generator 502 shown in Figure 5A may generate a control signal for driving the primary winding 504. The control signal may be provided to a control input 592 of a tuning circuit 312 coupled to the terminals of the primary winding 504. By driving the primary winding 504, the generator 502 may modulate the transformer's flux based on the PV waveform. As will be described in more detail herein, the transformer's flux may be modulated using modulation of the frequency, amplitude, or phase of the control signal. By modulating the transformer's flux, it is possible to adjust the resonance associated with the secondary winding 506 and the capacitive element 508 and adjust the impedance associated with the signal path 590. As described, the signal path 590 may be in parallel with the capacitive element 510. Therefore, by adjusting the impedance of the signal path 590, it is possible to adjust the total impedance between terminal 594 and the reference potential node (e.g., associated with the signal path 590 in parallel with the capacitive element 510) and adjust the impedance matching to the actual portion of the chamber impedance.

[0064]

[0071] Although dual-generator implementations (including, for example, generators 171 and 502) are shown, the RF matching and tuning techniques described herein may also be implemented with a single generator. For example, generator 171 may be a dual-output generator, with one of the outputs driving the primary winding 504. In this case, generator 502 is not used, and the second output of generator 171 may be used to drive the primary winding 504.

[0065]

[0072] In some embodiments, the secondary winding 506 and the capacitive element 508 may have a resonant frequency which is the main RF frequency provided to the electrodes of the chamber 100 (e.g., the RF frequency of the signal generated by the generator 171). The resonance of the secondary winding and the capacitive element 508 may be controlled by the phase, amplitude, or frequency of the current across the primary winding 504 (e.g., driven by the generator 502) based on the PV waveform. For example, the generator 502 may receive a synchronization signal associated with the PV waveform. In some embodiments, as described in more detail herein, the synchronization signal may trigger a switch between settings of the generator 502. The synchronization signal may be received from the generator 171, a controller (e.g., controller 126), or a pulser (e.g., PV waveform generator 175). Based on the synchronization signal, the output of the generator 502 changes within the cycle of the PV waveform, resulting in a change in the flux of the transformer in the tuning circuit 312, tracking the impedance change as described.

[0066]

[0073] In some embodiments, the capacitive element 512 may have a fixed capacitance (or may be an adjustable capacitive element). In some cases, the tuning circuit may be implemented without the capacitive element 508 (depending on, for example, the impedance range and the specifications of the circuit design). The impedance of the signal path 590 may be modified to track the real portion of the chamber impedance as the impedance changes during the cycle of the PV waveform, as shown in Graph 400.

[0067]

[0074] In some embodiments, a similar architecture can be implemented in parallel with the capacitive element 514, as shown in Graph 450, facilitating tracking of the imaginary portion of the chamber impedance within the cycle of the PV waveform. For example, signal path 573 may be in parallel with the capacitive element 514. Signal path 573 may include a secondary winding of a transformer, similar to the architecture described with respect to signal path 590. The primary winding of the transformer for signal path 573 may be driven by a generator, such as generator 503, based on the PV waveform. Thus, the real and imaginary portions of the chamber impedance can be tuned separately. Tuning of the image portion of the chamber impedance can be performed in some embodiments using frequency tuning via generator 171.

[0068]

[0075] As described herein, the magnetic flux of a transformer can be adjusted using frequency control, phase control, or amplitude control. In other words, the generator 502 adjusts the magnetic flux by adjusting the frequency of the control signal used to drive the primary winding 504, adjusts the magnetic flux by adjusting the amplitude of the control signal used to drive the primary winding 504, or adjusts the phase (e.g., phase offset) of the control signal used to drive the primary winding 504 to obtain the magnetic flux (or any combination thereof).

[0069]

[0076] For amplitude control, the magnetic flux can be adjusted by adjusting the output power of the generator 502. That is, the generator 502 can output a control signal having a frequency associated with the pulser (e.g., PV waveform generator 175), where the amplitude of the signal is adjusted based on the PV waveform.

[0070]

[0077] In some embodiments, the frequency of the control signal generated by generator 502 may be the same as the signal generated by generator 171 (for example, both generators 171 and 502 may generate RF frequency signals). In this case, a phase control mode or an amplitude control mode may be used to change the magnetic flux of the transformer. In other words, the phase or amplitude of the control signal used to drive the primary winding 504 may be adjusted based on the state of the PV waveform at any given moment. In some cases, generator 502 can switch between two settings related to when the PV waveform is "off" (e.g., in the sheath collapse stage) or "on" (e.g., in the ion current stage). In some cases, the effective matched impedance is rapidly controlled by adjusting the amplitude of the current supplied in the control signal provided by generator 502 in order to adjust and track (e.g., trace) the impedance change within the cycle of the PV waveform.

[0071]

[0078] A particular embodiment provides a method for high-speed impedance tuning. First, the PV waveform may be on-stage (e.g., stage 404). The capacitances of the variable capacitive elements (e.g., capacitive elements 510, 514) of the tuning circuit 312 may be set to reduce (e.g., minimize) reflected power. The first setting may be applied to the generator 502 (e.g., to drive the primary winding 504 using frequency, phase, or amplitude control). The PV waveform may then transition off-stage (e.g., stage 402). The capacitances of the variable capacitive elements (e.g., capacitive elements 510, 514) of the tuning circuit 312 may be set to reduce (e.g., minimize) off-stage reflected power. Furthermore, a second setting may be applied to the generator 502 to reduce (e.g., minimize) off-stage reflected power. The second setting may be recorded (e.g., stored). In some embodiments, the adjustment of the capacitance of the tuning circuit 312 and the setting of the generator 502 may be repeated until a generator setting is identified that minimizes reflected power during both the on-stage and off-stage phases of the PV waveform. The identification of two settings related to the off-stage and on-stage impedance matching of the PV waveform is described for ease of understanding, but any number of settings can be identified and used during the cycle of the PV waveform. In some cases, the tuning circuit may continuously track impedance changes during the cycle of the PV waveform, as described herein.

[0072]

[0079] Once the generator settings are identified and stored, the synchronization signal can be used to trigger tuning of the RF matcher (for example, by generating a control signal to drive the primary winding 504). Tuning can be switched between the identified first and second settings, or impedance changes within the PV waveform cycle can be continuously tracked by adjusting the frequency, phase, or amplitude of the control signal between the first and second settings.

[0073]

[0080] In some embodiments of the present disclosure, a sensor 516 and an impedance matching circuit 518 may be coupled between a generator 502 and a primary winding 504 (for example, at a control input 592), as shown in Figures 5A and 5B. The sensor 516 may measure the impedance associated with driving the primary winding 504 and provide the impedance matching circuit 518 with an index of the measured impedance. The impedance matching circuit 518 can perform impedance matching based on the measured impedance and improve the efficiency associated with driving the primary winding 504 by reducing reflected power.

[0074]

[0081] Figure 6 is a process flow diagram showing a method 600 for processing a substrate in a plasma processing system according to a particular embodiment of the present disclosure. Method 600 can be performed by a plasma processing system, such as the plasma processing system described with respect to Figures 5A and 5B.

[0075]

[0082] In step 610, the plasma processing system generates a control signal (e.g., via the generator 502) based on a pulse voltage (PV) waveform (e.g., the PV waveform 230 described with respect to Figure 2). The PV waveform may be supplied to the electrodes of the processing chamber as described herein.

[0076]

[0083] In step 620, the plasma processing system provides a control signal to the primary winding (e.g., primary winding 504) of a transformer in a tuning circuit (e.g., tuning circuit 312). The transformer may also include a secondary winding (e.g., secondary winding 506) magnetically coupled to the primary winding. In some embodiments, the tuning circuit may include a first impedance (e.g., capacitive element 510) and a second impedance (e.g., capacitive element 514) coupled to the first impedance. The secondary winding may be part of a signal path (e.g., signal path 590) coupled in parallel with the first or second impedance. The primary winding may be coupled to a control input section (e.g., control input section 592) for the tuning circuit.

[0077]

[0084] In some embodiments, a signal path including a secondary winding may be coupled in parallel with a first impedance. The first impedance may be a first capacitive element coupled between a first terminal of the tuning circuit (e.g., terminal 594) and a reference potential node. The second impedance may include a second capacitive element coupled between a first terminal of the tuning circuit and a second terminal (e.g., terminal 596).

[0078]

[0085] In some embodiments, the plasma processing system may supply a pulse voltage (PV) waveform to electrodes placed within the plasma processing system via a pulse voltage (PV) waveform generator. In some embodiments, the plasma processing system receives one or more synchronization signals (e.g., at generator 502) indicating stage transitions related to the PV waveform. Control signals may be generated based on the synchronization signals. In some embodiments, the plasma processing system controls the amplitude, phase, or frequency of the control signals based on the PV waveform. Generating control signals may, in some embodiments, involve tracking impedance changes related to the processing chamber using a matched output sensor 117. Control signals may be generated based on the processing chamber being in a sheath collapse stage or an ion current stage.

[0079]

[0086] The above description applies to embodiments of the present disclosure, but other embodiments and further embodiments of the present disclosure may be devised without departing from the basic scope of the present disclosure, and the scope of the present disclosure is determined by the following claims.

Claims

1. A tuning circuit, The first impedance and, The second impedance coupled to the first impedance, A transformer having a primary winding and a secondary winding magnetically coupled to the primary winding, wherein the primary winding is coupled to a control input section for the tuning circuit, A signal path coupled in parallel with the first impedance or the second impedance, The secondary winding is part of the signal path, which is coupled in parallel with the first impedance or the second impedance. Tuning circuit.

2. The tuning circuit according to claim 1, wherein the signal path is coupled in parallel with the first impedance, and the first impedance is a first capacitive element coupled between the first terminal of the tuning circuit and a reference potential node.

3. The tuning circuit according to claim 2, wherein the second impedance includes a second capacitive element coupled between the first terminal and the second terminal of the tuning circuit.

4. The tuning circuit according to claim 2, wherein the signal path further includes a third impedance coupled between the first terminal of the tuning circuit and the reference potential node.

5. The tuning circuit according to claim 1, further comprising a third impedance coupled in parallel with the secondary winding.

6. The tuning circuit according to claim 5, wherein the third impedance includes a capacitive element.

7. A plasma processing system having a tuning circuit according to claim 1, further comprising a generator having an output section coupled to the control input section of the tuning circuit.

8. The aforementioned generator, A control signal is generated based on the pulse voltage (PV) waveform. The control signal is provided to the control input section of the tuning circuit. The plasma processing system according to claim 7, configured as described above.

9. The plasma processing system according to claim 8, further comprising supplying the PV waveform to an electrode located in the plasma chamber of the plasma processing system by a PV waveform generator.

10. The plasma processing system according to claim 8, wherein the generator is configured to receive one or more synchronization signals indicating stage transitions related to the PV waveform, and the control signal is generated based on the one or more synchronization signals.

11. The plasma processing system according to claim 8, wherein the generator is configured to control the amplitude, phase, or frequency of the control signal based on the PV waveform.

12. The plasma processing system according to claim 8, wherein the generator is configured to generate the control signal by tracking impedance changes related to the processing chamber.

13. The plasma processing system according to claim 8, wherein the generator is configured to generate the control signal based on the fact that the processing chamber is in a sheath collapse stage or an ion current stage.

14. The plasma processing system according to claim 7, further comprising an impedance matching circuit coupled between the primary winding of the transformer and the generator.

15. A method for processing a substrate within a plasma processing system, The process involves generating a control signal based on the pulse voltage (PV) waveform supplied to the electrodes of the processing chamber, The aforementioned control signal is provided to the control input section for the tuning circuit, The control input unit is coupled to the primary winding of the transformer of the tuning circuit, the transformer further includes a secondary winding magnetically coupled to the primary winding, the tuning circuit includes a first impedance and a second impedance coupled to the first impedance, and the secondary winding is part of a signal path coupled in parallel with the first impedance or the second impedance. method.

16. The method according to claim 15, wherein the signal path is coupled in parallel with the first impedance, and the first impedance is a first capacitive element coupled between the first terminal of the tuning circuit and a reference potential node.

17. The method according to claim 16, wherein the second impedance includes a second capacitive element coupled between the first terminal and the second terminal of the tuning circuit.

18. The method according to claim 15, further comprising receiving one or more synchronization signals indicating stage transitions related to the PV waveform, wherein the control signal is generated based on the one or more synchronization signals.

19. The method according to claim 15, wherein generating the control signal includes controlling the amplitude, phase, or frequency of the control signal based on the PV waveform.

20. The method according to claim 15, wherein generating the control signal includes tracking impedance changes related to the processing chamber.

21. The method according to claim 15, wherein the control signal is generated based on the processing chamber being in a sheath collapse stage or an ion current stage.

22. A device for processing substrates within a plasma processing system, A pulse voltage (PV) waveform generator configured to generate a PV waveform supplied to the electrodes of a processing chamber, A tuning circuit including a transformer having a secondary winding magnetically coupled to a primary winding, the transformer having a first impedance and a second impedance coupled to the first impedance, wherein the secondary winding is part of a signal path coupled in parallel with the first impedance or the second impedance, A generator configured to generate a control signal based on the PV waveform and to provide the control signal to the primary winding, A device equipped with the following features.

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