Multi-threshold voltage integration scheme for complementary field-effect transistors

Abstract

Methods for manufacturing electronic devices are described. Embodiments of this disclosure are advantageous in that they reduce thickness, reduce leakage, reduce heat balance, and V t Requirements (Multi-V t The present invention provides a method for manufacturing an electronic device, such as a complementary field-effect transistor (CFET), that satisfies the following conditions (including) and has improved device performance and reliability. Some embodiments of the method include conventional dipole engineering techniques such as a dipole-first process and / or a dipole-final process, but do not require the repair of the interface layer after processing (in the dipole-first process) or the repair of the high-dielectric constant dielectric layer after the annealing process (in the dipole-final process).

Description

[Technical Field]

[0001]

[0001] Embodiments of the present disclosure relate to the field of electronic device manufacturing, and more particularly to transistors. More specifically, embodiments of the present disclosure relate to complementary field-effect transistors (CFETs) and methods for manufacturing CFETs. [Background technology]

[0002]

[0002] Integrated circuits have evolved into complex devices that can house millions of transistors, capacitors, and resistors on a single chip. In the course of integrated circuit evolution, the functional density (i.e., the number of interconnected devices per chip area) has increased overall, while the shape dimensions (i.e., the smallest component (or line) that can be manufactured using the manufacturing process) have decreased.

[0003]

[0003] A transistor is a circuit component or circuit element that is often formed on a semiconductor device. Depending on the circuit design, many transistors can be formed on a semiconductor device in addition to capacitors, inductors, resistors, diodes, conductive lines, or other elements. Integrated circuits incorporate a planar field-effect transistor (FET) through which current flows in response to a voltage applied to a control gate, through a semiconductor channel between the source and drain.

[0004]

[0004] Since the drive current of a transistor, and therefore its speed, is proportional to the gate width of the transistor, faster transistors generally require larger gate widths. Therefore, there is a trade-off between transistor size and speed, and "fin" field-effect transistors (finFETs) have been developed to address the conflicting goals of maximum drive current and minimum size. FinFETs feature a fin-shaped channel region that allows for a significant increase in transistor size without significantly increasing the transistor's mounting area, and are now applied to many integrated circuits. However, FinFETs also have drawbacks.

[0005]

[0005] In order to improve circuit density and achieve higher performance, the characteristic size of transistor devices continues to shrink, and improvements in transistor device structure are needed to improve electrostatic coupling and reduce adverse effects such as parasitic capacitance and leakage current in the off state. Examples of transistor device structures include planar structures, finFET structures, and gate-all-around (GAA) structures. GAA device structures include several lattice-matched channels suspended in a stacked configuration and connected by source / drain regions. GAA structures provide good electrostatic control and can be widely used in complementary metal-oxide-semiconductor (CMOS) wafer manufacturing.

[0006]

[0006] An example of GAA technology is a complementary field-effect transistor (CFET), in which nFET and pFET nanowires / nanosheets are stacked vertically on top of each other. Compared to GAA transistors, CFET transistors have increased on-chip device density and reduced area consumption. When nFETs and pFETs are stacked monolithically, the n and p superlattices are continuously deposited in an intermediate sacrificial layer during processing and selectively removed and replaced by an intermediate dielectric insulating (MDI) layer. The intermediate dielectric insulating (MDI) layer serves to electrically isolate the lower level GAA from the upper level GAA.

[0007]

[0007] Each n or p superlattice of the CFET includes alternating layers of channel layers and release layers. The channel layers typically contain silicon (Si). The release layers typically contain silicon germanium (SiGe) with a low concentration of germanium (Ge). Regarding the etching contrast between the intermediate dielectric insulating (MDI) layer and the channel and release layers, the intermediate dielectric insulating (MDI) layer contains SiGe with a high concentration of Ge.

[0008]

[0008] The reduction of materials currently used as nFETs and pFETs is due to the threshold voltage (V t Changes in fundamental characteristics such as these have become a challenge. tThe tuning range is limited by variations in film thickness, further reducing the device size.

[0009]

[0009] There are also challenges associated with conventional dipole techniques. To achieve the desired dipole effect, the desired element is driven from the deposited film using spike annealing and removed after the drive-in. Spike annealing can cause an equivalent oxide thickness (EOT) penalty and a high heat balance because free oxygen atoms in the gate dielectric layer and overlapping dipole stacks diffuse downward and oxidize the underlying silicon layer.

[0010]

[0010] In addition, the desired threshold voltage V of the transistor t (or multiple threshold voltages (multi-V) t To achieve this, precise control of the amount of dipole species is crucial. Conventional dipole techniques include "dipole-first" and "dipole-last" processes. Typically, a dipole-first process involves depositing metal atoms on an interface layer (forming a treated interface layer) to achieve the desired dipole effect, followed by flowing a metal-containing precursor and reactants to deposit a high-dielectric-constant dielectric layer on the treated interface layer. Conventional dipole-first processes also include repairing the interface layer after processing.

[0011]

[0011] The dipole last process typically includes forming an interface layer on a substrate, forming a high-k dielectric layer on the interface layer, flowing a metal-containing precursor and reactant over the high-k dielectric layer to deposit metal atoms thereon, and annealing the substrate to drive the metal atoms into the interface of the interface layer and the high-k dielectric layer to achieve the desired dipole effect. In the dipole last process, instead of forming an ultrathin surface adsorption layer, an atomic layer deposition (ALD) process is performed, and a dipole layer having a thickness in the range of 3 Å to 20 Å and typically in the form of an oxide or nitride and containing metal atoms is deposited. A capping material is typically required on top of the binary oxide / nitride layer to avoid regrowth of silicon oxide during the annealing process. The conventional dipole last process also includes repairing the high-k dielectric layer after the annealing process.

[0012]

[0012] In the conventional dipole last process, multiple annealing steps are required to reach an increased V t , for example, the V t achieved by the conventional dipole first process is required. Also, particularly in the dipole first process, there are issues related to V t shift and leakage. Due to the increase in the on-chip device density and the reduction in area consumption of CFETs, it is more difficult to adjust V t in CFETs compared to GAA transistors.

[0013]

[0013] Therefore, there is a need for an improved method of manufacturing CFETs that meets the requirements of thickness reduction, leakage reduction, heat budget reduction, and V t (including multi-V t ) with a minimum EOT penalty.

Summary of the Invention

[0014]

[0014] One or more embodiments of the present disclosure relate to a method for forming a complementary field-effect transistor (CFET). The method includes depositing an interface layer on a vertically stacked superlattice structure on a semiconductor substrate. The vertically stacked superlattice structure comprises a first horizontal gate-all-around (hGAA) structure on the upper surface of the semiconductor substrate, an intermediate dielectric insulating (MDI) layer on the upper surface of the first hGAA structure, and a second hGAA structure on the upper surface of the intermediate dielectric insulating (MDI) layer. The interface layer is formed on the first hGAA structure, the intermediate dielectric insulating (MDI) layer, and the second hGAA structure. Next, the method includes depositing a high dielectric constant dielectric layer on an interface layer, depositing a first p-type dipole layer on the high dielectric constant dielectric layer, depositing a first p-type capping layer on the first p-type dipole layer, depositing a first protective layer on a first portion of a semiconductor substrate to protect a first portion of the first p-type capping layer, and etching a vertical stacked superlattice structure such that the first protective layer is removed from the first portion of the semiconductor substrate, and a portion of the first p-type capping layer and a portion of the first p-type dipole layer are removed from the second portion. The first portion has a first threshold voltage (V t ) has, and the second part is the second V tThe method comprises: etching a vertical stacked superlattice structure such that a first protective layer is removed from a first portion of a semiconductor substrate and a portion of a first p-type capping layer and a portion of a first p-type dipole layer are removed from a second portion; then depositing a second p-type dipole layer on the first portion and the second portion, wherein the second p-type dipole layer is formed on a first hGAA structure, an MDI layer and a second hGAA structure; depositing a second p-type capping layer on the second p-type dipole layer; and the first portion of the semiconductor substrate The first p-type dipole layer, the first p-type capping layer, the second p-type dipole layer, and the second p-type capping layer are deposited on the first and second portions to protect them, and the vertical stacked superlattice structure is etched so as to remove the second protective layer from the first and second portions of the semiconductor substrate, and remove a portion of the first p-type capping layer, a portion of the first p-type dipole layer, a portion of the second p-type capping layer, and a portion of the second p-type dipole layer from the third portion, and the first p-type capping layer, the first p-type dipole layer, the second p-type capping layer Etching the vertical stacked superlattice structure to remove the second p-type dipole layer and expose the high dielectric constant layer on the second hGAA structure; depositing the first n-type dipole layer on the exposed high dielectric constant layer on the second hGAA structure; depositing the first n-type capping layer on the first n-type dipole layer; depositing the third protective layer on the first portion of the semiconductor substrate to protect the first portion of the first n-type capping layer; removing the third protective layer from the first portion of the semiconductor substrate, and removing a portion of the first n-type capping layer from the second portion. Etching a vertical stacked superlattice structure to remove a portion of the first n-type dipole layer, depositing a second n-type dipole layer on the first and second portions, wherein the second n-type dipole layer is formed on a second hGAA structure, depositing a second n-type capping layer on the second n-type dipole layer, depositing a fourth protective layer on the first and second portions of the semiconductor substrate to protect the second n-type capping layer, and removing the fourth protective layer from the first and second portions of the semiconductor substrate.Furthermore, etching the vertical stacked superlattice structure so as to remove a portion of the first p-type capping layer, a portion of the first p-type dipole layer, a portion of the second p-type capping layer, a portion of the second p-type dipole layer, a portion of the first n-type capping layer, a portion of the first n-type dipole layer, a portion of the second n-type capping layer, and a portion of the second n-type dipole layer from the third portion, and the first p-type dipole layer, the second p-type dipole layer, the first n-type dipole layer, and the second n-type dipole layer This method includes annealing a semiconductor substrate at a temperature of 1000°C or less to drive atoms into a high-dielectric-constant dielectric layer and form an annealed high-dielectric-constant dielectric layer, and etching a vertical stacked superlattice structure to remove the first p-type dipole layer, the first p-type capping layer, the second p-type dipole layer, the second p-type capping layer, the first n-type dipole layer, the first n-type capping layer, the second n-type dipole layer, and the second p-type capping layer, respectively.

[0015]

[0015] To enable a more detailed understanding of the above-mentioned features of the Disclosure, a more detailed description of the Disclosure, which has been briefly summarized above, can be given by reference to embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings show only typical embodiments of the Disclosure, and therefore should not be considered to limit the scope of the Disclosure, as other equally valid embodiments may be permitted. Embodiments described herein are shown in the drawings as examples, not as limitations, and similar reference numerals indicate similar elements. [Brief explanation of the drawing]

[0016] [Figure 1A] A process flow diagram of a method for manufacturing a complementary field-effect transistor (CFET) according to one or more embodiments is shown. [Figure 1B] A schematic cross-sectional view of a vertically stacked superlattice structure on a semiconductor substrate according to one or more embodiments is shown. [Figure 2A]The image shows a bi-cross-sectional view of a vertically stacked superlattice structure on a semiconductor substrate, illustrating a first cross-sectional view through the gate (crossing the fins) and a second cross-sectional view through the fins (crossing the gates) according to one or more embodiments. [Figure 2B] Figure 2A shows two cross-sectional views of the semiconductor substrate after deposition of an interface layer on a vertically stacked superlattice structure and deposition of a high-dielectric-constant dielectric layer on the interface layer, according to one or more embodiments. [Figure 2C] Figure 2B shows two cross-sectional views of a semiconductor substrate after a first p-type dipole layer has been deposited on a high-dielectric-constant dielectric layer, according to one or more embodiments. [Figure 2D] Figure 2C shows two cross-sectional views of the semiconductor substrate after a first p-type capping layer has been deposited on a first p-type dipole layer, according to one or more embodiments. [Figure 2E] Figure 2D shows two cross-sectional views of a semiconductor substrate after a first protective layer has been deposited on a first portion of the semiconductor substrate, according to one or more embodiments. [Figure 2F] Figure 2E shows two cross-sectional views of a semiconductor substrate after etching a vertical stacked superlattice structure to remove a first protective layer from a first portion of the semiconductor substrate, according to one or more embodiments. [Figure 2G] Figure 2F shows two cross-sectional views of a semiconductor substrate after a second p-type dipole layer has been deposited on a first portion and a second portion of the semiconductor substrate according to one or more embodiments. [Figure 2H] Figure 2G shows two cross-sectional views of the semiconductor substrate after a second p-type capping layer has been deposited on a second p-type dipole layer, according to one or more embodiments. [Figure 2I] Figure 2H shows two cross-sectional views of a semiconductor substrate after a second protective layer has been deposited on a first and second portion of the semiconductor substrate, according to one or more embodiments. [Figure 2J] Figure 2I shows two cross-sectional views of the semiconductor substrate after etching a vertically stacked superlattice structure according to one or more embodiments to remove the second protective layer from the first and second portions. [Figure 2K] Figure 2J shows two cross-sectional views of the semiconductor substrate after a gap-filling process has been performed to fill the trench with a p-type dipole gap-filling material according to one or more embodiments. [Figure 2L] Figure 2K shows two cross-sectional views of a semiconductor substrate after etching the vertical stacked superlattice structure to remove the first p-type capping layer, the first p-type dipole layer, the second p-type capping layer, and the second p-type dipole layer according to one or more embodiments, in order to expose the high dielectric constant dielectric layer. [Figure 2M] Figure 2L shows two cross-sectional views of a semiconductor substrate after a first n-type dipole layer has been deposited on an exposed high-dielectric-constant dielectric layer, according to one or more embodiments. [Figure 2N] Figure 2M shows two cross-sectional views of a semiconductor substrate after a first n-type capping layer has been deposited on a first n-type dipole layer, according to one or more embodiments. [Figure 2O] Figure 2N shows two cross-sectional views of a semiconductor substrate after a third protective layer has been deposited on a first portion of the semiconductor substrate, according to one or more embodiments. [Figure 2P] Figure 2O shows two cross-sectional views of the semiconductor substrate after etching the vertical stacked superlattice structure to remove a third protective layer from a first portion of the semiconductor substrate, according to one or more embodiments. [Figure 2Q] Figure 2P shows two cross-sectional views of the semiconductor substrate after a second n-type dipole layer has been deposited on the first and second portions according to one or more embodiments. [Figure 2R] Figure 2Q shows two cross-sectional views of the semiconductor substrate after a second n-type capping layer has been deposited on a second n-type dipole layer, according to one or more embodiments. [Figure 2S] Figure 2R shows two cross-sectional views of the semiconductor substrate after a fourth protective layer has been deposited on a first portion and a second portion of the semiconductor substrate, according to one or more embodiments. [Figure 2T]Figure 2S shows two cross-sectional views of the semiconductor substrate after etching a vertical stacked superlattice structure according to one or more embodiments to remove a fourth protective layer from the first and second portions of the semiconductor, and then annealing to form an annealed high-dielectric-constant dielectric layer. [Figure 2U] Figure 2T shows two cross-sectional views of the semiconductor substrate after etching the vertical stacked superlattice structure to remove the first p-type dipole layer, the first p-type capping layer, the second p-type dipole layer, the second p-type capping layer, the first n-type dipole layer, the first n-type capping layer, the second n-type dipole layer, and the second p-type capping layer, according to one or more embodiments. [Modes for carrying out the invention]

[0017]

[0039] Before describing some exemplary embodiments of this disclosure, it should be understood that this disclosure is not limited to the configuration or process step details described below. Other embodiments of this disclosure are possible and can be practiced or implemented in various ways.

[0018]

[0040] As used in this book, the term "approximately" means roughly or nearly, and refers to a variation of no more than ±15% of a given number or range. For example, values ​​that differ by only ±14%, ±10%, ±5%, ±2%, or ±1% satisfy the definition of "approximately."

[0019]

[0041] As used herein and in the appended claims, the terms “substrate” or “wafer” refer to a surface or portion of a surface on which a process is performed. Furthermore, when a substrate is referred to, it will be understood by those skilled in the art that unless otherwise explicitly stated in the context, it may refer to only a portion of the substrate. In addition, when a deposition on a substrate is referred to, it may mean both a bare substrate and a substrate on which one or more films or features are deposited or formed.

[0020]

[0042] As used herein, “substrate” refers to any substrate or material surface formed on a substrate on which a film treatment is performed during a manufacturing process. For example, substrate surfaces on which treatment may be performed include, depending on the application, silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials. Substrates include, but are not limited to, semiconductor wafers. Substrates can be exposed to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate, anneal, and / or bake the substrate surface. In addition to film treatment directly on the surface of the substrate itself, any of the disclosed film treatment steps may be performed on an underlying layer formed on the substrate, as disclosed in more detail below. The term “substrate surface” is intended to include an underlying layer as indicated in the context. Therefore, for example, when a film / layer or a partial film / layer is deposited on the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0021]

[0043] The term "on" indicates direct contact between elements. The term "directly on" indicates direct contact between elements without an intervening element.

[0022]

[0044] As used herein and in the appended claims, terms such as “precursor,” “reactant,” and “reactive gas” are used interchangeably to refer to any gas species capable of reacting with the substrate surface.

[0023]

[0045] As used herein, “atomic layer deposition” or “periodic deposition” refers to the sequential exposure of two or more reactive compounds to deposit a layer of material on a substrate surface. The substrate or a portion of the substrate is exposed separately to two or more reactive compounds introduced into the reaction zone of a processing chamber. In a time-domain ALD process, exposure to each reactive compound is separated by a time delay, so that each compound can adhere to and / or react on the substrate surface and then be purged from the processing chamber. These reactive compounds are said to be sequentially exposed to the substrate. In a spatial ALD process, various portions of the substrate surface, or material on the substrate surface, are exposed simultaneously to two or more reactive compounds such that no given point on the substrate is substantially exposed to multiple reactive compounds at the same time. As used herein and in the appended claims, the term “substantially” as used in this respect means, as understood by those skilled in the art, that a small portion of the substrate may be exposed simultaneously by diffusion to multiple reactive gases, but simultaneous exposure is not intended.

[0024]

[0046] In one embodiment of time-domain ALD processing, a first reactive gas (i.e., a first precursor or compound A) is pulsed into the reaction zone, followed by a first time delay. Next, a second precursor or compound B is pulsed into the reaction zone, followed by a second delay. During each time delay, a purge gas, such as argon, is introduced into the processing chamber to purge the reaction area, or otherwise remove any residual reactive compounds or reactive byproducts from the reaction area. Alternatively, the purge gas may flow continuously throughout the entire deposition process so that only the purge gas flows during the time delays between pulses of the reactive compounds. The reactive compounds are pulsed alternately until a desired film or thickness is formed on the substrate surface. In either case, one cycle consists of compound A, purge gas, compound B, and the ALD processing with pulsed purge gas. A cycle can begin with either compound A or compound B, and each stage of the cycle may continue until a film of a predetermined thickness is achieved.

[0025]

[0047] One or more of the layers deposited on the substrate or the substrate surface are continuous. As used herein, the term “continuous” refers to a layer that covers the entire exposed surface without gaps or bare spots that expose the material beneath the deposited layer. A continuous layer may have gaps or bare spots having a surface area of ​​less than about 15% or less than 10% of the total surface area of ​​the layer.

[0026]

[0048] In an embodiment of the spatial ALD process, a first reactive gas and a second reactive gas (e.g., nitrogen gas) are supplied simultaneously to the reaction zone but separated by an inert gas curtain and / or a vacuum curtain. By moving the substrate relative to the gas supply device, any given point on the substrate is exposed to the first and second reactive gases.

[0027]

[0049] A transistor is a circuit component or element that is often formed on a semiconductor device. Depending on the circuit design, transistors may be formed on a semiconductor device in addition to capacitors, inductors, resistors, diodes, conductive wires, or other elements. Generally, a transistor includes a gate formed between a source region and a drain region. In one or more embodiments, the source and drain regions include doped regions of a substrate, such as a semiconductor substrate, exhibiting a doping profile suitable for a particular application. The gate is located above the channel region and includes a gate dielectric interposed between the gate electrode in the semiconductor substrate and the channel region.

[0028]

[0050] As used herein, the term “field-effect transistor” or “FET” refers to a transistor that uses an electric field to control the electrical behavior of a device. A field-effect transistor is a voltage-controlled device whose current-transmitting ability changes when an electric field is applied. Field-effect transistors generally exhibit very high input impedance at low temperatures. The conductivity between the drain and source terminals is controlled by the electric field within the device, which is generated by the voltage difference between the body and the gate of the device. The three terminals of an FET are the source (S) through which carriers enter the channel, the drain (D) through which carriers exit the channel, and the gate (G), which is the terminal that regulates the conductivity of the channel. Conventionally, the current entering the channel from the source (S) is I S The current entering the channel from the drain (D) is I D This is what is displayed. The voltage between the drain and source is V DS It is called a gate (G) and drain (i.e., I D The current entering the channel can be controlled by this.

[0029]

[0051] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are a type of field-effect transistor (FET) used in integrated circuits and high-speed switching applications. MOSFETs have an insulated gate, and the voltage applied to it determines the device's conductivity. This ability to change conductivity in response to the applied voltage is used to amplify or switch electronic signals. MOSFETs are based on the modulation of charge concentration by metal-oxide-semiconductor (MOS) capacitance between the body electrodes and the gate electrode, which is located above the body and insulated from all other device regions by the gate dielectric layer. Compared to MOS capacitors, MOSFETs include two additional terminals (source and drain), each connected to a separate, highly doped region separated by the body region. These regions can be p-type or n-type, but both are the same type and are the opposite type to the body region. The source and drain (unlike the body) are highly doped, and the doping type is followed by a "+" symbol.

[0030]

[0052] If the MOSFET is an n-channel or nMOS FET, the source and drain are n+ regions, and the body is a p-type substrate region. If the MOSFET is a p-channel or pMOS FET, the source and drain are p+ regions, and the body is an n-type substrate region. The source is so named because it is the source of charge carriers (electrons in the case of n-channels, and holes in the case of p-channels) flowing through the channel. Similarly, the drain is where charge carriers exit the channel.

[0031]

[0053] An nMOS FET consists of an n-type source / drain and a p-type substrate. When a voltage is applied to the gate, holes in the body (p-type substrate) are driven away from the gate. This allows for the formation of an n-type channel between the source and drain, and current is carried by electrons from the source to the drain through the induced n-type channel. Logic gates and other digital devices implemented using NMOS are said to have NMOS logic. NMOS has three operating modes called cutoff, triode, and saturation. Circuits with NMOS logic gates dissipate electrostatic force when the circuit is idling because DC current flows through the logic gate when the output is low.

[0032]

[0054] A pMOS FET consists of a p-type source and drain and an n-type substrate. When a positive voltage is applied between the source and gate (or a negative voltage between the gate and source), a p-type channel is formed between the source and drain with opposite polarity. Current is carried from the source to the drain by holes through the induced p-type channel. When the gate voltage is high, the PMOS does not conduct, and when the gate voltage is low, the PMOS conducts. Logic gates and other digital devices implemented using PMOS are said to have PMOS logic. PMOS technology is low-cost and has good noise immunity.

[0033]

[0055] In NMOS, the carriers are electrons, while in PMOS, the carriers are holes. When a high voltage is applied to the gate, NMOS conducts, but PMOS does not. Furthermore, when a low voltage is applied to the gate, NMOS does not conduct, but PMOS does. Because the electron carriers in NMOS move twice as fast as the hole carriers in PMOS, NMOS is considered faster than PMOS. However, PMOS devices are more resistant to noise than NMOS devices. In addition, NMOS can provide half the impedance offered by PMOS (with the same shape dimensions and operating conditions), so NMOS ICs will be smaller than PMOS ICs (providing the same functionality).

[0034]

[0056] As used herein, the term “Fin-field-effect transistor (FinFET)” refers to a substrate-built MOSFET transistor in which the gate is located on two, three, or four sides of the channel, or wrapped around the channel, forming a double-gate structure. FinFET devices are given the common name FinFET because the source / drain regions form “fins” on the substrate. FinFET devices have fast switching times and high current density.

[0035]

[0057] As used herein, the term “gate all around (GAA)” is used to refer to electronic devices such as transistors in which the gate material completely surrounds the channel region. The channel region of a GAA transistor may include nanowires or nanoslabs or nanosheets, rod-shaped channels, or other suitable channel configurations known to those skilled in the art. In one or more embodiments, the channel region of a GAA device has a plurality of vertically spaced horizontal nanowires or horizontal bars, making the GAA transistor a stacked horizontal gate all around (hGAA) transistor.

[0036]

[0058] As used herein, the term “complementary field-effect transistor (CFET)” refers to a transistor comprising NMOS FET devices and PMOS FET devices stacked together. Each of the NMOS FET and PMOS FET devices forming the CFET is a GAA transistor or an hGAA transistor.

[0037]

[0059] As used herein, the term "nanowire" refers to a nanometer (10⁻¹⁰) -9 This refers to nanostructures having a diameter in units of meters. Nanowires can also be defined as structures with a length-to-width ratio greater than 1000. Alternatively, nanowires can be defined as structures whose thickness or diameter is limited to tens of nanometers or less, but whose length is not limited. Nanowires are used in transistors and some laser applications, and in one or more embodiments, they are made of semiconductor materials, metallic materials, insulating materials, superconducting materials, or molecular materials. In one or more embodiments, nanowires are used in logic CPUs, GPUs, MPUs, and transistors for volatile (e.g., DRAM) and non-volatile (e.g., NAND) devices. As used herein, the term “nanosheet” refers to two-dimensional nanostructures having a thickness in the range of about 0.1 nm to about 1000 nm, or 0.5 nm to 500 nm, or 0.5 nm to 100 nm, or 1 nm to 500 nm, or 1 nm to 100 nm, or 1 nm to 50 nm.

[0038]

[0060] While not intended to be theoretically binding, relaxation in vertical stacked superlattice structures containing one or more hGAAs is thought to induce defects in the nanosheet channel layers within the structure. Embodiments of this disclosure advantageously provide transistors comprising a fully strained vertical stacked superlattice structure having defect-free or substantially defect-free nanosheet channel layers. In some embodiments, the presence of defects in the nanosheet channel layers is determined by reciprocal space mapping (RSM) methods. Without intending to be theoretically binding, RSM is an X-ray diffraction method that collects diffraction data of a vertical stacked superlattice structure in which the presence of defects may be observed. As used herein, the term “substantially defect-free” means that the nanosheet channel layers substantially do not contain defects as determined by RSM.

[0039]

[0061] Embodiments of the present disclosure are illustrated by diagrams showing devices (e.g., transistors) and processes for forming devices according to one or more embodiments of the present disclosure. The illustrated processes are merely illustrative examples of possible uses of the disclosed processes, and those skilled in the art will recognize that the disclosed processes are not limited to the applications shown.

[0040]

[0062] Embodiments of this disclosure generally relate to the field of electronic device manufacturing, and more particularly to transistors. More specifically, embodiments of this disclosure relate to CFETs and methods for manufacturing CFETs. While devices and processes are described using this context, those skilled in the art will recognize that the disclosed devices and processes are not limited to the illustrated applications.

[0041]

[0063] Figure 1A shows a process flow diagram of method 100 for manufacturing a CFET. Figures 2A to 2U show bidirectional cross-sectional views of an electronic device (e.g., a transistor such as a CFET 200) according to one or more embodiments. Method 100 shown in Figure 1A is spread across the two sheets in Figure 2. The CFET 200 shown in Figures 2A to 2U can be manufactured by Method 100 shown in Figure 1A.

[0042]

[0064] Figure 1B shows a schematic cross-sectional view of a CFET 200 having a vertically stacked superlattice structure 260 on a semiconductor substrate 202. The semiconductor substrate 202 has a top surface 203. The semiconductor substrate 202 can be any suitable substrate material. In one or more embodiments, the semiconductor substrate 202 includes semiconductor materials, such as silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium phosphate (InP), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), germanium (Ge), silicon germanium (SiGe), other semiconductor materials, or any combination thereof. In one or more embodiments, the semiconductor substrate includes one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), indium (In), phosphorus (P), or selenium (Se). While some examples of materials that can form the substrate 202 are described herein, any material that can serve as a basis on which passive and active electronic devices (e.g., transistors, memories, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic devices) can be constructed falls within the spirit and scope of this disclosure.

[0043]

[0065] In one or more embodiments, the semiconductor substrate 202 is a p-type or n-type substrate. In this specification, the term “n-type” refers to a semiconductor produced by doping an intrinsic semiconductor with an electron donor element during manufacturing. The term “n-type” derives from the negative charge of electrons. In n-type semiconductors, electrons are majority carriers and holes are minority carriers. In this specification, the term “p-type” refers to the positive charge of wells (or holes). In contrast to n-type semiconductors, p-type semiconductors have a hole concentration greater than the electron concentration. In p-type semiconductors, holes are majority carriers and electrons are minority carriers.

[0044]

[0066] In one or more embodiments, the vertically stacked superlattice structure 260 includes one or more horizontal gate-all-around (hGAA) structures 215, 255 on the substrate 202. In some embodiments, the vertically stacked superlattice structure 260 includes a first or lower horizontal gate-all-around (hGAA) structure 215 on the substrate 202. In some embodiments, the vertically stacked superlattice structure 260 includes a first or lower horizontal gate-all-around (hGAA) structure 215 on the upper surface 203 of the substrate 202. In some embodiments, the vertically stacked superlattice structure includes a second or upper horizontal gate-all-around (hGAA) structure 255. Although not intended to be bound to any particular operating theory, the first hGAA 215 or second hGAA 215 and the second hGAA 255 or second hGAA 255 may independently comprise the same structure having the same layers. In one or more illustrated embodiments, the vertically stacked superlattice structure 260 includes a first hGAA structure 215 on the upper surface 203 of the substrate 202, an intermediate dielectric insulating (MDI) layer 240 on the upper surface 225 of the first hGAA structure 215, and a second hGAA structure 255 on the upper surface 245 of the intermediate dielectric insulating (MDI) layer 240.

[0045]

[0067] In some embodiments, each of the first hGAA215 and the second hGAA255 includes alternating layers of nanosheet channel layers 230 and nanosheet release layers 220. In some embodiments, the multiple nanosheet release layers 220 and the multiple nanosheet channel layers 230 may include any number of lattice-matched material pairs suitable for forming a vertically stacked superlattice structure 260. In some embodiments, each of the first hGAA215 and the second hGAA255 has alternating layers of nanosheet channel layers 230 and nanosheet release layers 220 in numbers between one and five pairs.

[0046]

[0068] The nanosheet release layer 220 may have any suitable thickness. In one or more embodiments, each nanosheet release layer 220 has a thickness in the range of 5 nm to 15 nm. The nanosheet channel layer 230 may have any suitable thickness. In one or more embodiments, each nanosheet channel layer 230 has a thickness in the range of 5 nm to 15 nm.

[0047]

[0069] In some embodiments, each of the nanosheet channel layers 230 independently contains silicon (Si). In some embodiments, each of the nanosheet release layers 220 independently contains silicon germanium (SiGe).

[0048]

[0070] In one or more embodiments, an intermediate dielectric insulation (MDI) layer 240 is formed between a first or lower hGAA 215 and a second or upper hGAA 255. In one or more embodiments, the intermediate dielectric insulation (MDI) layer 240 is shown after selectively removing the intermediate sacrificial layer and replacing it with the intermediate dielectric insulation (MDI) layer 240.

[0049]

[0071] Selective removal of the sacrificial layer can be carried out by any suitable means known to those skilled in the art. In some embodiments, selective removal of the sacrificial layer includes an etching process that removes the sacrificial layer but not the nanosheet release layer 220. In some embodiments, the etching process includes one or more of a wet etching process or a dry etching process. In some embodiments, the etching process is directional etching.

[0050]

[0072] The intermediate dielectric insulating (MDI) layer 240 functions to electrically isolate the source / drain region of the lower level GAA from the source / drain region of the upper level GAA. In one or more embodiments, the intermediate dielectric insulating (MDI) layer 240 comprises silicon germanium (SiGe). In one or more embodiments, the intermediate dielectric insulating (MDI) layer 240 comprises silicon germanium (SiGe) having a higher concentration of germanium (Ge) than the SiGe in the nanosheet release layer 220.

[0051]

[0073] In one or more embodiments, the intermediate dielectric insulating (MDI) layer 240 may have any suitable thickness. In some embodiments, the intermediate dielectric insulating (MDI) layer 240 has thicknesses in the ranges of 15 nm to 90 nm, 15 nm to 80 nm, 20 nm to 75 nm, 15 nm to 60 nm, 15 nm to 50 nm, 15 nm to 75 nm, and 20 nm to 50 nm. In some embodiments, increasing the thickness of the intermediate dielectric insulating (MDI) layer 240 to more than 40 nm increases the etching selectivity between the intermediate dielectric insulating (MDI) layer 240 and the nanosheet release layer 220.

[0052]

[0074] Embodiments of this disclosure are advantageous in that they reduce thickness, reduce leakage, reduce heat balance, and (multi-V t (including) V t The present invention provides a method for manufacturing electronic devices (e.g., CFETs) that meet requirements and have improved device performance and reliability. The embodiments of this disclosure are advantageously V t Increase and multi-V t It provides an improved integration scheme that enables enhanced tuning capabilities. Embodiments of this disclosure allow V without an EOT penalty. t This significantly improves the performance. Some embodiments advantageously provide an integrated scheme that eliminates the requirement of liner deposition on top of the CFET (e.g., top of the nFET or pFET), reduces the number of etching steps, and eliminates the requirement of a carbon packing step. By reducing the number of etching steps using the processes described herein, the performance of the CFET is advantageously improved. tIt is known that fluctuations are eliminated. Advantageously, embodiments of this disclosure provide an improved process that reduces the number of annealing steps for incorporating metal atoms from the p-type and n-type dipole layers.

[0053]

[0075] Embodiments of the present disclosure advantageously provide improved integration schemes that include conventional dipole techniques such as dipole-first processes and / or dipole-last processes. Advantageously, the integration schemes described herein may include conventional dipole engineering techniques without requiring post-processing of the interface layer (in the dipole-first process) or post-annealing of the high-dielectric-constant dielectric layer (in the dipole-last process).

[0054]

[0076] Figure 1A shows a process flow diagram of method 100 for manufacturing a complementary field-effect transistor (CFET). Method 100 includes, in step 10, depositing an interface layer on the upper surface of a vertically stacked superlattice structure on a semiconductor substrate. In step 12, method 100 includes depositing a high-dielectric-constant dielectric layer on the interface layer. In step 14, method 100 includes depositing a first p-type dipole layer on the high-dielectric-constant dielectric layer. In step 16, method 100 includes depositing a first p-type capping layer on the first p-type dipole layer. In step 18, the method includes depositing a first protective layer on a first portion of the semiconductor substrate. In step 20, method 100 optionally includes etching the vertically stacked superlattice structure to remove the first protective layer from the first portion, and removing a portion of the first p-type capping layer and a portion of the first p-type dipole layer from a second portion of the semiconductor substrate. In step 22, method 100 includes depositing a second p-type dipole layer on a first p-type capping layer and a high-dielectric-constant dielectric layer of the first portion. In step 24, method 100 includes depositing a second p-type capping layer on the second p-type dipole layer. In step 26, method 100 includes depositing a second protective layer on the first and second portions of the semiconductor substrate. In step 28, method 100 optionally includes performing a gap-filling process to fill trenches with p-type dipole gap-filling material. In step 30, method 100 includes etching the vertical stacked superlattice structure to remove the second protective layer from the first and second portions of the semiconductor substrate, and to remove a portion of the first p-type capping layer, a portion of the first p-type dipole layer, a portion of the second p-type capping layer, and a portion of the second p-type dipole layer from the third portion. In step 32, method 100 optionally includes etching the vertical stacked superlattice structure to remove the first p-type capping layer, the first p-type dipole layer, the second p-type capping layer, and the second p-type dipole layer to expose the high dielectric constant layer on the second hGAA structure. In step 34, method 100 includes depositing the first n-type dipole layer on the exposed high dielectric constant layer on the second hGAA structure.In step 36, method 100 includes depositing a first n-type capping layer on top of a first n-type dipole layer. In step 38, method 100 includes depositing a third protective layer on a first portion of a semiconductor substrate. In step 40, method 100 optionally includes etching a vertical stacked superlattice structure to remove the third protective layer from the first portion and removing a portion of the first n-type capping layer and a portion of the first n-type dipole layer from a second portion of the semiconductor substrate. In step 42, method 100 includes depositing a second n-type dipole layer on top of the first portion (on top of the first n-type capping layer) and on top of a high dielectric constant dielectric layer. In step 44, method 100 includes depositing a second n-type capping layer on top of the second n-type dipole layer. In step 46, method 100 includes depositing a fourth protective layer on the first and second portions of the semiconductor substrate. In step 48, method 100 includes optionally removing the fourth protective layer from the first and second portions of the semiconductor substrate and etching the vertical stacked superlattice structure from the third portion to remove a portion of the first p-type capping layer, a portion of the first p-type dipole layer, a portion of the second p-type capping layer, a portion of the second p-type dipole layer, a portion of the first n-type capping layer, a portion of the first n-type dipole layer, a portion of the second n-type capping layer, and a portion of the second n-type dipole layer. In step 50, method 100 includes annealing a semiconductor substrate at a temperature of 1000°C or less to drive atoms from each of the first p-type dipole layer, the second p-type dipole layer, the first n-type dipole layer, and the second n-type dipole layer into the high-dielectric-constant dielectric layer to form an annealed high-dielectric-constant dielectric layer. In step 52, method 100 includes etching the vertical stacked superlattice structure to remove each of the first p-type dipole layer, the first p-type capping layer, the second p-type dipole layer, the second p-type capping layer, the first n-type dipole layer, the first n-type capping layer, the second n-type dipole layer, and the second n-type capping layer.

[0055]

[0077] For example, if the work function is shifted to either a P-type dipole or N-type dipole band edge after dipole engineering, the method herein can be used to shift the band edge in the opposite direction. For example, the method herein shifts the band edge to the most P-type dipole and / or N-type dipole band edge, respectively, at the very low V t (ULV t ) from low V t (LV t ) or standard V t (SV t ), or intermediate gap: high V t (HV t It can be shifted to ).

[0056]

[0078] While not intended to be constrained by theory, selectively etching dipole layers (e.g., a first p-type dipole layer, a second p-type dipole layer, a first n-type dipole layer, and / or a second n-type dipole layer) and increasing the thickness of the dipole layers results in multiple threshold voltages (multiple V). t It is thought that a CFET having ) is formed. In other words, if one dipole layer has a first thickness (e.g., a first p-type dipole layer) and another dipole layer has a second thickness (e.g., a second p-type dipole layer), and the first and second thicknesses are different, then multiple threshold voltages (multiple V) are formed. t ) is formed.

[0057]

[0079] Figures 2A to 2U show bidirectional cross-sectional views of one or more embodiments of an electronic device (e.g., a transistor such as a complementary field-effect transistor (CFET)). The CFETs shown in Figures 2A to 2U can be manufactured by method 100 shown in Figure 1A.

[0058]

[0080] In some embodiments, in step 10, the interface layer 270 is deposited on the upper surface of the vertical stacked superlattice structure 260 using a deposition technique such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating deposition techniques known to those skilled in the art. In some embodiments, in step 10, the interface layer 270 is deposited on a first hGAA structure 215, an intermediate dielectric insulating (MDI) layer 240, and a second hGAA structure 255. In one or more embodiments, the interface layer 270 is silicon dioxide (SiO₂ x ) includes. In one or more embodiments, the interface layer 270 may be formed by etching and oxide formation on a surface (e.g., the upper surface of the vertical stacked superlattice structure 260).

[0059]

[0081] In some embodiments, a wet chemical technique is performed in step 10 to form the interface layer 270. The wet chemical technique may be any suitable technique known to those skilled in the art. In some embodiments, the wet chemical technique includes a pre-cleaning process. In some embodiments, the pre-cleaning process includes using an SC-1 solution containing one or more of ozone, ammonium hydroxide, or hydrogen peroxide. In some embodiments, the pre-cleaning process includes using an SC-1 solution that does not contain ozone, ammonium hydroxide, or hydrogen peroxide. In some embodiments, after using the SC-1 solution, the pre-cleaning process includes etching off native oxides on the substrate using dilute hydrofluoric acid (dilute HF, e.g., dilute HF of 130:1) in a ratio greater than 100:1 to form a hydrophobic surface (i.e., interface layer 270).

[0060]

[0082] In some embodiments, in step 10, rapid heat treatment (RTP) is used to form the interfacial layer 270. RTP may be any suitable process known to those skilled in the art. In some embodiments, in step 10, RTP is silicon dioxide (SiO₂) x This is a thermal oxidation process in which a layer (e.g., interface layer 270) grows on the upper surface of the vertically stacked superlattice structure.

[0061]

[0083] Referring to Figures 1A and 2B, in some embodiments, in step 12, the high dielectric constant dielectric layer 272 is deposited on the interface layer 270 using a deposition technique such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating deposition techniques known to those skilled in the art. In some embodiments, in step 12, the high dielectric constant dielectric layer 272 is deposited conformally on the interface layer 270 by ALD.

[0062]

[0084] In some embodiments, the high dielectric constant dielectric layer 272 is made of hafnium oxide (HfO x ), hafnium zirconium oxide (HfZrO x ), zirconium oxide (ZrO x ), nitrogen-doped hafnium oxide (HfO x ), nitrogen-doped hafnium zirconium oxide (HfZrO x ), and nitrogen-doped zirconium oxide (ZrO x ) includes one or more of the above. In some embodiments, the high dielectric constant dielectric layer 272 is made of hafnium oxide (HfO x ) includes.

[0063]

[0085] Referring to Figures 1A and 2C, in some embodiments, in step 14, the first p-type dipole layer 274 is deposited on the high dielectric constant dielectric layer 272 using a deposition technique such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating deposition techniques known to those skilled in the art. In some embodiments, the first p-type dipole layer 274 is made of aluminum oxide (AlO x ), aluminum nitride (AlN x ), or one or more of those alloys.

[0064]

[0086] In some embodiments, in step 14, depositing the first p-type dipole layer 274 includes exposing the semiconductor substrate 202 (e.g., the upper surface of the high dielectric constant layer 272) to pulses of an aluminum-containing precursor and pulses of an oxygen-containing reactant by an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process. In some embodiments, in step 14, depositing the first p-type dipole layer 274 includes exposing the upper surface of the high dielectric constant layer 272 to pulses of an aluminum-containing precursor and pulses of a nitrogen-containing reactant by an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process. In some embodiments, the semiconductor substrate 202 is purged after each pulse.

[0065]

[0087] In some embodiments, the oxygen-containing reactant includes one or more of oxygen (O2), ozone (O3), or water (H2O).

[0066]

[0088] In some embodiments, the nitrogen-containing reactant is nitrogen (N2), ammonia (NH3), hydrazine (N2H4), nitrogen radical (N2 * ) and hydrogen radicals (H * ) co-flow, nitrogen radicals (N2 * ) and hydrogen (H 2 ) Co-flow of gases, or nitrogen radicals (N2 * ) and deuterium ( 2 H) Includes one or more of the gas confluences.

[0067]

[0089] In some embodiments, the nitrogen-containing reactant comprises substituted or unsubstituted alkylhydrazines. In some embodiments, the alkylhydrazine comprises atoms ranging from 1 to 6 carbon atoms. In one or more embodiments, the alkylhydrazine is t-butylhydrazine. In some embodiments, the nitrogen-containing reactant comprises plasma. In some embodiments, the nitrogen-containing reactant comprises ammonia (NH3).

[0068]

[0090] The first p-type dipole layer 274 can be deposited as a single layer or a multilayer. The first p-type dipole layer 274 can be deposited to a predetermined thickness. In some embodiments, the first p-type dipole layer 274 has a thickness ranging from 3 angstroms to 25 angstroms.

[0069]

[0091] Referring to Figures 1A and 2D, in some embodiments, in step 16, a first p-type capping layer 276 is deposited on the first p-type dipole layer 274 using a deposition technique, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating deposition techniques known to those skilled in the art. In some embodiments, in step 16, the first p-type capping layer 276 is conformally deposited on the first p-type dipole layer 274 by ALD. In some embodiments, the first p-type capping layer 276 is silicon (Si), silicon oxide (SiO₂) x ), aluminum oxide (AlO x ), comprising one or more of titanium nitride (TiN) or tantalum nitride (TaN). In some embodiments, the first p-type capping layer 276 has a thickness ranging from 10 angstroms to 30 angstroms.

[0070]

[0092] Referring to Figures 1A and 2E, in some embodiments, in step 18, the first protective layer 278 is deposited on the first portion 202-1 of the semiconductor substrate using a deposition technique such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating deposition techniques known to those skilled in the art. In some embodiments, the first protective layer 278 protects a portion of the first p-type capping layer 276 on the first portion 202-1 of the semiconductor substrate. The first protective layer 278 may include any suitable material known to those skilled in the art. In some embodiments, the first protective layer 278 includes a hard mask material. In some embodiments, the first protective layer 278 includes carbon (C). In some embodiments, the first protective layer 278 includes spin-on carbon (C).

[0071]

[0093] Method 100 optionally includes selectively etching the vertical stacked superlattice structure 260 in step 20 such that, optionally, in step 20, the first protective layer 278 is removed from a first portion 202-1 of the semiconductor substrate, and a portion of the first p-type capping layer 276 and a portion of the first p-type dipole layer 274 are removed from a second portion 202-2 of the semiconductor substrate. In one or more embodiments, Method 100 applies a plurality of threshold voltages (multi-V) to the CFET. t Step 20 includes selective etching to form the ). Figure 2F shows two cross-sectional views of the semiconductor substrate 202 of Figure 2E after etching the vertical stacked superlattice structure 260 in step 20.

[0072]

[0094] The etching process of step 20 may be any suitable etching process known to those skilled in the art. In some embodiments, the etching process includes a wet etching process or a dry etching process. In some embodiments, the etching process includes a wet etching process. In some embodiments, the wet etching process includes a pre-washing process. In some embodiments, the pre-washing process includes using one or more ammonium hydroxide (NH4OH) or water (H2O). In some embodiments, water (H2O) is deionized water (DI). In some embodiments, the pre-washing process includes using a DI:NH4OH ratio ranging from DI:NH4OH to DI:NH4OH to DI:NH4OH to DI:NH4OH.

[0073]

[0095] In some embodiments, the pre-washing process includes using either the SC-1 solution or the SC-2 solution. In one or more embodiments, the SC-1 solution includes one or more of ozone, ammonium hydroxide, or hydrogen peroxide. In one or more embodiments, the SC-2 solution includes one or more of hydrochloric acid additives or hydrogen peroxide. Advantageously, it has been found that using either the SC-1 solution or the SC-2 solution in step 22 selectively etches the first p-type dipole layer (and other layers above it) without etching any portion of the interfacial layer.

[0074]

[0096] In step 20, selective etching of the vertical stacked superlattice structure 260 to remove the first protective layer 278 from the first portion 202-1 of the semiconductor substrate and a portion of the first p-type capping layer 276 and a portion of the first p-type dipole layer 274 from the second portion 202-2 of the semiconductor substrate, and by increasing the thickness of the dipole layer (for example by depositing the second p-type dipole layer 280 in step 24), advantageously, multi-V t It is believed that a CFET200 having the following characteristics will be provided.

[0075]

[0097] Referring to Figures 1A and 2G, in some embodiments, in step 22, the second p-type dipole layer 280 is deposited on the first p-type capping layer 27 and the high dielectric constant dielectric layer 272 in the first portion 202-1 using a deposition technique such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating deposition techniques known to those skilled in the art. In some embodiments, in step 22, the second p-type dipole layer 280 is formed on the first hGAA structure 215, the intermediate dielectric insulating (MDI) layer 240, and the second hGAA structure 255. In one or more embodiments, depositing the second p-type dipole layer 280 in step 22 involves the same process as depositing the first p-type dipole layer 274 in step 14.

[0076]

[0098] In some embodiments, the second p-type dipole layer 280 is made of aluminum oxide (AlO x ), aluminum nitride (AlN x ), or one or more of their alloys. The second p-type dipole layer 280 may be deposited as a single layer or a multilayer. The second p-type dipole layer 280 may be deposited to a predetermined thickness. In some embodiments, the second p-type dipole layer 280 has a thickness ranging from 3 angstroms to 25 angstroms.

[0077]

[0099] Referring to Figures 1A and 2H, in some embodiments, in step 24, the second p-type capping layer 282 is deposited on the second p-type dipole layer 280 using a deposition technique such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating deposition techniques known to those skilled in the art. In some embodiments, in step 24, the second p-type capping layer 282 is conformally deposited on the second p-type dipole layer 280 by ALD. In some embodiments, the second p-type capping layer 282 is made of silicon (Si), silicon oxide (SiO₂) x ), aluminum oxide (AlO x ), comprising one or more of titanium nitride (TiN) or tantalum nitride (TaN). In some embodiments, the second p-type capping layer 282 has a thickness ranging from 10 angstroms to 30 angstroms.

[0078]

[0100] Referring to Figures 1A and 2I, in some embodiments, in step 26, a second protective layer 284 is deposited on the first portion 202-1 and the second portion 202-2 of the semiconductor substrate using a deposition technique such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating deposition techniques known to those skilled in the art. In some embodiments, the second protective layer 284 protects the first p-type capping layer 274, the first p-type capping layer 276, the second p-type capping layer 280, and the second p-type capping layer 282. The second protective layer 284 may include any suitable material known to those skilled in the art. In some embodiments, the second protective layer 284 includes a hard mask material. In some embodiments, the second protective layer 284 includes carbon (C). In some embodiments, the second protective layer 284 includes spin-on carbon (C).

[0079]

[0101] Referring to Figures 1A and 2K, in some embodiments, in step 28, method 100 optionally includes performing a gap-filling process to fill the trench with p-type dipole gap-filling material 286. Advantageously, filling the trench with p-type gap-filling material 286 allows for multi-V-shaped gaps within the same gate trench. t It is known that a multi-V in the same gate trench is formed. In some embodiments, method 100 is a multi-V in the same gate trench t If this is undesirable, the process does not include performing the gap-filling process of step 28. In one or more embodiments, each of the p-type dipole gap material 286, the second p-type capping layer 282, and the first p-type capping layer 276 is independently made of silicon (Si) or silicon oxide (SiO2). x ), aluminum oxide (AlO x ), titanium nitride (TiN), or tantalum nitride (TaN) are included in one or more of these materials. In one or more embodiments, each of the p-type dipole gap material 286, the second p-type capping layer 282, and the first p-type capping layer 276 independently comprises the same material.

[0080]

[0102] In some embodiments, step 30 includes etching the vertical stacked superlattice structure 260 such that the second protective layer 284 is removed from the first portion 202-1 and the second portion 202-2 of the semiconductor substrate, and portions of the first p-type capping layer 276, the first p-type dipole layer 274, the second p-type capping layer 282, and the second p-type dipole layer 280 are removed from the third portion 202-3. In some embodiments, step 30 includes the same process as step 20.

[0081]

[0103] Referring to Figures 1A and 2L, in some embodiments, in step 32, Method 100 includes selectively etching the vertical stacked superlattice structure to remove the first p-type capping layer 276, the first p-type dipole layer 274, the second p-type capping layer 282, and the second p-type dipole layer 280, exposing the high dielectric constant dielectric layer 272 on the second hGAA structure 255. In some embodiments, step 32 includes the same process as step 20 and / or step 30. In one or more embodiments, Method 100 applies multiple threshold voltages (multi-V) to the CFET. t The process includes selective etching in step 32 to form the following:

[0082]

[0104] Referring to Figures 1A and 2M, in some embodiments, in step 34, the first n-type dipole layer 290 on the exposed high dielectric constant dielectric layer 272 on the second hGAA structure 255 is deposited by, but is not limited to, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating deposition techniques known to those skilled in the art. In some embodiments, the first n-type dipole layer 290 is made of lanthanum oxide (LaO x ), lanthanum nitride (LaN x ), or one or more of those alloys.

[0083]

[0105] In some embodiments, in step 34, depositing the first n-type dipole layer 290 includes exposing the semiconductor substrate 202 (e.g., the upper surface of the exposed high-dielectric-constant dielectric layer 272) to pulses of a lanthanum-containing precursor and pulses of an oxygen-containing reactant by an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process. In some embodiments, in step 34, depositing the first n-type dipole layer 290 includes exposing the upper surface of the exposed high-dielectric-constant dielectric layer 272 to pulses of a lanthanum-containing precursor and pulses of a nitrogen-containing reactant by an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process. In some embodiments, the semiconductor substrate 202 is purged after each pulse.

[0084]

[0106] In some embodiments, the oxygen-containing reactant includes one or more of oxygen (O2), ozone (O3), or water (H2O).

[0085]

[0107] In some embodiments, the nitrogen-containing reactant is nitrogen (N2), ammonia (NH3), hydrazine (N2H4), nitrogen radical (N2 * ) and hydrogen radicals (H * ) co-flow, nitrogen radicals (N2 * ) and co-flow of hydrogen (H2) gas, or nitrogen radicals (N2 * ) and deuterium ( 2 H) Confluence of gases, including one or more of the above.

[0086]

[0108] In some embodiments, the nitrogen-containing reactant comprises substituted or unsubstituted alkylhydrazines. In some embodiments, the alkylhydrazine comprises atoms ranging from 1 to 6 carbon atoms. In one or more embodiments, the alkylhydrazine is t-butylhydrazine. In some embodiments, the nitrogen-containing reactant comprises plasma. In some embodiments, the nitrogen-containing reactant comprises ammonia (NH3).

[0087]

[0109] The first n-type dipole layer 290 may be deposited as a single layer or a multilayer film. The first n-type dipole layer 290 may be deposited to a predetermined thickness. In some embodiments, the first n-type dipole layer 290 has a thickness ranging from 3 angstroms to 25 angstroms.

[0088]

[0110] Referring to Figures 1A and 2N, in some embodiments, in step 36, the first n-type capping layer 292 is deposited on the first n-type dipole layer 290 using a deposition technique such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating deposition techniques known to those skilled in the art. In some embodiments, in step 36, the first n-type capping layer 292 is conformally deposited on the first n-type dipole layer 290 (on the second hGAA structure 255) by ALD. In some embodiments, the first n-type capping layer 292 is silicon (Si), silicon oxide (SiO₂) x ), aluminum oxide (AlO x ), comprising one or more of titanium nitride (TiN) or tantalum nitride (TaN). In some embodiments, the first n-type capping layer 292 has a thickness ranging from 10 angstroms to 30 angstroms.

[0089]

[0111] Referring to Figures 1A and 2O, in some embodiments, in step 38, a third protective layer 294 is deposited on a first portion 202-1 of a semiconductor substrate using a deposition technique such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating deposition techniques known to those skilled in the art. In some embodiments, the third protective layer 294 protects a first portion of the first n-type capping layer 292 (and the layer beneath the first n-type capping layer 292). The third protective layer 294 may include any suitable material known to those skilled in the art. In some embodiments, the third protective layer 294 includes a hard mask material. In some embodiments, the third protective layer 294 includes carbon (C). In some embodiments, the third protective layer 294 includes spin-on carbon (C).

[0090]

[0112] Method 100 optionally includes selective etching of the vertical stacked superlattice structure 260 in step 40 to remove the third protective layer 294 from the first portion 202-1, and a portion of the first n-type capping layer 292 and a portion of the first n-type dipole layer 290 from the second portion 202-2 of the semiconductor substrate. In one or more embodiments, Method 100 includes applying multiple threshold voltages (multi-V) within the CFET 200. t Step 40 includes selective etching to form the ). Figure 2P shows two cross-sectional views of the semiconductor substrate 202 of Figure 2O after etching the vertical stacked superlattice structure 260 in step 40.

[0091]

[0113] Referring to Figures 1A and 2Q, in some embodiments, in step 42, the second n-type dipole layer 296 is deposited on the first portion 202-1 (on the first n-type capping layer 292) and the high dielectric constant dielectric layer 272 using a deposition technique such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating deposition techniques known to those skilled in the art. In some embodiments, in step 42, the second n-type dipole layer 296 is conformally deposited on the second hGAA structure 255 by ALD. In one or more embodiments, depositing the second n-type dipole layer 296 in step 42 involves the same process as depositing the first n-type dipole layer 290 in step 34.

[0092]

[0114] In some embodiments, the second n-type dipole layer 296 is made of lanthanum oxide (LaO x ), lanthanum nitride (LaN x ), or one or more of their alloys. The second n-type dipole layer 296 may be deposited as a single layer or a multilayer. The second n-type dipole layer 296 may be deposited to a predetermined thickness. In some embodiments, the second n-type dipole layer 296 has a thickness ranging from 3 angstroms to 25 angstroms.

[0093]

[0115] Referring to Figures 1A and 2R, in some embodiments, in step 44, the second n-type capping layer 298 is deposited on the second n-type dipole layer 296 using a deposition technique such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating deposition techniques known to those skilled in the art. In some embodiments, in step 44, the second n-type capping layer 298 is conformally deposited on the second n-type dipole layer 296 by ALD. In some embodiments, the second n-type capping layer 298 is silicon (Si), silicon oxide (SiO₂) x ), aluminum oxide (AlO x ), comprising one or more of titanium nitride (TiN) or tantalum nitride (TaN). In some embodiments, the second n-type capping layer 298 has a thickness ranging from 10 angstroms to 30 angstroms.

[0094]

[0116] Referring to Figures 1A and 2S, in some embodiments, in step 46, a fourth protective layer 300 is deposited on the first portion 202-1 and the second portion 202-2 of the semiconductor substrate 202 using a deposition technique such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating deposition techniques known to those skilled in the art. In some embodiments, the fourth protective layer 300 protects the second n-type capping layer 298 (and the layer beneath the second n-type capping layer 298). The fourth protective layer 300 may include any suitable material known to those skilled in the art. In some embodiments, the fourth protective layer 300 includes a hard mask material. In some embodiments, the fourth protective layer 300 includes carbon (C). In some embodiments, the fourth protective layer 300 includes spin-on carbon (C).

[0095]

[0117] Referring to Figures 1A and 2T, Method 100 optionally includes etching the vertical stacked superlattice structure 260 in step 48 to remove the fourth protective layer 300 from the first portion 202-1 and the second portion 202-2 of the semiconductor substrate 202-3, and from the third portion to remove a portion of the first p-type capping layer 276, a portion of the first p-type dipole layer 274, a portion of the second p-type capping layer 282, a portion of the second p-type dipole layer 280, a portion of the first n-type capping layer 292, a portion of the first n-type dipole layer 290, a portion of the second n-type capping layer 298, and a portion of the second n-type dipole layer 296. In one or more embodiments, Method 100 applies a multi-V threshold voltage to the CFET. t The process includes selective etching in step 48 to form the following:

[0096]

[0118] Referring further to Figures 1A and 2T, in some embodiments, step 50 of method 100 includes annealing the semiconductor substrate 202 (indicated by arrow 302) at a temperature of 1000°C or less to drive atoms from the first p-type dipole layer 274, the second p-type dipole layer 280, the first n-type dipole layer 290, and the second n-type dipole layer 296 into the high-dielectric-constant dielectric layer 272' (shown in Figure 2U).

[0097]

[0119] In some embodiments, step 50 of method 100 includes annealing the semiconductor substrate 202 at a temperature of 950°C or less. In some embodiments, the temperature is in the range of 500°C to 1000°C, including the range of 600°C to 1000°C, the range of 700°C to 1000°C, the range of 750°C to 950°C, or the range of 800°C to 900°C.

[0098]

[0120] While not intended to be theoretically binding, it is believed that annealing the semiconductor substrate 202 according to step 50 increases the number of atoms driven from one or more dipole layers (e.g., a first p-type dipole layer 274, a second p-type dipole layer 280, a first n-type dipole layer 290, and / or a second n-type dipole layer 296) to the interface between the interface layer 270 and the high-dielectric-constant dielectric layer, compared to a method in which annealing is not performed. In one or more embodiments, annealing the semiconductor substrate 202 in step 50 includes rapid heat treatment (RTP). The RTP may be any suitable process known to those skilled in the art. Without intending to be constrained by theory, in step 50, method 100 anneals the semiconductor substrate 202 at a temperature of 1000°C or less to drive atoms from the dipole layer to the interface between the interface layer 270 and the high dielectric constant dielectric layer 272, the interface between the interface layer 270 and the high dielectric constant dielectric layer 272 possesses the properties of the dielectric layer.

[0099]

[0121] Referring to Figures 1A and 2U, in some embodiments, step 52 of method 100 includes etching the vertical stacked superlattice structure 260 to remove a first p-type dipole layer 274, a first p-type capping layer 276, a second p-type dipole layer 280, a second p-type capping layer 282, a first n-type dipole layer 290, a first n-type capping layer 292, a second n-type dipole layer 296, and a second n-type capping layer 298.

[0100]

[0122] After step 52, method 100 may include any post-processing steps for semiconductor manufacturing known to those skilled in the art.

[0101]

[0123] In one or more embodiments, the CFET has any suitable number of different dipole layer thicknesses and multiple threshold voltages (multiple V) t ) may include. In one or more embodiments, the CFET has two different dipole layer thicknesses and two multiple threshold voltages (multiple V t ) includes. In one or more embodiments, the CFET has three different dipole layer thicknesses and three multiple threshold voltages (multi-V). t) includes. In one or more embodiments, the CFET has four different dipole layer thicknesses and four multiple threshold voltages (multiple V t ) and include.

[0102]

[0124] Further embodiments of the present disclosure relate to electronic devices having a plurality of CFET regions. In one or more embodiments, the electronic device includes a CFET 200 formed by Method 100.

[0103]

[0125] In some embodiments, an electronic device (e.g., CFET200) has a first threshold voltage (V t A first complementary field-effect transistor (CFET) region having ) and a second V t A second CFET region having and a third V t The present invention comprises a third CFET region having a first CFET region, a second CFET region, and a third CFET region, each formed on a vertical stacked superlattice structure 260 on a semiconductor substrate, the vertical stacked superlattice structure 260 comprising a first horizontal gate-all-around (hGAA) structure 215 including a positive metal-oxide-semiconductor (pMOS) transistor on the upper surface 203 of the semiconductor substrate 202, an intermediate dielectric insulating (MDI) layer 240 on the upper surface 225 of the first hGAA structure 215, a second hGAA structure 255 including a negative metal-oxide-semiconductor (nMOS) transistor on the upper surface 245 of the intermediate dielectric insulating (MDI) layer 240, and interface layers 270 on the first hGAA structure 215, the intermediate dielectric insulating (MDI) layer 240, and the second hGAA structure 255, respectively.

[0104]

[0126] In some embodiments, the first CFET region has hafnium oxide (HfO) on the interface layer 270. x ) Layer 272, Hafnium Oxide (HfO x The layer 272 includes a first p-type dipole layer 274, and the first p-type capping layer 276 includes a first p-type dipole layer 274.

[0105]

[0127] In some embodiments, the second CFET region is a hafnium oxide (HfO) layer on the interface layer 270. x) layer 272, hafnium oxide (HfO x ) a first p-type bipolar layer 274 on layer 272, a first p-type capping layer 276 on the first p-type bipolar layer 274, hafnium oxide (HfO x ) a second p-type bipolar layer 280 on a first exposed portion of layer 272, and a second p-type capping layer 282 on the second p-type bipolar layer 280.

[0106]

[0128] In some embodiments, the third CFET region includes hafnium oxide (HfO x ) layer 272, hafnium oxide (HfO x ) a first p-type bipolar layer 274 on layer 272, a first p-type capping layer 276 on the first p-type bipolar layer 274, hafnium oxide (HfO x ) a second p-type bipolar layer 280 on a first exposed portion of layer 272, a second p-type capping layer 282 on the second p-type bipolar layer 280, a first n-type bipolar layer 290 on an exposed high-k dielectric layer 272 on the second hGAA structure 255, a first n-type capping layer 292 on the first n-type bipolar layer 290, a second n-type bipolar layer 296 on the second hGAA structure 255, and a second n-type capping layer 298 on the second n-type bipolar layer 296.

[0107]

[0129] In one or more embodiments, each of the first p-type bipolar layer 274 and the second p-type bipolar layer 280 independently includes one or more of aluminum oxide (AlO x ), aluminum nitride (AlN x ), or an alloy thereof. In some embodiments, each of the first n-type bipolar layer 290 and the second n-type bipolar layer 296 independently includes one or more of lanthanum oxide (LaO x ), lanthanum nitride (LaN x ), or an alloy thereof.

[0108]

[0130] In some embodiments, each of the first p-type capping layer 276, the second p-type capping layer 282, the first n-type capping layer 292, and the second n-type capping layer 298 is independently composed of silicon (Si) and silicon oxide (SiO₂). x ), aluminum oxide (AlO x ), comprising one or more of titanium nitride (TiN) or tantalum nitride (TaN).

[0109]

[0131] Additional embodiments of this disclosure relate to processing tools (i.e., cluster tools) for forming CFETs and the methods described. In one or more embodiments, the cluster tool comprises an integrated processing system such that the steps of Method 100 are performed without vacuum breaking. In one or more embodiments, there is a vacuum breaking during at least one of the steps of Method 100.

[0110]

[0132] The specific arrangement of the processing chamber and its components can be modified depending on the cluster tool and should not be considered to limit the scope of this disclosure.

[0111]

[0133] Embodiments of this disclosure relate to non-temporary computer-readable media. In one or more embodiments, the non-temporary computer-readable media includes instructions, when executed by a controller of a processing chamber, that cause the processing chamber to perform any of the steps of the methods described herein. In one or more embodiments, the controller causes the processing chamber to perform the steps of Method 100.

[0112]

[0134] Spatially relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” may be used here to describe the relationship between one element or feature shown in the drawing and another, for the sake of clarity. It will be understood that spatially relative terms are intended to encompass various orientations of the device in use or operation, in addition to the orientation shown in the drawing. For example, if the device in the drawing is upside down, an element described as “below” or “directly below” another element or feature will therefore be oriented “above” the other element or feature. Thus, the exemplary term “below” may encompass both up and down orientations. The device may be oriented in ways other than those described (it may be rotated 90 degrees or rotated to other orientations), and the spatially relative descriptions used herein shall be interpreted accordingly.

[0113]

[0135] In the context of describing the materials and methods discussed herein (in particular in the context of the following claims), the use of “a” and “an,” “the,” and similar references should be interpreted as encompassing both singular and plural, unless otherwise indicated herein or unless the context clearly contradicts this. The enumeration of ranges of values ​​herein is merely intended to serve as a shorthand notation for independently referring to each individual value within the range, unless otherwise indicated herein, and each individual value is incorporated into the specification as if it were independently stated herein. All methods described herein may be performed in any appropriate order, unless otherwise indicated herein or unless the context clearly contradicts this. Any and all examples or illustrative language provided herein (e.g., “such as”) is merely intended to better describe the materials and methods and does not impose any limitation of scope unless specifically asserted. Nothing in this specification should be interpreted as indicating any unclaimed element essential to the practice of the disclosed materials and methods.

[0114]

[0136] Throughout this Specification, any reference to “one embodiment,” “a particular embodiment,” “one or more embodiments,” or “embodiment” means that any particular feature, structure, material, or property described in relation to an embodiment is included in at least one embodiment of this Disclosure. Therefore, any other occurrences of the phrases “in one or more embodiments,” “in a particular embodiment,” “in one embodiment,” or “in an embodiment” throughout this Specification do not necessarily refer to the same embodiment of this Disclosure. In one or more embodiments, the particular feature, structure, material, or property is combined in any suitable manner.

[0115]

[0137] While the disclosures herein are described with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and uses of the disclosure. It will be obvious to those skilled in the art that various modifications and variations can be made to the methods and apparatus of the disclosure without departing from the essence and scope of the disclosure. Therefore, the disclosure is intended to include modifications and variations that fall within the scope of the appended claims and their equivalents.

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21. A method for forming a complementary field-effect transistor (CFET), First threshold voltage (V ｔ To form a first complementary field-effect transistor (CFET) region having ) A second V adjacent to the first CFET region ｔ To form a second CFET region having, A third V adjacent to the second CFET region ｔ To form a third CFET region having, Includes, Each of the first CFET region, the second CFET region, and the third CFET region is formed on a high dielectric constant dielectric layer on an interface layer of a vertical stacked superlattice structure on a semiconductor substrate, and the vertical stacked superlattice structure includes a second hGAA structure on an intermediate dielectric insulating (MDI) layer of a first horizontal gate all-around (hGAA) structure. method.

22. Forming the first CFET region described above is A first p-type dipole layer is deposited on the high dielectric constant dielectric layer, Depositing a first p-type capping layer on the first p-type dipole layer, A first protective layer is deposited on the first portion of the semiconductor substrate to protect the first portion of the first p-type capping layer, The method according to claim 21, comprising etching the vertical stacked superlattice structure such that the first protective layer is removed from the first portion of the semiconductor substrate, and a portion of the first p-type capping layer and a portion of the first p-type dipole layer are removed from the second portion.

23. Forming the aforementioned second CFET region The method involves depositing a second p-type dipole layer on the first and second portions, wherein the second p-type dipole layer is formed on the first hGAA structure, the MDI layer, and the second hGAA structure. Depositing a second p-type capping layer on the second p-type dipole layer, A second protective layer is deposited on the first and second portions of the semiconductor substrate to protect the first p-type dipole layer, the first p-type capping layer, the second p-type dipole layer, and the second p-type capping layer. Etching the vertical stacked superlattice structure such that the second protective layer is removed from the first and second portions of the semiconductor substrate, and a portion of the first p-type capping layer, a portion of the first p-type dipole layer, a portion of the second p-type capping layer, and a portion of the second p-type dipole layer are removed from the third portion. The method according to claim 22, comprising etching the vertical stacked superlattice structure so as to expose the high dielectric constant dielectric layer on the second hGAA structure.

24. Forming the above-mentioned third CFET region is The first n-type dipole layer is deposited on the exposed high dielectric layer on the second hGAA structure, Depositing a first n-type capping layer on the first n-type dipole layer, A third protective layer is deposited on the first portion of the semiconductor substrate to protect the first portion of the first n-type capping layer. The method according to claim 23, comprising etching the vertical stacked superlattice structure such that the third protective layer is removed from the first portion of the semiconductor substrate, and a portion of the first n-type capping layer and a portion of the first n-type dipole layer are removed from the second portion.

25. Forming the above-mentioned third CFET region is A second n-type dipole layer is deposited on the first and second portions, wherein the second n-type dipole layer is formed on the second hGAA structure. Depositing a second n-type capping layer on the second n-type dipole layer, A fourth protective layer is deposited on the first and second portions of the semiconductor substrate to protect the second n-type capping layer. The method according to claim 24, further comprising: removing the fourth protective layer from the first and second portions of the semiconductor substrate; and etching the vertical stacked superlattice structure from the third portion such that a portion of the first p-type capping layer, a portion of the first p-type dipole layer, a portion of the second p-type capping layer, a portion of the second p-type dipole layer, a portion of the first n-type capping layer, a portion of the first n-type dipole layer, a portion of the second n-type capping layer, and a portion of the second n-type dipole layer are removed.

26. The method according to claim 25, further comprising annealing the semiconductor substrate to form an annealed high dielectric constant dielectric layer.

27. The method according to claim 26, further comprising etching the vertical stacked superlattice structure after annealing.

28. The method according to claim 27, wherein etching of the vertical stacked superlattice structure after annealing is configured to remove the first p-type dipole layer, the first p-type capping layer, the second p-type dipole layer, the second p-type capping layer, the first n-type dipole layer, the first n-type capping layer, the second n-type dipole layer, and the second p-type capping layer, respectively.

29. Each of the first p-type dipole layer and the second p-type dipole layer independently comprises aluminum oxide (AlO2). ｘ ), aluminum nitride (AlN ｘ The method according to claim 22, comprising one or more of the following: ), or alloys thereof.

30. Each of the first p-type capping layer and the second p-type capping layer independently contains silicon (Si) and silicon oxide (SiO₂). ｘ ), aluminum oxide (AlO ｘ The method according to claim 22, comprising one or more of ), titanium nitride (TiN), or tantalum nitride (TaN).

31. Each of the first n-type dipole layer and the second n-type dipole layer independently contains one or more of lanthanum oxide (LaO ｘ ), lanthanum nitride (LaN ｘ ), or an alloy thereof. The method according to claim 25.

32. Each of the first n-type capping layer and the second n-type capping layer independently contains silicon (Si) and silicon oxide (SiO₂). ｘ ), aluminum oxide (AlO ｘ The method according to claim 25, comprising one or more of ), titanium nitride (TiN), or tantalum nitride (TaN).

33. The method according to claim 25, wherein each of the first protective layer, the second protective layer, the third protective layer, and the fourth protective layer independently comprises a hard mask material.

34. The method according to claim 21, wherein the first hGAA structure is a positive metal-oxide-semiconductor (pMOS) transistor and the second hGAA structure is a negative metal-oxide-semiconductor (nMOS) transistor.

35. The aforementioned interface layer is silicon dioxide (SiO ｘ ) contains, and the high dielectric constant dielectric layer is hafnium oxide (HfO ｘ ), zirconium oxide (ZrO ｘ ), or hafnium zirconium oxide (HfZrO ｘ The method according to claim 21, comprising one or more of the following.

36. It is an electronic device, First threshold voltage (V ｔ A first complementary field-effect transistor (CFET) region having ) The second V ｔ A second CFET region having, The third V ｔ A third CFET region having, The first CFET region, the second CFET region, and the third CFET region are each formed on an interface layer on a vertical stacked superlattice structure on a semiconductor substrate, and the vertical stacked superlattice structure includes a second hGAA structure on an intermediate dielectric insulating (MDI) layer on a first horizontal gate-all-around (hGAA) structure. Electronic devices.

37. The electronic device according to claim 36, wherein the first CFET region includes a high dielectric constant dielectric layer on the interface layer, a first p-type dipole layer on the high dielectric constant dielectric layer, and a first p-type capping layer on the first p-type dipole layer.

38. The electronic device according to claim 37, wherein the second CFET region includes the high dielectric constant dielectric layer on the interface layer, the first p-type dipole layer on the high dielectric constant dielectric layer, the first p-type capping layer on the first p-type dipole layer, the second p-type dipole layer, and the second p-type capping layer on the second p-type dipole layer.

39. The electronic device according to claim 38, wherein the third CFET region includes the high dielectric constant dielectric layer on the interface layer, the first p-type dipole layer on the high dielectric layer, the first p-type capping layer on the first p-type dipole layer, the second p-type dipole layer, the second p-type capping layer on the second p-type dipole layer, the first n-type dipole layer on the exposed high dielectric constant dielectric layer on the second hGAA structure, the first n-type capping layer on the first n-type dipole layer, the second n-type dipole layer on the second hGAA structure, and the second n-type capping layer on the second n-type dipole layer.

40. Each of the first p-type dipole layer and the second p-type dipole layer is independently composed of aluminum oxide (AlO2). ｘ ), aluminum nitride (AlN ｘ The first n-type dipole layer and the second n-type dipole layer each independently contain lanthanum oxide (LaO2). ｘ ), lanthanum nitride (LaN ｘ The first p-type capping layer, the second p-type capping layer, the first n-type capping layer, and the second n-type capping layer each independently comprises silicon (Si), silicon oxide (SiO₂) ｘ ), aluminum oxide (AlO ｘ The electronic device according to claim 39, comprising one or more of ), titanium nitride (TiN), or tantalum nitride (TaN).

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