Source contact for 3D memory with CMOS junction array

Abstract

A method for manufacturing a memory device is provided. The method comprises forming a first epitaxial layer on a substrate and forming a memory array on the first epitaxial layer, the memory array comprising a memory stack of alternating layers of oxide material and metal material on the first epitaxial layer, at least one memory cell extending from the first epitaxial layer through the memory stack, and a slit filled with a filler material adjacent to the at least one memory cell.

Description

Technical Field

[0001]

[0001] Embodiments of the present disclosure relate to the field of electronic devices, and methods and apparatuses for manufacturing electronic devices. More specifically, embodiments of the present disclosure provide a method for forming a backside source contact for a 3D-NAND device.

[0002]

[0002] Semiconductor technology has advanced rapidly, and as technology progresses to increase processing and storage speed per unit area, the dimensions of devices have been reduced. Memory devices are widely used to store information included in various electronic devices such as computers, wireless communication devices, cameras, and digital displays.

[0003]

[0003] Wafer bonding technology (such as CMOS bonding array technology) has been introduced into 3D NAND devices to improve device performance and reduce chip area.

[0004]

[0004] A backside source contact (BSSC) has been proposed as a common source line (CSL) contact for a CMOS under array (CuA). The substrate polished from the backside of the array wafer was the CSL line to expose the channel polysilicon of the memory hole and deposit n+ polysilicon. The CSL n+ polysilicon needs to be activated using a high temperature (>700 °C). However, since the Cu metallization is damaged, a processing temperature exceeding 400 °C cannot be used after wafer bonding. Therefore, the incompletely activated n+ poly-Si is connected to TiN / W, and thus the contact resistance of TiN n+ poly-Si (Rc) and the sheet resistance of n+ Si (Rs) are one order of magnitude higher than those of epitaxial Si doped with n+.

[0005]

[0005] Therefore, in the art there is a need for 3D-NAND devices with high quality and lower sheet resistance (Rs) and resistive-capacitance (Rc), along with high aspect ratio contact (HARC) etching stop capability. Furthermore, in the art there is a need for methods and apparatus for forming 3D-NAND devices. [Overview of the project]

[0006]

[0006] One or more embodiments of the present disclosure relate to a method for forming a semiconductor memory device. In one or more embodiments, the method for forming a semiconductor memory device includes forming a first epitaxial layer on a substrate and forming a memory array on the first epitaxial layer, the memory array including a memory stack of alternating layers of oxide material and a first metallic material on the first epitaxial layer, at least one memory cell extending from the first epitaxial layer through the memory stack and a slit filled with a filler material adjacent to the at least one memory cell.

[0007]

[0007] Further embodiments of the present disclosure relate to 3D-NAND memory devices. In one embodiment, the 3D-NAND memory device includes a common source line having a highly doped epitaxial layer on a substrate, and at least one memory stack formed on the common source line, the memory stack including alternating layers of oxide material and metallic material, at least one memory cell extending from the common source line through at least one memory stack, and a slit filled with a filler material adjacent to the at least one memory cell, wherein the at least one memory cell includes a semiconductor channel in contact with a highly doped epitaxial layer via a first material.

[0008]

[0008] Further embodiments of the present disclosure relate to methods for forming semiconductor memory devices. In one or more embodiments, a method for forming a semiconductor memory device includes forming a first epitaxial layer on a primary epitaxial layer on a substrate; forming a memory array on the first epitaxial layer, wherein the memory array includes a memory stack of alternating layers of oxide material and metal material on the first epitaxial layer; at least one memory cell extending from the first epitaxial layer through the memory stack; and a slit filled with a filler material adjacent to the at least one memory cell; bonding the memory array to a peripheral wafer; polishing the substrate to expose the primary epitaxial layer; removing the primary epitaxial layer; etching the first epitaxial layer to form an opening and expose a portion of the memory cell; depositing a first material in the first opening; and forming contacts on the filled slit.

[0009]

[0009] To allow for a more detailed understanding of the features of the Disclosure outlined above, a more specific description of the Disclosure can be obtained by reference to embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings show only typical embodiments of the Disclosure, and therefore should not be considered limiting in scope, as the Disclosure may allow for other equally valid embodiments. Embodiments described herein are shown in the figures of the accompanying drawings as examples, not limitations, and similar reference numerals indicate similar elements. [Brief explanation of the drawing]

[0010] [Figure 1] This document shows a process flow diagram of one or more methods according to the embodiments described herein. [Figure 2A] A cross-sectional view of a device according to one or more embodiments is shown. [Figure 2B] A cross-sectional view of the device according to one or more alternative embodiments is shown. [Figure 2C]Cross-sectional views of one or more alternative embodiments of the device are shown. [Figure 2D] Cross-sectional views of one or more alternative embodiments of the device are shown. [Figure 3] A cross-sectional view of a device according to one or more embodiments is shown. [Figure 4] A cross-sectional view of a device according to one or more embodiments is shown. [Figure 5] A cross-sectional view of a device according to one or more embodiments is shown. [Figure 6A] A cross-sectional view of a device according to one or more embodiments is shown. [Figure 6B] An enlarged cross-sectional view of region 132 of the device in Figure 6A is shown according to one or more embodiments. [Figure 7] A cross-sectional view of a device according to one or more embodiments is shown. [Figure 8] A cross-sectional view of a device according to one or more embodiments is shown. [Figure 9] A cross-sectional view of a device according to one or more embodiments is shown. [Figure 10A] A cross-sectional view of a device according to one or more embodiments is shown. [Figure 10B] An enlarged cross-sectional view of region 136 of the device in Figure 10A is shown according to one or more embodiments. [Figure 11] A cross-sectional view of a device according to one or more embodiments is shown. [Figure 12] A cross-sectional view of a device according to one or more embodiments is shown. [Figure 13] A cross-sectional view of a device according to one or more embodiments is shown. [Figure 14] A cross-sectional view of a device according to one or more embodiments is shown. [Figure 15A] A cross-sectional view of a device according to one or more embodiments is shown. [Figure 15B] An enlarged cross-sectional view of region 148 of the device in Figure 15A is shown according to one or more embodiments. [Figure 16A]A cross-sectional view of a device according to one or more embodiments is shown. [Figure 16B] An enlarged cross-sectional view of region 148 of the device of FIG. 16A according to one or more embodiments is shown. [Figure 17A] A cross-sectional view of a device according to one or more embodiments is shown. [Figure 17B] An enlarged cross-sectional view of region 148 of the device of FIG. 17A according to one or more embodiments is shown. [Figure 18] A cluster tool according to one or more embodiments is shown. **DETAILED DESCRIPTION OF THE INVENTION**

[0011]

[0036] Before describing some exemplary embodiments of the present disclosure, it should be understood that the present disclosure is not limited to the details of the configurations or processing steps described in the following description. The present disclosure can have other embodiments and can be practiced or executed in various ways.

[0012]

[0037] As used in this specification and the appended claims, terms such as "precursor", "reactant", "reactive gas", etc. are used interchangeably to refer to any gas species that can react with the substrate surface.

[0013]

[0038] In the following description, numerous specific details such as specific materials, chemical properties, element dimensions, etc. are described in order to provide a complete understanding of one or more embodiments of the present disclosure. However, it will be apparent to those skilled in the art that one or more embodiments of the present disclosure can be implemented without these specific details. In other instances, semiconductor manufacturing processes, techniques, materials, equipment, etc. are not described in detail to avoid unnecessarily obscuring the description herein. Those skilled in the art will be able to implement appropriate functionality using the description contained herein without performing more experiments than necessary.

[0014]

[0039] While certain exemplary embodiments of this disclosure are described and shown in the accompanying drawings, such embodiments are merely illustrative and not limiting to this disclosure. Modifications may occur in the art, so please understand that this disclosure is not limited to the specific configurations and arrangements shown and described.

[0015]

[0040] One or more embodiments provide a processing method in an integrated processing tool for forming a common source line including a highly doped epitaxial layer on a substrate and forming a memory stack on the common source line.

[0016]

[0041] In one or more embodiments, the common source line (CSL) layer is grown on a blanket silicon substrate and exhibits significantly lower common source line sheet resistance (Rs) and resistance-capacitance (Rc) compared to known common source line layers. In one or more embodiments, the common source line layer comprises a highly doped epitaxial layer that is fully activated at high temperatures without temperature limitations. More specifically, in one or more embodiments, the common source line layer comprises N+ epitaxial silicon that is fully activated at high temperatures without temperature limitations. Advantageously, low sheet resistance (Rs) and low resistance-capacitance (Rc) are obtained. Furthermore, the epitaxial layer on the silicon substrate can function as an etching stop layer for high aspect ratio contact (HARC) etching by tuning its material properties with additional elemental doping into the layer.

[0017]

[0042] One or more embodiments of this disclosure are described with reference to the drawings. Methods of one or more embodiments manufacture logic devices or memory devices. In certain embodiments, three-dimensional NAND cell structures are manufactured. In some embodiments, the method forms a first epitaxial layer and forms a memory array on the first epitaxial layer. The memory array may include a memory stack of alternating layers of oxide material and metallic material on the first epitaxial layer, at least one memory cell extending from the first epitaxial layer through the memory stack, and a slit filled with filler material adjacent to the at least one memory cell. In some embodiments, the processing method is performed within a processing tool without breaking the vacuum.

[0018]

[0043] Figure 1 shows a process flow diagram of an exemplary method 10 for forming a memory device. Those skilled in the art will recognize that method 10 may include any or all of the illustrated processes. The order of each step may also be partially modified. Method 10 may begin with any of the enumerated processes without departing from the present disclosure. Referring to Figure 1, in step 12, a first epitaxial layer is formed on the substrate. In some embodiments, the substrate is initially provided before the formation of the epitaxial layer. As used herein, the term “provided” means that the substrate is made available for processing (e.g., positioned in a processing chamber). In step 14, a memory array is formed on the first epitaxial layer. In step 16, the memory array is bonded to a peripheral wafer. In step 18, the substrate is polished. In step 20, the first epitaxial layer is etched. In step 22, the first material is deposited. In step 24, contacts are formed.

[0019]

[0044] Figures 2A to 17B show partial cross-sectional views of the electronic device 100 following the process flow shown in Method 10 of Figure 1.

[0020]

[0045] Referring to Figures 1 and 2A to 2D, in step 12, a first epitaxial layer 104 is formed on the substrate. Figures 2A to 2D show an electronic device 100 according to one or more embodiments of the present disclosure. In some embodiments, the electronic device 100 shown in Figures 2A to 2D is formed on a substrate 102. The substrate 102 may be bare in layers, as shown. The electronic device in Figure 2A consists of a substrate 102 and a first epitaxial layer 104. The electronic device in Figure 2B consists of a substrate 102, a primary epitaxial layer 106, and a first epitaxial layer 104. The electronic device in Figure 2C consists of a substrate 102, a first epitaxial layer 104, and a second epitaxial layer 108. The electronic device shown in Figure 2D consists of a substrate 102, a primary epitaxial layer 106, a first epitaxial layer 104, and a second epitaxial layer 108.

[0021]

[0046] The substrate 102 may be any suitable material known to those skilled in the art. As used in this specification and the accompanying claims, the term “substrate” refers to the surface on which a process is performed or a portion of such surface. It will also be understood to those skilled in the art that, unless otherwise clearly indicated in the context, a reference to a substrate may refer to only a portion of a substrate. In addition, when a reference is made to deposition on a substrate, it may mean both a bare substrate and a substrate on which one or more films or features are deposited or formed.

[0022]

[0047] As used herein, “substrate” refers to any substrate or material surface formed on a substrate on which a film treatment is performed during a manufacturing process. For example, substrate surfaces on which treatment may be performed include, depending on the application, materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials. A substrate includes, but is not limited to, a semiconductor wafer. A substrate can be exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal, and / or bake the substrate surface. In addition to film treatment directly on the surface of the substrate itself, any of the disclosed film treatment steps may be performed on an underlying layer formed on the substrate, as will be disclosed in more detail below. The term “substrate surface” is intended to include an underlying layer as indicated in the context. Therefore, for example, when a film / layer or partial film / layer is deposited on the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0023]

[0048] As used herein, the term “epitaxial” refers to a type of crystal growth or material deposition in which a new crystalline layer is formed with respect to a crystalline seed layer in one or more clearly defined orientations. The deposited crystalline film is called an epitaxial layer. In one or more embodiments, an epitaxial stack 109 comprising one or more epitaxial layers is grown or formed on a substrate 102. In one or more embodiments, the epitaxial stack 109 comprises one or more of a first epitaxial layer 104, a first epitaxial layer 106, and a second epitaxial layer 108. In one or more embodiments, the first epitaxial layer 106, the first epitaxial layer 106, and the second epitaxial layer 108 are doped silicon layers. In one or more embodiments, the presence of the first epitaxial layer 106 and the second epitaxial layer 108 is optional, but the presence of the first epitaxial layer 104 is required. Therefore, the structure of the epitaxial layer on the substrate 102 may include any configuration shown in Figures 2A to 2D, although the structure in Figure 2A is used in subsequent Figures 3 to 17B for ease of illustration.

[0024]

[0049] In one or more embodiments, the first epitaxial layer 104 may include a highly doped epitaxial layer. In one or more embodiments, the highly doped epitaxial layer includes one or more N+ silicon doped with one or more of phosphorus (P), arsenic (As), and tin (Sn). In other embodiments, the highly doped epitaxial layer includes P+ silicon doped with one or more of boron (B), aluminum, gallium (Ga), and carbon (C). In further embodiments, the highly doped epitaxial layer includes one or more of carbon-doped N+ silicon, germanium-doped N+ silicon, carbon-doped P+ silicon, and germanium-doped P+ silicon.

[0025]

[0050] In one or more embodiments, the first epitaxial layer 104 is N+ silicon doped with one or more of phosphorus (P), arsenic (As), carbon (C), germanium (Ge), or tin (Sn). In other embodiments, the first epitaxial layer 104 is P+ silicon doped with one or more of boron (B), aluminum (Al), gallium (Ga), and carbon (C). The first epitaxial layer 104 may have any suitable thickness. In one or more embodiments, the first epitaxial layer 104 has a thickness in the range of 20 nm to 500 nm. While not intended to be theoretically binding, it is assumed that the first epitaxial layer 104 should have a higher removal rate compared to silicon in a particular etching process. The first epitaxial layer 104 can be grown by any suitable process. In one or more embodiments, the first epitaxial layer 104 is grown in a hydrogen (H2) atmosphere at a temperature ranging from 400°C to 1100°C using a precursor comprising one or more of DCS, siren, or TCS.

[0026]

[0051] In one or more embodiments, the primary epitaxial layer 106 is boron (B)-doped P+ silicon. The primary epitaxial layer 106 may have any suitable thickness. In one or more embodiments, the primary epitaxial layer 106 has a thickness in the range of 5 nm to 50 nm. Although not intended to be theoretically binding, it is assumed that the primary epitaxial layer 106 should have a higher removal rate compared to silicon in a particular etching process. The primary epitaxial layer 106 can be grown by any suitable process. In one or more embodiments, the primary epitaxial layer 106 is grown in a hydrogen (H2) atmosphere at a temperature in the range of 400°C to 1100°C using a precursor containing one or more of DCS, siren, or TCS. In some embodiments, the first epitaxial layer 106 has a different dopant concentration than the first epitaxial layer 104 (or the highly doped epitaxial layer). In one or more embodiments, the primary epitaxial layer 106 has a different dopant type than the first epitaxial layer 104 (or the highly doped epitaxial layer).

[0027]

[0052] In one or more embodiments, the second epitaxial layer 108 is epitaxially doped silicon. While not intended to be theoretically binding, the second epitaxial layer 108 is expected to enhance etching stop capability during subsequent etching of memory holes. The second epitaxial layer 108 may have any suitable thickness. In one or more embodiments, the second epitaxial layer 108 has a thickness in the range of 5 nm to 50 nm. The second epitaxial layer 108 can be grown by any suitable process. In one or more embodiments, the second epitaxial layer 108 is grown in a hydrogen (H2) atmosphere at a temperature in the range of 400°C to 1100°C using a precursor containing one or more of DCS, siren, or TCS. In some embodiments, the second epitaxial layer 108 has a different dopant concentration than the first epitaxial layer 104 (or the highly doped epitaxial layer). In one or more embodiments, the second epitaxial layer 108 has a different dopant type than the first epitaxial layer 104 (or the highly doped epitaxial layer).

[0028]

[0053] Referring to Figures 1 and 3 to 12, in step 14, a memory array is formed on the first epitaxial layer 104. Referring to Figure 3, in one or more embodiments, a laminate 114 is formed on the epitaxial stack 109. The laminate 114 in the illustrated embodiments includes a plurality of alternating layers of first material layers 110 and second material layers 112. In one or more embodiments, the first material layer 110 includes an oxide layer, and the second material layer 112 includes a nitride layer. The second material layer 112 includes a material that is etching selective to the first material layer 110 so that the second material layer 112 can be removed without substantially affecting the first material layer 110. In one or more embodiments, the second material layer 112 includes one or more of polysilicon, silicon nitride (SiN), silicon carbide (SiC), silicon oxycarbide (SiOC), germanium (Ge), and titanium nitride (TiN). In one or more embodiments, the second material layer 112 includes silicon nitride. In one or more embodiments, the first material layer 110 includes silicon oxide.

[0029]

[0054] Each alternating layer can be formed to an appropriate thickness of any choice. In some embodiments, the thickness of each second material layer 112 is approximately equal. In one or more embodiments, each second material layer 112 has the thickness of the first second layer 112. In some embodiments, the thickness of each first material layer 110 is approximately equal. When used in this respect, approximately equal thickness is within + / - 5% of each other. In some embodiments, a silicon layer (not shown) is formed between the second material layer 112 and the first material layer 110. The thickness of the silicon layer may be relatively thin compared to the thickness of the second material layer 112 or the first material layer 110.

[0030]

[0055] In one or more embodiments, at least one memory hole channel 116 is opened through the laminate 114. In some embodiments, opening the memory hole channel 116 involves etching through the laminate 114 to the epitaxial stack 109. Referring to Figure 4, the memory hole channel 116 has side walls that penetrate the laminate 114, exposing the surface 120 of the second material layer 112 and the surface 118 of the first material layer 110. The memory hole channel 116 extends to the epitaxial stack 109 such that the bottom 122 of the memory hole channel 116 is the uppermost surface of the epitaxial stack 109.

[0031]

[0056] In one or more embodiments, the memory hole channel 116 has a high aspect ratio. As used herein, the term “high aspect ratio” refers to a feature having a height-to-width ratio of about 10, 20, 50, 100, or more.

[0032]

[0057] Referring to Figure 5, the memory hole channel 116 deepens to etch the first epitaxial layer 104. The first epitaxial layer 104 can be etched by any preferred means. In one or more embodiments, the first epitaxial layer 104 is etched using a plasma etching process that includes chlorine (Cl2) and helium (He). In one or more embodiments, etching the epitaxial layer 104 leaves a thin layer of the epitaxial layer 104 on the substrate 102. Thus, in one or more embodiments, the bottom 126 of the memory hole channel 116 can be formed at any point within the thickness range of the first epitaxial layer 104. In some embodiments, the memory hole channel 116 extends within the first epitaxial layer 104 to a thickness ranging from about 10% to about 90%, or from about 20% to about 80%, or from about 30% to about 70%, or from about 40% to about 60% of the thickness of the first epitaxial layer 104. In some embodiments, the memory hole channel 116 extends within the first epitaxial layer 104 for a distance of 10 nm or more. In some embodiments, the memory hole channel 116 extends from the top surface of the memory stack 114 to the top surface of the substrate 102.

[0033]

[0058] Referring to Figures 6A and 6B, the memory cells are formed within the memory hole channel 116. Figure 6A shows the deposition of the transistor layer 128 within the memory hole channel 116. The transistor layer 128 can be formed by any suitable technique known to those skilled in the art. In some embodiments, the transistor layer 128 is formed by a conformal deposition process. In some embodiments, the transistor layer is formed by one or more of atomic layer deposition or chemical vapor deposition.

[0034]

[0059] In one or more embodiments, the deposition of the transistor layer 128 is substantially conformal. As used herein, a “substantially conformal” layer is one in which the thickness is substantially the same throughout (for example, at the top, middle, and bottom of the sidewalls, and at the bottom of the memory hole channel 114). The thickness of a substantially conformal layer varies by about 5%, 2%, 1%, or 0.5% or less. The transistor layer 128 within the memory hole may include one or more of a blocking layer, a trapping layer, a tunneling layer, and a polysilicon channel.

[0035]

[0060] Referring to Figure 6B, which is an enlarged view of region 132 in Figure 6A, in one or more embodiments, the transistor layer 128 includes a blocking oxide layer 128a, a nitride trap layer 128b, a tunnel oxide layer 128c, and a channel material 128d within the memory hole channel 114. In one or more embodiments, the memory hole channel 116 further includes a core oxide layer 128e. In certain embodiments, the core oxide layer 128e includes silicon oxide (SiOx).

[0036]

[0061] The transistor layer 128 may have any suitable thickness, for example, depending on the dimensions of the memory hole channel 116. In some embodiments, the transistor layer 128 has a thickness in the range of about 0.5 nm to about 50 nm, or in the range of about 0.75 nm to about 35 nm, or in the range of about 1 nm to about 20 nm.

[0037]

[0062] Figures 6A and 6B show the bit line pad 130 formed on the uppermost surface of the transistor layer 128. Although not shown, those skilled in the art will recognize that the channel material 128d and the core oxide layer 128e are recessed to form an opening, which is then filled with material to form the bit line pad 130. In one or more embodiments, the core oxide layer 128e is recessed by an amount in the range of about 100 nm to 250 nm. The bit line pad 130 may contain any suitable material known to those skilled in the art. In one or more embodiments, the bit line pad 130 contains polysilicon. In some embodiments, the polysilicon bit line pad 130 is doped. In other embodiments, the polysilicon bit line pad 130 is not doped.

[0038]

[0063] Referring to Figure 7, device 100 is slit-patterned to form a slit pattern opening 134 that extends from the top surface of stack 114 to the common source line epitaxial stack 109.

[0039]

[0064] Referring to Figure 8, the slit pattern opening 134 deepens to etch the first epitaxial layer 104. The first epitaxial layer 104 can be etched by any preferred means. In one or more embodiments, the first epitaxial layer 104 is etched using a plasma etching process that includes chlorine (Cl2) and helium (He). In one or more embodiments, etching the epitaxial layer 104 leaves a thin layer of the epitaxial layer 104 on the substrate 102. Thus, in one or more embodiments, the bottom 135 of the slit pattern opening 134 can be formed at any point within the thickness range of the first epitaxial layer 104, or, if present, within the thickness range of the first epitaxial layer 106. In some embodiments, the slit pattern opening 134 extends within the first epitaxial layer 104 to a thickness ranging from about 10% to about 90%, or from about 20% to about 80%, or from about 30% to about 70%, or from about 40% to about 60% of the thickness of the first epitaxial layer 104. In some embodiments, the slit pattern opening 134 extends within the first epitaxial layer 104 for a distance of 10 nm or more. In some embodiments, the slit pattern opening 134 extends from the top surface of the memory stack 114 to the top surface of the substrate 102.

[0040]

[0065] Figure 9 shows the location where the second layer 112 is removed. The second layer 112 can be removed by any suitable means known to those skilled in the art. In one or more embodiments, the second layer 112 is removed by selective etching, for example, selective wet etching or selective dry etching. The removal of the second layer 112 forms the opening 136.

[0041]

[0066] Figures 10A and 10B show the formation of the word line 138. Figure 10B is an enlarged view of region 137 in Figure 10A. The word line 138 comprises one or more of the oxide layer 138a, the barrier layer 138b, and the word line metal 138c. The oxide layer 138a may comprise any suitable material known to those skilled in the art. In one or more embodiments, the oxide layer 138a is an aluminum oxide layer. The barrier layer 138b may comprise any suitable material known to those skilled in the art. In one or more embodiments, the barrier layer 138b comprises one or more of the following: titanium nitride (TiN), tantalum nitride (TaN), etc. In one or more embodiments, the ward wire metal 138c comprises a bulk metal comprising one or more of the following: copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo), platinum (Pt), tantalum (Ta), titanium (Ti), or rhodium (Rh). In one or more embodiments, the ward wire metal 138c comprises tungsten (W). In other embodiments, the ward wire metal 138c comprises ruthenium (Ru). In one or more embodiments, the ward wire 138 comprises one or more of the following: metals, metal nitrides, conductive metal compounds, and semiconductor materials. The metal may be selected from one or more of tungsten (W), molybdenum (Mo), tantalum (Ta), niobium (Nb), osmium (Os), zirconium (Zr), iridium (Ir), rhenium (Re), or titanium (Ti). The metallic nitride may be selected from one or more of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), and zirconium nitride (ZrN). The conductive metallic compound may be selected from one or more of tungsten oxide (WOx), ruthenium oxide (RuOx), and iridium oxide (IrOx). The semiconductor material may be selected from one or more of silicon (Si), silicon germanium (SiGe), and germanium (Ge).

[0042]

[0067] Figure 11 shows where the slit 134 is filled with a liner 140 and a conductive material 142. The liner 140 may include any suitable material known to those skilled in the art. In one or more embodiments, the liner 140 includes silicon oxide (SiOx). The conductive material 142 may also be any suitable material known to those skilled in the art. In one or more embodiments, the filled slit contains a conductive material 142 selected from one or more of N+ silicon or silicon germanium (SiGe).

[0043]

[0068] Referring to Figures 1 and 12, in step 16, the memory array 144 is rotated 180 degrees so that the substrate 102 is at the top of the drawing and the top surface of the memory stack 114 is at the bottom of the drawing. The top surface 115 of the memory stack 114 is bonded to the peripheral wafer 146. The array substrate 102 and the peripheral wafer 146 are bonded by a Cu-Cu hybrid bond.

[0044]

[0069] Referring to Figures 1 and 13, in step 18, the substrate 102 is removed or polished. The substrate 102 can be removed by any suitable means known to those skilled in the art. In one or more embodiments, the substrate 102 is removed using one or more of chemical mechanical polishing (CMP) or wet etching.

[0045]

[0070] Referring to Figures 1 and 14, in step 20, the primary epitaxial layer 106 (if present) is removed. The primary epitaxial layer 106 can be removed by any suitable means known to those skilled in the art. In one or more embodiments, the primary epitaxial layer 106 is removed by CMP or etched again to expose the bottom 155 of the filled memory hole channel 128 and a portion 157 of the first epitaxial layer 104.

[0046]

[0071] Referring to Figures 15A to 15B, a portion of the blocking oxide layer 128a, nitride trap layer 128b, and tunnel oxide layer 128c present within the epitaxial layer 104 is removed to form the opening 150. The portion of the blocking oxide layer 128a, nitride trap layer 128b, and tunnel oxide layer 128c present within the epitaxial layer 104 can be removed by any suitable means known to those skilled in the art. In one or more embodiments, the portions of the blocking oxide layer 128a, nitride trap layer 128b, and tunnel oxide layer 128c present within the epitaxial layer 104 are removed by wet etching or selective dry etching to form the opening 150. By forming the opening 150, the channel material 128d within the epitaxial layer 104 is exposed.

[0047]

[0072] Referring to Figures 1 and 16A to 16B, in step 22, the first material 152 is deposited in the opening 150. The first material 152 may include any suitable material known to those skilled in the art. In one or more embodiments, the first material 152 is silicon (Si), carbon-doped silicon (SiC), phosphorus-doped silicon (SiP x ), silicon germanium (SiGe), carbon-doped germanium (GeC), carbon-doped silicon germanium (SiGeC), and phosphorus-doped silicon germanium (SiGeP x The first material 152 may be deposited by any suitable means known to those skilled in the art. In one or more embodiments, the first material 152 is deposited by low-temperature epitaxial growth or low-temperature chemical vapor deposition (CVD).

[0048]

[0073] In other embodiments, the first material 152 comprises a metal silicide. The metal silicide may be any suitable metal silicide known to those skilled in the art. In one or more embodiments, the metal silicide comprises one or more of titanium silicide (TiSi), tungsten silicide (WSi), nickel platinum silicide (NiPtSi), and cobalt silicide (CoSi). The metal silicide may be deposited by any suitable means known to those skilled in the art. In one or more embodiments, the metal silicide is deposited by one or more of physical vapor deposition (PVD) or low-temperature chemical vapor deposition (CVD). In other embodiments, the metal silicide is formed by metal deposition followed by silicidding annealing.

[0049]

[0074] Referring to Figures 1 and 17A to 17B, in step 24, a contact 153 is formed adjacent to the filled slit pattern 142. The contact 153 includes a contact liner 154 and a contact metal 156. The contact liner 154 may include any suitable material known to those skilled in the art. In one or more embodiments, the contact liner 154 includes one or more of titanium nitride (TiN) and tantalum nitride (TaN). The contact metal 156 may include any suitable metal known to those skilled in the art. In one or more embodiments, the contact metal 156 includes one or more of tungsten (W), copper (Cu), cobalt (Co), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo), platinum (Pt), tantalum (Ta), titanium (Ti), or rhodium (Rh). In one or more embodiments, the contact metal 156 includes tungsten (W).

[0050]

[0075] One or more embodiments relate to a method for forming a memory device. In one or more embodiments, the method includes, essentially, or consists of, forming a first epitaxial layer on a substrate and forming a memory array on the first epitaxial layer, wherein the memory array includes a memory stack of alternating layers of oxide material and metallic material on the first epitaxial layer, at least one memory cell extending from the first epitaxial layer through the memory stack, and a slit filled with filler material adjacent to the at least one memory cell.

[0051]

[0076] Other embodiments relate to methods for forming memory devices. In one or more embodiments, the method includes, essentially, or consists of, forming a first epitaxial layer on a primary epitaxial layer on a substrate; forming a memory array on the first epitaxial layer, wherein the memory array includes a memory stack of alternating layers of oxide material and metallic material on the first epitaxial layer; at least one memory cell extending from the first epitaxial layer through the memory stack; and a slit filled with a filler material adjacent to the at least one memory cell; bonding the memory array to a peripheral wafer; polishing the substrate to expose the primary epitaxial layer; removing the primary epitaxial layer; etching the first epitaxial layer to form an opening and expose a portion of the memory cell; depositing a first material in the opening; and forming contacts on the filled slit.

[0052]

[0077] Further embodiments relate to memory devices, more specifically, 3D-NAND memory devices. In one or more embodiments, a 3D-NAND memory device includes, is essentially, or consists of, a common source line having a highly doped epitaxial layer on a substrate, and at least one memory stack formed on the common source line, the memory stack including at least one memory stack having alternating layers of oxide material and metallic material, at least one memory cell extending from the common source line through the at least one memory stack, and a slit filled with a filler material adjacent to the at least one memory cell, wherein the at least one memory cell includes a semiconductor channel in contact with a highly doped epitaxial layer via a first material.

[0053]

[0078] One or more embodiments of the method is an integrated method. In one or more embodiments, the method can be carried out in one or more processing chambers without breaking the vacuum.

[0054]

[0079] Additional embodiments of this disclosure, as shown in Figure 18, relate to a processing tool 900 for forming the described logic or memory devices and methods. Method 10 of one or more embodiments is an integration method. In one or more embodiments, Method 10 may be performed in one or more processing chambers without breaking the vacuum between any of steps 12, 14, 16, 18, 20, and 22.

[0055]

[0080] In one or more embodiments, the processing tool 900 is a cluster tool including at least one central transfer station having multiple sides, for example, a first transfer chamber 921 and a second transfer chamber 931. At least one robot 925, 935 is positioned within at least one central transfer station (e.g., the first transfer chamber 921 and the second transfer chamber 931) and configured to move robot blades and wafers to each of the multiple sides.

[0056]

[0081] In one or more embodiments, the processing tool 900 is a cluster tool comprising a plurality of processing chambers 902, 904, 906, 908, 910, 912, 914, 916, and 918, also called processing stations, connected to a central transfer station. The various processing chambers provide separate processing areas isolated from adjacent processing stations. The processing chambers can be any suitable chambers, including, but are not limited to, pre-washing chambers, deposition (ALD / CVD / PVD) chambers, and epitaxial growth chambers. The specific arrangement of processing chambers and components can vary depending on the cluster tool and should not be considered as limiting the scope of this disclosure.

[0057]

[0082] In the embodiment shown in Figure 18, the factory interface 950 is connected to the front of the processing tool 900. The factory interface 950 includes a loading chamber 954 and an unloading chamber 956 on its front. The loading chamber 954 is shown on the left and the unloading chamber 956 is shown on the right, but those skilled in the art will understand that this is merely a typical example of one possible configuration.

[0058]

[0083] The size and shape of the loading chamber 954 and the unloading chamber 956 may vary depending on the substrate being processed within the processing tool 900, such as a cluster tool. In the illustrated embodiment, the loading chamber 954 and the unloading chamber 956 are sized to hold a wafer cassette in which multiple wafers are arranged within the cassette.

[0059]

[0084] Robot 952 is located within the factory interface 950 and can move between the loading chamber 954 and the unloading chamber 956. Robot 952 can transfer wafers from a cassette in the loading chamber 954 to the load lock chamber 960 through the factory interface 950. Robot 952 can also transfer wafers from the load lock chamber 962 to a cassette in the unloading chamber 956 through the factory interface 950. As will be understood by those skilled in the art, the factory interface 950 may have multiple robots 952. For example, the factory interface 950 may have a first robot that transfers wafers between the loading chamber 954 and the load lock chamber 960, and a second robot that transfers wafers between the load lock chamber 962 and the unloading chamber 956.

[0060]

[0085] In one or more embodiments, the processing tool 900 is a cluster tool having a first section 920 and a second section 930. The first section 920 is connected to the factory interface 950 through load lock chambers 960, 962. The first section 920 includes a first transfer chamber 921 in which at least one robot 925 is located. The at least one robot 925 is also called a robotic wafer transfer mechanism. The first transfer chamber 921 is centrally located relative to the load lock chambers 960, 962, processing chambers 902, 904, 916, 918, and buffer chambers 922, 924. In some embodiments, at least one robot 925 is a multi-arm robot capable of independently moving multiple wafers at once. In some embodiments, the first transfer chamber 921 includes multiple robotic wafer transfer mechanisms. At least one robot 925 within the first transfer chamber 921 is configured to move wafers between chambers around the first transfer chamber 921. Each wafer is supported on a wafer transfer blade located at the distal end of the first robotic mechanism.

[0061]

[0086] After processing the wafer in the first section 920, the wafer may be passed through a pass-through chamber to the second section 930. For example, chambers 922, 924 may be one-way or two-way pass-through chambers. Pass-through chambers 922, 924 can be used, for example, to cool the wafer to a low temperature before processing in the second section 930, or to allow cooling or post-processing of the wafer before returning it to the first section 920.

[0062]

[0087] The system controller 990 communicates with the first robot 925, the second robot 935, the first set of processing chambers 902, 904, 916, 918, and the second set of processing chambers 906, 908, 910, 912, 914. The system controller 990 can be any suitable component capable of controlling the processing chambers and robots. For example, the system controller 990 may be a computer including a central processing unit, memory, appropriate circuitry, and storage.

[0063]

[0088] The processing may generally be stored as a software routine in the memory of the system controller 990, and when executed by the processor, causes the processing chamber to execute the processing of the disclosure. The software routine may be stored and / or executed by a second processor (not shown) located remotely from the hardware controlled by the processor. Some or all of the methods of the disclosure may also be executed in hardware. Thus, the process may be implemented in software and executed by a computer system in hardware (e.g., application-specific integrated circuits or other types of hardware implementations) or in a combination of software and hardware. When executed by the processor, the software routine transforms a general-purpose computer into a dedicated computer (controller) that controls the chamber operation so that the process can be executed.

[0064]

[0089] In one or more embodiments, the processing tool includes a central transfer station including a robot configured to move a wafer; a plurality of processing stations, each processing station including one or more of a pre-cleaning chamber, a deposition chamber, and an epitaxial growth chamber, which are connected to the central transfer station and provide a processing area separated from the processing areas of adjacent processing stations; and a controller connected to the central transfer station and the plurality of processing stations, which is configured to activate the robot to move the wafer between the processing stations and to control the processing that occurs at each of the processing stations. In one or more embodiments, the controller causes the processing tool to perform operations: forming a first epitaxial layer on a substrate; forming a memory array on the first epitaxial layer, wherein the memory array includes a memory stack of alternating layers of oxide material and metallic material on the first epitaxial layer; at least one memory cell extending from the first epitaxial layer through the memory stack; and a slit filled with filler material adjacent to the at least one memory cell. In one or more embodiments, the processing tool is maintained under vacuum during each processing step.

[0065]

[0090] In the context of describing the materials and methods discussed herein (particularly in the context of the following claims), the terms “a,” “an,” and “the,” and similar references, should be interpreted as covering both singular and plural forms, unless otherwise stated herein or unless clearly contradicted by the context. The enumeration of value ranges herein is merely intended to serve as a shorthand notation for individually referring to each individual value within the range, unless otherwise stated herein, and each individual value is incorporated into the specification as if it were individually stated herein. All methods described herein may be performed in any appropriate order, unless otherwise stated herein or unless clearly contradicted by the context. Any and all examples or illustrative language provided herein (e.g., “such as”) is merely intended to better describe the materials and methods and does not impose any limitation of scope unless specifically asserted. Nothing in this specification should be interpreted as indicating any unclaimed element essential to the practice of the disclosed materials and methods.

[0066]

[0091] Throughout this specification, any reference to “one embodiment,” “a particular embodiment,” “one or more embodiments,” or “embodiment” means that a particular feature, structure, material, or property described in relation to an embodiment is included in at least one embodiment of this disclosure. Therefore, any other occurrences of the phrases “in one or more embodiments,” “in a particular embodiment,” “in one embodiment,” or “in an embodiment” throughout this specification do not necessarily refer to the same embodiment of this disclosure. Furthermore, a particular feature, structure, material, or property may be combined in any suitable manner in one or more embodiments.

[0067]

[0092] Although the disclosures herein have been described with reference to specific embodiments, these embodiments should be understood as merely illustrative examples of the principles and uses of the disclosures. It will be obvious to those skilled in the art that various modifications and variations can be made to the methods and apparatuses of the disclosures without departing from the essence and scope of the disclosures. Accordingly, the disclosures are intended to include modifications and variations that fall within the scope of the appended claims and their equivalents.

Claims

1. A method for forming a semiconductor memory device, Forming a first epitaxial layer on the substrate, Forming a memory array on the first epitaxial layer, wherein the memory array includes a memory stack of alternating layers of oxide material and metal material on the first epitaxial layer, at least one memory cell extending from the first epitaxial layer through the memory stack, and a slit filled with a filler material adjacent to the at least one memory cell. Methods that include...

2. The method according to claim 1, further comprising forming the first epitaxial layer on the primary epitaxial layer on the substrate.

3. The method according to claim 1, further comprising forming a second epitaxial layer between the first epitaxial layer and the memory array before forming the memory array.

4. The method according to claim 3, further comprising forming the first epitaxial layer on the primary epitaxial layer on the substrate.

5. The method according to claim 1, wherein the first epitaxial layer comprises N+ silicon doped with one or more of phosphorus (P), arsenic (As), and tin (Sn).

6. The method according to claim 1, wherein the first epitaxial layer comprises P+ silicon doped with one or more of boron (B), aluminum (Al), gallium (Ga), and carbon (C).

7. A 3D-NAND memory device, A common source line including a highly doped epitaxial layer on the substrate, At least one memory stack formed on the common source line, comprising alternating layers of oxide material and metal material, at least one memory cell extending from the common source line through the at least one memory stack, and a slit filled with a filler material adjacent to the at least one memory cell, The invention includes a semiconductor channel in which at least one memory cell is in contact with the highly doped epitaxial layer via a first material, Memory device.

8. The memory device according to claim 7, wherein the highly doped epitaxial layer is located on a primary epitaxial layer on the substrate.

9. The memory device according to claim 7, further comprising a second epitaxial layer between the highly doped epitaxial layer and the at least one memory stack.

10. The memory device according to claim 9, wherein the highly doped epitaxial layer is located on a primary epitaxial layer on the substrate.

11. The first material is silicon (Si), carbon-doped silicon (SiC), phosphorus-doped silicon (SiP ｘ ), silicon germanium (SiGe), carbon-doped germanium (GeC), carbon-doped silicon germanium (SiGeC), and phosphorus-doped silicon germanium (SiGeP ｘ The memory device according to claim 7, comprising one or more of the following:

12. The memory device according to claim 7, wherein the first material includes a metal silicide.

13. The memory device according to claim 12, wherein the metal silicide comprises one or more of titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel platinum silicide (NiPtSi), and cobalt silicide (CoSi).

14. The memory device according to claim 7, wherein the highly doped epitaxial layer comprises N+ silicon doped with one or more of phosphorus (P), arsenic (As), and tin (Sn).

15. The memory device according to claim 7, wherein the highly doped epitaxial layer comprises P+ silicon doped with one or more of boron (B), aluminum, gallium (Ga), and carbon (C).

16. The memory device according to claim 7, wherein the highly doped epitaxial layer comprises one or more of the following: carbon-doped N+ silicon, germanium-doped N+ silicon, carbon-doped P+ silicon, and germanium-doped P+ silicon.

17. The memory device according to claim 8, wherein the primary epitaxial layer has a different dopant type than the highly doped epitaxial layer.

18. The memory device according to claim 8, wherein the primary epitaxial layer has a dopant concentration different from that of the highly doped epitaxial layer.

19. The memory device according to claim 9, wherein the second epitaxial layer has a different dopant type than the highly doped epitaxial layer.

20. The memory device according to claim 9, wherein the second epitaxial layer has a dopant concentration different from that of the highly doped epitaxial layer.

21. A method for forming a semiconductor memory device, Forming a first epitaxial layer on a primary epitaxial layer on a substrate, Forming a memory array on the first epitaxial layer, wherein the memory array includes a memory stack of alternating layers of oxide material and metal material on the first epitaxial layer, at least one memory cell extending from the first epitaxial layer through the memory stack, and a slit filled with a filler material adjacent to the at least one memory cell. Bonding the aforementioned memory array to a peripheral wafer, The substrate is polished to expose the primary epitaxial layer, Removing the primary epitaxial layer, Etching the first epitaxial layer to form an opening and exposing a portion of the memory cell, The first material is deposited in the opening, Forming a contact on the filled slit, Methods that include...

22. The method according to claim 21, further comprising forming a second epitaxial layer between the first epitaxial layer and the memory array before forming the memory array.

23. The method according to claim 21, wherein the first epitaxial layer comprises N+ silicon doped with one or more of phosphorus (P), arsenic (As), and tin (Sn).

24. The method according to claim 21, wherein the first epitaxial layer comprises P+ silicon doped with one or more of boron (B), aluminum (Al), gallium (Ga), and carbon (C).

25. The first material is silicon (Si), carbon-doped silicon (SiC), phosphorus-doped silicon (SiP ｘ ), silicon germanium (SiGe), carbon-doped germanium (GeC), carbon-doped silicon germanium (SiGeC), and phosphorus-doped silicon germanium (SiGeP ｘ The method according to claim 21, comprising one or more of the following.

26. The method according to claim 21, wherein the primary epitaxial layer has a dopant concentration different from that of the first epitaxial layer.

27. The method according to claim 21, wherein the first material comprises a metal silicide.

28. The method according to claim 27, wherein the metal silicide comprises one or more of titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel platinum silicide (NiPtSi), and cobalt silicide (CoSi).

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