Co-packaging assembly, and method for mounting photonic dies / modules to multi-chip active / passive substrates.

Abstract

A method and apparatus are provided for manufacturing an integrated circuit package assembly comprising: a multichip package substrate having active and / or passive circuit devices embedded in one or more substrate core layers; a plurality of encapsulated integrated circuit devices mounted on the multichip package substrate; and an optical waveguide fiber connected to a photonic integrated circuit device located on either the multichip package substrate or the plurality of encapsulated integrated circuit devices, the optical waveguide fiber being optically coupled to an exposed fiber coupling region of the photonic integrated circuit device.

Description

Technical Field

[0001] The present invention generally relates to integrated circuit packages and methods of manufacturing the same. In one aspect, the present invention relates to integrated circuit package assemblies, photonic integrated circuit dies or modules mounted together on a multi-chip active / passive substrate.

Background Art

[0002] Due to the increasing cost and complexity of manufacturing integrated chips with high density requirements, facing the limitations of lithography reticles, there is an increasingly realistic upper limit on the size of integrated circuit dies that can be manufactured. Another manufacturing challenge is the increasing difficulty of integrating heterogeneous functional blocks using different transistor node and line copper interconnect schemes in the backend on a single integrated circuit chip. In addition, increasing device density means that a single defect on a single IC chip can dramatically reduce the overall yield of the wafers used to manufacture the IC chip. One promising solution to improve yield and performance at a low cost is to divide the overall circuit functionality among multiple smaller integrated circuits (or chiplets) with special functions. In this approach, assuming a uniform failure distribution rate based on the results of separate testing of individual chiplets, a smaller amount of silicon is rejected as defective than if the combined functionality was manufactured on a single chip. However, this approach also requires extensive technical challenges related to interconnecting multiple chiplets together, including potentially higher losses, lower available bandwidth, higher power consumption, and / or longer signal routing paths with higher latency. The additional interconnect complexity is caused by the different voltages, timing requirements, and protocols used by the chiplets, all of which make the chiplets appear in a less obvious manner.

[0003] One solution to address these challenges is to connect chiplets to a single semiconductor package substrate, such as a common interposer or board, thereby allowing individually tested chiplets to be reassembled and packaged into a complete final SoC, thereby yielding a significantly larger number of functional SoCs. Such assemblies are referred to as System-in-Package (SiP) assemblies. An example of such a semiconductor package substrate is described in U.S. Patent Application No. 17 / 692587, “Semiconductor Package with Integrated Circuits,” filed March 11, 2022, which is incorporated herein by reference in its entirety as fully described herein. A single semiconductor package substrate may embody a silicon interposer or board to which passive or active components are embedded, such as a network of thin-film capacitors provided for vertical power supply within the package, with capacitors embedded in the package substrate core, thereby facilitating the connection of multiple ICs in a single package for critical AI workloads, immersive consumer experiences, and high-performance computing. While existing WLP methods can provide interconnection between die pads with a pitch of <50 μm and solder balls with a pitch of approximately 0.5 mm, there are processing cost and design constraints that limit the ability of existing bumping technology solutions to achieve finer pitches while meeting the applicable performance, design, complexity, and cost constraints for packaging integrated circuit devices.

[0004] As is understood, SiP assemblies have several advantages over System-on-Chip (SoC) assemblies, including the ability to combine many different IC chips (e.g., analog, digital, and radio frequency (RF) dies) within the same package, with each die implemented using the most appropriate technical process for its domain. Furthermore, designers may employ several off-the-shelf dies coupled with a limited number of relatively small, internally developed components. However, there are challenges in combining different chips into a single package assembly, as individual dies often have different lateral and longitudinal dimensions, different heat dissipation requirements, different pitch spacing requirements, etc. There are also interface-related challenges in integrating different types of circuits, such as optical and electrical circuits. As a result, existing solutions for providing SiP assemblies are extremely difficult at a practical level. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] U.S. Patent Application No. 17 / 692587 [Overview of the project]

[0006] The present invention, as well as its many purposes, features, and advantages, can be understood by considering the following detailed description in conjunction with the following drawings. [Brief explanation of the drawing]

[0007] [Figure 1a] This figure shows the development of integrated circuit package assemblies for integrating optical elements and switch ASIC dies. [Figure 1b] This figure shows the development of integrated circuit package assemblies for integrating optical elements and switch ASIC dies. [Figure 1c]This figure shows the development of integrated circuit package assemblies for integrating optical elements and switch ASIC dies. [Figure 1d] This figure shows the development of integrated circuit package assemblies for integrating optical elements and switch ASIC dies. [Figure 2] This is a simplified cross-sectional view of an integrated circuit package assembly where edge coupling is used to connect fibers to a photonic integrated circuit. [Figure 3] This is a simplified cross-sectional view of an integrated circuit package assembly in which grating coupling is used to connect fibers to a photonic integrated circuit. [Figure 4] This is a simplified cross-sectional view of an integrated circuit package assembly, including a multi-chip substrate in which a photonic integrated circuit is embedded, connected to a mounted ASIC die having a built-in electronic integrated circuit, according to a selected embodiment of the present disclosure. [Figure 5] This is a simplified cross-sectional view of an integrated circuit package assembly, including a multi-chip substrate in which photonic integrated circuits are embedded and connected to individual mounted electronic integrated circuits, according to a selected embodiment of the present disclosure. [Figure 6] This is a simplified cross-sectional view of an integrated circuit package assembly including a multi-chip substrate in which face-up photonic integrated circuits are embedded, according to a selected embodiment of the present disclosure. [Figure 7] This is a simplified cross-sectional view of an integrated circuit package assembly, comprising a multi-chip substrate in which an embedded face-up photonic integrated circuit is located within a blind cavity, according to a selected embodiment of the present disclosure. [Figure 8] A series of simplified cross-sectional views illustrating a blind cavity manufacturing process for embedding a photonic integrated circuit into a multi-chip substrate, according to selected embodiments of the present disclosure. [Figure 9] A series of simplified cross-sectional views illustrating a through-cavity manufacturing process for embedding a photonic integrated circuit into a multi-chip substrate, according to selected embodiments of the present disclosure. [Figure 10]A series of simplified cross-sectional views illustrating a through-cavity fabrication process for using a sacrificial protection layer when embedding a photonic integrated circuit in a multi-chip substrate, according to selected embodiments of the present disclosure. [Figure 11] This is a simplified cross-sectional view of an integrated circuit package assembly, including a multi-chip substrate mounted on a face-down photonic integrated circuit and an ASIC circuit, according to a selected embodiment of the present disclosure. [Figure 12] Simplified plan view and simplified perspective view of a face-down photonic integrated circuit overhanging a mounted multi-chip substrate below, according to a selected embodiment of the present disclosure. [Figure 13] Simplified plan view and simplified perspective view of a face-down photonic integrated circuit that overhangs a notched region from a mounted multichip substrate below, according to a selected embodiment of the present disclosure. [Figure 14] A simplified cross-sectional view of an integrated circuit package assembly including a multi-chip substrate mounted on a face-down photonic integrated circuit connected to an optical fiber using vertical back coupling, according to a selected die-level reconfiguration embodiment of the present disclosure. [Figure 15] This is a simplified cross-sectional view of an integrated circuit package assembly including a multi-chip substrate mounted on a face-down photonic integrated circuit connected to an optical fiber using vertical back coupling, according to a selected substrate-level reconfiguration embodiment of the present disclosure. [Figure 16] This is a simplified flowchart illustrating a method for manufacturing a package assembly in which a photonic integrated circuit die is copackaged with a multi-chip package substrate, according to selected embodiments of the present disclosure. [Modes for carrying out the invention]

[0008] Disclosed are integrated circuit package assemblies and associated manufacturing methods for forming integrated circuit package assemblies having encapsulated photonic integrated circuit (IC) dies or chip modules embedded in or mounted on a multi-chip package substrate on which active and / or passive circuit elements or devices are embedded. In embodiments in which the photonic IC is embedded in a multi-chip package substrate, waveguide fibers can be attached to the face-up embedded photonic IC using an edge coupling mechanism. When manufacturing a photonic IC embedded in a multi-chip package substrate, a sacrificial protection layer can be formed on the fiber coupling region of the face-up embedded photonic IC to protect the fiber coupling region until the waveguide fiber is attached. In addition, or alternatively, the embedded photonic IC may be formed in the multi-chip package substrate such that electrical connections are included on both the top and bottom surfaces of the photonic IC, or on only one of the surfaces. In other embodiments in which the photonic IC is mounted on a multi-chip package substrate, waveguide fibers can be attached to the face-down photonic IC using an edge coupling or grating coupling mechanism. When a face-down photonics IC is mounted on a multi-chip package substrate, the active face-down surface of the photonics IC is positioned to extend beyond the sides of the multi-chip package substrate so that waveguide fibers can be attached to the exposed fiber-coupled region on the active face-down surface of the photonics IC using an edge coupling mechanism. Alternatively, when a face-down photonics IC is mounted on a multi-chip package substrate, the back surface of the photonics IC can be thinned, and then waveguide fibers can be attached to the back surface of the face-down photonics IC using a vertical back surface or grating coupling mechanism.

[0009] In a selected die-level reconfiguration embodiment, one or more photonic ICs are mounted on a first transient carrier as part of a plurality of multi-height integrated circuit dies or chip modules. After the multi-height integrated circuit dies or chip modules are encapsulated in a molding compound, a grinding process can be applied to expose the integrated circuit dies or chip modules on a flat heat dissipation surface. Subsequently, the encapsulated and ground integrated circuit dies or chip modules are transferred to a second transient carrier to form an assembly interface of interconnecting conductor structures (e.g., microbumps, C4 bumps, solder balls, Cu-Cu junctions, nanosintered silver, or Cu) on the integrated circuit dies or chip modules. Subsequently, the integrated circuit dies or chip modules are transferred to a dicing tape to separate them into individual modules. Each individual module may be mounted on a multi-chip package substrate with embedded active and / or passive circuit elements, after which a heat sink lid / cover can be formed such that one or more thermal conductive layers are in contact with at least the exposed integrated circuit dies / chip modules. By applying a selective etching process to remove the heat sink cover, the fiber coupling region on the back surface of the photonic IC can be exposed and thinned, thereby allowing waveguide fibers to be attached to the fiber coupling region of the photonic IC using a vertical back or grating coupling mechanism.

[0010] In selected substrate-level reconfiguration embodiments, a panel of a package substrate with embedded active and / or passive circuit elements is mounted on a temporary carrier. Subsequently, multiple multi-height integrated circuit dies or chip modules (including one or more photonic ICs) having an assembly interface of interconnect conductor structures are mounted to each of the package substrates. After the multi-height integrated circuit dies or chip modules are encapsulated in a molding compound, a grinding process can be applied to expose the integrated circuit dies or chip modules on a flat heat dissipation surface, and the encapsulated and ground panel of the integrated circuit dies or chip modules is then transferred to a dicing tape to be pieced into individual modules that can be mounted on a heat sink lid / cover with one or more thermal conductive layers in contact with at least the exposed integrated circuit die / chip module. By applying a selective etch process to remove the heat sink lid / cover, the back surface of the photonic IC can be exposed and thinned, and then a vertical back or grating coupling mechanism can be formed for attaching waveguide fibers to the fiber coupling region of the thinned photonic IC. Subsequently, the encapsulated panel / package substrate can be pieced into individual integrated circuit package assemblies.

[0011] Next, various exemplary embodiments will be described in detail with reference to the accompanying drawings. While various details are described below, it will be understood that the present invention can be carried out without these specific details, and that numerous implementation-specific decisions can be made to the invention described herein to achieve specific objectives of the device designer, such as compliance with process technology or design-related constraints, which will vary from implementation to implementation. Such development efforts may be complex and time-consuming, but nevertheless, they are routine work for those skilled in the art who are interested in this disclosure. For example, selected embodiments are shown with reference to simplified cross-sectional views of the package assembly without including all device features or geometric shapes, in order to avoid limiting or obscuring the invention. Throughout this detailed description, it should also be noted that certain materials are formed and removed to manufacture the package assembly structure. Where specific procedures for forming or removing such materials are not detailed below, it is intended that the prior art for growing, depositing, removing, or otherwise forming such layers of appropriate thickness is intended for those skilled in the art. Such details are well known, and it is considered unnecessary to instruct those skilled in the art on how to manufacture or use the present invention.

[0012] To provide contextual background information for this disclosure, we will now refer to Figures 1a to 1d illustrating the development of optical element and ASIC integration over time, where the ASIC die provides computational functionality in the electrical domain and the optical element die converts signals from the electrical domain to the optical domain and vice versa. As these figures show, there is a general trend in the fields of networking and high-performance computing to bring optical transceiver functionality closer to ASIC computing functionality. This trend is driven by the need for system performance in terms of increasing bandwidth density requirements, cost per unit capacity, and energy efficiency. However, improvements in system performance are limited by the electrical link between the ASIC die and the optical die, which is in the form of a long copper trace. While designs have been proposed to shorten this electrical link, there is a design challenge regarding the complete elimination of the electrical link, which has not been addressed by existing solutions.

[0013] To illustrate the evolving trends in integrated circuit package assemblies for integrating optical elements and ASIC circuit functionality, Figure 1a here refers to a pluggable optical element configuration for connecting a switch ASIC die 12 (or other integrated circuit such as a GPU or CPU) to an optical transceiver module 16 using a faceplate mounting technique. As shown, the switch IC die 12 is connected to a host printed circuit board (PCB) 10 via an assembly interface 11. In addition, the optical transceiver module 16 is connected to a printed circuit board (PCB) 15 via an assembly interface. When providing photonic transceiver functionality, the optical transceiver module 16 may be connected to an optical fiber 17 for transmitting and receiving optical domain signals, and may also be connected to the switch ASIC 12 for transmitting and receiving electrical domain signals. In addition, the optical transceiver module 16 may include an electrical block 16A, a photonic block 16B, and a laser unit (not shown). Depending on the technology, specifications, and cost of the system, these functions may be built as a single IC or divided into multiple ICs. For example, the photonics function may be built on a photonics-compatible silicon process technology such as Radio Frequency Silicon On Insulator (RF-SOI) and may be referred to as a silicon photonics IC (SiPh or simply photonics IC or PIC). In addition, the electronic function may be built on a 14nm or 5nm CMOS process (electronic IC or EIC). In addition, the laser may be entirely external to the optical transceiver module 16. The EIC 16A generally acts as an electrical front-end that communicates bidirectionally with the switch ASIC 12 and may also include test and control signals for the PIC 16B. The EIC 16A is connected to the PIC 16B via an electrical interface such as die routing (if the EIC 16A and PIC 16B are on the same die) or by package-level connections such as bump routing (if the EIC 16A and PIC 16B are on different dies).The PIC16B may include photonic waveguides, interferometers, resonators, filters, couplers, etc., which are constructed using appropriate semiconductor materials and processes. In this way, the PIC16B provides an optical / electrical interface for modulating / demodulating optical signals with respect to the optical fiber / fiber array 17 and communicating electrical data signals with the EIC16A. In FIG. 1a, the optical transceiver module 16 is connected to communicate with the switch ASIC 12 using a conductor or copper trace 13 that extends from the optical transceiver module 16 through the PCB 15, the Quad Small Form-factor Pluggable (QSFP) connector 14, the host PCB 10, and the assembly interface 11.

[0014] To further illustrate the trend in integrating optical elements and ASIC circuit functionality, refer to FIG. 1b showing an on-board optics configuration for connecting a switch ASIC die 22 to an optical transceiver module 26 using a mid-board mounting approach where the switch IC die 22 is connected to the host PCB 20 via an assembly interface 21 and the optical transceiver module 26 is connected to the host PCB 20 via an assembly interface 25 and an on-board optics (OBO) connector 24. In this configuration, the optical transceiver module 26 includes a PIC26B coupled to an optical fiber 28 via a connector 27 for transmitting and receiving optical domain signals. Additionally, the optical transceiver module 26 includes an EIC26A electrically connected to the switch ASIC 22 for transmitting and receiving electrical domain signals. However, the electrical connection path from the optical transceiver module 26 is much shorter since it uses a conductor or copper trace 23 that extends from the optical transceiver module 26 through the assembly interface 25, the OBO connector 24, the host PCB 20, and the assembly interface 21.

[0015] To further illustrate the trend in integrating optical elements and ASIC circuit functionality, hereby refer to Figure 1c, which shows a 2.5D integration on a common board configuration for connecting the switch ASIC die 32 to the optical transceiver module or engine 36 using a co-packaged optics (CPO) technique, where the switch IC die 32 and the optical transceiver module 36 are connected on a common board 35, which is connected to the host PCB 30 via an assembly interface 31. In this configuration, the optical transceiver module 36 includes a PIC36B coupled to an optical fiber 38 via a connector 37 for transmitting and receiving optical domain signals. In addition, the optical transceiver module 36 includes an EIC36A electrically connected to the switch ASIC 32 via copper traces 33 formed on the common board 35 for transmitting and receiving electrical domain signals. As shown in the figure, the length of the electrical connection 33 is much shorter because the electrical connection path from the optical transceiver module 36 uses a wire or copper trace 33 extending from the optical transceiver module 36 through the CPO connector 34 and the common board 35.

[0016] To further illustrate the trends in integrating optical elements and ASIC circuit functionality, Figure 1d shows a fully 3D integrated configuration for connecting a switch ASIC die 44 to an optical transceiver engine 43 integrated into an active photonic interposer 42. In this configuration, the interposer 42 can be implemented as an active photonic interposer having a fully integrated optical element 43 coupled to an optical fiber 46 via a connector 45 for transmitting and receiving optical domain signals. In addition, the interposer 42 connects the fully integrated optical element 43 to a switch ASIC 44 that implements EIC functionality. As a result, the electrical connections between the fully integrated optical element 43 and the EIC functionality are significantly reduced. Although copackage optics have been proposed, the industry has not yet achieved complete alignment with CPO, and there are many unresolved design challenges to address, not only regarding the design of copackage optics circuit configurations. In addition, there are design challenges regarding connecting optical fibers to photonic integrated circuits. Generally, there are two main methods of fiber-to-chip coupling: vertical coupling (or out-of-plane coupling) and edge coupling (or in-plane coupling), which differ in terms of the relative position of the fiber and the photonic chip. In the case of vertical coupling, grating couplers are usually used, and the fiber is positioned vertically above the PIC or slightly tilted to some extent to ensure high coupling efficiency. Grating couplers have several major advantages, including compact size, wafer-level testability, and flexible coupling position, but also several disadvantages, such as relatively low coupling efficiency, narrow bandwidth, and high wavelength sensitivity. For edge couplers, where the optical fiber is usually positioned in a wafer facet and aligned horizontally with the Si waveguide, it is common to form a V-groove on the side edge of the photonic IC, thereby providing an opening used to align the coupling or connection of the optical fiber to the end-fire waveguide on the photonic IC. Edge couplers can achieve fairly high coupling efficiency, wide bandwidth, and polarization independence, but also have several limitations, including a relatively larger footprint than grating couplers, fixed coupling position, and stricter requirements for the coupling facet.

[0017] To illustrate some of the design challenges related to connecting optical fibers to photonic integrated circuits, hereby refer to Figure 2, which shows a simplified cross-sectional view of integrated circuit package assemblies 51-55 in which edge coupling is used to connect optical waveguide fibers 56 to the active area 54 of the photonic integrated circuit 55. As shown in the figure, the photonic IC 55 has an active area 54 formed on the bottom surface of the photonic IC 55. On the bottom surface, a first-level interconnect 53 is formed to connect the photonic IC 55 to the first surface of the substrate 51 below, and is filled with an underfill layer or material 52. On the second opposing surface of the substrate 51, a second-level interconnect 50 is formed for electrical connection to a PCB or other external circuit configuration (not shown). At the first side edge of the photonic IC 55, the optical fiber 56A and waveguide 56B are positioned for edge coupling to the active area 54 of the photonic IC 55. As will be understood by those skilled in the art, edge coupling refers to a technique in which one or more optical fibers are abutted against the edge of an end-fire waveguide on a photonic IC. Because edge coupling is sensitive to the alignment between the optical fiber 56A and the active area 54, V-grooves may be formed on the side edges of the photonic IC to provide openings used to align the coupling or connection of the optical fibers to the end-fire waveguide on the photonic IC. However, as the number of optical fibers increases to provide more bandwidth, the size of the V-groove dimensions and fiber diameters begin to decrease, thereby requiring expensive active fiber alignment techniques that require the fiber coupling area of ​​each photonic IC to be exposed for a fiber pick-and-place handler to view and actively align the optical fibers.

[0018] To illustrate other design challenges related to connecting optical fibers to photonic integrated circuits, hereby refer to Figure 3, which shows a simplified cross-sectional view of integrated circuit package assemblies 60-65 in which grating coupling is used to connect optical waveguide fibers 68 to the active area 64 of the photonic integrated circuit 65. As shown, the active area 64 at the bottom of the photonic IC 65 is connected to the first surface of the substrate 61 below via a first-level interconnect 63, where an underfill layer or material 62 surrounds the first-level interconnect 63 between the photonic IC 65 and the substrate 61. On the second opposing surface of the substrate 51, a second-level interconnect 50 is formed for electrical connection to a PCB or other external circuit configuration (not shown). On the fiber coupling region formed on the upper surface of the photonic IC 55, the optical fibers 68A and waveguide 68B are positioned for vertical coupling or grating coupling to the active area 64 of the photonic IC 65. As will be understood by those skilled in the art, grating coupling describes a coupling mechanism in which light is coupled across the vertical thickness of the photonic IC 65, thereby resulting in a beam-expanding effect 66 in which the light is partially diffused by the body of the photonic IC. As a result of this diffusion effect, grating couplers have the inefficiency of requiring complex mirror and lens structures 67 to obtain a reasonable level of optical transmission efficiency. Grating couplers are less sensitive to alignment problems than edge couplers, but are more sensitive to the distance between the active area 64 and the lens 67. One solution to the diffusion problem is to shorten the working distance between the active area 64 and the lens 67, for example by applying local thinning of the photonic IC 65, but this makes it difficult to handle the photonic IC 65 during assembly and also makes it difficult to attach thermal heat / cover dissipation structures to the photonic IC 65 during subsequent processing.

[0019] As mentioned above, the trend in integrating optical elements and ASIC circuits is to bring photonic functionality very close to ASIC computing functionality using co-package optics (CPO) integration. However, the use of silicon photonics (SiPh) die manufacturing technology and fiber coupling processes must be compatible with state-of-the-art advanced packaging flow and assembly technologies, and there are several challenges in implementing co-package optics using SiPh die manufacturing technology.

[0020] For example, existing photonic ICs are typically mounted face-up (active side up) with the "face-up" pads wire-bonded to the underlying package substrate / board, thereby allowing the exposed fiber coupling area on the "face-up" surface to use conventional fiber mounting processes. However, advanced packaging options now utilize flip-chip mounting processes where the die is "face-down," thereby connecting to the underlying package substrate / board via solder bumps (e.g., C4 bumps), microbumps (solder with copper pillars), etc. While such flip-chip connections allow for more connections compared to wire bonding, mounting optical fibers to the "face-down" surface of the photonic IC is difficult. To enable edge coupling of optical fibers to face-down photonic ICs, the package assembly can position the photonic IC so that it extends beyond or over the underlying substrate, thereby exposing the fiber mounting area on the exposed underside of the photonic IC. However, "overhang" techniques have difficulties, including underfill bleed-out and incompatibility with state-of-the-art advanced packaging techniques. For example, advanced packaging techniques require high-density, fine-pitch wiring between two or more dies and die stacks via silicon interposers or wafer-level fan-out (both wafer-level processes). In addition, or alternatively, it may be necessary to etch notch areas into the underlying substrate to accommodate optical waveguide fibers that are too thick to fit beneath the overhanging photonic IC. Thus, advanced packaging techniques are not suitable for forming overhanging dies or notches in them to support edge-coupled optical fiber connections.

[0021] The use of overhanging "face-down" photonic ICs also presents compatibility challenges with state-of-the-art thermal solutions in multi-die packages (e.g., 2.5D silicon interposers, multi-die fan-out packages, bridges, etc.) that require flat tops or backs of multiple dies to mount heat spreader lids or covers. In particular, when co-packaging dissimilar dies or die stacks, their heights may not be the same, resulting in a non-flat back. Existing solutions can address this by forming a molded cover and then back-grinding the molded compound to achieve a uniform height across all dies. However, in the case of overhanging photonic ICs, the use of back-grinding is not feasible because it cannot withstand the mechanical grinding stress.

[0022] Another compatibility challenge with state-of-the-art thermal solutions is reflow compatibility, which involves attaching optical waveguide fibers during the optical copackaging process. For example, optical waveguide fibers are typically attached to photonic ICs using optical fiber ferrules, tacking adhesives, and glove-top materials. Unfortunately, these materials cannot withstand the reflow temperatures (>240C) of the optical copackaging process that is often used. There are also problems caused by dangling fibers throughout the rest of the module and system integration process. While some advances have been made to make ferrules and glove-top materials more heat-resistant, it is difficult to fabricate fiber tack adhesives that can withstand high temperatures because obtaining better optical and heat-resistant properties of polymers is inversely correlated.

[0023] To provide a better understanding of the aforementioned challenges of connecting optical fibers to photonic ICs, the Specified herein discloses integrated circuit package assemblies and related methods for manufacturing encapsulated photonic integrated circuit (IC) dies or chip modules that enable reflow optical waveguide fiber mounting to fiber-coupled regions on the photonic ICs, which can be exposed while still being tightly integrated with a copackaged ASIC die. For this purpose, the disclosed integrated circuit package assemblies eliminate the need for interposers or fan-out modules by integrating or mounting one or more photonic ICs to a multi-chip package substrate having integrated fine-pitch wiring layers and embedded passive and active components within a substrate core, where each photonic IC includes an exposed fiber-coupled region that can be connected to optical fibers using any suitable fiber mounting process and materials.

[0024] For a better understanding of selected embodiments of the present disclosure, we refer here to Figure 4, which shows a simplified cross-sectional view of an integrated circuit package assembly 4 including a multi-chip substrate 86 on which photonic integrated circuits 82A, 82B are embedded, connected to a mounted ASIC die 89 having built-in electronic integrated circuits 88A, 88B. As shown, the integrated circuit package assembly 4 is mounted as a flip-chip package, with the ASIC die / chip module 89 connected to the multi-chip substrate 86 using first-level interconnects 87 (e.g., solder bumps or microbump conductors), and the multi-chip substrate 86 being externally connected using second-level interconnects 80 (e.g., solder balls or bumps). As understood, the first and second-level interconnects 87, 80 are not limited to solder balls / bumps and may include land grid arrays (LGA), ball grid arrays (BGA), etc.

[0025] The ASIC die / chip module 89 has built-in electronic integrated circuits 88A, 88B, which are positioned on the periphery side of the ASIC die / chip module 89 and have a face-down active layer. The multi-chip substrate 86 has one or more face-up photonic ICs 82A, 82B embedded in the substrate core 83, either alone or in combination with other active / passive (AC / DC) components 84. In addition, the embedded photonic ICs 82, core 83, and AC / DC chip / module 84 are sandwiched between a first or upper redistribution line (RDL) stack 85 and a second or lower RDL stack 81. (Although shown in a simplified form as a single layer, each stack 81, 85 will be understood to be a combination of conductive elements or layers formed in one or more first insulating layers). Once formed, the face-up photonic ICs 82A, 82B are positioned to overlap and align with the electronic ICs 88A, 88B. In addition, the first or upper RDL stack 85 is selectively formed or patterned to expose a fiber coupling region above the photonic ICs 82A and 82B, leaving the remaining first or upper RDL stack 85 for connecting the photonic ICs 82A and 82B to the electrical ICs 88A and 88B. In this configuration, the EIC 88 is positioned close to the PIC 82 and therefore tightly coupled with very short vertical RDL and via connections. In addition, the exposed fiber coupling region above the photonic ICs 82A and 82B is positioned to allow direct mounting to an optical waveguide fiber (not shown) without having an overhang of the photonic IC 82 and without requiring notches or etching of the multi-chip substrate 86. As a result, optical waveguide fibers can be attached to the exposed fiber coupling region on top of the face-up photonic ICs 82A and 82B using any suitable fiber attachment technique. This attachment can be performed after the board mounting process, thereby eliminating problems that arise when the optical fiber attachment material is not reflow compatible.

[0026] For a better understanding of selected embodiments of the present disclosure, we refer here to Figure 5, which shows a simplified cross-sectional view of an integrated circuit package assembly 5, which includes a multi-chip substrate 96 on which photonic integrated circuits 92 connected to a plurality of mounted dies, including individual electronic integrated circuits 98A, 98B and ASIC 99. The integrated circuit package assembly 5, which is implemented as a flip-chip package, includes a first level interconnect 97 connecting the individual chips 98-99 to the multi-chip substrate 96, and also includes a second level interconnect 90 connecting the multi-chip substrate 96 to an external circuit, such as a printed circuit board (not shown). As shown, the electronic integrated circuits 98A, 98B are positioned and mounted on the periphery side of the ASIC 99, which has a face-down active layer, so as to overlap and align with the embedded face-up photonic ICs 92A, 92B within the multi-chip substrate 96. In addition, the embedded photonic IC 92, core 93, and AC / DC chip / module 94 are sandwiched between a first or upper RDL stack 95 and a second or lower RDL stack 91. Furthermore, the first or upper RDL stack 95 is selectively formed or patterned to expose a fiber coupling region above the photonic IC 92, leaving the remaining first or upper RDL stack 95 for connecting the photonic IC 92 to the electrical IC 98. In this configuration, the EIC 98 is positioned in close proximity to the PIC 92 and therefore tightly coupled with very short vertical RDL and via connections. In addition, the exposed fiber coupling region above the photonic IC 92 is positioned to allow direct mounting to an optical waveguide fiber (not shown) without having an overhang of the photonic IC 92 and without requiring notches or etching of the multi-chip substrate 96. As a result, optical waveguide fibers can be attached to the exposed fiber coupling region on top of the face-up photonic IC92 using any suitable fiber attachment technique, and this attachment can be performed after the board mounting process, thereby eliminating problems that arise when the optical fiber attachment material is not reflow compatible.

[0027] For a better understanding of selected embodiments of the present disclosure, refer here to Figure 6, which shows a cross-sectional view of an integrated circuit package assembly 6 in which a plurality of die / chip modules 121-123 are fixed to multi-chip package substrates 101-115 in which active and / or passive modules 108-111 and face-up photonic ICs 107, 112 are embedded. As shown, the integrated circuit package assembly 6 is mounted as a flip-chip package, and the die / chip modules 121-123 are connected to each other and to a printed circuit board 100 using defined conductive elements and the active and / or passive modules embedded in the multi-chip package substrates 101-115. In particular, the flip-chip package assembly has a plurality of surface-mountable die or module devices 121-123, including individual electronic integrated circuits 121, 123 and ASIC 122. The illustrated die / module devices 121-123 are mounted to the first surface or top surface of the multichip package substrates 101-115 using a set of first-level interconnects 120, such as solder bumps or microbump conductors. Similarly, the second surface or bottom surface of the multichip package substrates 101-115 is mounted to the printed circuit board 100 using a set of second-level interconnects 101, such as a plurality of solder balls or bumps.

[0028] To support and enable electrical connections between die / chip modules 121-123 and the printed circuit board 100, the multi-chip package substrates 101-115 include a substrate core formed of an insulating material (e.g., plastic and / or glass fiber) sandwiched between first and second redistribution (RDL) stacks 102-104, 113-115. One or more embedded active and / or passive modules 107-112 are formed on the substrate core. As shown, the multiple embedded active and / or passive modules 107-112 may be formed separately in separate cavities of the substrate core, which will be separated from each other by an intervening insulating layer 105, but in other embodiments, the embedded active and / or passive modules 107-112 may be formed in a single continuous cavity of the substrate core.

[0029] As shown in the figure, the embedded active and / or passive modules 107-112 may contain a variety of different circuit components that can take on any suitable form, shape, size, thickness, or structure. In addition, one or more of the embedded active and / or passive modules 107-112 can be positioned in alignment with the outline or power domain of the IC die / chip modules 121-123. For example, there may be design and performance benefits from positioning one or more surface-mountable devices (e.g., die / module 122) such that the underlying embedded circuit components (e.g., capacitor C2 or active circuit component A3) have a "shadow" in which they are positioned. As a result, each embedded circuit component may conform to the physical layout or profile of each domain / functional block of a single surface-mountable device. One or more embedded circuit components can be positioned to serve a single surface-mountable device beneath their shadow, while the connection between the capacitor and the surface-mountable device via the package RDL stack 113-115 can also enable the embedded circuit components to serve multiple surface-mountable devices.

[0030] By providing exemplary embedded circuit components, one or more "face-up" photonic IC dies 107, 112 can be embedded in a multi-chip substrate. In addition, the multi-chip substrate may include an embedded vertical planar capacitor C1 in an embedded module 108 which includes a pair of capacitor plates formed from a conductive via structure 106 separated by a capacitor dielectric. In addition, or alternatively, the multi-chip substrate may include a second embedded vertical multilayer capacitor C2 in an embedded module 109 which consists of sandwiched capacitor plate layers including alternating conductive fingers attached to the conductive via structure 106 and separated by a capacitor dielectric. Thus, any suitable capacitor, including multilayer ceramic capacitors (MLCCs), thin-film bases (Al, Ta, etc.), polymer caps, etc., can be embedded, and combinations of different types of capacitors for different voltages (1.2V, 5V, 100V depending on the capacitor), frequencies, and densities can be included. To provide another example of embedded circuit components, the multichip board may include an active circuit component A3 in the embedded module 110 to implement specific power, RF, digital, and / or photonic functionalities such as filtering power noise, converting and / or adjusting regulated voltages, and assisting in inter-die communication. Also to provide another example of embedded circuit components, the multichip board may include a passive circuit component P4 in the embedded module 111, which may include any type of passive component such as a capacitor, resistor, or inductor.

[0031] As shown in the figure, one or more of the embedded active and / or passive modules 107-112 may be connected to the first and second RDL stacks 102-104, 113-115 on both the top and bottom surfaces so that electrical signals and / or heat conduction can pass between the first and second level interconnects 101, 120. However, it will be understood that one or more of the photonic ICs may be connected to the RDL stack on only one side, as shown in photonic IC 107 which is connected only via the first RDL stack 113-115 to the electronic IC 121.

[0032] By forming at least a portion of the multi-chip substrate with embedded capacitors, at least a portion of the vertical connections of the first and second RDL stacks 102-104, 113-115 can connect the capacitors to external circuit configurations on PCB 100 and to at least one of the mountable IC die / chip modules 121-123 for filtering AC noise from DC power. Furthermore, by embedding or forming the multi-chip substrate with capacitors and providing vertical delivery of DC power via the capacitors, RC signal delays and insufficient device density caused by the use of decoupling capacitors with terminals on the left and right sides are avoided for lateral power delivery and signal routing via capacitors or placement of capacitors on the surface of the package.

[0033] The multichip substrate also includes one or more defined conductive signal or power via elements 106 for providing electrical and / or thermal conduction paths through the multichip substrate and embedded active and / or passive modules 107-112. The conductive signal or power via elements 106 may be formed as conductive via structures extending through the multichip substrate and having top and bottom terminal landing pads. At least one of the conductive via elements 106 is provided to allow DC power to pass vertically from the external circuit configuration 100 either directly to one or more of the die / chip modules 121-123 or through one of the embedded active / passive modules 107-112. In selected embodiments, each conductive signal or power via element 106 may be embodied as a plated-through hole (PTH).

[0034] On a first surface or top surface of a multichip substrate, the first RDL stacks 113-115 may include a set of first-level interconnects 120 defined conductive signal or power via elements 106, and conductive elements 114 formed within one or more insulating layers 113 for connecting to embedded active and / or passive modules 107-112. When used to interconnect to IC die / chip modules 121-123, the first RDL stacks 113-115 may have fine-pitch routing layers. In addition, one or more fine-pitch IC traces 115 may be provided within the first RDL stack for signal transmission between die / chip modules 121-123. Furthermore, on the second surface or bottom surface of the multichip substrate, the second RDL stacks 102-104 may include a set of second-level interconnects 101, defined conductive signal or power via elements 106, and conductive elements 104 formed within one or more second insulating layers 103 for connecting to embedded active and / or passive modules 107-112. When used to interconnect to the second-level interconnects 101, the second RDL stacks 102-104 may have several coarse-pitch routing layers for power or I / O connections to the PCB 100. As a result of the configuration of the first and second RDL stacks 102-104, 113-115, the terminal metals can be very close to each other, and the small-pitch first-level interconnect microbumps 120 (e.g., 80 micron pitch) can be aligned perpendicularly with the second-level interconnect solder balls 101 without the need for lateral routing of DC power lines through the RDL stacks 102-104, 113-115.

[0035] As shown in the figure, the die / module devices 121-123 may be any suitable integrated circuit device, integrated passive device, or microelectromechanical system (MEMS). In a selected embodiment, the die / module devices 121-123 include individual electronic integrated circuits 121, 123 and a switch ASIC 122 mounted "face down" on multichip package substrates 101-115. By positioning and mounting the peripheral electronic integrated circuits 121, 123 of the ASIC 122 in a manner that partially overlaps with the embedded face-up photonic ICs 107, 112 in the multichip substrate 96, each photonic IC (e.g., 107) communicates closely with its corresponding electronic IC (e.g., 121).

[0036] On the upper part of the face-up photonic ICs 107, 112, the first or upper RDL stacks 113-115 may be selectively formed and / or etched to expose the fiber coupling region on the upper peripheral side of the face-up photonic ICs 107, 112, while leaving the remaining first or upper RDL stacks 113-115 for connecting the photonic ICs 107, 112 to the electrical ICs 121, 123. As a result, the optical fiber 131 can be positioned on top of the photonic IC 107 using a ferrule 130 for edge coupling with the exposed fiber coupling region before using a tacking adhesive or glove top material 132 to fix the optical fiber 131 to the photonic IC 107. By forming the multi-chip substrates 101-115 to include fiber coupling regions exposed above the photonic ICs 107 and 112, optical waveguide fibers can be directly mounted without requiring overhangs of the photonic ICs, without requiring notches or etching of the multi-chip substrates 101-115, and without requiring the optical fiber mounting material to be reflow compatible.

[0037] For a better understanding of selected embodiments of the present disclosure, refer here to Figure 7, which shows a cross-sectional view of an integrated circuit package assembly 7 in which a plurality of die / chip modules 221-223 are fixed to multi-chip package substrates 201-216, each of which is embedded with active and / or passive modules 209-212, and face-up photonic ICs 208, 213, each of which is seated or positioned in a blind cavity formed by a cavity layer 207. As shown, the integrated circuit package assembly 6 is mounted as a flip-chip package, and the die / chip modules 221-223 are connected to each other and to a printed circuit board 200 using defined conductive elements and the embedded active and / or passive modules in the multi-chip package substrates 201-216. In particular, the flip-chip package assembly has a plurality of surface-mountable die or module devices 221-223, each including individual electronic integrated circuits 221, 223, and ASIC 222, which are each mounted to a first or upper RDL stack 214-216 via first-level interconnects 220 (e.g., solder bumps or microbumps). Conductors within the first or upper RDL stack 214-216 then provide electrical and / or thermal conduction paths to embedded active and / or passive modules 208-213 within the multi-chip package substrate 201-216. As shown in the figure, the embedded active and / or passive modules 208-213 may be embedded in the substrate core layer and may include one or more different circuit components such as one or more "face-up" photonic IC dies 208, 213, an embedded vertical planar capacitor C1 in embedded module 209, an embedded sandwich multilayer capacitor C2 in embedded module 210, an active circuit component A3 in embedded module 211, and / or a passive circuit component P4 in embedded module 212. In addition, conductors in the second or lower RDL stacks 202-204 provide electrical and / or thermal conduction paths to the second level interconnect 201.

[0038] On the upper part of the face-up photonic ICs 208, 213, the first or upper RDL stacks 214-216 may be selectively formed and / or etched to expose the fiber coupling region on the upper peripheral side of the face-up photonic ICs 208, 213, while leaving the remaining first or upper RDL stacks 214-216 for connecting the photonic ICs 208, 213 to the electrical ICs 221, 223. As a result, the optical fiber 231 can be positioned on top of the photonic IC 208 using a ferrule 230 for edge coupling with the exposed fiber coupling region before using a tacking adhesive or glove top material 232 to fix the optical fiber 231 to the photonic IC 208. By forming the multi-chip substrates 201-216 to include the fiber coupling region exposed above the photonic ICs 208 and 213, optical waveguide fibers can be directly mounted without requiring an overhang of the photonic ICs, without requiring notches or etching of the multi-chip substrates 201-216, and without requiring the optical fiber mounting material to be reflow compatible. Furthermore, by forming the face-up photonic ICs 208 and 213 within a blind cavity formed by the cavity layer 207, the multi-chip substrates 201-216 can be made thicker without requiring the photonic ICs 208 and 213 to be thicker as well. As a result, the thicker multi-chip substrates 201-216 provide more space for the ferrule 230 in the z-axis (when the fiber ferrule composite is much thicker than the substrate).

[0039] To illustrate an exemplary set of process steps for manufacturing an integrated circuit package assembly according to a selected blind cavity embodiment of the present disclosure, we hereby refer to Figure 8, which shows cross-sectional views 301–305 of exemplary manufacturing process steps for embedding photonic integrated circuits 310, 311 into a multi-chip substrate. As illustrated, the multi-chip substrate shown in Figure 8 is similar to the multi-chip substrates 201–216 shown in Figure 7, so the reference numbering for components and layers within the multi-chip package substrate is not repeated.

[0040] In the illustrated process flow shown in cross-sectional figure 301, a glass substrate A is processed to form blind cavities B and through-glass vias (TGVs) C at predetermined locations using any suitable selective etching and / or laser drilling techniques. In the TGVs, one or more metallization layers are selectively formed using any suitable deposition process to form conductive TGV structures and landing pads on opposing sides of the glass substrate.

[0041] In the illustrated process flow shown in cross-sectional view 302, the photonic ICs 310 and 311 are embedded in blind cavities, followed by a cavity filling and grinding process to flatten the upper surface of the glass substrate so that the photonic ICs 310 and 311 are fully embedded. As shown, each photonic IC 310 and 311 can be positioned as a face-up PIC with the fiber coupling region exposed, located on the upper surface of the PIC where the V-groove is formed. As shown, the photonic ICs 310 and 311 are "blind" in the sense that they have electrical signal connections provided only on their upper surfaces to the upper redistribution layer 314. As part of the embedding process flow, one or more active and / or passive circuit component modules 312 can also be embedded in the glass substrate. Once the photonic ICs 310 and 311 are positioned within the blind cavity, one or more dielectric layers 313 can be deposited to cover the photonic ICs 310 and 311 and fill the cavity, followed by a grinding or polishing process to flatten the upper surface of the dielectric layers 313.

[0042] In the illustrated process flow shown in cross-sectional view 303, redistribution layers 314 and 315 are constructed on the top and bottom surfaces of the glass substrate. As shown, the redistribution layers 314 and 315 can be formed by sequentially forming and patterning insulating and conductive layers to connect the embedded photonic ICs 310 and 311 with the active and / or passive circuit component modules 312. As shown, there may be first or second levels of interconnection formed on the redistribution layers 314 and 315 by attaching BGA solder balls, bumps, microbumps, etc.

[0043] In the illustrated process flow shown in section 304, selective etching can be applied to expose the fiber coupling regions on the embedded photonic ICs 310, 311, where V-grooves are formed. Any suitable selective etching process can be used, but a selected embodiment employs a patterned masking layer (not shown) formed on the upper redistribution layer 314, followed by the application of a directional and / or local etching process to form openings 316 that expose the fiber coupling regions on the embedded photonic ICs 310, 311. Once any patterned masking layer is removed, one or more integrated circuit chips (not shown) of the die can be mounted to the upper redistribution layer 314, along with the injected underfill material or layer (not shown) between the IC chip / die and the underlying multi-chip package substrate. As indicated by the directional cutting lines 317, the integrated circuit package assembly can be pieced using a saw, laser, or other cutting device applied along a saw-cut line or scribe grid defined for cutting the multi-chip package substrate.

[0044] In the illustrated process flow shown in cross-sectional figure 305, the individualized multi-chip package substrate is formed to include an upper redistribution layer stack 314 that covers a portion of the multi-chip package substrate but leaves the side edges of the photonic ICs 310, 311, which have V-grooves formed (etched), exposed. At this point, additional packaging processing steps can be applied, including board-level assembly and mounting of optical fibers to the exposed fiber coupling regions on the embedded photonic ICs 310, 311.

[0045] To illustrate an exemplary set of process steps for manufacturing an integrated circuit package assembly according to a selected through-cavity embodiment of the present disclosure, we hereby refer to Figure 9, which shows cross-sectional views 351–355 of exemplary manufacturing process steps for embedding photonic integrated circuits 360, 361 into a multi-chip substrate. As illustrated, the multi-chip substrate shown in Figure 9 is similar to the multi-chip substrates 101–115 shown in Figure 6, so the reference numbering for components and layers within the multi-chip package substrate is not repeated.

[0046] In the illustrated process flow shown in cross-sectional figure 351, a glass substrate A is processed to form a through-cavity B that completely penetrates the glass substrate using any suitable selective etching and / or laser drilling technique. In addition, through-glass vias (TGVs) C are formed at predetermined locations within the glass substrate using any suitable selective etching and / or laser drilling technique. In the TGVs, one or more metallization layers are selectively formed using any suitable deposition process to form conductive TGV structures and landing pads on opposing sides of the glass substrate.

[0047] In the illustrated process flow shown in cross-sectional figure 352, the photonic ICs 360, 361 are embedded in through-cavities formed in the substrate core (A), followed by a cavity filling and grinding process to flatten the upper surface of the glass substrate so that the photonic ICs 360, 361 are fully embedded. As shown, each photonic IC 360, 361 can be positioned as a face-up PIC with an exposed fiber coupling region located on the upper surface of the PIC where the V-groove is formed. As shown, the photonic ICs 360, 361 are positioned to extend across the through-cavities of the substrate core (A) in the sense that they can have electrical signal connections to the photonic ICs 360, 361 in the upper redistribution layer stacks 364, 365 that are later formed from both the upper and lower sides. As part of the embedding process flow, one or more active and / or passive circuit component modules 362 (cross-hatched) can also be embedded in the glass substrate core. Once the photonic ICs 360 and 361 are positioned within the through-cavity, one or more dielectric layers 363 can be deposited to cover the photonic ICs 360 and 361 and fill the cavity, followed by a grinding or polishing process to flatten the upper surface of the dielectric layers 363.

[0048] In the illustrated process flow shown in cross-sectional view 353, redistribution layers 364 and 365 are constructed on the top and bottom surfaces of the glass substrate. As shown, the redistribution layers 364 and 365 can be formed by sequentially forming and patterning insulating and conductive layers to connect the embedded photonic ICs 360 and 361 with the active and / or passive circuit component modules 362. As shown, there may be first or second level interconnections formed on the redistribution layers 364 and 365 by attaching BGA solder balls, bumps, microbumps, etc.

[0049] In the illustrated process flow shown in section 354, selective etching can be applied to expose the fiber coupling regions on the embedded photonic ICs 360, 361, where V-grooves are formed. Any suitable selective etching process can be used, but a selected embodiment employs a patterned masking layer (not shown) formed on the upper redistribution layer 364, followed by the application of a directional and / or local etching process to form openings 366 that expose the fiber coupling regions on the embedded photonic ICs 360, 361. Once any patterned masking layer is removed, one or more integrated circuit chips (not shown) of the die can be mounted to the upper redistribution layer 364, along with the injected underfill material or layer (not shown) between the IC chip / die and the underlying multi-chip package substrate. As indicated by the directional cutting lines 367, the integrated circuit package assembly can be pieced using a saw, laser, or other cutting device applied along a saw-cut line or scribe grid defined for cutting the multi-chip package substrate.

[0050] In the illustrated process flow shown in cross-sectional view 365, the individualized multi-chip package substrate is formed to include an upper redistribution layer stack 364 that covers a portion of the multi-chip package substrate but leaves the side edges of the photonic ICs 360, 361, which have V-grooves formed (etched), exposed. At this point, additional packaging processing steps can be applied, including board-level assembly and mounting of optical fibers to the exposed fiber coupling regions on the embedded photonic ICs 360, 361.

[0051] To illustrate an exemplary set of process steps for manufacturing an integrated circuit package assembly according to a selected embodiment of the present disclosure that uses a sacrificial protection layer when embedding a photonic integrated circuit, we here refer to Figure 10, which shows cross-sectional views 401–405 of exemplary manufacturing process steps for embedding photonic integrated circuits 410, 411 into a multichip substrate. As illustrated, the multichip substrate shown in Figure 10 is similar to the multichip substrates 101–115 shown in Figure 6, so the reference numbering for components and layers within the multichip package substrate is not repeated.

[0052] In the illustrated process flow shown in cross-sectional figure 401, a glass substrate core A is processed to form through-cavities B and through-glass vias (TGVs) C that penetrate the entire glass substrate at predetermined locations using any suitable selective etching and / or laser drilling technique. In the TGVs, one or more metallization layers are selectively formed using any suitable deposition process to form conductive TGV structures and landing pads on opposing sides of the glass substrate.

[0053] In the illustrated process flow shown in cross-sectional figure 402, the photonic ICs 410, 411 are embedded in through-cavities of the substrate core (A), followed by a cavity filling and grinding process to flatten the upper surface of the glass substrate so that the photonic ICs 410, 411 are fully embedded. As shown, each photonic IC 410, 411 can be positioned as a face-up PIC with an exposed fiber coupling region located on the upper surface of the PIC where a V-groove is formed. In addition, a sacrificial protective layer 412 can be deposited or otherwise formed on the upper surface of the PIC to protect the exposed fiber coupling region from any chemical treatment exposure that may be used during subsequent manufacturing processes (e.g., RDL and assembly processes). Once formed, the sacrificial protective layer 412 remains in place throughout the embedding process and can be removed before the fiber mounting step. As part of the embedding process flow, one or more active and / or passive circuit component modules 413 (cross-hatched) can also be embedded in the glass substrate. Once the photonic ICs 410 and 411 are positioned within the through-cavity, one or more dielectric layers 414 can be deposited to cover the photonic ICs 410 and 411 and fill the cavity, followed by a grinding or polishing process to flatten the upper surface of the dielectric layers 414.

[0054] In the illustrated process flow shown in cross-sectional figure 403, redistribution layers 415 and 416 are constructed on the top and bottom surfaces of the glass substrate. As shown, the redistribution layers 415 and 416 can be formed by sequentially forming and patterning insulating and conductive layers to connect the embedded photonic ICs 410 and 411 with the active and / or passive circuit component modules 413. As shown, there may be first or second level interconnections formed on the redistribution layers 415 and 416 by attaching BGA solder balls, bumps, microbumps, etc.

[0055] In the illustrated process flow shown in cross-sectional figure 404, a selective etching process can be applied to expose the sacrificial protective layer 412 formed on the fiber coupling regions of the embedded photonic ICs 410, 411. Any suitable selective etching process can be used that is selective in removing the redistribution layer 415 without removing the sacrificial protective layer 412. For example, a patterned masking layer (not shown) can be formed on the upper redistribution layer 415, and then a directional and / or local etching process can be applied to form an opening 417 that exposes the sacrificial protective layer 412 formed on the fiber coupling regions of the embedded photonic ICs 410, 411. Once any patterned masking layer is removed, one or more integrated circuit chips (not shown) of the die can be mounted to the upper redistribution layer 415, along with the injected underfill material or layer (not shown) between the IC chip / die and the underlying multi-chip package substrate. As indicated by the directional cutting line 418, the integrated circuit package assembly can be pieced using a saw, laser, or other cutting device applied along a saw-cut line or scribe grid defined for cutting the multi-chip package substrate.

[0056] In the illustrated process flow shown in cross-sectional figure 405, the sacrificial protective layer 412 is selectively etched or otherwise removed using any suitable process, thereby forming a fragmented multi-chip package substrate including an upper redistribution layer stack 415 that covers a portion of the multi-chip package substrate but leaves the side edges of the (etched) photonic ICs 410, 411 with V-grooves exposed. At this point, additional packaging processing steps can be applied, including board-level assembly and mounting of optical fibers to the exposed fiber coupling regions on the embedded photonic ICs 410, 411.

[0057] For a better understanding of selected embodiments of the present disclosure, hereby refer to Figure 11, which shows a cross-sectional view of an integrated circuit package assembly 11 in which face-down photonic integrated circuits 510, 512 and ASIC circuits 511 are mounted on a multi-chip package substrate 501 in which active and / or passive modules 502-507 are embedded. As shown, the integrated circuit package assembly 11 is implemented as a flip-chip package, and the die / chip modules 510-512 are connected to each other and to a printed circuit board 500 using defined conductive elements and embedded active and / or passive modules in the multi-chip package substrates 501-509. In particular, the flip-chip package assembly has a plurality of surface-mountable die or module devices 510-512, each including individual photonic integrated circuits 510, 512 and ASIC 511, each mounted to a first or upper RDL stack 509 via first-level interconnections (e.g., solder bumps or microbumps). Next, the conductors in the first or upper RDL stack 509 provide electrical and / or thermal conduction paths to the embedded active and / or passive modules 502-507 in the multichip package substrate 501. As shown in the figure, the embedded active and / or passive modules 502-507 may include various different circuit components such as embedded vertical planar capacitors, embedded sandwich multilayer capacitors, active circuit components, and / or passive circuit components. In addition, the conductors in the second or lower RDL stack 508 provide electrical and / or thermal conduction paths to the second level interconnects (e.g., solder balls).

[0058] As shown in the figure, face-down photonics ICs 510, 512 and ASIC 511 each have an active area formed on the bottom surface so that the dies / chips 510-512 are connected to communicate with each other via a first level interconnect and defined conductive elements in the first or upper RDL stack 509. In a selected embodiment, the dies / chips 510-512 may be encapsulated within a planarized and / or ground molding compound 513, while in other embodiments, the dies / chips 510-512 may be mounted on multi-chip package substrates 501-509 without a molding compound encapsulating the dies / chips 510-512.

[0059] To facilitate the attachment of waveguide fibers to the active face-down surface of the photonic ICs 510, 512, the photonic ICs 510, 512 are positioned on the side of the ASIC 511 and mounted on the multi-chip package substrate 501 so as to extend beyond the side of the multi-chip package substrate 501, thereby exposing the fiber coupling region on the peripheral bottom surface of the photonic ICs 510, 512. As disclosed herein, the fiber coupling region may include a V-groove on the side edge of the photonic IC for use in aligning the connection of optical fibers to edge-coupled or end-fire waveguides on the photonic ICs 510, 512. Such mounting is shown at the bottom of the face-down photonic ICs 510, 512, where ferrules 520, 530 are used to position the optical fibers 521, 531 at the bottom of the photonic ICs 510, 512 for edge coupling with the exposed fiber coupling region before using tacking adhesive or glove-top material 522, 532 to secure the optical fibers 521, 531 to the photonic ICs 510, 512. By forming the multi-chip substrates 501-509 to expose the fiber coupling region at the bottom of the photonic ICs 510, 512, optical waveguide fibers can be directly mounted without requiring the optical fiber mounting material to be reflow-compatible.

[0060] To provide a first example of forming a multichip substrate to expose the fiber coupling region at the bottom of the photonic IC, we hereby refer to Figure 12, which shows a simplified plan view 12A and a simplified perspective view 12B of a face-down photonic integrated circuit overhanging a mounted multichip substrate below, according to a selected embodiment of the present disclosure. In particular, plan view 12A shows that the multichip package substrate 501A may have a rectangular shape, which can be positioned beneath the photonic ICs 510, 512 and ASIC 511, except for the protruding side edges of the photonic ICs 510, 512 that extend beyond the sides of the multichip package substrate 501A (indicated by dashed lines). This same spatial relationship between the rectangular multichip package substrate 501A and the protruding photonic ICs 510, 512 is shown in perspective view 12B.

[0061] To provide a second example of forming a multichip substrate to expose a fiber coupling region at the bottom of a photonic IC, we hereby refer to Figure 13, which shows a simplified plan view 13A and a simplified perspective view 13B of a face-down photonic integrated circuit that overhangs a notched region from a lower mounted multichip substrate according to a selected embodiment of the present disclosure. In particular, plan view 13A shows that the multichip package substrate 501B may have a rectangular shape with notched regions on opposing sides so that the photonic ICs 510, 512 are positioned to have protruding side edges extending over the notched region (indicated by dashed lines) of the multichip package substrate 501B. This same spatial relationship between the notched region of the multichip package substrate 501B and the protruding photonic ICs 510, 512 is shown in perspective view 13B.

[0062] For a better understanding of selected die-level reconfiguration embodiments of the present disclosure, refer here to Figure 14, which shows a cross-sectional view of an integrated circuit package assembly 14 in which vertical back coupling is used with face-down photonic integrated circuits 610 and electronic IC or ASIC circuits 611 mounted on a multi-chip package substrate 601 in which active and / or passive modules 602-607 are embedded. As shown, the integrated circuit package assembly 14 is mounted as a flip-chip package, and the die / chip modules 610-611 are connected to each other and to a printed circuit board 600 using defined conductive elements and embedded active and / or passive modules in the multi-chip package substrates 601-609. In particular, the flip-chip package assembly has a plurality of surface-mountable die or module devices 610-611, each including individual photonic integrated circuits 610 and EIC / ASIC 611, each mounted to a first or upper RDL stack 609 via first-level interconnections (e.g., solder bumps or microbumps). Next, the conductors in the first or upper RDL stack 609 provide electrical and / or thermal conduction paths to embedded active and / or passive modules 602-607 in the multichip package substrate 601. As shown in the figure, the embedded active and / or passive modules 602-607 may include substrate core layers 602, 607 in which one or more circuit components such as an embedded vertical planar capacitor 603, an embedded sandwich multilayer capacitor 604, an active circuit component 605, and / or passive circuit component 606 are embedded. In addition, the conductors in the second or lower RDL stack 608 provide electrical and / or thermal conduction paths to the second level interconnects (e.g., solder balls).

[0063] As shown in the figure, the face-down photonics IC 610 and EIC / ASIC 611 each have an active area formed on the bottom surface so that the dies / chips 610-611 are connected to communicate with each other via a first level interconnect and defined conductive elements in the first or upper RDL stack 609. The illustrated dies / chips 610-611 are encapsulated within a molding compound 612 which can be flattened or ground to align the height of the chips 610-611. In selected die-level reconfiguration embodiments, a heat spreader lid or heat sink cover 615 is formed on the package assembly to make thermal contact with the dies / chips 610-611. As a preliminary step, one or more backside metallization (BSM) layers 613 may be formed as patterned thermal interface material layers selectively formed or applied on the exposed surfaces of the dies / chips 610-611 to make direct thermal conduction contact with the dies / chips 610-611. In addition, to minimize thermal resistance between the die / chip 610-611 and the subsequently mounted heat spreader cover array and to protect the die / chip 610-611 from compression-related damage, one or more patterned thermal interface material (TIM) layers 614 may be selectively formed or applied to each exposed surface of the die / chip 610-611 using a flexible thermal conductive grease or non-curing silicon material. Subsequently, a single heat spreader cover 615 is formed of a thermal conductive material such as copper (e.g., CDA194 copper) or other copper alloys, nickel-iron alloy (e.g., Alloy 42) or other Ni alloys. The illustrated heat spreader cover 615 is positioned and mounted to be in direct thermal contact with the multiple die / chip 610-611 using the patterned TIM layer 614 and BSM layer 613 as thermal conductive layers.

[0064] After the heat spreader cover / sink 615 is installed, a selective etching process can be applied to expose the back-facing fiber coupling region on the top or back surface of the face-down photonic IC 610. Any suitable selective etching process can be used to etch through the heat spreader cover / sink 615 and the underlying layers 613-614. For example, a patterned masking layer (not shown) can be formed on the heat spreader cover / sink 615, and then one or more directional and / or localized etching processes can be applied to form an opening that exposes the back-facing fiber coupling region on the photonic IC 610. In a selected embodiment, the localized etching process may include thinning etching applied to the back surface of the photonic IC 610 to reduce its thickness so as to reduce the beam-expanding effect. After removing any patterned masking layer, the optical waveguide fibers 620-621 and lens structure 622 are installed to provide vertical back-facing coupling to the exposed back-facing fiber coupling region. By exposing the photonic IC 610, which has a thinned or recessed back fiber coupling region, optical waveguide fibers 620-621 can be directly mounted without requiring an overhang of the photonic IC, without requiring notches or etching of the multi-chip substrates 601-609, and without requiring the optical fiber mounting material to be reflow compatible. In addition, by partially thinning the photonic IC 610 after it has been encapsulated within the molded compound 612, the assembly process avoids problems related to handling the partially thinned photonic IC, which lacks structural support during assembly.

[0065] For a better understanding of selected die-level reconfiguration embodiments of the present disclosure, refer here to Figure 15, which shows a cross-sectional view of an integrated circuit package assembly 15 including a face-down photonic integrated circuit 710 connected to an optical fiber 720 using vertical back coupling, and multi-chip substrates 701-709 mounted on an electronic IC or ASIC circuit 711, according to a selected substrate-level reconfiguration embodiment of the present disclosure. In such a substrate-level reconfiguration embodiment, the multi-chip substrates are mounted on a first temporary carrier before mounting multiple instances of the bump integrated circuit die onto the multi-chip substrates, and then the multi-chip substrates are covered with a molding compound and a heat sink lid / cover before piece formation. Before or after mounting multiple instances of the bump integrated circuit die onto the multi-chip substrates, one or more optional reinforcing structures can be formed on each of the multi-chip substrates to surround or enclose the integrated circuit die.

[0066] As shown in the figure, the integrated circuit package assembly 15 is mounted as a flip-chip package, and the die / chip modules 710-711 are connected to each other and to the printed circuit board 700 using defined conductive elements and embedded active and / or passive modules within the multi-chip package substrates 701-709. In particular, the surface-mountable die or module devices 710-711 include individual face-down photonic integrated circuits 710 and EIC / ASIC 711, each mounted to the first or upper RDL stack 709 via first-level interconnects (e.g., solder bumps or microbumps). The conductors within the first or upper RDL stack 709 then provide electrical and / or thermal conduction paths within the multi-chip package substrate 701, which may include substrate core layers 702, 707, and one or more embedded components such as embedded vertical planar capacitors 703, embedded sandwich multilayer capacitors 704, active circuit components 705, and / or passive circuit components 706. In addition, the conductors in the second or lower RDL stack 708 provide electrical and / or thermal conduction paths to the second level interconnects (e.g., solder balls).

[0067] In the manufacturing process, the face-down photonics ICs 710 and EIC / ASIC 711 are mounted on a multi-chip substrate and encapsulated within a molded compound 713 which can be planarized or ground to align the heights of the chips 710-711. Before or after mounting the face-down photonics ICs 710 and EIC / ASIC 711 to the multi-chip substrate, a reinforcing structure 712 can be formed on the multi-chip substrate 701 with any suitable material having structural properties suitable for providing mechanical support and structural integrity to reduce warping or bending of the multi-chip substrate 701. In addition, the material properties of the reinforcing structure 712 may include thermal conductivity properties that enable the reinforcing structure 712 to provide thermal conduction or thermal diffusion paths for the heat generated by the embedded elements within the integrated circuit dies 710, 711 and / or the multi-chip substrate 701. As understood, the reinforcing structure 712 may be formed to include a thermally conductive adhesive layer used to attach the reinforcing structure 712 to one or more thermal conduction paths formed on the multi-chip substrate 701. For example, the thermally conductive adhesive layer may be a TIM film or tape and may be applied to the bottom surface of each reinforcing structure 712. In a selected embodiment, each reinforcing structure 712 is formed as a ring-shaped structure surrounding the integrated circuit dies 710-711 formed on a multichip package substrate (e.g., 701). In another selected embodiment, where the reinforcing structure 712 provides a heat conduction path for the heat generated by the integrated circuit dies 710-711 and / or embedded elements within the multichip substrate, the height of each reinforcing structure 712 is at least the same as the height of the shortest integrated circuit die (e.g., 710). In other embodiments, where the reinforcing structure 712 does not provide a heat conduction path, the height of the reinforcing structure 712 may be shorter than any of the dies. In other embodiments, the reinforcing structure 712 may be omitted.

[0068] After the integrated circuit dies 710, 711 and reinforcing structures 712 are mounted and encapsulated in a planarized molding compound 713, a heat spreader lid or heat sink cover 716 is formed on the package assembly to make thermal contact with the dies / chips 710-711. As a preliminary step, one or more back metallization (BSM) layers 714 are formed as patterned thermal interface material layers on the exposed surfaces of the dies / chips 710-711 to make direct thermal conduction contact with the dies / chips 710-711. In addition, one or more patterned thermal interface material (TIM) layers 715 may be selectively formed or applied on each exposed surface of the dies / chips 710-711 using a flexible thermal conductive grease or non-curing silicon material to minimize thermal resistance between the dies / chips 710-711 and the subsequently mounted heat spreader lid array 716 and to protect the dies / chips 710-711 from compression-related damage. Next, a single heat spreader cover 715 is formed from a thermally conductive material.

[0069] After mounting the heat spreader cover / sink 716, a selective etching process can be applied to expose the back-facing fiber coupling region on the top or back surface of the face-down photonic IC 710. Any suitable selective etching process can be used to etch through the heat spreader cover / sink 716 and the underlying layers 714-715. For example, a patterned masking layer (not shown) can be formed on the heat spreader cover / sink 716, and then one or more directional and / or localized etching processes can be applied to form an opening that exposes the back-facing fiber coupling region on the photonic IC 710. In a selected embodiment, the localized etching process may include thinning etching applied to the back surface of the photonic IC 710 to reduce its thickness so as to reduce the beam-expanding effect. After removing any patterned masking layer, the optical waveguide fibers 720-721 and the lens structure 722 are mounted to provide vertical back-facing coupling to the exposed back-facing fiber coupling region. By exposing the photonic IC 710, which has a thinned or recessed back fiber coupling region, optical waveguide fibers 720-721 can be directly mounted without requiring an overhang of the photonic IC, without requiring notches or etching of the multi-chip substrates 701-709, and without requiring the optical fiber mounting material to be reflow compatible. In addition, by partially thinning the photonic IC 710 after it has been encapsulated within the molded compound 713, the assembly process avoids problems related to handling the partially thinned photonic IC, which lacks structural support during assembly.

[0070] Referring here to Figure 16, a simplified flowchart 16 is shown illustrating an exemplary set of steps 160–170 for manufacturing an integrated circuit package assembly in which an embedded photonic integrated circuit die is copackaged with a multichip package substrate. After the process has started (in step 160), one or more multichip package substrates are flaked and / or assembled (step 161), where each multichip package substrate includes at least an embedded face-up photonic integrated circuit sandwiched between a fine-pitch RDL stack and a coarse-pitch RDL stack. As supplementarily shown in step 161, each embedded photonic integrated circuit includes a fiber-coupled region which may be located on the active surface of the embedded photonic integrated circuit, and the fiber-coupled region may optionally be covered by one or more sacrificial protective layers.

[0071] In step 162, interconnects are formed on the landing pads of the multichip package substrate. For example, interconnect conductor elements (e.g., microbumps) may optionally be formed on the contact terminals (e.g., landing pads) of the multichip package substrate. In selected embodiments, interconnect conductor elements can be constructed on the multichip package substrate to electrically contact internally exposed contact terminals by sequentially depositing, patterning, and etching insulating and conductive layers (e.g., plated copper) to form fine-pitch plated conductor wires.

[0072] In step 163, one or more integrated circuit components are fixed to interconnects on the first surface of the multichip package substrate. Any suitable method can be used to position the integrated circuit components, but in one embodiment, a pick-and-place machine is used to position the integrated circuit components for mounting to the multichip package substrate. As supplementarily shown in step 163, the IC components may have multiple different heights, and as a result, some IC components extend further up the multichip package substrate than others.

[0073] In step 164, a grinding or etching process can be optionally applied to any multi-height IC component to expose the IC component on the first surface of the multi-chip package substrate at a uniform height. In selected embodiments, the grinding or etching process may use a laser ablation process applied to a molded compound formed on the multi-height IC component, thereby forming a thinned and encapsulated IC component panel. For example, by back-grinding the top of the molded compound to thin the encapsulated IC component panel to a desired thickness that is at least the same height as the shortest integrated circuit component, the multi-height IC component (and any reinforcing elements) are etched or ground to a uniform height and exposed on top of the etched molded compound. As indicated by the dashed line, step 164 is optionally applied when there is a multi-height IC component.

[0074] In step 165, the fiber-coupled regions on the embedded photonic integrated circuit are exposed, for example, by applying a selective etching process to the multi-chip package substrate. Any suitable selective etching process can be used, but a selected embodiment may employ a patterned masking layer formed on the multi-chip package substrate, followed by the application of one or more directional and / or local etching processes to form openings in the multi-chip package substrate that expose the fiber-coupled regions on the embedded photonic IC. As supplementarily shown in step 165, the sacrificial protective layer may be removed to expose the fiber-coupled regions on the photonic integrated circuit.

[0075] In step 166, the multi-chip package substrate can be pieced into dies by cutting the multi-chip package substrate to expose the side surfaces of the fiber coupling regions on the photonic integrated circuit. For example, the multi-chip package substrate can be pieced using a saw, laser, or other cutting device applied along a defined saw-cut line or scribe grid to cut the multi-chip package substrate and thereby expose the side surfaces of the fiber coupling regions.

[0076] In step 167, one or more board-level assembly steps are performed to connect the opposing surface of the multi-chip package substrate to the printed circuit board.

[0077] In step 168, any sacrificial protective layer formed on the fiber coupling region can be removed. By maintaining the sacrificial protective layer in place throughout the manufacturing process, the underlying fiber coupling region is protected from the chemical effects of the manufacturing process. As understood, the sacrificial protective layer can be removed without damaging the rest of the multichip package substrate using any suitable selective etching process. As indicated by the dashed line, step 168 is optionally applied when there is a sacrificial protective layer that was previously formed in the manufacturing process.

[0078] By this point, it should be understood that methods and apparatus for fabricating integrated circuit package assemblies are provided herein. As disclosed, an integrated circuit package assembly includes a multichip package substrate having active and / or passive circuit devices embedded in one or more substrate core layers. In addition, the integrated circuit package assembly includes a plurality of encapsulated integrated circuit devices mounted on the multichip package substrate. The integrated circuit package assembly also includes optical waveguide fibers connected to a photonic integrated circuit device located either on the multichip package substrate or in the plurality of encapsulated integrated circuit devices, the optical waveguide fibers being optically coupled to an exposed fiber coupling region of the photonic integrated circuit device. In a selected embodiment, the integrated circuit package assembly also includes a heat spreader cover formed on the plurality of encapsulated integrated circuit devices using one or more thermal conductive layers and thermally connected to the plurality of encapsulated integrated circuit devices in order to remove heat from the plurality of encapsulated integrated circuit devices. In a selected embodiment, the photonic integrated circuit device is embedded as a face-up photonic integrated circuit device within a cavity of the multichip package substrate, and the exposed fiber coupling region is positioned for edge-coupled mounting to the optical waveguide fiber. In another selected embodiment, the photonic integrated circuit device is embedded as a face-up photonic integrated circuit device within a blind cavity of a multi-chip package substrate, with the exposed fiber coupling region positioned for edge coupling attachment to an optical waveguide fiber. In another selected embodiment, the photonic integrated circuit device is mounted as a face-down photonic integrated circuit device within a plurality of encapsulated integrated circuit devices, with the face-down photonic integrated circuit device extending laterally beyond the side of the multi-chip package substrate so that the exposed fiber coupling region is positioned for edge coupling attachment to an optical waveguide fiber.In other selected embodiments, the photonic integrated circuit device is mounted as a face-down photonic integrated circuit device within a plurality of encapsulated integrated circuit devices, and the face-down photonic integrated circuit device extends laterally beyond a notched area in the multi-chip package substrate so that an exposed fiber coupling region is positioned for edge coupling attachment to an optical waveguide fiber. In other selected embodiments, the photonic integrated circuit device is mounted as a face-down photonic integrated circuit device within a plurality of encapsulated integrated circuit devices, and the face-down photonic integrated circuit device has a partially thinned back surface that forms an exposed fiber coupling region positioned for vertical back coupling attachment to an optical waveguide fiber. In another embodiment, integrated circuit package assemblies and associated manufacturing methods are provided. The disclosed method includes assembling a multichip package substrate including a photonic integrated circuit device sandwiched between a first redistribution stack and a second redistribution stack, the photonic integrated circuit device being positioned on the periphery side of the multichip package substrate and including a fiber coupling region covered by the first redistribution stack. In a selected embodiment, assembling the multichip package substrate includes embedding the photonic integrated circuit device as a face-up photonic integrated circuit device having a plurality of active and / or passive circuit components within the multichip package substrate so as to be sandwiched between the first and second redistribution stacks. In another embodiment, assembling the multichip package substrate includes embedding the photonic integrated circuit device within a substrate core cavity of the multichip package substrate. In yet another embodiment, assembling the multichip package substrate includes locating the photonic integrated circuit device within a blind substrate core cavity of the multichip package substrate. In addition, the disclosed method includes selectively etching the first redistribution stack to expose the fiber coupling region. The disclosed method also includes mounting a plurality of first surface-mountable devices to a multichip package substrate, each having interconnection surfaces facing the multichip package substrate and not covering exposed fiber-coupled regions of a photonic integrated circuit device, at least one of the first plurality of surface-mountable devices comprising an electronic integrated circuit device positioned on the photonic integrated circuit device and connected to communicate with the photonic integrated circuit device. In a selected embodiment, during the assembly of the multichip package substrate (e.g., while embedding the photonic integrated circuit device into the multichip package substrate), a sacrificial protection layer is placed over the fiber-coupled regions of the face-up embedded photonic integrated circuit device, and subsequently, the sacrificial protection layer is removed from the fiber-coupled regions before mounting optical waveguide fibers.In other selected embodiments, the face-up embedded photonic integrated circuit device is connected to one or both of the first and second redistribution stacks. The disclosed method also includes cutting the multichip package substrate to expose the side edges and exposed fiber coupling regions of the photonic integrated circuit device. In addition, the disclosed method includes mounting the second redistribution stack of the multichip package substrate to the circuit board and then mounting optical waveguide fibers to the exposed fiber coupling regions of the photonic integrated circuit device.

[0079] In yet another embodiment, integrated circuit package assemblies and associated manufacturing methods are provided. The disclosed method includes assembling a multichip package substrate including a plurality of active and / or passive circuit components sandwiched between a first redistribution stack and a second redistribution stack. The disclosed method also includes mounting a first plurality of surface-mountable devices to the first redistribution stack of the multichip package substrate, the first plurality of surface-mountable devices having interconnection surfaces facing the multichip package substrate, at least one of the first plurality of surface-mountable devices comprising a photonic integrated circuit device including a fiber-coupled region positioned to extend laterally beyond the side edges of the multichip package substrate. In addition, the disclosed method includes mounting a second redistribution stack of the multichip package substrate to a circuit board, and then mounting optical waveguide fibers to the exposed fiber-coupled region of the photonic integrated circuit device. In a selected embodiment, the photonic integrated circuit device is mounted as a face-down photonic integrated circuit device in which the fiber-coupled region faces the multichip package substrate for mounting to optical waveguide fibers. In another selected embodiment, the first plurality of surface-mountable devices are mounted to the multichip package substrate as a plurality of encapsulated surface-mountable devices.

[0080] In yet another embodiment, integrated circuit package assemblies and associated manufacturing methods are provided. The disclosed method includes assembling a multichip package substrate including a plurality of active and / or passive circuit components sandwiched between a first redistribution stack and a second redistribution stack. The disclosed method also includes mounting a first plurality of surface-mountable devices to the first redistribution stack of the multichip package substrate, each having interconnection surfaces facing the multichip package substrate, wherein at least one of the first plurality of surface-mountable devices comprises a photonic integrated circuit device including a fiber coupling region positioned on the periphery side of the first plurality of surface-mountable devices. In addition, the disclosed method includes encapsulating the first plurality of surface-mountable devices in the multichip package substrate using a molded compound structure. In a selected embodiment, encapsulating the first plurality of surface-mountable devices includes mounting a reinforcing ring surrounding the first plurality of surface-mountable devices in the multichip package substrate, encapsulating the first plurality of surface-mountable devices and the reinforcing ring using a molded compound material, and curing the molded compound material to form a molded compound structure. The disclosed method also includes grinding or etching a portion of the molded compound structure and the back surface of the photonic integrated circuit device to form a thinned back surface aligned with the fiber coupling region. In addition, the disclosed method includes mounting an optical waveguide fiber to the thinned back surface of the photonic integrated circuit device. In selected embodiments, the photonic integrated circuit device is mounted as a face-down photonic integrated circuit device with the active photonic integrated circuit device side facing the multi-chip package substrate for perpendicular back coupling to the optical waveguide fiber.

[0081] Various exemplary embodiments of the present invention have been described in detail with reference to the accompanying drawings. While various details have been described herein, it will be understood that the present invention can be carried out without these specific details, and that numerous implementation-specific decisions can be made to the invention described herein to achieve specific objectives of the device designer, such as compliance with process technology or design-related constraints, which will differ from implementation to implementation. Such development efforts may be complex and time-consuming, but nevertheless, they are routine work for those skilled in the art who are interested in this disclosure. For example, selected embodiments are shown with reference to simplified cross-sectional views and simplified flowcharts illustrating process and structural details of the package assembly and associated manufacturing processes, without including all device features or embodiments, in order to avoid limiting or obscuring the invention. Such descriptions and expressions are used by those skilled in the art to explain and communicate the content of their work to others skilled in the art, and it is considered unnecessary for well-known omitted details to teach those skilled in the art how to manufacture or use the present invention. In addition, certain elements in the figures are shown for simplicity and clarity and are not necessarily drawn to scale. Throughout this detailed description, it should be noted that specific layers of material are deposited, removed, and otherwise processed to form the illustrated integrated circuit die and associated packaging structure. Where specific procedures for forming such layers are not detailed below, it is assumed that the prior art for depositing, removing, or otherwise forming such layers to an appropriate thickness is intended for those skilled in the art. Such details are well known, and it is considered unnecessary to instruct those skilled in the art on how to manufacture or use the present invention.

[0082] The exemplary embodiments described herein cover a variety of packaging assemblies and methods for fabricating them, but the present invention is not necessarily limited to exemplary embodiments that demonstrate inventive aspects of the present invention applicable to a wide variety of packaging processes and / or devices. Accordingly, the specific embodiments disclosed above are illustrative only, and the present invention can be modified and practiced in different but equivalent ways that will be obvious to those skilled in the art who are interested in the teachings herein, and should not be construed as limitations on the invention. For example, a multichip package substrate is described with reference to embedded passive components such as capacitors, resistors, inductors, diodes, and other passive devices, but active devices may also be included as embedded components when forming a multichip package substrate, and therefore these are merely exemplary circuits presented to provide useful reference when considering various aspects of the present invention, and are not intended to be limiting, and thus those skilled in the art will understand that the principles taught herein are applicable to other types of devices. In addition, process steps may be performed in a different order than those presented. Furthermore, since it is understood that any electrical connection can be made using leads, vias, bonds, circuit traces, and other means of connection, the drawings do not show all details of the connections between the various elements of the package. Accordingly, the foregoing description is not intended to limit the invention to the specific forms described, but rather to cover alternatives, modifications, and equivalents that may fall within the spirit and scope of the invention as defined by the appended claims, so that those skilled in the art will understand that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the invention in its broadest form.

[0083] Benefits, other advantages, and solutions to problems are described above with respect to specific embodiments. However, benefits, advantages, solutions to problems, and any elements that may cause or make more prominent any benefit, advantage, or solution should not be construed as important, necessary, or essential features or elements of any or all of the claims. As used herein, the terms “comprises,” “comprising,” or any other variation thereof are intended to encompass non-exclusive inclusion, so that a process, method, article, or apparatus containing a list of elements may include not only those elements but also other elements not expressly enumerated or that are inherent to such process, method, article, or apparatus. In addition, as used herein, the term “combined” is not intended to be limited to direct or mechanical bonding. Furthermore, as used herein, the terms “a” or “an” are defined as one or more. Furthermore, the use of introductory phrases such as "at least one" and "one or more" in the claims should not be interpreted as meaning that the introduction of another claim element with the indefinite article "a" or "an" limits any particular claim containing such introduced claim element to an invention containing only one such element, even if the same claim contains the introductory phrase "one or more" or "at least one" and an indefinite article such as "a" or "an". The same applies to the use of definite articles. Unless otherwise specified, terms such as "first" and "second" are used to arbitrarily distinguish the elements described by such terms. Therefore, these terms are not necessarily intended to indicate a temporal or other priority of such elements.

Claims

1. A multi-chip package substrate comprising active and / or passive circuit devices embedded in one or more substrate core layers, Multiple integrated circuit devices mounted on the multi-chip package substrate, An optical waveguide fiber connected to a photonic integrated circuit device located on the multi-chip package substrate or one of the plurality of integrated circuit devices, wherein the optical waveguide fiber is optically coupled to an exposed fiber coupling region of the photonic integrated circuit device. An integrated circuit package assembly comprising the above features.

2. The integrated circuit package assembly according to claim 1, further comprising a heat spreader cover formed on the plurality of integrated circuit devices using one or more thermal conductive layers and thermally connected to the plurality of integrated circuit devices, for removing heat from the plurality of integrated circuit devices.

3. The integrated circuit package assembly according to claim 1, wherein the photonic integrated circuit device is embedded as a face-up photonic integrated circuit device within a cavity of the multi-chip package substrate, and the exposed fiber coupling region is positioned for edge coupling attachment to the optical waveguide fiber.

4. The integrated circuit package assembly according to claim 1, wherein the photonic integrated circuit device is embedded as a face-up photonic integrated circuit device within a blind cavity of the multi-chip package substrate, and the exposed fiber coupling region is positioned for edge coupling attachment to the optical waveguide fiber.

5. The integrated circuit package assembly according to claim 1, wherein the photonic integrated circuit device is mounted as a face-down photonic integrated circuit device within the plurality of integrated circuit devices, and the face-down photonic integrated circuit device extends laterally beyond the side surface of the multi-chip package substrate so that the exposed fiber coupling region is positioned for edge coupling attachment to the optical waveguide fiber.

6. The integrated circuit package assembly according to claim 1, wherein the photonic integrated circuit device is mounted as a face-down photonic integrated circuit device within the plurality of integrated circuit devices, and the face-down photonic integrated circuit device extends laterally beyond a notched region in the multi-chip package substrate so that the exposed fiber coupling region is positioned for edge coupling attachment to the optical waveguide fiber.

7. The integrated circuit package assembly according to claim 1, wherein the photonic integrated circuit device is mounted as a face-down photonic integrated circuit device within the plurality of integrated circuit devices, and the face-down photonic integrated circuit device has a partially thinned back surface that forms the exposed fiber coupling region which is positioned for vertical back coupling mounting to the optical waveguide fiber.

8. The integrated circuit package assembly according to claim 1, comprising a plurality of encapsulated integrated circuit devices mounted on the multi-chip package substrate.

9. A method for manufacturing a package assembly, The assembly of a multi-chip package substrate comprising a photonic integrated circuit device sandwiched between a first redistribution stack and a second redistribution stack, wherein the photonic integrated circuit device is positioned on the peripheral side of the multi-chip package substrate and includes a fiber-coupled region covered by the first redistribution stack. Selective etching of the first rewiring stack in order to expose the fiber coupling region, Attaching a plurality of first surface-mountable devices to the multi-chip package substrate, each having an interconnection surface facing the multi-chip package substrate and not covering the exposed fiber coupling region of the photonic integrated circuit device, wherein at least one of the plurality of first surface-mountable devices comprises an electronic integrated circuit device positioned on the photonic integrated circuit device and connected to communicate with the photonic integrated circuit device. Cutting the multi-chip package substrate to expose the side edges of the photonic integrated circuit device and the exposed fiber coupling region, The second redistribution stack of the multi-chip package substrate is attached to the circuit board, To attach an optical waveguide fiber to the exposed fiber coupling region of the photonic integrated circuit device. Methods that include...

10. The method according to claim 9, wherein assembling the multichip package substrate includes embedding the photonic integrated circuit device as a face-up photonic integrated circuit device having a plurality of active and / or passive circuit components within the multichip package substrate so as to be sandwiched between the first redistribution stack and the second redistribution stack.

11. The method according to claim 9, wherein assembling the multi-chip package substrate includes embedding the photonic integrated circuit device in the substrate core cavity of the multi-chip package substrate.

12. The method according to claim 9, wherein assembling the multichip package substrate includes arranging the photonic integrated circuit device in a blind substrate core cavity of the multichip package substrate.

13. During the assembly of the multi-chip package substrate, a sacrificial protection layer is placed on the fiber coupling region of the face-up embedded photonic integrated circuit device, Before installing the optical waveguide fiber, remove the sacrificial protective layer from the fiber coupling region. The method according to claim 10, further comprising:

14. The method according to claim 10, wherein the photonic integrated circuit device embedded in the face-up configuration is connected to one or both of the first redistribution stack and the second redistribution stack.

15. A method for manufacturing a package assembly, Assembling a multi-chip package substrate comprising multiple active and / or passive circuit components sandwiched between a first redistribution stack and a second redistribution stack, Attaching a first plurality of surface-mountable devices having interconnection surfaces facing the multi-chip package substrate to the first redistribution stack of the multi-chip package substrate, wherein at least one of the first plurality of surface-mountable devices comprises a photonic integrated circuit device including a fiber coupling region positioned to extend laterally beyond the side edge of the multi-chip package substrate. The second redistribution stack of the multi-chip package substrate is attached to the circuit board, To attach an optical waveguide fiber to the exposed fiber coupling region of the photonic integrated circuit device. Methods that include...

16. The method according to claim 15, wherein the photonic integrated circuit device is mounted as a face-down photonic integrated circuit device in which the fiber coupling region faces the multi-chip package substrate for attachment to the optical waveguide fiber.

17. The method according to claim 15, wherein the first plurality of surface-mountable devices are mounted on the multi-chip package substrate as a plurality of encapsulated surface-mountable devices.

18. A method for manufacturing a package assembly, Assembling a multi-chip package substrate comprising multiple active and / or passive circuit components sandwiched between a first redistribution stack and a second redistribution stack, Attaching a first plurality of surface-mountable devices having interconnection surfaces facing the multi-chip package substrate to the first redistribution stack of the multi-chip package substrate, wherein at least one of the first plurality of surface-mountable devices comprises a photonic integrated circuit device including a fiber coupling region positioned on the peripheral side of the first plurality of surface-mountable devices. Encapsulating the first plurality of surface-mountable devices on the multi-chip package substrate using a molded compound structure, In order to form a thinned back surface aligned with the fiber coupling region, a portion of the molded compound structure and the back surface of the photonic integrated circuit device are ground or etched. To attach an optical waveguide fiber to the thinned back surface of the photonic integrated circuit device. Methods that include...

19. The method according to claim 18, wherein the photonic integrated circuit device is mounted as a face-down photonic integrated circuit device with the active photonic integrated circuit device side facing the multi-chip package substrate for vertical back coupling to the optical waveguide fiber.

20. Encapsulating the first plurality of surface-mountable devices using the aforementioned molded compound structure is The multi-chip package substrate is fitted with a reinforcing ring surrounding the first plurality of surface-mountable devices, Encapsulating the first plurality of surface-mountable devices and the reinforcing ring using a molded compound material, The molding compound material is cured in order to form the aforementioned molding compound structure. The method according to claim 18, including the method described in claim 18.

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