Fully controllable power semiconductor switching assemblies, power semiconductor devices, snubberless power converters, and manufacturing methods.

Abstract

This disclosure relates to a fully controllable power semiconductor switching assembly (40) comprising a first unit (51, 61, 71) having a latching power semiconductor switching device (41) controlled by a first gate terminal (44), a second unit (52, 62, 72) having a non-latching power semiconductor switching device (42) controlled by a second gate terminal (45), and a power semiconductor diode (43). The latching power semiconductor switching device (41) and the non-latching power semiconductor switching device (42) are connected in parallel with respect to the current switched by the switching assembly (40). The power semiconductor diode (43) is connected in antiparallel with respect to the current switched by the switching assembly (40). This disclosure further provides a power semiconductor device (100), a snubberless power converter, and a method for manufacturing the same.

Description

Technical Field

[0001] The present disclosure relates to a fully controllable power semiconductor switching assembly comprising a latching power semiconductor switching device, a non-latching power semiconductor switching device, and a power semiconductor diode. The present disclosure further relates to a power semiconductor device comprising an insulated housing package, a non-latching power semiconductor switching device, and a power semiconductor diode. The present invention further relates to a snubberless power converter and a method for manufacturing a power converter.

Background Art

[0002] In the field of power semiconductor devices, turn-off power semiconductor devices such as gate turn-off (GTO) thyristors, particularly integrated gate-commutated thyristors (IGCTs), are known. Such power semiconductor devices are useful in various applications, particularly in power converters such as inverters used, for example, in power transmission networks or electric vehicles.

[0003] FIG. 1 shows a simplified circuit diagram of a first switching circuit 10 for switching high voltage and / or high current. The circuit 10 shown in FIG. 1 is based on two switching elements 11, such as a pair of GTO thyristors, connected to a common central node 12 to form two halves of a switching bridge. The switching elements 11 in FIG. 1 become conductive upon appropriate switch-on, typically upon application of a positive gate control signal. They remain conductive as long as sufficient current flows through the GTO thyristor 11 or an appropriate switch-off, typically a negative gate control signal, is provided.

[0004] To turn off the switching circuit 10 shown in Figure 1, it is necessary to provide one or more snubber circuits 13 to reduce the voltage change rate dv / dt in the switching element 11, as shown in the figure. For example, a resistor-capacitor-diode (RCD) dv / dt snubber circuit may be used.

[0005] Furthermore, the switching circuit 10 includes a choke circuit 14 (or di / dt snubber circuit) for limiting the current change di / dt during switching on, and a clamp circuit 15 for clamping the induced overvoltage generated by the choke circuit 14. Its function is to clamp the induced overvoltage generated by the choke circuit 14 to a level safe for all components of the switching circuit 10. The choke circuit 14 may include, for example, an inductor 16. The clamp circuit 15 may include, for example, a diode 17, a resistor 18, and a capacitor 19, as shown in the figure. Note that in a typical insulated-gate bipolar transistor (IGBT) based switching circuit, a choke circuit is not required, and therefore a clamp circuit is not required.

[0006] Figure 2 shows an improved second switching circuit 20 for switching high voltage and / or high current. In contrast to the circuit shown in Figure 1, the circuit shown in Figure 2 is based on a pair of two IGCTs 21 that can be turned off without a snubber to reduce the voltage change dv / dt. Two freewheeling diodes 22 are connected in antiparallel to the corresponding IGCTs 21. When the current across the two IGCTs 21 is switched on, the voltage across the IGCTs 21 collapses uncontrollably. To avoid overstressing the two freewheeling diodes 22, a choke circuit 14 is used to limit the rate of increase of the anode current di / dt, as described with respect to the first switching circuit 10 in Figure 1.

[0007] In either case, the inductor 16 provided in the choke circuit 14 is a relatively large device and actually determines the overall volume of the switching circuits 10 and 20 shown in Figures 1 and 2.

[0008] International Publication No. 2021 / 197774 discloses a power semiconductor device comprising a thyristor and a bipolar junction transistor (BJT) that can avoid some of the drawbacks of known IGCTs and / or switching circuits. In particular, it provides a power semiconductor device in which system losses are reduced and the need for protection circuits such as the snubber circuit mentioned above is reduced. [Overview of the project] [Problems that the invention aims to solve]

[0009] In particular, an object of this disclosure is to provide components suitable for implementing improved power semiconductor devices that can be integrated and packaged together in order to provide a simple but effective and fully controllable power semiconductor switching assembly. [Means for solving the problem]

[0010] According to one aspect of the present disclosure, a fully controllable power semiconductor switching assembly is provided. The assembly comprises a first unit comprising a latching power semiconductor switching device controlled by a first gate terminal, a second unit comprising a non-latching power semiconductor switching device controlled by a second gate terminal, and a power semiconductor diode. The latching power semiconductor switching device and the non-latching power semiconductor switching device are connected in parallel with respect to the current switched by the switching assembly, and the power semiconductor diode is connected in antiparallel with respect to the current switched by the switching assembly.

[0011] The disclosed assembly enables control of the switch-on and switch-off operation of a power semiconductor-based switching circuit, where voltage changes during switch-on and current changes during switch-off can be controlled by corresponding gate control signals. This, in particular, enables fully snubberless operation of a fully controllable power semiconductor switching assembly. To avoid any integration problems, at least at the packaging level, the latching power semiconductor switching device and the non-latching power semiconductor switching device are integrated into two separate units, each having its own gate terminal. Therefore, standard packaging and integration techniques for semiconductor power devices having only a single control terminal can be employed.

[0012] According to different embodiments, the power semiconductor diode may be integrated into a first unit, a second unit, or a further third unit. This degree of freedom is based on the insight that the power semiconductor diode does not need to be controlled by a corresponding gate terminal. For example, if the power semiconductor diode is integrated into one of the first or second units, further housing and / or control terminals are not required for the entire assembly, thus facilitating integration.

[0013] According to at least one embodiment, the diode structure of a semiconductor diode is integrated into a common housing, such as the housing of a non-latching power semiconductor switching device.

[0014] According to at least one embodiment, the first unit and / or the second unit may further comprise gate units for a latching power semiconductor switching device and / or a non-latching power semiconductor switching device, respectively. For example, the power semiconductor switching device and the corresponding gate unit may be arranged on a common printed circuit board (PCB).

[0015] According to at least one embodiment, the size of the first unit corresponds to the size of the second unit, and / or the latching power semiconductor switching device is integrated into the first housing, in particular the housing of the first presspack device, and the non-latching power semiconductor switching device is integrated into the second housing, in particular the housing of the second presspack device, and the size of the first housing corresponds to the size of the second housing. By using first and second units and / or power semiconductor devices of essentially the same size, it becomes possible to integrate different functional units into a larger switching assembly. In particular, when semiconductor power diodes are integrated in a common housing with non-latching power semiconductor switching devices, the power densities of the first and second units can be equivalent, thus resulting in a symmetrical thermal load for both the unit and the power semiconductor devices contained therein.

[0016] Further aspects of the present disclosure provide a power semiconductor device, particularly for the switching assembly described above. The power semiconductor device comprises a sealed housing having a first power terminal, a second power terminal, and a gate terminal; a non-latching power semiconductor switching device disposed within the sealed housing and configured to selectively switch current from the first power terminal to the second power terminal based on a control signal provided via the gate terminal; and a power semiconductor diode disposed within the sealed housing and configured to conduct current from the second power terminal to the first power terminal.

[0017] Such a power semiconductor device, which integrates a non-latching power semiconductor switching device and a power semiconductor diode into a single encapsulated housing having a single gate terminal and two power terminals, is particularly useful for implementing a second unit of the non-latching power semiconductor switching device in the assembly. However, it does not integrate the functionality of a latching power semiconductor switching device into the same housing, thus reducing the need for a second gate terminal in the same housing.

[0018] In at least one embodiment, a non-latching power semiconductor switching device and a power semiconductor diode are formed as a semiconductor structure on or within a common semiconductor substrate. Such substrate or wafer-level integration of two functional semiconductor structures further facilitates device integration.

[0019] In at least one embodiment, the power semiconductor device is a presspack device, and the sealing housing comprises a conductive first housing portion forming a first power terminal, a conductive second housing portion forming a second power terminal, an insulating sidewall separating the first metal housing portion from the second metal portion, and a bushing disposed in or within the insulating sidewall and configured to provide a control signal to the gate terminal. Such a presspack device having a bushing configured to provide a single control signal to a single gate terminal can be easily integrated with existing power electronic components.

[0020] In different embodiments, the latching power semiconductor switching device may include at least one integrated gate commutation thyristor (IGCT) structure. Such an IGCT structure is particularly useful for switching and holding high currents and / or high voltages. Using such a structure, it is possible to control the dv / dt voltage change while the latching power semiconductor switching device is being switched off.

[0021] Non-latching power semiconductor switching devices: Power semiconductor devices may comprise at least one bipolar junction transistor (BJT) structure or a non-latching thyristor structure. Such structures can be used to control di / dt current changes while a latching power semiconductor switching device is being switched on.

[0022] Further aspects of the present disclosure provide a snubberless power converter, in particular a power inverter, comprising a fully controllable power semiconductor switching assembly as detailed above.

[0023] The advantages of the power converters offered correspond to those detailed above with respect to the switching assemblies and power semiconductor devices, respectively. In particular, such power converters do not require internal or external snubber circuits, thus reducing the need to provide relatively bulky additional circuit components such as inductors or other throttling components.

[0024] In at least one embodiment, the power converter further comprises a control circuit configured to provide at least one control signal for controlling a non-latching power semiconductor switching device and / or a latching power semiconductor switching device. By also providing the corresponding control circuit, a fully integrated switching device and / or power converter can be realized.

[0025] According to different embodiments, the control circuit may be directly or indirectly connected to the first and second units, and may be configured to provide a first control signal to the first gate terminal and a second control signal to the second terminal. In particular, in the case of indirect connection, a master control unit forming part of one of the two units may be used to indirectly provide control signals to the other unit, for example, the slave control units of the other unit.

[0026] In at least one embodiment, the controller may be specifically configured to apply a positive gate current between the gate terminal and the cathode terminal of the non-latching power semiconductor switching device when the switching assembly is switched on. Further, after triggering the gate of the latching power semiconductor switching device and after the voltage between the anode and the gate terminal of the latching power semiconductor switching device collapses, the positive gate current between the gate terminal and the cathode terminal of the non-latching power semiconductor switching device may be reduced to zero. Further, when the switching assembly is switched off, a negative gate current may be applied to the gate terminal of the latching power semiconductor switching device and optionally to the gate terminal of the non-latching power semiconductor switching device.

[0027] The above operations enforce a safe operation of the switching assembly or a forced switch-on and non-operation or switch-off, and thus enable a snubberless operation of the power converter.

[0028] According to a further aspect of the present disclosure, a method for manufacturing a power converter is provided. The manufacturing method comprises - providing a first unit comprising a latching power semiconductor switching device controlled by a first gate terminal; - providing a second unit comprising a non-latching power semiconductor switching device controlled by a second gate terminal; - providing a power semiconductor diode within the first unit, within the second unit, or within a separate third unit; - connecting the latching power semiconductor switching device and the non-latching power semiconductor switching device in a parallel configuration with respect to a current switched by the power converter; - connecting the power semiconductor diode in an anti-parallel configuration with respect to the current switched by the power converter and including.

[0029] The steps described above essentially enable the manufacture of power converters as detailed above.

[0030] This disclosure provides several embodiments of power semiconductor switching assemblies. All features described in relation to one embodiment are also disclosed herein in relation to other embodiments, even if each feature is not explicitly mentioned in the context of a particular embodiment.

[0031] The accompanying drawings are included to provide a further understanding of the disclosed devices, systems, and methods. In the drawings, elements of the same structure and / or function may be referred to by the same reference numerals. Please understand that the embodiments shown in the drawings are illustrative and not necessarily drawn to a specific scale. [Brief explanation of the drawing]

[0032] [Figure 1] This shows a semiconductor switching circuit equipped with a snubber circuit. [Figure 2] Figure 1 shows a semiconductor switching circuit that includes a snubber circuit, different from the one shown in Figure 1. [Figure 3] This shows a snubberless semiconductor switching circuit. [Figure 4] This shows a switching assembly with three power semiconductor structures and corresponding devices. [Figure 5] Figure 4 shows the implementation of a switching assembly based on three semiconductor device functional units. [Figure 6] Figure 4 shows the implementation of a switching assembly based on two semiconductor device functional units. [Figure 7] Figure 6 shows a different implementation of the switching assembly shown in Figure 4, based on two semiconductor device functional units. [Figure 8] An embodiment of an inverter circuit comprising an inverter controller and a power semiconductor switching assembly is shown. [Figure 9]Figure 8 shows an embodiment of an inverter circuit comprising an inverter controller and a power semiconductor switching assembly. [Figure 10] Figures 8 and 9 show an embodiment of an inverter circuit comprising an inverter controller and a power semiconductor switching assembly. [Figure 11] Figures 8 to 10 show an embodiment of an inverter circuit comprising an inverter controller and a power semiconductor switching assembly. [Figure 12] A perspective view of a unit comprising a power semiconductor switching device and a corresponding gate unit is shown. [Figure 13] This shows a cross-sectional view of a power semiconductor switching device. [Figure 14] This shows a comparison of substrate regions for two different power semiconductor switching devices. [Figure 15] The steps for manufacturing a power converter are shown. [Modes for carrying out the invention]

[0033] Figure 3 shows a third switching circuit 30 that can be safely switched on and off without a snubber circuit. This is made possible by using two improved power semiconductor switching elements 31 that can be switched on and off in a controlled manner, similar to an insulated-gate bipolar transistor (IGBT). The power semiconductor switching element 31 comprises a fully controllable integrated gate-controlled thyristor (FCGCT) 32 and a freewheeling diode 22. The FCGCT 32 can be realized by integrating two functional structures, such as an IGCT structure, and a non-latching switching structure, such as a BJT structure, on a common substrate forming a single power semiconductor device. Optionally, the diode structure for the freewheeling diode 22 may also be formed on the common substrate.

[0034] While the switch is on, the current change di / dt of the switching element 31 can be controlled by driving the gate of the BJT structure of the FCGCT32. Similarly, while the switch is off, the voltage change dv / dt of the switching element 31 can also be controlled by driving the gate of the IGCT structure of the FCGCT32. While such an FCGCT-based switching element 31 may be desirable for the reasons described above regarding its switching behavior, providing two separate gate terminals results in a relatively complex housing when the FCGCT32 is installed in a larger assembly such as a converter or similar power switching circuit.

[0035] According to different embodiments of this disclosure, this problem and other problems are addressed by packaging at least some of the structures for implementing the FCGCT32 into two or three separate chips or devices rather than a single chip or device, each device or chip having only a single control terminal.

[0036] Figure 4 shows a typical switching assembly 40 according to this disclosure that implements the functionality corresponding to the functionality of the improved power semiconductor switching element 31. The switching assembly 40 comprises an IGCT structure 46, a BJT structure 47, and a diode structure 48. In contrast to the improved power semiconductor switching element 31 based on an integrated FCGCT 32, each of the IGCT structure 46, BJT structure 47, and diode structure 48 may be integrated into a separate power semiconductor device. As shown in Figure 4, these three devices are referred to in the context of this disclosure as a “thyristor device” or latching power semiconductor switching device 41, a “transistor device” or non-latching power semiconductor switching device 42, and a power semiconductor diode 43. Each of the two switching devices 41, 42 has its own gate terminals 44, 45, respectively.

[0037] Generally, such a switching assembly 40 may be integrated into two or three units, as will be further detailed below with respect to Figures 5 to 7. Here, the term “unit” may refer to a physically separate unit, such as a complete integrated circuit chip or device, or to several circuit chips or devices arranged on a common carrier substrate, such as a PCB, and / or incorporated into a common housing. The term “device,” in particular “semiconductor switching device,” may refer to the unit itself or one of its components. For example, the first unit may refer to a first PCB, and the latching power semiconductor switching device may be a first presspack device arranged on or permanently connected to the first PCB. Similarly, the second unit may refer to a second PCB, and the non-latching power semiconductor switching device may be a second presspack device arranged on or permanently connected to the second PCB. In contrast, the term “structure,” in particular the terms “IGCT structure,” “thyristor structure,” “BJT structure,” “transistor structure,” and “diode structure,” typically refer to the internal parts of a larger device or unit. For example, the IGCT structure and diode structure may be integrally formed on or within the substrate of a first semiconductor power device, such as a first presspack. Similarly, the BJT structure and diode structure may be integrally formed on or within the substrate of a second semiconductor power device, such as a second presspack device.

[0038] In the configuration shown in Figure 5, a total of three units 51 to 53 are provided. The first unit 51 comprises a latching power semiconductor switching device 41 and a corresponding first gate control unit 54. The second unit 52 comprises a non-latching power semiconductor switching device 42 and a corresponding second gate unit 55. The third unit 53 comprises a power semiconductor diode 43.

[0039] As shown in Figure 5, each of the power semiconductor devices 41 to 43 is provided with a first power terminal 56 and a second power terminal 57. In the described embodiment, the latching power semiconductor switching device 41 is implemented by an IGCT structure 46. In this case, the first power terminal 56 corresponds to the anode of the thyristor structure contained therein, and the second power terminal 57 corresponds to the cathode.

[0040] The non-latching power semiconductor switching device 42 may be implemented in the form of a BJT structure 47 or a non-latching thyristor structure. For example, the non-latching power semiconductor switching device 42 may have a quench or non-standalone thyristor structure that automatically turns off when a reasonable gate current through its gate electrode turns off. In other words, the non-latching thyristor structure may have a low current gain product that does not latch in normal operation. In particular, the thyristor structure is designed to be non-standalone, for example, by automatically turning off when a gate current through its assigned gate electrode turns off.

[0041] In the case of the BJT structure 47, the first power terminal 56 corresponds to the collector of the BJT or the anode of the non-latching thyristor structure. The second power terminal 57 corresponds to the emitter of the BJT structure 47 or the cathode of the non-latching thyristor structure. That is, the first latching power semiconductor switching device 41 and the second non-latching power semiconductor switching device 42 are configured in parallel with respect to the current switched by the switching assembly 40.

[0042] In contrast, the anode of the power semiconductor diode 43 or the diode structure 48 contained therein is connected to the second power terminal 57, and its cathode is connected to the first power terminal 56. That is, the power semiconductor diode 43 is configured in antiparallel with respect to the power semiconductor switching devices 41 and 42. Therefore, during operation, the power semiconductor diode 43 functions as a freewheeling diode.

[0043] The first and second gate units 54 and 55 are connected to the first gate terminal 44 of the latching power semiconductor switching device 41 and the second gate terminal 45 of the non-latching power semiconductor switching device 42. They are provided to supply appropriate control signals to their respective gate terminals to safely switch the first gate unit 54 of the switching assembly 40 off and the second gate unit 55 on.

[0044] In particular, the switching assembly 40 operates as described below. When turned on, a gate current is applied between the second gate terminal 45 and the second power terminal 57 of the non-latching power semiconductor switching device 42. When a thyristor structure is used as a non-latching power semiconductor switching device 41, the current change di / dt of the current, especially the anode current, is controlled by the current change di / dt of the applied gate current. In the case of a BJT structure, the operation is basically the same. However, a higher gate current is used to drive the BJT structure. In this case, the second gate terminal 44 of the latching switching device 41 is kept in the off state.

[0045] As soon as the anode / cathode voltage across the latching power semiconductor switching device 41 collapses to, for example, 25% of the DC link voltage typically switched by the switching assembly 40, the gate of the latching power semiconductor switching device 41 is triggered by the corresponding gate current supplied from the first gate unit 54 to the first gate terminal 44. The gate current of the non-latching power semiconductor switching device 42 then drops back down to zero. Thus, the current flowing through the switching assembly 40 is commutated from the non-latching power semiconductor switching device 42 to the latching power semiconductor switching device 41. Once current flows through the latching power semiconductor switching device 41, the gate current of the latching power semiconductor switching device 41 can also be deactivated.

[0046] When the switching assembly 40 is to be turned off, a negative gate current is applied to the gate IGCT structure 46 of the latching power semiconductor switching device 41 by the first gate unit 54 and the first gate contact 44. Optionally, a negative gate current may also be applied to the non-latching semiconductor switching device 42 by the second control unit 55 and the second gate terminal 45.

[0047] Figure 6 shows an alternative embodiment of the switching assembly 40 according to one embodiment of the present disclosure. In contrast to the configuration detailed above with respect to Figure 5, the configuration shown in Figure 6 comprises only two units 61 and 62. Each of the units 61 and 62 comprises a single power semiconductor switching device, namely a latching power semiconductor switching device 41 and a non-latching power semiconductor switching device 42. In addition, the first unit 61 further comprises a diode 48 structure directly integrated into the latching power semiconductor switching device 41. In other words, the semiconductor switching device 41 of the first unit 61 comprises an IGCT structure 46 and a diode structure 48. The non-latching power semiconductor switching device 42 comprises only a transistor structure such as a BJT structure 47 or a quenched IGCT, as detailed above with respect to the second unit 52. Various terminals and their interconnections correspond to the configuration shown in Figure 5 and will not be described again for brevity.

[0048] Note that despite the integration of the diode structure 48 into the first power semiconductor switching device 41, it is necessary to provide only a single gate terminal 44 for the latch-type power semiconductor switching device 41. Therefore, each of the first and second power semiconductor switching devices 41 and 42 can be integrated into a conventional housing, such as a press-pack device housing having a single control gate terminal.

[0049] Figure 7 shows a further configuration of the switching assembly 40, similar to the configuration shown in Figure 6, in that it also comprises only two units, namely the first unit 71 and the second unit 72. In contrast to the configuration shown with respect to Figure 6, the diode structure 48 is integrated into the non-latching power semiconductor switching device 42. In contrast, the non-latching power semiconductor switching device 41 comprises only the IGCT structure 46. Other embodiments of the switching assembly 40 in Figure 7 correspond to the embodiments in Figures 5 and 6 and will not be described again for brevity.

[0050] As detailed above, integrating the diode structure 48 into the non-latching power semiconductor switching device 42 eliminates the need for additional gate terminals. Therefore, the non-latching power semiconductor switching device 42 also has only a single gate terminal 45. Furthermore, as detailed in Figure 14 below, this particular configuration has the advantage of enabling thermal equilibrium of the two power semiconductor switching devices 41 and 42.

[0051] Figures 8 to 11 show different embodiments of a portion of the converter circuit 80, particularly a portion of the inverter. In the embodiments shown in Figures 8 to 11, a switching assembly 40 comprising three separate power semiconductor devices 41 to 43 is shown. However, the control signals described with respect to Figures 8 to 11 can be equally applied to either of the two unit configurations of the switching assembly 40 shown in Figures 6 and 7.

[0052] In particular, in the converter circuit 80 shown in Figure 8, the inverter control circuit 81 directly provides two different control signals to the first gate unit 54 and the second gate unit 55, respectively. In contrast, in the configuration shown in Figure 9, the inverter controller 81 simply directly supplies a single control signal to the first gate unit 54. The gate unit 54 is configured as a master controller and generates a second control signal corresponding to the second gate unit 55, which is configured as a slave controller. Figure 10 shows a complementary configuration in which the controller 81 directly provides a control signal to the second gate unit 55. The second gate unit 55 is configured as a master controller and provides a control signal corresponding to the first gate unit 54, which is configured as a slave controller.

[0053] In the configuration shown in Figure 11, only a single composite gate unit 82 is provided and is directly controlled by a control circuit 81. The composite gate unit 82 provides a first control signal to the first gate terminal 44 of the latching power semiconductor switching device 41 and a second control signal to the second gate terminal 45 of the non-latching power semiconductor switching device 42. The composite gate unit 82 may be, for example, part of the first unit 51, 61, or 71 or the second unit 52, 62, or 72. Alternatively, the composite gate unit 82 may be part of a PCB having a separate entity, such as an inverter controller 81.

[0054] Figure 12 shows one of the switching units 90 of at least two units of the switching assembly 40. In particular, the switching unit 90 shown in Figure 12 may correspond to the second unit 72 shown in Figure 7.

[0055] As shown in Figure 12, the switching unit 90 comprises a printed circuit board (PCB) 91, a first housing 92 covering a portion of the PCB 91, and a press pack device 94 placed on the PCB 91 and having a second housing 93. As will be described in more detail below, the first housing 92 may be, for example, an open metal housing, and the second housing 93 may be, for example, a sealed high-voltage protective housing.

[0056] In the embodiment described above, the presspack device 94 corresponds to the non-latching power semiconductor switching device 42. The first and second power terminals 56 and 57 of the non-latching power semiconductor switching device 42 are formed on the upper and lower sides of the presspack device 94. The gate terminal 45 and auxiliary contacts connected to the second power terminal 57 of the non-latching power semiconductor switching device 42 (neither of which are shown in Figure 12) are electrically connected to the respective control terminals of the PCB 91. The processing circuit for mounting the second gate unit 55 is located within the first housing 92. Optionally, all or part of the processing circuitry required to mount the inverter controller 81 or the first gate unit 54 may also be located on the PCB 91.

[0057] Figure 13 shows a cross-sectional view of the power semiconductor device 100. In the described embodiment, the power semiconductor device 100 implements a non-latching type power semiconductor switching device 42 having an integrated semiconductor power diode 43. Figure 13 specifically shows the internal configuration of a presspack device such as the presspack device 94 in Figure 12.

[0058] As seen in the cross-section of Figure 13, the housing of the power semiconductor device 100 comprises a first housing portion 101, shown as the lower housing portion in Figure 13, a second housing portion 102, shown as the upper housing portion in Figure 13, and one or more insulating sidewalls 103. A portion of the second housing portion 102 forms an auxiliary cathode contact 108. The first and second housing portions 101, 102 are formed from a material having good conductivity, such as copper or another suitable metal, and form the external portions of the power terminals 56, 57 of both the power semiconductor switching device 42 and the integrated semiconductor power diode 43. They are separated by the insulating sidewalls 103. For example, the insulating sidewalls 103 may take the form of a hollow cylinder made from ceramic or other insulating material. As further shown in Figure 13, the outer surface of the insulating sidewalls 103 may have an integrated shed structure 104 to increase the creep distance between the first housing portion 101 and the second housing portion 102. The insulating sidewall 103 further comprises a bushing 105 for passing the gate lead 106. The housing portions 101-103 and 105 together form a hermetically sealed cavity 107 for one or more electronic components of the presspack device.

[0059] In the illustrated embodiment, the electronic component takes the form of a semiconductor structure formed within a semiconductor substrate 110, such as a semiconductor wafer. The substrate 110 is held in place by a wafer edge insulator 111. The wafer edge insulator 111 may be made of, for example, silicon. As seen in the cross section of Figure 13, the semiconductor substrate 110 has different functional regions related to different semiconductor structures formed therein. Moving outward from the center, the semiconductor substrate 110 comprises a thyristor gate contact region 112, a turn-on thyristor region 113, and a diode region 114. The lower main surface of the turn-on thyristor region 113, corresponding to the anode of the non-latching thyristor structure, and the diode region 114, corresponding to the cathode of the diode structure, are in direct contact with a first internal portion 116 of a first power terminal 56, which may be made of molybdenum. The upper surface of the turn-on thyristor portion 113, which corresponds to the cathode of the non-latching thyristor structure, and the upper surface of the diode portion 114, which corresponds to the anode of the diode structure, are in direct contact with the second internal portion 117 of the second power terminal 57, which is formed from, for example, molybdenum. The thyristor gate contact region 112 is separated from the two internal portions 116 and 117 and is connected to the gate lead 106.

[0060] The left side of Figure 14 shows a schematic top view of the semiconductor substrate 110 of Figure 13. The thyristor gate contact region 112 and the turn-on thyristor portion 113 of the semiconductor substrate 110 are used to mount the non-self-supporting thyristor structure 118 of the non-latching power semiconductor switching device 42. Although the non-self-supporting thyristor structure 118 is shown in Figures 13 and 14, the corresponding BJT structure 47 may be mounted as detailed above with respect to Figures 4 to 11. The external portion of the semiconductor substrate 110 is used to mount the diode structure 48 of the non-latching power semiconductor switching device 42.

[0061] The right-hand portion of Figure 14 shows another semiconductor substrate 120 used to mount a latching power semiconductor switching device 41 having an IGCT structure 46. It comprises a central thyristor gate contact region 121 and a retaining thyristor portion 122 surrounding it. By comparing the top views of Figure 14, it becomes clear that more surface area is available for mounting the freestanding IGCT structure 46 of the latching power semiconductor switching device 41 than for the non-freestanding thyristor structure of the non-latching power semiconductor switching device 42. This is advantageous for thermal equilibrium or load equilibrium, as the IGCT structure 46 carries the majority of the current switched by the corresponding semiconductor power switching assembly 30 on average. Thus, thermal equilibrium between the two devices 41 and 42 can be achieved when the same housing type or housing type having at least similar size is used to encapsulate the first and second semiconductor switching devices 41 and 42.

[0062] Further details regarding suitable IGCT, BJT, and diode structures, as well as their fabrication and integration, can be found in International Publication No. 2021 / 197774, which is incorporated herein by reference. Further details regarding suitable self-supporting thyristor, non-self-supporting thyristor, and diode structures, as well as their fabrication and integration, can be found in European Patent Application No. 21212227.9, which is incorporated herein by reference.

[0063] Figure 15 shows a schematic flowchart of steps S1 to S5 used to manufacture a power converter such as the converter circuit 80.

[0064] In step S1, a first unit having a first gate terminal is provided. As detailed with respect to the various embodiments described above, the first unit comprises at least a latching power semiconductor switching device and may also comprise further components such as a diode structure or device and / or a first gate unit.

[0065] In step S2, a second unit having a second gate terminal is provided. As detailed with respect to the various embodiments described above, the second unit comprises at least a non-latching power semiconductor switching device and may comprise further components such as a diode structure or device and / or a second gate unit. In particular, if the first unit does not comprise a diode structure or device, the second unit may comprise a diode structure or device.

[0066] In step S3, a power semiconductor diode is provided. As detailed above, this may be a diode structure or device that forms part of the first unit or the second unit. Alternatively, a separate third unit comprising a diode structure or device may be provided in step S3.

[0067] In step S4, the latching power semiconductor switching device included in the first unit and the non-latching power semiconductor switching device included in the second unit are connected in parallel with respect to the current switched by the power converter. For example, this can be achieved by placing the corresponding conductive housing components of the corresponding press-pack devices between common busbars.

[0068] In step S5, the power semiconductor diode is connected in antiparallel to the current switched by the power converter. If the power semiconductor diode is formed in a separate unit, such as a third unit, this can be achieved by oriented the third unit in the opposite direction to the first and second units. If the power semiconductor device is formed as an integration of the first or second units, this is typically achieved in the design phase by arranging the anode contact of the diode structure on the same surface of the semiconductor substrate as the cathode portion of the corresponding thyristor structure or the emitter of the corresponding transistor structure. Similarly, the cathode of the diode structure may be formed on the same surface as the anode portion of the thyristor structure or the collector of the corresponding transistor structure.

[0069] The embodiments shown in Figures 1 to 15 above represent exemplary embodiments of improved power semiconductor switching configurations, power semiconductor devices, converter circuits, and methods for manufacturing them. Therefore, they do not constitute a complete list of all embodiments of the improved devices, systems, and methods. Actual devices, configurations, and methods may differ from the embodiments shown, for example, with respect to their relative configurations, specific components, and signals provided for their control. [Explanation of Symbols]

[0070] Reference sign 10 (First) Switching Circuit 11 Switching elements 12 Central Nodes 13. Snubber Circuit 14. Choke circuit 15. Clamp Circuit 16 Inductors 17 Diodes 18 resistors 19 Capacitors 20 (Second) Switching Circuit 21. Integrated Gate Commutation Thyristor (IGCT) 22 Freewheeling diode 30 (Third) Switching Circuit 31 Power semiconductor switching elements 32. Fully controllable gate commutation thyristor (FCGCT) 40 Switching Assembly 41 (Latching type) power semiconductor switching devices 42 (Non-Latching) Power Semiconductor Switching Devices 43 Power semiconductor diodes 44 First gate terminal 45 Second gate terminal 46 IGCT structure 47 BJT structure 48 Diode Structure 51. Unit 1 52. Second Unit 53. The Third Unit 54 First Gate Unit 55 Second Gate Unit 56 First power terminal 57 Second power terminal 61. Unit 1 62. Second Unit 71. The First Unit 72. Second Unit 80 Converter Circuit 81 Control circuits 82 Composite Gate Unit 90 Switching Units 91 Printed circuit board (PCB) 92 First Housing 93 Second Housing 94 Press Pack Devices 100 Power Semiconductor Devices 101 First Housing Section 102 Second Housing Section 103 Insulating sidewall 104 Shed-like structure 105 Bushing 106 Gate Lead 107 Cavity 108 Auxiliary Cathode Contact 110 Semiconductor substrates 111 Wafer edge insulation 112 Thyristor gate contact region 113 Turn-on thyristor section 114 Diode section 116 First internal part (of the first power terminal) 117 Second internal part (of the second power terminal) 118 Non-self-supporting thyristor structure 120 (Further) Semiconductor Substrates 121 Thyristor gate contact region 122 Holding thyristor section

Claims

1. A fully controllable power semiconductor switching assembly (40), - A first unit (51, 61, 71) comprising a latch-type power semiconductor switching device (41) controlled by a first gate terminal (44), - A second unit (52, 62, 72) comprising a non-latching power semiconductor switching device (42) controlled by a second gate terminal (45), - Power semiconductor diode (43) and Equipped with, - The latching power semiconductor switching device (41) and the non-latching power semiconductor switching device (42) are connected in parallel to the current switched by the switching assembly (40), and the power semiconductor diode (43) is connected in antiparallel to the current switched by the switching assembly (40). Switching assembly (40).

2. The switching assembly (40) according to claim 1, wherein the semiconductor diode (43) is integrated into the second unit (72) as a diode structure (48) particularly integrated in the housing of the non-latching power semiconductor switching device (42).

3. - The semiconductor diode (43) is integrated into the first unit (61) as a diode structure (48) integrated in a housing for the latch-type power semiconductor switching device (41), or - The switch assembly further comprises a third unit (53) having the power semiconductor diode (43) as a diode structure (48) integrated in a separate housing, The switching assembly (40) according to claim 1.

4. The first unit (51, 61, 71) further comprises a composite gate unit (82) for the latching power semiconductor switching device (41) and the non-latching power semiconductor switching device (42), - The second unit (52, 62, 72) further comprises a composite gate unit (82) for the latching power semiconductor switching device (41) and the non-latching power semiconductor switching device (42), or - The first unit (51, 61, 71) further comprises a first gate unit (54) for the latching power semiconductor switching device (41), and the second unit (52, 62, 72) further comprises a second gate unit (55) for the non-latching power semiconductor switching device (42), A switching assembly (40) according to any one of claims 1 to 3.

5. - The size of the first unit (51, 61, 71) corresponds to the size of the second unit (52, 62, 72), and / or - The latching power semiconductor switching device (41) is integrated into a first housing, particularly the housing of a first presspack device, and the non-latching power semiconductor switching device (42) is integrated into a second housing (93), particularly the housing (103) of a second presspack device (94), and the size of the first housing corresponds to the size of the second housing (93), A switching assembly (40) according to any one of claims 1 to 4.

6. The switching assembly (40) according to any one of claims 1 to 5, wherein the latch-type power semiconductor switching device (41) comprises at least one integrated gate-commutated thyristor (IGCT) structure (46).

7. A power semiconductor device (100), particularly a power semiconductor device (100) for a switching assembly (40) according to any one of claims 1 to 6, - A sealing housing (93) having a first power terminal (56), a second power terminal (57), and a gate terminal (45), - A non-latching power semiconductor switching device (42) is disposed within the sealing housing (93) and configured to selectively switch the current from the first power terminal (56) to the second power terminal (57) based on a control signal provided via the gate terminal (45), - A power semiconductor diode (43) is disposed within the sealing housing (93) and configured to conduct current from the second power terminal (57) to the first power terminal (56). A power semiconductor device (100) comprising the above.

8. The power semiconductor device (100) according to claim 7, wherein the non-latching power semiconductor switching device (42) and the power semiconductor diode (43) are formed as semiconductor structures (47, 48, 118) on or inside a common semiconductor substrate (110).

9. The press pack device (94) is the sealing housing (93), - A conductive first housing portion (101) that forms at least a part of the first power terminal (56), - A conductive second housing portion (102) that forms at least a part of the second power terminal (57), - An insulating side wall (103) separating the first housing portion (101) and the second housing portion (102), - A bushing (105) is disposed on or inside the insulating side wall (103) and is configured to provide the control signal to the gate terminal (45). A power semiconductor device (100) according to claim 7 or 8, comprising the above.

10. - The non-latching power semiconductor switching device (42) comprises a bipolar transistor structure (47), or - The non-latching type power semiconductor switching device (42) includes a non-self-standing thyristor structure (118), A switching assembly (40) according to any one of claims 1 to 6, or a power semiconductor device (100) according to any one of claims 7 to 9.

11. A snubberless power converter, particularly a power inverter, comprising a fully controllable power semiconductor switching assembly (40) according to any one of claims 1 to 6.

12. - A control circuit (81) configured to provide at least one control signal for controlling the non-latching power semiconductor switching device (41) and / or the latching power semiconductor switching device (42). The snubberless power converter according to claim 11, further comprising:

13. - The control circuit (81) is connected to both the first units (51, 61, 71) and the second units (52, 62, 72) and is configured to provide a first control signal to the first gate unit (54) associated with the first gate terminal (44) and a second control signal to the second gate unit (55) associated with the second gate terminal (45), - The control circuit (81) is connected to the first unit (51, 61, 71) and configured to provide a first control signal to a master control unit associated with the first gate terminal (44), in particular the composite gate unit (82) or the first gate unit (54) as described in claim 4, and the master control unit is configured to provide a second control signal to the second unit (52, 62, 72), or - The control circuit (81) is connected to the second units (52, 62, 72) and configured to provide a second control signal to a master control unit associated with the second gate terminal (45), in particular the composite gate unit (82) or the second gate unit (55) described in claim 4, and the master control unit is configured to provide a first control signal to the first units (51, 61, 71). The snubberless power converter according to claim 12.

14. The controller (81) - When the switching assembly (40) is switched on, a positive gate current is applied between the gate terminal (45) and the cathode terminal of the non-latching power semiconductor switching device (42). - After the voltage between the anode and gate terminal (44) of the latching power semiconductor switching device (41) collapses, the gate of the latching power semiconductor switching device (41) is triggered, and the positive gate current between the gate terminal (45) and cathode terminal of the non-latching power semiconductor switching device (42) is reduced to zero, and - When the switching assembly (40) is switched off, a negative gate current is applied to the gate terminal (44) of the latching power semiconductor switching device (41), and optionally a negative gate current is applied to the gate terminal (45) of the non-latching power semiconductor switching device (42). A snubberless power converter according to claim 12 or 13, particularly configured as described above.

15. A method for manufacturing a power converter, particularly a snubberless power converter according to any one of claims 11 to 14, - To provide a first unit (51, 61, 71) comprising a latch-type power semiconductor switching device (41) controlled by a first gate terminal (44), To provide a second unit (52, 62, 72) comprising a non-latching power semiconductor switching device (42) controlled by a second gate terminal (45), - To provide a power semiconductor diode (43) within the first unit (61), within the second unit (72), or within a separate third unit (53), - The latching power semiconductor switching device (41) and the non-latching power semiconductor switching device (42) are connected in parallel to the current that is switched by the power converter, The power semiconductor diode (43) is connected in an antiparallel configuration to the current that is switched by the power converter. Methods that include...

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