Avalanche Photodiode Device

Abstract

The present invention relates to an avalanche photodiode (APD) subassembly and an APD device (400). The APD subassembly comprises a substrate (401), a first contact layer (403) formed on the substrate (401), a second contact layer (402), and an antimony-containing avalanche layer (406). The avalanche layer (406) is disposed between the first contact layer (403) and the second contact layer (402). The first contact layer (403) is an n-type contact layer. The second contact layer (403) includes a p-type contact region (450) formed by diffusing zinc. The p-type contact region (450) has a smaller cross-sectional area than the avalanche layer (406), and its cross-sectional area is perpendicular to the direction from the substrate (401) to the second contact layer (402).

Description

[Technical Field]

[0001] The present invention relates to an avalanche photodiode (APD) device, and more particularly to an APD device comprising an avalanche layer containing antimony. [Background technology]

[0002] Avalanche photodiode (APD) devices possess internal gain and are used to improve the sensitivity of optical systems. Examples of applications include laser ranging, light detection and ranging (LIDAR) systems using time-of-flight and frequency-modulated continuous wave measurements, optical time-domain reflectance measurements, telecommunications, quantum communications, and computing. The internal gain of an APD is generated through a process called collisional ionization, in which a charge carrier gains energy in a high electric field and multiplies it. InGaAs lattices matched to InP have a bandgap energy of 0.75 eV at room temperature and are used as absorption layers in a wide range of infrared detectors. However, InGaAs is not suitable for generating avalanche gain because its narrow bandgap generates excessive tunneling current in the high electric fields required for collisional ionization. To minimize tunneling current, infrared APDs use a design called SAM (Separate Absorption and Multiplication) APDs. In SAMAPDs, a broader bandcap semiconductor is used for avalanche gain, while a separate, narrower bandcap semiconductor is used for light absorption.

[0003] From GB2591320B, it is known that a SAMAPD structure is provided comprising an absorption layer containing InGaAs, InGaAlAs, InGaAsP, or an InGaAs / GaAsSb type II superlattice, and an avalanche layer containing AlGaAsSb. In APDs, AlGaAsSb has near-ideal avalanche multiplication characteristics, resulting in an ultra-low noise APD. AlGaAsSb-based APDs can operate at ultra-high levels of avalanche gain while remaining linear or sub-Geiger mode. However, operating AlGaAsSb-based SAMAPDs at high gain and low noise requires a very uniform electric field region within the multiplication region.

[0004] The presence of antimony (Sb) in the avalanche layer can result in defects or irregularities when manufacturing SAMAPDs. These defects or irregularities can be caused by the Sb-containing alloy having a different etch rate compared to other semiconductors in the structure, or by the antimony-containing alloy oxidizing during wet etching. For example, when wet etching an AlGaAsSb-based SAMAPD, the different etch rate of the antimony-containing alloy compared to the antimony-free semiconductor can form irregular profiles on the sidewalls of the SAMAPD. Defects or irregularities within the SAMAPD can create localized areas of high electric fields (known as hot spots) within the device, leading to current leakage and reliability problems, thereby limiting the performance of the device.

[0005] The objective of certain embodiments of the present invention is to overcome certain drawbacks associated with the prior art. In particular, embodiments of the present invention may provide an APD having an antimony-containing avalanche layer that is capable of high-gain, low-noise operation and has improved manufacturing reliability. [Overview of the project]

[0006] According to one aspect of the present invention, circuit board and A first contact layer formed on the substrate, The second contact layer, An avalanche layer containing antimony, wherein the avalanche layer is disposed between a first contact layer and a second contact layer. an avalanche photodiode (APD) subassembly comprising, The first contact layer is an n-type contact layer. The second contact layer includes a p-type contact region formed by diffusing zinc. An avalanche photodiode (APD) subassembly is provided in which the p-type contact region has a smaller cross-sectional area than the avalanche layer, and the cross-sectional area is perpendicular to the direction from the substrate to the second contact layer.

[0007] In certain embodiments, the avalanche layer may comprise AlGaAsSb, InAlAsSb, or AlAsSb.

[0008] Optionally, the distance between the sidewall of the avalanche layer and the edge of the p-type contact region in a direction perpendicular to the direction from the substrate to the second contact layer may be at least 7.5 μm.

[0009] In certain embodiments, the avalanche layer may have a thickness of 100 nm to 1500 nm or 300 nm to 1000 nm.

[0010] In certain embodiments, the APD subassembly may comprise a first cladding layer having a thickness of at least 1 μm, disposed between the avalanche layer and the second contact layer, and the second contact layer is formed within the cladding layer.

[0011] The first cladding layer may include a zinc diffusion area, which has a smaller cross-sectional area than the avalanche layer, and the cross-sectional area is perpendicular to the direction from the substrate to the second contact layer.

[0012] In certain embodiments, the distance between the sidewall of the avalanche layer and the edge of the zinc diffusion area in the first cladding layer, in a direction perpendicular to the direction from the substrate to the second contact layer, may be at least 7.5 μm.

[0013] The zinc diffusion area may include local regions within the first cladding layer.

[0014] In certain embodiments, the APD subassembly may include an absorbent layer disclosed between the avalanche layer and the second contact layer.

[0015] The absorption layer may include InGaAs, GaAsSb, InGaAlAs, InGaAsP, or an InGaAs / GaAsSb type II superlattice.

[0016] In certain embodiments, the APD subassembly may comprise at least one stopper layer disposed between the absorption layer and the second contact layer. The at least one stopper layer may have a lower zinc diffusivity than the second contact layer.

[0017] At least one stopper layer may contain InGaAs or InGaAlAs, and / or at least one stopper layer may be intrinsic.

[0018] In certain embodiments, the APD subassembly may include a transition section disposed between the avalanche layer and the absorption layer. The transition section may include a first grading layer of InAlGaAs or InGaAsP and a charge sheet disposed between the first grading layer and the avalanche layer. The charge sheet may have a band gap between the band gap of the absorption layer and the band gap of the avalanche layer.

[0019] The charge sheet may be p-doped and / or may contain InAlAs or InP.

[0020] In certain embodiments, the APD subassembly may include a second grading layer of InAlGaAs or InGaAsP disposed between the charge sheet and the avalanche layer.

[0021] In certain embodiments, the APD subassembly is a quasi-planar subassembly.

[0022] In certain embodiments, the p-type contact region may include a local region of the second contact layer.

[0023] In certain embodiments, the second contact layer may have substantially the same cross-sectional area as the avalanche layer, and this cross-sectional area is perpendicular to the direction from the substrate to the second contact layer.

[0024] In certain embodiments, the second contact layer may include an outer first portion and an inner second portion. The first portion may be separated from the second portion, and the second portion may include a p-type contact region.

[0025] In certain embodiments, the APD device may include an electric field control layer disposed between the first contact layer and the avalanche layer. The electric field control layer may be n-doped.

[0026] In certain embodiments, the APD device may comprise a second cladding layer formed on a first contact layer. The second cladding layer may be n-doped.

[0027] According to one aspect of this disclosure, an APD device comprising the above-described APD subassembly is provided.

[0028] In certain embodiments, the APD device may comprise electrodes formed on a p-type contact layer and an n-type contact layer, respectively.

[0029] According to one aspect of the present invention, a method for manufacturing an APD subassembly is provided. This method is To provide a substrate, The first contact layer is formed on the substrate, and the first contact layer is an n-type contact layer. Multiple layers, including an avalanche layer containing antimony and a second contact layer, are laminated on a first contact layer such that the avalanche layer is positioned between the first contact layer and the second contact layer, and The method includes creating a p-type contact region within the second contact layer by diffusing zinc into the second contact layer, wherein the p-type contact region has a smaller cross-sectional area than the avalanche layer, and the cross-sectional area is perpendicular to the direction from the substrate to the second contact layer.

[0030] In certain embodiments, creating a p-type contact region may involve a single zinc diffusion.

[0031] In certain embodiments, the method may include etching the second contact layer to divide it into an outer first portion and an inner second portion, and applying a mask over the first portion of the second contact layer to suppress zinc diffusion into the first portion, before creating a p-type contact region.

[0032] In certain embodiments, creating a p-type contact region may involve etching a second portion of a second contact layer to provide a p-type contact region after zinc diffusion.

[0033] In certain embodiments, the method may include etching a plurality of layers such that the distance between the sidewall of the avalanche layer and the edge of the p-type contact region in a direction perpendicular to the direction from the substrate to the second contact layer is at least 7.5 μm.

[0034] In certain embodiments, the layers may include a first cladding layer disposed between the avalanche layer and the second contact layer. The method may involve creating a p-type contact region by creating a zinc diffusion area within the first cladding layer.

[0035] In certain embodiments, etching of multiple layers may be performed such that the distance between the sidewall of the avalanche layer and the edge of the zinc diffusion area in the first cladding layer in a direction perpendicular to the direction from the substrate to the second contact layer is at least 7.5 μm.

[0036] Embodiments of the present invention will be further described with reference to the accompanying drawings. [Brief explanation of the drawing]

[0037] [Figure 1] This figure schematically shows a cross-section of an avalanche photodiode device according to an embodiment of the present invention. [Figure 2] This graph shows the dark current of an avalanche photodiode of the type described in Figure 1. [Figure 3] This figure schematically shows a cross-section of an avalanche photodiode device according to an embodiment of the present invention. [Figure 4] This figure schematically shows a cross-section of an avalanche photodiode device according to an embodiment of the present invention. [Figure 5] This figure schematically shows a cross-section of an avalanche photodiode device according to an embodiment of the present invention. [Figure 6] Figure 5 is a graph showing the electric field inside the avalanche photodiode. [Figure 7] Figure 5 shows a graph of the zinc concentration across the avalanche photodiode. [Figure 8] This figure schematically shows a cross-section of an avalanche photodiode device according to an embodiment of the present invention. [Figure 9]This diagram schematically shows the stages of an avalanche photodiode device according to an embodiment of the present invention in the manufacturing method. [Figure 10] This diagram schematically shows the stages of an avalanche photodiode device according to an embodiment of the present invention in the manufacturing method. [Figure 11] This diagram schematically shows the stages of an avalanche photodiode device according to an embodiment of the present invention in the manufacturing method. [Figure 12] This diagram schematically shows the stages of an avalanche photodiode device according to an embodiment of the present invention in the manufacturing method. [Figure 13] This diagram schematically shows the stages of an avalanche photodiode device according to an embodiment of the present invention in the manufacturing method. [Figure 14] This diagram schematically shows the stages of an avalanche photodiode device according to an embodiment of the present invention in the manufacturing method. [Figure 15] This diagram schematically shows the stages of an avalanche photodiode device according to an embodiment of the present invention in the manufacturing method. [Figure 16] This diagram schematically shows the stages of an avalanche photodiode device according to an embodiment of the present invention in the manufacturing method. [Modes for carrying out the invention]

[0038] Throughout this specification, the terms avalanche and multiplication are used synonymously (for example, “avalanche layer” is synonymous with “multiplication layer”).

[0039] In one embodiment shown in Figure 1, a SAMAPD device 100 is provided. The SAMAPD device 100 comprises a substrate 101 and a p-type contact layer 102 formed on the substrate 101. The SAMAPD device 100 also comprises an n-type contact layer 103. As shown in Figure 1, the device 100 is in a nip configuration because the p-type contact layer 102 is grown on the substrate 101. Thus, the n-type contact layer 103 may form an outer layer 104 of the device 100. In the embodiment shown in Figure 1, the substrate 101 may include InP. In certain embodiments, any semiconductor material in the device 100 (i.e., disposed on the substrate 101) may be lattice-matched to InP. In the embodiment shown in Figure 1, the p-type contact layer 102 may include InAlAs. In alternative embodiments, the p-type contact layer 102 may include InGaAs, InP, InGaAsP, or InGaAlAs. The p-type contact layer 102 is p-doped. The p-type contact layer 102 can be doped to a high concentration. In certain embodiments, the p-type contact layer 102 may be doped to approximately 1.0 × 10⁻⁶ 18 cm -3 ~Approximately 5.0 x 10 19 cm -3 It can be p-doped at a concentration of . The p-type contact layer 102 may have a thickness of approximately 100 nm to approximately 1000 nm. In the embodiment shown in Figure 1, the thickness of each layer in the device 100 is measured in the direction from the substrate 101 to the n-type contact layer 103. The layer thicknesses in Figure 1 are not shown to scale. In the embodiment shown in Figure 1, the n-type contact layer 103 may contain InGaAs. In an alternative embodiment, the n-type contact layer 103 may contain InP, InGaAsP, InAlAs, or InGaAlAs. The n-type contact layer 103 is n-doped. The n-type contact layer 103 can be doped to a high concentration. In a particular embodiment, the n-type contact layer 103 may have a thickness of approximately 1.0 × 10 18 cm -3 ~Approximately 5.0 x 10 19 cm -3It can be doped with n at a concentration of. The n-type contact layer 103 can have a thickness of approximately 30 nm to approximately 100 nm. As shown in FIG. 1, one or more electrodes 105 can be provided on each of the p-type contact layer 102 and the n-type contact layer 103. In the embodiment of FIG. 1, one electrode is provided on each of the p-type contact layer 102 and the n-type contact layer 103. The electrode 105 provided on the n-type contact layer 103 is in the shape of a ring. Therefore, in the cross-section of the device 100 shown in FIG. 1, two portions of a single ring-shaped electrode 105 are illustrated.

[0040] The device 100 includes an avalanche layer 106 containing antimony (Sb). The avalanche layer 106 is disposed between the n-type contact layer 103 and the p-type contact layer 102. The avalanche layer 106 can be intrinsic. The avalanche layer 106 can have a thickness of 75 nm to 2000 nm. In the embodiment shown in FIG. 1, the avalanche layer 106 can include AlGaAsSb. In a particular embodiment, the avalanche layer 106 is Al x Ga 1-x As y S 1-y and can include, where x is 0.4 or more and 1.0 or less, and optionally 0.85 or more and 1.0 or less. In a particular embodiment, y can be selected to lattice-match the avalanche layer 106 to the InP substrate 101. In a particular embodiment, the avalanche layer 106 is Al x Ga 1-x As y Sb 1-y and can include, where x is 0.85 and y is 0.56. In an alternative embodiment, the avalanche layer 106 can instead include InAlAsSb or AlAsSb.

[0041] As shown in Figure 1, the SAMAPD device 100 has a multi-stage structure. The multi-stage structure includes a first stage 107 and a second stage 108. The first stage 107 includes an n-type contact layer 103, and the second stage 108 includes an avalanche layer 106. As shown in the embodiment of Figure 1, the first stage 107 may be centered on the second stage 108. The second stage 108 may be centered relative to the substrate 101. As shown in the embodiment of Figure 1, the first stage 107 includes a side wall 109, and the second stage 108 includes a side wall 110. The side wall 109 of the first stage may extend in the direction from the second stage 108 toward the upper surface 111 of the device 100. The side wall 110 of the second stage 108 may extend in the direction from the substrate 101 toward the first stage 107. As shown in Figure 1, each layer within the first and second steps 107, 108 extends to the respective side walls 109, 110 of steps 107, 108. The embodiment shown in Figure 1 includes two steps, but in alternative embodiments, the multi-step structure may include two, three, or more steps.

[0042] The first stage 107 has a smaller cross-sectional area than the second stage 108, and the cross-sectional area is defined to be perpendicular to the direction from the substrate 101 to the n-type contact layer 103. Therefore, the width of the n-type contact layer 103 is smaller than the width of the avalanche layer 106. As shown in Figure 1, the layers in the first stage 107 have substantially the same cross-sectional area as the layers in the second stage 108 have substantially the same cross-sectional area as the layers in the second stage 108.

[0043] The multi-stage structure ensures that, during use, the high-electric-field region within the avalanche layer 106 of the device 100 is confined to the area directly beneath the n-type contact layer 103, as indicated by the area between the dashed lines 140 in Figure 1. The high-electric-field region does not extend to the sidewall 110 of the second stage 108. Consequently, only the low-electric-field extends across the outer surface (i.e., sidewall) of the avalanche layer 106. Therefore, the effect of any irregularities within the sidewalls 109, 110 of the device 100 caused by manufacturing on the performance of the device 100 is reduced, and hot spots are not formed (or at least reduced) in the irregularities within the sidewalls 109, 110. Thus, the multi-stage structure results in a device 100 with improved performance and reliability.

[0044] In certain embodiments, the distance between the sidewall 109 of the first stage 107 and the sidewall 110 of the second stage 108 in a direction perpendicular to the direction from the substrate 101 to the n-type contact layer 103 is between 5 μm and 100 μm. Figure 2 shows a graph of dark current values ​​for various distances between the sidewalls 109 and 110 of the first and second stages 107 and 108 in a direction perpendicular to the direction from the substrate 101 to the n-type contact layer 103. Dark current provides an indicator of the performance of the device 100, with smaller dark current values ​​indicating improved performance. The dark current value at a distance of 0 μm indicates the performance of a device having only a single stage, i.e., the n-type contact layer 103 and the avalanche layer 106 have the same cross-sectional area in a direction perpendicular to the direction from the substrate 101 to the n-type contact layer 103. As shown in Figure 2, the performance of device 100 is improved by providing first and second stages 107 and 108 within the device compared to a device having only a single stage. In certain embodiments, the distance between the sidewall 109 of the first stage 107 and the sidewall 110 of the second stage 108 may be at least 15 μm. At such a distance, the high-electric-field region is sufficiently far from the sidewall of the avalanche layer 106 to significantly reduce the risk of hot spots forming on the sidewall of the avalanche layer 106 due to irregularities, and the tolerance of device 100 to defects is further improved compared to a device where this distance is less than 15 μm. In certain embodiments, the distance between the sidewall 109 of the first stage 107 and the sidewall 110 of the second stage 108 may be at least 20 μm. As shown in Figure 2, the performance of device 100 may be considered optimal when the distance is at least 20 μm. In certain embodiments, the distance between the side wall 109 of the first stage 107 and the side wall 110 of the second stage 108 may be 30 μm or less to limit the size and capacitance of the device.

[0045] In a non-limiting specific embodiment shown in Figure 1, the multi-stage structure is a multi-stage mesa structure. The first stage 107 is the first mesa, and the second stage 108 is the second mesa.

[0046] As shown in Figure 1, the multi-stage structure may be a stepped structure. A first stage 107 provides a first step, and a second stage 108 provides a second step. The first step may be relative to the second stage 108. The second step may be relative to the substrate 101. That is, the second step has a smaller cross-sectional area than the substrate 101, and the cross-sectional area is defined to be perpendicular to the direction from the substrate 101 to the n-type contact layer 103. As shown in the embodiment of Figure 1, each step may have side walls 109, 110 that are substantially perpendicular to the substrate 101. Each step may have top surfaces 111, 112 that are substantially parallel to the substrate 101.

[0047] In certain non-limiting examples, each layer within the device 100 may have a substantially circular cross-section, and the cross-section is oriented perpendicular to the direction from the substrate 101 to the n-type contact layer 103. Thus, each of the first layer 107 and the second layer 108 may have a substantially cylindrical shape. However, the present invention is not limited to each layer of the device 100 having a substantially circular cross-section. Each layer may have any preferred cross-section. In certain embodiments, each layer may have a substantially rectangular or substantially square cross-section, and each corner of the rectangle or square may be rounded.

[0048] The inventors have discovered that using a multi-stage structure in the SAMAPD device 100 in combination with an antimony-containing avalanche layer 106 yields unexpected synergistic advantages due to the low-noise characteristics and wide bandgap of the avalanche layer 106. The properties of the antimony-based avalanche layer 106 allow for the use of a thicker avalanche layer 106 than in other known devices, which yields beneficial results in the multi-stage structure. A thick antimony avalanche layer can reduce the voltage sensitivity of the device 100 during use. The thick avalanche layer 106 can significantly reduce the peak electric field across the avalanche region required for avalanche gain. Therefore, the build-up of gain due to voltage is slower, and as a result, the device becomes less sensitive to voltage, and the peak electric field at any hot spots in the device 100 is reduced. Thus, the impact of any defects in the device 100 on the device's performance is reduced. In certain embodiments, the avalanche layer 106 may have a thickness of 300 to 1000 nm.

[0049] Device 100 comprises an APD subassembly. The APD subassembly may comprise a subset of the features of device 100 shown in Figure 1. In the embodiment shown in Figure 1, the APD subassembly comprises a substrate 101, a p-type contact layer 102 formed on the substrate 101, and an n-type contact layer 103. The subassembly also comprises an antimony-containing avalanche layer 106 disposed between the p-type contact layer 102 and the n-type contact layer 103. The APD subassembly has a multi-stage structure comprising a first stage 107 containing the n-type contact layer 103 and a second stage 108 containing the avalanche layer 106. As described above, the first stage 107 has a smaller cross-sectional area than the second stage 108, and the cross-sectional area is perpendicular to the direction from the substrate 101 to the n-type contact layer 103. Thus, the APD subassembly is a component of device 100. Device 100 may include further features in addition to the APD subassembly. The APD subassembly may optionally include one or more additional features of device 100 as shown and described with reference to Figure 1.

[0050] As shown in the embodiment of Figure 1, the device 100 may include a spacer layer 113. The spacer layer 113 may be included in a subassembly. The spacer layer 113 may be disposed between the avalanche layer 106 and the n-type contact layer 103. The spacer layer 113 does not contain antimony. The spacer layer 113 may be intrinsic. The spacer layer 113 may have a thickness of 50 nm to 4000 nm. As shown in Figure 1, the spacer layer 113 includes a lower part 113a located within the second step 108 and an upper part 113b located within the first step 107. Thus, the second step 108 may include the lower part 113a, and the first step 107 may include the upper part 113b. Therefore, the upper part 113b has a smaller cross-sectional area, which is measured in a direction perpendicular to the direction from the substrate to the n-type contact layer.

[0051] As shown in Figure 1, the first stage 107 begins within the spacer layer 113. Therefore, when manufacturing the device 100, it can be advantageously etched such that the transition between the first stage 107 and the second stage 108 occurs within the spacer layer 113. The transition between the first stage 107 and the second stage 108 can occur at any point within the spacer layer 113. This can improve manufacturability because there is no requirement that the transition between the first stage 107 and the second stage 108 occur at the boundary between two different layers within the device 100, which can constrain the material selection within the device 100. Ending the second stage within the spacer layer 113 rather than the avalanche layer 106 may also allow for reduced surface leakage.

[0052] Additionally, the lower part 113a of the spacer layer 113 defines the upper boundary of the second step 108. As shown in Figure 1, the lower part of the spacer layer 113 provides the upper surface 112 of the second step 108, ensuring that the sidewalls of the avalanche layer 106 are the only outer surfaces of the avalanche layer 106. This is advantageous because the antimony-containing avalanche layer 106 can oxidize violently when used as an etch stop during wet etching. Such oxidation can create irregularities within the device 100, leading to the formation of hot spots in use. The antimony-free spacer layer 113 can help create a uniform electric field across the avalanche layer 106 within the second step 108, limiting the peak electric field away from the outer surface of the device 100. Because only a low electric field extends across the outer surface of the avalanche layer 106, the spacer layer 113 can improve the device 100's resistance to manufacturing irregularities and defects.

[0053] In certain embodiments, the spacer layer 113 may also reduce the capacitance of the device 100, thereby improving the performance of the device 100. This can be achieved by increasing the thickness of the device 100. This may be most beneficial when the device 100 is used in low-speed applications such as LiDAR. In certain embodiments, the spacer layer 113 may have a thickness of 250 nm to 4000 nm to reduce the capacitance of the device 100. However, when the device 100 is used in high-speed applications such as telecommunications, the capacitance reduction by a thick spacer layer 113 may not be more important than the speed of the device. Therefore, in certain embodiments, the spacer layer 113 may have a thickness of 50 to 250 nm.

[0054] In the embodiment shown in Figure 1, the spacer layer 113 may contain InAlAs. In an alternative embodiment, the spacer layer 113 may contain InP.

[0055] Device 100 may comprise one or more additional layers located between the spacer layer 113 and the n-type contact layer 103. These layers may be located within the first stage 107 of a multi-stage structure, as shown in Figure 1.

[0056] Device 100 may comprise a first cladding layer 114 on which an n-type contact layer 103 is formed. The APD subassembly may comprise the first cladding layer 114. The first cladding layer 114 may be disposed between the upper part 113b of the spacer layer 113 and the n-type contact layer 103. The first stage may include the first cladding layer 114. The first cladding layer 114 may be n-doped. The first cladding layer 114 may be highly doped. In certain embodiments, the first cladding layer 114 may be approximately 1.0 × 10⁻¹⁶ 17 cm -3 ~Approximately 5.0 x 10 19 cm -3It can be doped with n at a concentration of . The first cladding layer 114 can be doped with silicon or tellurium. Using silicon or tellurium as an n dopant within the device 100 is advantageous because the dopant does not significantly migrate or diffuse through the layers within the device during manufacturing. The first cladding layer 114 may have a thickness of approximately 50 nm to approximately 500 nm.

[0057] Device 100 may include a gradient cladding layer 115 between the spacer layer 113 and the n-type contact layer 103. The APD subassembly may include the gradient cladding layer 115. The gradient cladding layer 115 may be formed on the upper part 113b of the spacer layer 113. Therefore, the gradient cladding layer 115 may be disposed between the spacer layer 113 and the first cladding layer 114. Therefore, the first stage 107 may include the gradient cladding layer 115. The gradient cladding layer 115 may be n-doped. The concentration or level of dopant in the gradient cladding layer 115 may increase in the direction from the substrate 101 to the n-type contact layer 103. In certain embodiments, the concentration of dopant is 1.0 × 10⁻⁶. 16 cm -3 From 1.0 × 10 18 cm -3 The concentration can be increased to or toward the concentration of the first cladding layer 114. The gradient cladding layer 115 can be doped with silicon or tellurium. In the embodiment shown in Figure 1, the gradient cladding layer 115 may contain InAlAs. In an alternative embodiment, the gradient cladding layer 115 may contain InP, InGaAlAs, or InGaAsP. The gradient cladding layer 115 may have a thickness of approximately 50 nm to approximately 500 nm.

[0058] In certain embodiments, the doping of the gradient cladding layer 115 can be gradient such that the dopant concentration at the interface between it and an adjacent layer in the device 100 is substantially the same as the concentration in one or both of the adjacent layers. The gradient cladding layer 115 may be substantially intrinsic adjacent to the interface between the spacer layer 113 and the gradient cladding layer 115. The dopant concentration in the gradient cladding layer 115 may be substantially the same as the concentration in the first cladding layer 114 adjacent to the interface between the gradient cladding layer 115 and the first cladding layer 114. Graduating the gradient cladding layer 115 in this manner may further help reduce the occurrence of hot spots in the device 100 during use by reducing abrupt changes in the gradient.

[0059] Therefore, as shown in the embodiment of Figure 1, the device 100 may include a first cladding layer 114 and a gradient cladding layer located between the spacer layer 113 and the n-type contact layer 103 within the first stage 107. However, the present invention is not limited to the specific layers or layer order shown in Figure 1.

[0060] Device 100 may comprise one or more additional layers located between the p-type contact layer 102 and the spacer layer 113, as shown in Figure 1. These layers may be located within the second stage 108 of the multi-stage structure.

[0061] Device 100 may include an electric field control layer 116. The APD subassembly may include an electric field control layer 116. The electric field control layer 116 may be disposed between the avalanche layer 106 and the spacer layer 113. Thus, the second stage 108 may include an electric field control layer 116. The electric field control layer 116 may be disposed on the opposite side of the spacer layer 113 from the inclined first cladding layer 114. The electric field control layer may be n-doped. The electric field control layer 116 is approximately 1.0 × 10 17 cm -3 ~Approximately 1.0 × 10 18 cm -3It can be doped with n at a concentration of . The field control layer 116 can be n-doped with silicon or tellurium. The field control layer 116 does not have to contain antimony. Thus, in a similar manner to the spacer layer 113, the field control layer 116 can further help reduce the risk of oxidation to the avalanche layer 106 during manufacturing using wet etching. In the embodiment shown in Figure 1, the field control layer 116 may contain InAlAs. In alternative embodiments, the field control layer 116 may contain InGaAlAs, InP, or InGaAsP. The field control layer 116 may have a thickness of approximately 60 nm to approximately 300 nm.

[0062] As described above, the spacer layer 113 can reduce the capacitance of device 100, thereby improving the performance of device 100. This effect of the spacer layer 113 can be enhanced by placing the intrinsic spacer layer 113 between the n-doped gradient cladding layer 115 and the n-doped field control layer 116, where the n-dopant is selected so that it does not significantly move or diffuse through the layers within device 100 during manufacturing.

[0063] As shown in the embodiment of Figure 1, the device 100 may include an absorption layer 117 disposed between the p-type contact layer 102 and the avalanche layer 106. The APD subassembly may include the absorption layer 117. Thus, the second stage may include the absorption layer 117. In the embodiment shown in Figure 1, the absorption layer 117 may include InGaAs. In alternative embodiments, the absorption layer 117 may include InGaAlAs, InGaAsP, GaAsSb, or an InGaAs / GaAsSb type II superlattice. In certain embodiments, the absorption layer 117 may be intrinsic. The absorption layer 117 may have a thickness of approximately 500 nm to approximately 2500 nm.

[0064] Device 100 may include a transition section 118 disposed between the absorption layer 117 and the avalanche layer 106. The APD subassembly may include the transition section 118. As shown in Figure 1, the second stage 108 may include the transition section 118. The transition section 118 may include a first grading layer 119 and a charge sheet 120. The charge sheet 120 may be disposed between the first grading layer 119 and the avalanche layer 106. The charge sheet 120 may have a band gap between the band gap of the absorption layer 117 and the band gap of the avalanche layer 106.

[0065] In the embodiment shown in Figure 1, the avalanche layer 106 containing AlGaAsSb has a wide band gap, while the absorption layer 117 containing InGaAs has a narrow band gap. The effect of the charge sheet 120 is that the electric field profile of the SAMAPD device 100 is altered so that electrons are mainly located in the X valley. Therefore, under operation, most electrons are located in the band structure region with minimal band offset relative to the avalanche layer 106 and the absorption layer 117. The charge sheet 120 can be fabricated from a material with a wider band gap relative to the absorption layer 117 and can be used to increase the electric field to a suitable value to ensure that electrons are mainly located in the X valley while minimizing tunnel current. Thus, the charge sheet 120 improves the transport of charge carriers into the avalanche layer 106.

[0066] In certain embodiments, the charge sheet 120 may be p-doped. In certain embodiments, the charge sheet 120 may be 1 × 10 17 cm -3 ~1 × 10 18 cm -3 At a concentration of 1 × 10, arbitrarily selected 17 cm -3 ~5×10 17 cm -3 It can be p-doped at a concentration of [value missing]. In certain embodiments, the charge sheet 120 may have a thickness of 40 nm to 300 nm. In the embodiment shown in Figure 1, the charge sheet 120 may contain InAlAs. In alternative embodiments, the charge sheet 120 may contain InP.

[0067] In certain embodiments, the first grading layer 119 may have a constant band gap over its thickness. In the embodiment shown in Figure 1, the first grading layer 119 may contain AlGaInAs. In alternative embodiments, the first grading layer 119 may contain InGaAsP. The first grading layer 119 may be intrinsic. The first grading layer 119 may have a thickness of approximately 25 nm to approximately 50 nm.

[0068] As shown in the embodiment of Figure 1, the transition layer 118 may include a second grading layer 121 disposed between the first grading layer 119 and the charge sheet 120. In certain embodiments, the second grading layer 121 may have a constant band gap over its thickness. The second grading layer 121 may contain AlGaInAs. The second grading layer 121 may be intrinsic. The second grading layer 121 may have a thickness of approximately 25 nm to approximately 50 nm. The second grading layer 121 has a different band gap than the first grading layer 119. The second grading layer 121 may have a band gap between the band gap of the first grading layer 119 and the band gap of the avalanche layer 106.

[0069] Between the p-type contact layer 102 and the absorption layer 117, the device 100 may include a third grading layer 122. The APD subassembly may include a third grading layer 122. As shown in the embodiment of Figure 1, the second stage 108 may include the third grading layer 122. The third grading layer 122 may be intrinsic. As shown in the embodiment of Figure 1, the third grading layer 122 may include two separate layers. Each layer has a different band gap. The second layer 122b of the third grading layer 122 may have a band gap between the band gap of the first layer 122a of the third grading layer 122 and the band gap of the absorption layer 117. The third grading layer 122 may include the first layer 122a and the second layer 122b. The second layer 122b may be disposed between the first layer 122a and the absorption layer 117. The second layer 122b may be formed on the first layer 122a. The absorption layer 117 may be formed on the second layer 122b. Each layer in the third grading layer 122 may contain AlGaInAs. The third grading layer 122 may have a thickness of approximately 25 nm to approximately 50 nm. The first and second layers 122a and 122b of the third grading layer 122 may each have the same thickness. Therefore, the first and second layers 122a and 122b of the third grading layer 122 may each have a thickness of 25 nm.

[0070] The device may comprise a second cladding layer 123. The APD subassembly may comprise a second cladding layer 123. The second cladding layer 123 may be formed on a p-type contact. The second cladding layer 123 may be disposed between the p-type contact layer and a third grading layer. The third grading layer may be formed on the second cladding layer 123. The second cladding layer 123 may be p-doped. The second cladding layer 123 is approximately 1.0 × 10⁻⁶ 17 cm -3 ~Approximately 5.0 x 10 18 cm -3 It can be p-doped at a concentration of . The second cladding layer 123 may have a thickness of approximately 50 nm to approximately 300 nm.

[0071] Therefore, as shown in the embodiment of Figure 1, the device 100 may comprise a second cladding layer 123, a third grading layer 122, an absorption layer 117, a first grading layer 119, a second grading layer 121, a charge sheet 120, an avalanche layer 106, and an electric field control layer 116, located between the p-type contact layer 102 and the spacer layer 113 within the second stage 108. However, the present invention is not limited to the specific layers or layer order shown in Figure 1.

[0072] In the embodiment shown in Figure 1, the p-type contact layer 102 may include an upper 102b and a lower 102a, as shown in the embodiment of Figure 1. The second cladding layer 123 may be formed on the upper 102b of the p-type contact layer 102. The lower 102a of the p-type contact layer 102 may be adjacent to the substrate 101. The second stage 108 of the multi-stage structure may include the upper 102b of the p-type contact layer 102. The upper 102b of the p-type contact layer 102 may have a smaller cross-sectional area than both the lower 102a of the p-type contact layer 102 and the substrate 101, and the cross-sectional area is defined to be perpendicular to the direction from the substrate 101 to the n-type contact layer 103. Therefore, the lower 102a of the p-type contact layer 102 may not be present with the second stage 108 of the device. Thus, the second stage 108 may begin within the p-type contact layer 102. The lower portion 102b of the p-type contact layer 102 may have substantially the same cross-sectional area as the substrate 101. As shown in Figure 1, one or more electrodes 105 may be formed on the lower portion 102a of the p-type contact layer 102. In an alternative embodiment, the p-type contact layer 102 may have a uniform cross-sectional area, which is defined as being perpendicular to the direction from the substrate 101 to the n-type contact layer 103. The cross-sectional area of ​​the p-type contact layer 102 may be larger than the cross-sectional area of ​​the second stage 108. Therefore, the second stage 108 may not include the p-type contact layer 102.

[0073] In another embodiment shown in Figure 3, a SAMAPD device 200 is provided. The SAMAPD device 200 comprises a substrate 201 and an n-type contact layer 203 formed on the substrate 201. The SAMAPD device 200 also comprises a p-type contact layer 202. As shown in Figure 3, the device 200 is in a pin configuration because the n-type contact layer 203 is grown on the substrate 201. Thus, the p-type contact layer 202 may form the outer layer of the device 200. In the embodiment shown in Figure 3, the substrate 201 may contain InP. In certain embodiments, any semiconductor material in the device 200 (i.e., disposed on the substrate 201) may be lattice-matched to InP. In the embodiment shown in Figure 3, the n-type contact layer 203 may contain InAlAs. In alternative embodiments, the n-type contact layer 203 may contain any one of InP, InGaAsP, InGaAs, or InGaAlAs. The n-type contact layer 203 is n-doped. The n-type contact layer 203 can be doped to a high concentration. In certain embodiments, the n-type contact layer 203 may be doped to approximately 1.0 × 10⁻⁶ 18 cm -3 ~Approximately 5.0 x 10 19 cm -3 It can be doped with n at a concentration of . The n-type contact layer 203 may have a thickness of approximately 100 nm to approximately 1000 nm. In the embodiment shown in Figure 3, the thickness of each layer in the device 200 is measured in the direction from the substrate 201 to the p-type contact layer 202. The layer thicknesses in Figure 3 are not shown to scale. In the embodiment shown in Figure 3, the p-type contact layer 202 may contain InGaAs. In an alternative embodiment, the p-type contact layer 202 may contain InP, InGaAsP, InAlAs, or InGaAlAs. The p-type contact layer 202 is p-doped. The p-type contact layer 202 can be doped to a high concentration. In a particular embodiment, the p-type contact layer 202 may have a thickness of approximately 1.0 × 10⁻⁶ 18 cm -3 ~Approximately 5.0 x 10 19 cm -3It can be p-doped at a concentration of . The p-type contact layer 202 may have a thickness of approximately 30 nm to approximately 50 nm. As shown in Figure 3, one or more electrodes 205 may be provided on each of the n-type contact layer 203 and the p-type contact layer 202. In the embodiment of Figure 3, one electrode is provided on each of the n-type contact layer 203 and the p-type contact layer 202. The electrode 205 provided on the p-type contact layer 202 is in the shape of a ring. Thus, in the cross-section of the device 200 shown in Figure 3, two portions of a single ring-shaped electrode 205 are illustrated.

[0074] The device 200 comprises an avalanche layer 206 containing antimony (Sb). The avalanche layer 206 is disposed between a p-type contact layer 202 and an n-type contact layer 203. The avalanche layer 206 may be intrinsic. The avalanche layer 206 may have a thickness of 75 to 2000 nm. In the embodiment shown in Figure 3, the avalanche layer 206 may contain AlGaAsSb. In certain embodiments, the avalanche layer 206 may contain Al x Ga 1-x As y S 1-y It may include, where x is 0.4 or more and 1.0 or less, and optionally 0.85 or more and 1.0 or less. In certain embodiments, y may be selected to lattice match the avalanche layer 206 to the InP substrate 201. In certain embodiments, the avalanche layer 206 is Al x Ga 1-x As y S 1-y It may include, where x is 0.85 and y is 0.56. In an alternative embodiment, the avalanche layer 206 may instead contain InAlAsSb or AlAsSb.

[0075] As shown in Figure 3, the SAMAPD device 200 has a multi-stage structure. The multi-stage structure includes a first stage 207 and a second stage 208. The first stage 207 includes a p-type contact layer 202, and the second stage 208 includes an avalanche layer 206. As shown in the embodiment of Figure 3, the first stage 207 may be centered on the second stage 208. The second stage 208 may be centered relative to the substrate 201. As shown in the embodiment of Figure 3, the first stage 207 includes a side wall 209, and the second stage 208 includes a side wall 210. The side wall 209 of the first stage may extend in the direction from the second stage 208 toward the upper surface 211 of the device 200. The side wall 210 of the second stage 208 may extend in the direction from the substrate 201 toward the first stage 207. As shown in Figure 3, each layer within the first and second steps 207, 208 extends to the respective side walls 209, 210 of steps 207, 208. The embodiment shown in Figure 3 includes two steps, but in alternative embodiments, the multi-step structure may include two, three, or more steps.

[0076] The first stage 207 has a smaller cross-sectional area than the second stage 208, and the cross-sectional area is defined to be perpendicular to the direction from the substrate 201 to the p-type contact layer 202. Therefore, the width of the p-type contact layer 202 is smaller than the width of the avalanche layer 206. As shown in Figure 3, the layers in the first stage 207 have substantially the same cross-sectional area as the layers in the second stage 208 have substantially the same cross-sectional area as the layers in the second stage 208.

[0077] In a manner similar to that of the embodiment shown in Figure 1, the multi-stage structure ensures that during use, the high-electric-field region of the device 200 is confined to the area directly beneath the p-type contact layer 202, as indicated by the area between the dashed lines 240 in Figure 3. The high-electric-field region does not extend to the sidewall of the second stage 208. Therefore, the multi-stage structure results in a device 200 with improved performance and reliability.

[0078] In certain embodiments, the distance between the sidewall 209 of the first step 207 and the sidewall 210 of the second step 208 in the direction from the substrate 201 to the n-type contact layer 203 is 5 μm to 100 μm. At distances of 5 μm or more, the high-electric-field region is away from the sidewall of the avalanche layer 206 during use. In certain embodiments, the distance between the sidewall 209 of the first step 207 and the sidewall 210 of the second step 208 may be at least 15 μm. At such distances, the high-electric-field region is sufficiently far from the sidewall of the avalanche layer 206 to significantly reduce the risk of hot spots forming on the sidewall of the avalanche layer 206 due to irregularities, and the resistance of the device 200 to defects is further improved compared to distances of less than 15 μm. In certain embodiments, the distance between the sidewall of the first stage 207 and the sidewall of the second stage 208 may be 30 μm or less in order to limit the size and capacitance of the device 200.

[0079] In a non-limiting specific embodiment shown in Figure 3, the multi-stage structure is a multi-stage mesa structure. The first stage 207 is the first mesa, and the second stage 208 is the second mesa.

[0080] As shown in Figure 3, the multi-stage structure may be a stepped structure, where the first stage 207 provides the first step, and the second stage 208 provides the second step. The first set may be relative to the second stage 208. The second step may be relative to the substrate 201. That is, the second step has a smaller cross-sectional area than the substrate 201, and the cross-sectional area is defined to be perpendicular to the direction from the substrate to the p-type contact layer 202. As shown in Figure 3, each step may have side walls that are substantially perpendicular to the substrate 201. Each step may have top surfaces 211, 212 that are substantially parallel to the substrate 201.

[0081] In certain non-limiting examples, each layer within the device 200 may have a substantially circular cross-section, and the cross-section is oriented perpendicular to the direction from the substrate 201 to the p-type contact layer 202. Thus, each of the first layer 207 and the second layer 208 may have a substantially cylindrical shape. However, the present invention is not limited to each layer of the device 200 having a substantially circular cross-section. Each layer may have any preferred cross-section. In certain embodiments, each layer may have a substantially rectangular or substantially square cross-section, and each corner of the rectangle or square may be rounded.

[0082] In a manner similar to that of the embodiment shown in Figure 1, the inventors discovered that using a multi-stage structure in the SAMAPD device 200 in combination with an antimony-containing avalanche layer 206 yields unexpected synergistic advantages due to the low-noise characteristics and wide bandgap of the avalanche layer 206. The properties of the antimony-based avalanche layer 206 allow for the use of a thicker avalanche layer 206 than in other known devices, which yields beneficial results in the multi-stage structure. In certain embodiments, the avalanche layer 206 may have a thickness of 300 to 1000 nm. A thicker avalanche layer 206 can significantly reduce the peak electric field across the avalanche region required for avalanche gain. Therefore, the impact of any defects in the device 200 on the device performance is reduced.

[0083] Device 200 comprises an APD subassembly. The APD subassembly may comprise a subset of the features of device 200 shown in Figure 3. In the embodiment shown in Figure 3, the APD subassembly comprises a substrate 201, an n-type contact layer 203 formed on the substrate 201, and a p-type contact layer 202. The subassembly also comprises an antimony-containing avalanche layer 206 disposed between the n-type contact layer 203 and the p-type contact layer 202. The APD subassembly has a multi-stage structure comprising a first stage 207 containing the p-type contact layer 202 and a second stage 208 containing the avalanche layer 206. As described above, the first stage 207 has a smaller cross-sectional area than the second stage 208, and the cross-sectional area is perpendicular to the direction from the substrate 201 to the p-type contact layer 202. Thus, the APD subassembly is a component of device 200. Device 200 may include further features in addition to the APD subassembly. The APD subassembly may optionally include one or more additional features of device 200 as shown and described with reference to Figure 3.

[0084] As shown in the embodiment of Figure 3, the device 200 may include a spacer layer 213. The spacer layer 213 may be included in the APD subassembly. The spacer layer 213 may be disposed between the avalanche layer 206 and the p-type contact layer 202. The spacer layer 213 may be intrinsic. The spacer layer 213 may have a thickness of 50 nm to 4000 nm. The spacer layer 213 includes a lower 213a and an upper 213b. The upper 213b has a smaller cross-sectional area than the lower 213a, and the cross-sectional area is perpendicular to the direction from the substrate 201 to the p-type contact layer 202. As shown in Figure 3, the lower 213a is located within the second step 208, and the upper 213b is located within the first step 207. Thus, the second step 208 may include the lower 213a, and the first step 207 may include the upper 213b. As shown in Figure 3, the first stage 207 begins within the spacer layer 213. Therefore, when manufacturing the device 200, it can be advantageously etched such that the transition between the first stage 207 and the second stage 208 occurs within the spacer layer 213. The transition between the first stage 207 and the second stage 208 can occur at any point within the spacer layer 213. This can improve the ease of manufacturing the device 200.

[0085] Additionally, the lower part 213a of the spacer layer 213 defines the upper boundary of the second step 208. As shown in Figure 3, the lower part 213a of the spacer layer 213 provides the upper surface 212 of the second step 208, ensuring that the sidewalls of the avalanche layer 206 are the only outer surfaces of the avalanche layer 206. As described above, the spacer layer 213 improves the manufacturability of the device because the transition between the first step 207 and the second step 208 can occur at any point within the spacer layer 213. Additionally, terminating the second step within the spacer layer 213 rather than the avalanche layer 206 may also allow for reduced surface leakage.

[0086] In certain embodiments, the spacer layer may not contain antimony. In the embodiment shown in Figure 3, the spacer layer may contain InAlAs. In an alternative embodiment, the spacer layer 213 may contain InP. As described above, antimony can oxidize violently when used as an etch stop during wet etching. Therefore, providing an antimony-free spacer layer 213 can help create a uniform electric field across the avalanche layer 206 in the second stage 208, limiting the peak electric field away from the outer surface of the device 200. Because only a low electric field extends across the outer surface of the avalanche layer 206, the spacer layer 213 improves the device 200's resistance to manufacturing imperfections and defects.

[0087] In certain embodiments, the spacer layer 213 may also reduce the capacitance of the device 200, thereby improving the performance of the device 200. This can be achieved by increasing the thickness of the device 200. This may be most beneficial when the device 200 is used in low-speed applications such as LiDAR. In certain embodiments, the spacer layer 213 may have a thickness of 250 nm to 4000 nm to reduce the capacitance of the device 200. However, when the device 200 is used in high-speed applications such as telecommunications, the capacitance reduction by a thick spacer layer 213 may not be more important than the speed of the device 200. Therefore, in certain embodiments, the spacer layer 213 may have a thickness of 50 to 250 nm.

[0088] The device 200 may comprise one or more additional layers located between the spacer layer 213 and the p-type contact layer 202. These layers may be located within the first stage 207 of a multi-stage structure, as shown in Figure 3.

[0089] The device 200 may include an absorption layer 217 disposed between the avalanche layer 206 and the p-type contact layer 202. The APD subassembly may include the absorption layer 217. In the embodiment shown in Figure 3, the absorption layer 217 is disposed between the spacer and the p-type contact layer 202. Therefore, the first stage of the multi-stage structure may include the absorption layer 217. In the embodiment shown in Figure 3, the absorption layer 217 may include InGaAs. In alternative embodiments, the absorption layer 217 may include any one of InGaAlAs, InGaAsP, GaAsSb, or InGaAs / GaAsSb type II superlattices. In certain embodiments, the absorption layer 217 may be intrinsic. The absorption layer 217 may have a thickness of approximately 500 nm to approximately 2500 nm.

[0090] The device 200 may include a transition section 218 disposed between the avalanche layer 206 and the absorption layer 217. The APD subassembly may include the transition section 218. As shown in Figure 3, the first stage 207 of the multi-stage structure may include the transition section 218. Thus, the transition section is disposed between the spacer layer 213 and the absorption layer 217.

[0091] The transition layer 218 may include a first grading layer 219 and a charge sheet 220. The charge sheet 220 may be disposed between the first grading layer 219 and the avalanche layer 206. The charge sheet 220 may have a band gap between the band gap of the absorption layer 217 and the band gap of the avalanche layer 206. As shown in Figure 3, the charge sheet 220 may be formed on a spacer layer 213. The absorption layer 217 may be formed on the first grading layer 219.

[0092] The charge sheet 220 in the embodiment of Figure 3 has substantially the same effect as the charge sheet 120 in the embodiment of Figure 1 described above. In certain embodiments, the charge sheet 220 may be p-doped. In certain embodiments, the charge sheet 220 may be 1 × 10 17 cm -3 ~1 × 10 18 cm -3At a concentration of 1 × 10, arbitrarily selected 17 cm -3 ~5×10 17 cm -3 It can be p-doped at a concentration of [amount]. In certain embodiments, the charge sheet 220 may have a thickness of 40 nm to 300 nm. In certain embodiments, the charge sheet 220 may contain InAlAs. In certain embodiments, the charge sheet 220 may have a band gap of 1 eV or more.

[0093] In certain embodiments, the first grading layer 219 may have a constant band gap over its thickness. In the embodiment shown in Figure 3, the first grading layer 219 may contain AlGaInAs. In alternative embodiments, the first grading layer 219 may contain InGaAsP. The first grading layer 219 may be intrinsic. The first grading layer 219 may have a thickness of approximately 25 nm to approximately 50 nm.

[0094] As shown in the embodiment of Figure 3, the transition layer 218 may include a second grading layer 221 disposed between the first grading layer 219 and the charge sheet 220. In certain embodiments, the second grading layer 221 may have a constant band gap over its thickness. In the embodiment shown in Figure 3, the second grading layer 221 may contain AlGaInAs. In alternative embodiments, the second grading layer 221 may contain InGaAsP. The second grading layer 221 may be intrinsic. The second grading layer 221 may have a thickness of approximately 25 nm to approximately 50 nm. The second grading layer 221 has a different band gap from that of the first grading layer 219. The second grading layer 221 may have a band gap between the band gap of the first grading layer 219 and the band gap of the charge sheet 220.

[0095] The device 200 may include a third grading layer 230 disposed between the absorption layer 217 and the p-type contact layer 202. The APD subassembly may include the third grading layer 230. As shown in the embodiment of Figure 3, the first stage 207 of a multi-stage structure may include the third grading layer 230. The third grading layer 230 may be formed on the absorption layer 217. In the embodiment shown in Figure 3, the third grading layer 230 is on the opposite side of the absorption layer 217 from the transition 218. In the embodiment shown in Figure 3, the third grading layer 230 may include AlGaInAs. The third grading layer 230 may be intrinsic. In an alternative embodiment, the third grading layer 230 may include InGaAsP.

[0096] As shown in the embodiment of Figure 3, the third grading layer 230 may include two separate layers 230a and 230b. Each layer may have a different band gap. The third grading layer 230 may include a first layer 230a formed on the absorption layer 217 and a second layer 230b formed on the first layer 230a. The first layer 230a of the third grading layer 230 may have a band gap between the band gap of the absorption layer 217 and the band gap of the second layer 230b of the third grading layer 230. In the embodiment shown in Figure 3, each layer in the third grading layer 230 may contain AlGaInAs. The third grading layer 230 may have a thickness of approximately 50 nm to approximately 100 nm. Each of the first and second layers of the third grading layer 230 may have the same thickness as each other. Therefore, the first and second layers of the third grading layer 230 may each have a thickness of approximately 25 nm to approximately 50 nm. In an alternative embodiment, each layer of the third grading layer 230 may contain InGaAsP.

[0097] The device 200 may comprise a first cladding layer 214. The APD subassembly may comprise a first cladding layer 214. As shown in the embodiment of Figure 3, the first cladding layer 214 may be disposed between the absorption layer 217 and the p-type contact layer 202. The first cladding layer 214 may be formed on a third grading layer 230. The p-type contact layer 202 may be formed on the first cladding layer 214. As shown in Figure 3, the first stage 207 of a multi-stage structure may include the first cladding layer 214. In the embodiment shown in Figure 3, the first cladding layer 214 may contain InAlAs. The first cladding layer 214 may have a thickness of approximately 50 nm to approximately 500 nm. In certain embodiments, the first cladding layer 214 may be p-doped. The concentration of the dopant in the first cladding layer 214 is approximately 1.0 × 10⁻⁶. 18 cm -3 ~Approximately 1.0 × 10 19 cm -3 This is possible. The concentration of the dopant in the first cladding layer 214 may be lower than the concentration of the dopant in the p-type contact layer 202.

[0098] Therefore, as shown in the embodiment of Figure 3, the device 200 may comprise, within the first stage 207, a charge sheet 220 located between the spacer layer 213 and the p-type contact layer 202, a second grading layer 221, a first grading layer 219, an absorption layer 217, a third grading layer 230, and a cladding layer 214. However, the present invention is not limited to the specific layers or layer order shown in Figure 3.

[0099] The device 200 may comprise one or more additional layers located between the n-type contact layer 203 and the spacer layer 213. These layers may be located within the first layer 207 of a multi-layer structure, as shown in Figure 3.

[0100] Device 200 may include an electric field control layer 216. The APD subassembly may include an electric field control layer 216. As shown in Figure 3, the second stage 208 of the multi-stage structure may include an electric field control layer 216. The electric field control layer 216 may be disposed between the avalanche layer 206 and the spacer layer 213. The electric field control layer 216 may be formed on the avalanche layer 206. The spacer layer 213 may be formed on the electric field control layer 216. Therefore, the electric field control layer 216 may be disposed on the opposite side of the spacer layer 213 from the charge sheet 220.

[0101] The electric field control layer 216 can be p-doped. The dopant concentration in the electric field control layer 216 is approximately 1.0 × 10⁻¹⁶. 17 cm -3 ~Approximately 1.0 × 10 18 cm -3 This is possible. In certain embodiments, the field control layer 216 may not contain antimony. Thus, in a similar manner to the spacer layer 213, the field control layer 216 may further help reduce the risk of oxidation to the avalanche layer 206 during manufacturing using wet or dry etching. In the embodiment shown in Figure 3, the field control layer 216 may contain InAlAs. In alternative embodiments, the field control layer 216 may contain InGaAlAs, InP, or InGaAsP. The field control layer 216 may have a thickness of approximately 70 nm. In certain embodiments, the field control layer 216 may contain substantially the same material as the charge sheet 220. In certain embodiments, the field control layer 216 may be substantially the same as the charge sheet 220.

[0102] Device 200 may include a second cladding layer 231. The APD subassembly may include a second cladding layer 231. As shown in the embodiment of Figure 3, the second cladding layer 231 may be disposed between the avalanche layer 206 and the n-type contact layer 203. The second cladding layer 231 may be formed on the n-type contact layer 203. The avalanche layer 206 may be formed on the second cladding layer 231. As shown in Figure 3, the second stage 208 of a multi-stage structure may include the second cladding layer 231.

[0103] In the embodiment shown in Figure 3, the second cladding layer 231 may contain InAlAs. The second cladding layer 231 may have a thickness of approximately 200 nm to approximately 750 nm. In certain embodiments, the second cladding layer 231 may be n-doped. The concentration of the dopant in the second cladding layer 231 is approximately 1.0 × 10⁻¹⁶. 18 cm -3 ~Approximately 1.0 × 10 19 cm -3 It is possible.

[0104] Therefore, as shown in the embodiment of Figure 3, the device 200 may include a cladding layer 231, an avalanche layer 206, and an electric field control layer 216 located between the n-type contact layer 203 and the spacer layer 213 within the second stage 208. However, the present invention is not limited to the specific layers or layer order shown in Figure 3.

[0105] As described above, the second cladding layer 231 may be formed on the n-type contact. In the embodiment shown in Figure 3, the n-type contact layer 203 is formed on the substrate 201. As shown in the embodiment of Figure 3, the n-type contact layer 203 may have a larger cross-sectional area than the second step 208 substrate 201, and the cross-sectional area is perpendicular to the direction from the substrate 201 to the p-type contact layer 202. Therefore, the second step 208 of the device 200 does not have to include the n-type contact layer 203. Rather, the second step 208 of the device 200 may be formed on the n-type contact layer 203. In certain embodiments, the n-type contact may have substantially the same cross-sectional area as the substrate 201, and the cross-sectional area is perpendicular to the direction from the substrate 201 to the p-type contact layer 202. Therefore, one or more electrodes 205 may be formed on the n-type contact layer 203.

[0106] However, the present invention is not limited to the arrangement of the n-type contact layer 203 shown in Figure 3. In alternative embodiments, the second layer 208 of the multi-stage structure may include at least a portion of the n-type contact layer 203. In certain embodiments, the n-type contact layer 203 may reside within the second layer 208; that is, the second layer 208 may substantially include the entire n-type contact layer 203. In certain embodiments, the n-type contact layer 203 may include an upper and a lower section. The second cladding layer 231 may be formed on top of the upper section of the n-type contact layer 203. The lower section of the n-type contact layer 203 may be adjacent to the substrate 201. The second layer 208 of the multi-stage structure may include the upper section of the n-type contact layer 203. The upper section of the n-type contact layer 203 may have a smaller cross-sectional area than both the lower section of the n-type contact layer 203 and the substrate 201, and the cross-sectional area is defined to be perpendicular to the direction from the substrate 201 to the n-type contact layer 203. Therefore, the lower part of the n-type contact layer 203 does not have to be present with the second stage 208 of the device 200. Thus, the second stage 208 may begin within the n-type contact layer 203. The lower part of the n-type contact layer 203 may have substantially the same cross-sectional area as the substrate 201. One or more electrodes 205 may be formed on the lower part of the n-type contact layer 203.

[0107] In another embodiment shown in Figure 4, a SAMAPD device 300 is provided. The SAMAPD device 300 comprises a substrate 301 and an n-type contact layer 303 formed on the substrate 301. The SAMAPD device 300 also comprises a p-type contact layer 302. As shown in Figure 4, the device 300 has a pin configuration because the n-type contact layer 303 is grown on the substrate 301. Thus, the p-type contact layer 302 may form the outer layer of the device 300. Therefore, the device 300 of the embodiment shown in Figure 4 has an alternative pin configuration compared to the device 200 of the embodiment shown in Figure 3. In the embodiment shown in Figure 4, the substrate 301 may include InP. In certain embodiments, any semiconductor material in the device 300 (i.e., disposed on the substrate 301) may be lattice-matched to InP. In the embodiment shown in Figure 4, the n-type contact layer 303 may include InAlAs. In an alternative embodiment, the n-type contact layer 303 may contain any one of InP, InGaAsP, InGaAs, or InGaAlAs. The n-type contact layer 303 is n-doped. The n-type contact layer 303 may be highly doped. In a particular embodiment, the n-type contact layer 303 may contain approximately 1.0 × 10⁻¹⁶ 18 cm -3 ~Approximately 5.0 x 10 19 cm -3 It can be doped with n at a concentration of . The n-type contact layer 303 may have a thickness of approximately 100 nm to approximately 1000 nm. In the embodiment shown in Figure 4, the thickness of each layer in the device 300 is measured in the direction from the substrate 301 to the p-type contact layer 302. The layer thicknesses in Figure 4 are not shown to scale. In the embodiment shown in Figure 4, the p-type contact layer 302 may contain InGaAs. In an alternative embodiment, the p-type contact layer 302 may contain InP, InGaAsP, InAlAs, or InGaAlAs. The p-type contact layer 302 is p-doped. The p-type contact layer 302 can be doped to a high concentration. In a particular embodiment, the p-type contact layer 302 may have a thickness of approximately 1.0 × 10 18 cm -3 From approximately 5.0 x 10 19cm -3 can be p-doped at a concentration of. The p-type contact layer 302 can have a thickness of approximately 30 nm to 100 nm. As shown in FIG. 4, one or more electrodes 305 can be provided on each of the n-type contact layer 303 and the p-type contact layer 302. In the embodiment of FIG. 4, one electrode is provided on each of the n-type contact layer 303 and the p-type contact layer 302. The electrode 305 provided on the p-type contact layer 302 is in the shape of a ring. Thus, in the cross-section of the device 300 shown in FIG. 4, two portions of a single ring-shaped electrode 305 are illustrated.

[0108] The device 300 includes an avalanche layer 306 containing antimony (Sb). The avalanche layer 306 is disposed between the p-type contact layer 302 and the n-type contact layer 303. The avalanche layer 306 can be intrinsic. The avalanche layer 306 can have a thickness of 75 to 3000 nm. In the embodiment shown in FIG. 4, the avalanche layer 306 can include Al x Ga 1-x As y Sb 1-y and x is 0.4 or more and 1.0 or less, and optionally 0.85 or more and 1.0 or less. In a particular embodiment, y can be selected to lattice match the avalanche layer 306 to the InP substrate 301. In a particular embodiment, the avalanche layer 306 is Al x Ga 1-x As y Sb 1-y and x is 0.85 and y is 0.56. In an alternative embodiment, the avalanche layer 306 can instead include InAlAsSb or AlAsSb.

[0109] As shown in Figure 4, the SAMAPD device 300 has a multi-stage structure. The multi-stage structure includes a first stage 307 and a second stage 308. The first stage 307 includes a p-type contact layer 302, and the second stage 308 includes an avalanche layer 306. The device 300 also includes a third stage 325 disposed between the second stage 308 and the first stage 307. As shown in the embodiment of Figure 4, the first stage 307 may be centered on the third stage 325. The third stage 325 may be centered on the second stage 308. The second stage 308 may be centered relative to the substrate 301. As shown in the embodiment of Figure 4, the first stage 307 includes a side wall 309, the second stage 308 includes a side wall 310, and the third stage 325 includes a side wall 326. The side wall 309 of the first stage may extend from the third stage 325 toward the top surface 311 of the device 300. The side wall 310 of the second stage 308 may extend from the substrate 301 toward the first stage 307. The side wall 326 of the third stage 325 may extend from the second stage 308 toward the first stage 307. As shown in Figure 4, the layers within the first, second, and third stages 307, 308, and 325 each extend toward the respective side walls 309, 310, and 326 of the stages 307, 308, and 325. The embodiment shown in Figure 4 includes three stages, but in alternative embodiments, the multi-stage structure may include three, four, or more stages.

[0110] The first layer 307 has a smaller cross-sectional area than both the third layer 325 and the second layer 308, and the cross-sectional area is defined to be perpendicular to the direction from the substrate 301 to the p-type contact layer 302. Therefore, the width of the p-type contact layer 302 is smaller than the width of the avalanche layer 306.

[0111] The third stage 325 has a smaller cross-sectional area than the second stage 308, and its cross-sectional area is defined to be perpendicular to the direction from the substrate 301 to the p-type contact layer 302. As shown in Figure 4, the layers in the first stage 307 have substantially the same cross-sectional area as the layers in the second stage 308 have substantially the same cross-sectional area as the layers in the third stage 325 have substantially the same cross-sectional area as the layers in the third stage 325.

[0112] In a manner similar to that of the embodiment shown in Figure 1, the multi-stage structure ensures that during use, the high-electric-field region of the device 300 is confined to the area directly beneath the p-type contact layer 302, as indicated by the area between the dashed lines in Figure 4. The high-electric-field region does not extend to the sidewall of the second stage 308. Therefore, the multi-stage structure results in a device 300 with improved performance and reliability.

[0113] In certain embodiments, the distance between the sidewall 309 of the first step 307 and the sidewall 310 of the second step 308 in a direction perpendicular to the direction from the substrate 301 to the n-type contact layer 303 is 5 μm to 100 μm. At distances of 5 μm or more, the high-electric-field region is away from the sidewall of the avalanche layer 306 during use. In certain embodiments, the distance between the sidewall 309 of the first step 307 and the sidewall 310 of the second step 308 may be at least 15 μm. At such distances, the high-electric-field region is sufficiently far from the sidewall of the avalanche layer 306 to significantly reduce the risk of hot spots forming on the sidewall of the avalanche layer 306 due to irregularities, and the resistance of the device 300 to defects is further improved compared to distances of less than 15 μm. In certain embodiments, the distance between the sidewall of the first stage 307 and the sidewall of the second stage 308 may be 30 μm or less in order to limit the size and capacitance of the device 300.

[0114] In a non-limiting specific embodiment shown in Figure 4, the multi-stage structure is a multi-stage mesa structure. The first stage 307 is the first mesa, the second stage 308 is the second mesa, and the third stage 325 is the third mesa. Thus, device 300 is a triple mesa structure. Devices 100 and 200 shown in Figures 1 and 2 are double mesa structures.

[0115] As shown in Figure 4, the multi-stage structure may be a stepped structure. The first stage 307 provides the first step, the second stage 308 provides the second step, and the third stage 325 provides the third step. The first step may be relative to the third stage 325. The third step may be relative to the second stage 308. The second step may be relative to the substrate 301. That is, the second step has a smaller cross-sectional area than the substrate 301, and the cross-sectional area is defined to be perpendicular to the direction from the substrate to the p-type contact layer 302. As shown in Figure 4, each step may have side walls that are substantially perpendicular to the substrate 301. Each step may have top surfaces 311, 312, 327 that are substantially parallel to the substrate 301.

[0116] In certain non-limiting examples, each layer within the device 300 may have a substantially circular cross-section, and the cross-section is oriented perpendicular to the direction from the substrate 301 to the p-type contact layer 302. Thus, each of the first layer 307, the second layer 308, and the third layer 325 may have a substantially cylindrical shape. However, the present invention is not limited to each layer of the device 300 having a substantially circular cross-section. Each layer may have any preferred cross-section. In certain embodiments, each layer may have a substantially rectangular or substantially square cross-section, and each corner of the rectangle or square may be rounded.

[0117] In a manner similar to the embodiment shown in Figure 1, the inventors discovered that using a multi-stage structure in the SAMAPD device 300 in combination with an antimony-containing avalanche layer 306 yields unexpected synergistic advantages due to the low-noise characteristics and wide bandgap of the avalanche layer 306. The properties of the antimony-based avalanche layer 306 allow for the use of a thicker avalanche layer 306 than in other known devices, which yields beneficial results in the multi-stage structure. In certain embodiments, the avalanche layer 306 may have a thickness of 300 to 1000 nm. A thicker avalanche layer 306 can significantly reduce the peak electric field across the avalanche region required for avalanche gain. Therefore, the impact of any defects in the device 300 on the device performance is reduced.

[0118] As described above with respect to device 200 of the embodiment shown in Figure 3, device 300 comprises an APD subassembly. The APD subassembly may comprise a subset of the features of device 300 shown in Figure 4. In the embodiment shown in Figure 4, the APD subassembly comprises a substrate 301, an n-type contact layer 303 formed on the substrate 301, and a p-type contact layer 302. The subassembly also comprises an antimony-containing avalanche layer 306 disposed between the n-type contact layer 303 and the p-type contact layer 302. The APD subassembly has a multi-stage structure comprising a first stage 307 containing the p-type contact layer 302 and a second stage 308 containing the avalanche layer 306. As described above, the first stage 307 has a smaller cross-sectional area than the second stage 308, and the cross-sectional area is perpendicular to the direction from the substrate 301 to the p-type contact layer 302. Thus, the APD subassembly is a component of device 300. Device 300 may include further features in addition to the APD subassembly. The APD subassembly may optionally include one or more additional features of device 300 as shown and described with reference to Figure 4.

[0119] As shown in the embodiment of Figure 4, the device 300 may include a first spacer layer 313. The spacer layer 313 may be included in the APD subassembly. The spacer layer 313 may be disposed between the avalanche layer 306 and the p-type contact layer 302. The first spacer layer 313 may be intrinsic. The first spacer layer 313 may have a thickness of 50 nm to 4000 nm. The first spacer layer 313 includes a lower 313a and an upper 313b. The upper 313b has a smaller cross-sectional area than the lower 313a, and the cross-sectional area is perpendicular to the direction from the substrate 301 to the p-type contact layer 302. As shown in Figure 4, the lower 313a is located within the second step 308 and the upper 313b is located within the third step 325. Thus, the second step 308 includes the lower 313a and the third step 325 includes the upper 313b. As shown in Figure 4, the third stage 325 begins within the first spacer layer 313. Therefore, when manufacturing the device 300, it can be advantageously etched such that the transition between the second stage 308 and the third stage 325 occurs within the first spacer layer 313. The transition between the second stage 308 and the third stage 325 can occur at any point within the first spacer layer 313. This can improve the ease of manufacturing the device 300.

[0120] Additionally, the lower part 313a of the first spacer layer 313 defines the upper boundary of the second step 308. As shown in Figure 4, the lower part 313a of the first spacer layer 313 provides the upper surface 312 of the second step 308, ensuring that the sidewalls of the avalanche layer 306 are the only outer surfaces of the avalanche layer 306. As described above, the first spacer layer 313 improves the manufacturability of the device because the transition between the second step 308 and the third step 325 can occur at any point within the first spacer layer 313. Additionally, terminating the second step within the first spacer layer 313 rather than the avalanche layer 306 may also allow for reduced surface leakage.

[0121] In certain embodiments, the spacer layer may not contain antimony. In the embodiment shown in Figure 4, the spacer layer may contain InAlAs. In an alternative embodiment, the first spacer layer 313 may contain InP. As described above, antimony can oxidize severely when used as an etch stop during wet etching. Therefore, providing an antimony-free first spacer layer 313 can help create a uniform electric field across the avalanche layer 306 in the second stage 308, limiting the peak electric field away from the outer surface of the device 300. Because only a low electric field extends across the outer surface of the avalanche layer 306, the first spacer layer 313 can improve the device 300's resistance to manufacturing imperfections and defects.

[0122] In certain embodiments, the first spacer layer 313 may also reduce the capacitance of the device 300, thereby improving the performance of the device 300. This can be achieved by increasing the thickness of the device 300. This may be most beneficial when the device 300 is used in low-speed applications such as LiDAR. In certain embodiments, the first spacer layer 313 may have a thickness of 250 nm to 4000 nm to reduce the capacitance of the device 300. However, when the device 300 is used in high-speed applications such as telecommunications, the capacitance reduction by a thick first spacer layer 313 may not be more important than the speed of the device 300. Therefore, in certain embodiments, the first spacer layer 313 may have a thickness of 50 to 300 nm.

[0123] As shown in the embodiment of Figure 4, the device 300 may include a second spacer layer 322 disposed between the first spacer layer 313 and the p-type contact layer 302. The APD subassembly may include the second spacer layer 322. The second spacer layer 322 may be intrinsic. The second spacer layer 322 may have a thickness of 50 nm to 4000 nm. The second spacer layer 322 includes a lower 322a and an upper 322b. The upper 322b has a smaller cross-sectional area than the lower 322a, and the cross-sectional area is perpendicular to the direction from the substrate 301 to the p-type contact layer 302. As shown in Figure 4, the lower 322a is located within the third 325 and the upper 322b is located within the first step 307. Thus, the third step 325 includes the lower 322a and the first step 307 includes the upper 322b. As shown in Figure 4, the first stage 307 begins within the second spacer layer 322. Therefore, when manufacturing the device 300, it can be advantageously etched such that the transition between the first stage 307 and the third stage 325 occurs within the second spacer layer 322. The transition between the first stage 307 and the third stage 325 can occur at any point within the second spacer layer 322. This can improve the ease of manufacturing the device 300.

[0124] In certain embodiments, the spacer layer may not contain antimony. In the embodiment shown in Figure 4, the spacer layer may contain InAlAs. In an alternative embodiment, the second spacer layer 322 may contain InP. As described above, antimony can oxidize severely when used as an etch stop during wet etching. Therefore, providing a second spacer layer 322 that defines the upper surface 327 of the third step 325 and does not contain antimony may improve the performance of the device 300.

[0125] In certain embodiments, the second spacer layer 322 may also reduce the capacitance of the device 300, thereby improving the performance of the device 300. This can be achieved by increasing the thickness of the device 300. In certain embodiments, the second spacer layer 322 may have a thickness of 250 nm to 4000 nm to reduce the capacitance of the device 300. However, when the device 300 is used in high-speed applications such as telecommunications, the capacitance reduction by a thick second spacer layer 322 may not be more important than the superior speed of the device 300. Therefore, in certain embodiments, the second spacer layer 322 may have a thickness of 50 to 300 nm.

[0126] As shown in Figure 4, the device 300 may comprise one or more additional layers located between the second spacer layer 323 and the p-type contact layer 302. These layers may be located within the first stage 307 of the multi-stage structure, as shown in Figure 4.

[0127] The device 300 may comprise a first cladding layer 314. The APD subassembly may comprise a first cladding layer 314. As shown in the embodiment of Figure 4, the first cladding layer 314 may be disposed between a second spacer layer 322 and a p-type contact layer 302. The first cladding layer 314 may be formed on the second spacer layer 322. The p-type contact layer 302 may be formed on the first cladding layer 314. As shown in Figure 4, the first stage 307 of a multi-stage structure may include the first cladding layer 314. In the embodiment shown in Figure 4, the first cladding layer 314 may contain InAlAs. The first cladding layer 314 may have a thickness of approximately 50 nm to approximately 500 nm. In certain embodiments, the first cladding layer 314 may be p-doped. The concentration of the dopant in the first cladding layer 314 is approximately 1.0 × 10⁻¹⁶. 18 cm -3 ~Approximately 1.0 × 10 19 cm -3 This is possible. The concentration of the dopant in the first cladding layer 314 may be lower than the concentration of the dopant in the p-type contact layer 302.

[0128] Device 300 may include an inclined cladding layer 315 between the second spacer layer 322 and the p-type contact layer 302. The APD subassembly may include the inclined cladding layer 315. The inclined cladding layer 315 may be formed on the upper portion 322b of the second spacer layer 322. Thus, the inclined cladding layer 315 may be disposed between the second spacer layer 313 and the first cladding layer 314. Therefore, the first stage 307 may include the inclined cladding layer 315. The inclined cladding layer 315 may be p-doped. The concentration or level of dopants in the inclined cladding layer 315 may increase in the direction from the substrate 301 to the p-type contact layer 303. In certain embodiments, the dopant concentration may increase from 1.0×10 16 cm -3 to 1.0×10 18 cm -3 . In certain embodiments, the dopant concentration may increase to or towards the concentration of the first cladding layer 314. In the embodiment shown in FIG. 4, the inclined cladding layer 315 may include InAlAs. In an alternative embodiment, the inclined cladding layer 315 may include InP, InGaAlAs, or InGaAsP. The inclined cladding layer 315 may have a thickness of approximately 100 nm to approximately 500 nm.

[0129] In certain embodiments, the doping of the inclined cladding layer 315 may be inclined such that at the interface between the inclined cladding layer 315 and an adjacent layer within the device 300, the concentration of dopants is substantially the same as the concentration in one or both of the adjacent layers. The inclined cladding layer 315 may be substantially intrinsic adjacent to the interface between the second spacer layer 322 and the inclined cladding layer 115. The concentration of dopants in the inclined cladding layer 315 may be substantially the same as the concentration in the first cladding layer 314 adjacent to the interface between the inclined cladding layer 315 and the first cladding layer 314. Inclining the inclined cladding layer 315 in this manner may help further reduce the occurrence of hot spots within the device 300 during use by reducing abrupt changes in grading.

[0130] Therefore, as shown in the embodiment of Figure 4, the device 300 may include a gradient cladding layer 315 and a first cladding layer 314 located between the second spacer layer 322 and the p-type contact layer 302 within the first stage 307. However, the present invention is not limited to the specific layers or layer order shown in Figure 4.

[0131] The device 300 may comprise one or more additional layers located between the n-type contact layer 303 and the first spacer layer 313. These layers may be located within a second layer 308 of a multi-layer structure, as shown in Figure 4.

[0132] Device 300 may include an electric field control layer 316. The APD subassembly may include an electric field control layer 316. As shown in Figure 4, the second stage 308 of the multi-stage structure may include an electric field control layer 316. The electric field control layer 316 may be disposed between the avalanche layer 306 and the first spacer layer 313. The electric field control layer 316 may be formed on the avalanche layer 306. The first spacer layer 313 may be formed on the electric field control layer 316.

[0133] The electric field control layer 316 can be p-doped. The dopant concentration in the electric field control layer 316 is approximately 1.0 × 10⁻⁶. 17 cm -3 ~Approximately 1.0 × 10 18 cm -3 This is possible. In certain embodiments, the field control layer 316 may not contain antimony. Thus, in a similar manner to the first spacer layer 313, the field control layer 316 may further help reduce the risk of oxidation to the avalanche layer 306 during manufacturing using wet etching. In the embodiment shown in Figure 4, the field control layer 316 may contain InAlAs. In alternative embodiments, the field control layer 316 may contain InGaAlAs, InP, or InGaAsP. The field control layer 316 may have a thickness of approximately 30 nm to approximately 250 nm.

[0134] Device 300 may include a second cladding layer 331. The APD subassembly may include a second cladding layer 331. As shown in the embodiment of Figure 4, the second cladding layer 331 may be disposed between the avalanche layer 306 and the n-type contact layer 303. The second cladding layer 331 may be formed on the n-type contact layer 303. The avalanche layer 306 may be formed on the second cladding layer 331. As shown in Figure 4, the second stage 308 of a multi-stage structure may include the second cladding layer 331.

[0135] In the embodiment shown in Figure 4, the second cladding layer 331 may contain InAlAs. The second cladding layer 331 may have a thickness of approximately 100 nm to approximately 750 nm. In certain embodiments, the second cladding layer 331 may be n-doped. The concentration of the dopant in the second cladding layer 331 is approximately 1.0 × 10⁻¹⁶. 18 cm -3 ~Approximately 1.0 × 10 19 cm -3 It is possible.

[0136] Therefore, as shown in the embodiment of Figure 4, the device 300 may include a second cladding layer 331, an avalanche layer 306, and an electric field control layer 316 within the second stage 308, located between the n-type contact layer 303 and the first spacer layer. However, the present invention is not limited to the specific layers or layer order shown in Figure 4.

[0137] Device 300 may include one or more additional layers located between the first spacer layer 313 and the second spacer layer 322. These layers may be located within a third layer 325 of a multi-layer structure, as shown in Figure 4.

[0138] The device 300 may include an absorption layer 317 disposed between the avalanche layer 306 and the p-type contact layer 302. The APD subassembly may include the absorption layer 317. In the embodiment shown in Figure 4, the absorption layer 317 is disposed between the first spacer layer 313 and the second spacer layer 322. Therefore, the third stage 325 of the multi-stage structure may include the absorption layer 317. In the embodiment shown in Figure 4, the absorption layer 317 may include InGaAs. In alternative embodiments, the absorption layer 317 may include any one of InGaAlAs, GaAsSb, InGaAsP, or InGaAs / GaAsSb type II superlattices. In certain embodiments, the absorption layer 317 may be intrinsic. The absorption layer 317 may have a thickness of approximately 500 nm to approximately 2500 nm.

[0139] The device 300 may include a transition section 318 disposed between the avalanche layer 306 and the absorption layer 317. The APD subassembly may include a transition section 318. As shown in Figure 4, the third stage 325 of the multi-stage structure may include a transition section 318. Therefore, the transition section 318 may be disposed between the first and second spacer layers 313, 322. As shown in Figure 4, the transition section 318 may be disposed between the first spacer layer 313 and the absorption layer 317.

[0140] The transition layer 318 may include a first grading layer 319 and a charge sheet 320. The charge sheet 320 may be disposed between the first grading layer 319 and the avalanche layer 306. The charge sheet 320 may have a band gap between the band gap of the absorption layer 317 and the band gap of the avalanche layer 306. As shown in Figure 4, the charge sheet 320 may be formed on the first spacer layer 313. Therefore, the charge sheet 320 may be disposed on the opposite side of the first spacer layer 313 from the electric field control layer 316. The absorption layer 317 may be formed on the first grading layer 319.

[0141] The charge sheet 320 in the embodiment of Figure 4 has substantially the same effect as the charge sheet 120 in the embodiment of Figure 1 described above. In certain embodiments, the charge sheet 320 may be p-doped. In certain embodiments, the charge sheet 320 may be 1 × 10 17 cm -3 ~1 × 10 18 cm -3 At a concentration of 1 × 10, arbitrarily selected 17 cm -3 ~5×10 17 cm -3 It can be p-doped at a concentration of . In certain embodiments, the charge sheet 320 may have a thickness of 40 nm to 300 nm. In certain embodiments, the charge sheet 320 may contain InAlAs. In certain embodiments, the charge sheet 320 may have a band gap of 1 eV or more. In certain embodiments, the charge sheet 320 may contain substantially the same material as the field control layer 316. In certain embodiments, the charge sheet 320 may be substantially the same as the field control layer 316.

[0142] In certain embodiments, the first grading layer 319 may have a constant band gap over its thickness. In the embodiment shown in Figure 4, the first grading layer 319 may contain AlGaInAs. In alternative embodiments, the first grading layer 319 may contain InGaAsP. The first grading layer 319 may be intrinsic. The first grading layer 319 may have a thickness of approximately 25 nm to approximately 50 nm.

[0143] As shown in the embodiment of Figure 4, the transition layer 318 may include a second grading layer 321 disposed between the first grading layer 319 and the charge sheet 320. In certain embodiments, the second grading layer 321 may have a constant band gap over its thickness. In the embodiment shown in Figure 4, the second grading layer 321 may contain AlGaInAs. In alternative embodiments, the second grading layer 321 may contain InGaAsP. The second grading layer 321 may be intrinsic. The second grading layer 321 may have a thickness of approximately 25 nm to approximately 50 nm. The second grading layer 321 has a different band gap than the first grading layer 319. The second grading layer 321 may have a band gap between the band gap of the first grading layer 319 and the band gap of the avalanche layer 306.

[0144] The device 300 may include a third grading layer 330 disposed between the absorption layer 317 and the second spacer layer 322. The APD subassembly may include the third grading layer 330. As shown in the embodiment of Figure 4, the third stage 325 of a multi-stage structure may include the third grading layer 330. The third grading layer 330 may be formed on the absorption layer 317. In the embodiment shown in Figure 4, the third grading layer 330 is on the opposite side of the absorption layer 317 from the transition 318. In the embodiment shown in Figure 4, the third grading layer 330 contains AlGaInAs. The third grading layer 330 may be intrinsic.

[0145] As shown in the embodiment of Figure 4, the third grading layer 330 may include two separate layers 330a and 330b, each having a different band gap. The third grading layer 330 may include a first layer 330a formed on the absorption layer 317 and a second layer 330b formed on the first layer 330a. A second spacer layer 322 may be formed on the second layer 330b of the third grading layer 330. The first layer 330a of the third grading layer 330 may have a band gap between the band gap of the absorption layer 317 and the band gap of the second layer 330b of the third grading layer 330. In the embodiment shown in Figure 4, each layer in the third grading layer 330 may contain AlGaInAs. The third grading layer 330 may have a thickness of approximately 50 nm to 100 nm. Each of the first and second layers of the third grading layer 330 may have the same thickness as the other. Therefore, each of the first and second layers of the third grading layer 330 may have a thickness of approximately 25 nm to approximately 50 nm. In an alternative embodiment, each layer of the third grading layer 330 may contain InGaAsP.

[0146] Therefore, as shown in the embodiment of Figure 4, the device 300 may include, within the third stage 325, a charge sheet 320, a second grading layer 321, a first grading layer 319, an absorption layer 317, and a third grading layer 330, located between the first spacer layer 313 and the second spacer layer 322. However, the present invention is not limited to the specific layers or layer order shown in Figure 4.

[0147] As described above, the second cladding layer 331 may be formed on the n-type contact. In the embodiment shown in Figure 4, the n-type contact layer 303 is formed on the substrate 301. As shown in the embodiment of Figure 4, the n-type contact layer 303 may have a larger cross-sectional area than the second step 308, and the cross-sectional area is perpendicular to the direction from the substrate 301 to the p-type contact layer 302. Therefore, the second step 308 of the device 300 does not have to include the n-type contact layer 303. Rather, the second step 308 of the device 300 may be formed on the n-type contact layer 303. In certain embodiments, the n-type contact may have substantially the same cross-sectional area as the substrate 301, and the cross-sectional area is perpendicular to the direction from the substrate 301 to the p-type contact layer 302. Therefore, one or more electrodes may be formed on the n-type contact layer 303.

[0148] However, the present invention is not limited to the arrangement of the n-type contact layer 303 shown in Figure 4. In alternative embodiments, the second layer 308 of the multi-stage structure may include at least a portion of the n-type contact layer 303. In certain embodiments, the n-type contact layer 303 may reside within the second layer 308; that is, the second layer 308 may substantially include the entire n-type contact layer 303. In certain embodiments, the n-type contact layer 303 may include an upper and a lower section. The second cladding layer 331 may be formed on top of the upper section of the n-type contact layer 303. The lower section of the n-type contact layer 303 may be adjacent to the substrate 301. The second layer 308 of the multi-stage structure may include the upper section of the n-type contact layer 303. The upper section of the n-type contact layer 303 may have a smaller cross-sectional area than both the lower section of the n-type contact layer 303 and the substrate 301, and the cross-sectional area is defined to be perpendicular to the direction from the substrate 301 to the n-type contact layer 303. Therefore, the lower part of the n-type contact layer 303 does not have to be present with the second stage 308 of the device 300. Thus, the second stage 308 may begin within the n-type contact layer 303. The lower part of the n-type contact layer 303 may have substantially the same cross-sectional area as the substrate 301. One or more electrodes 305 may be formed on the lower part of the n-type contact layer 303.

[0149] The device 300 having the first, second, and third stepped structures in the embodiment shown in Figure 4 may have a longer device life and improved reliability than the device 200 in the embodiment shown in Figure 3. This is because the electric fields at the sidewalls of both the avalanche layer and the absorber layer are lower in the device 300 of the embodiment shown in Figure 4 than in the device 200 of the embodiment shown in Figure 3. However, the device 400 of the embodiment shown in Figure 4 may be more complex to manufacture compared to the device 200 of the embodiment shown in Figure 3.

[0150] In another embodiment shown in Figure 5, a SAMAPD device 400 is provided. The SAMAPD device 400 comprises a substrate 401 and a first contact layer 403 formed on the substrate 401. The SAMAPD device 400 also comprises a second contact layer 402. One or more electrodes 405 may be provided on each of the first contact layer 403 and the second contact layer 402. In the embodiment of Figure 5, one electrode is provided on each of the first contact layer 403 and the second contact layer 402. The electrode 405 provided on the second contact layer 402 is in the shape of a ring. Thus, in the cross-section of the device 500 shown in Figure 5, two portions of a single ring-shaped electrode 405 are illustrated.

[0151] The first contact layer 403 is an n-type contact layer. Therefore, the first contact layer 403 is n-doped. In certain embodiments, the first contact layer 403 is approximately 1.0 × 10⁻¹⁶ 18 cm -3 ~Approximately 2.0 × 10 19 cm -3 It can be doped with n at a concentration of . The first contact layer 403 may have a thickness of approximately 100 nm to approximately 1000 nm. In the embodiment shown in Figure 5, the thickness of each layer in the device 400 is measured in the direction from the substrate 401 to the second contact layer 402. The layer thicknesses in Figure 5 are not shown to scale.

[0152] The second contact layer 402 includes a p-type contact region 450 formed by diffusing zinc. In Figure 5, the p-type contact region 450 is indicated by the area between the dotted lines 451 within the second contact layer 402. The p-type contact region 450 may be characterized by having a high concentration of zinc atoms. As shown in the embodiment of Figure 1, the p-type contact region 450 may be a localized region within the second contact layer 402. That is, the p-type contact region 450 may have a smaller width than the second contact layer 402, and this width is perpendicular to the direction from the substrate 401 to the second contact layer 403. The second contact layer 402 may have a thickness of approximately 25 nm to approximately 50 nm. As shown in Figure 5, one or more electrodes 405 may be formed on the second contact layer 402. The electrodes 405 may be in contact with the p-type contact region 450.

[0153] As shown in Figure 5, the device 400 is in a pin configuration because the first contact layer 403 is grown on the substrate 401. Therefore, the second contact layer 402 may form the outer layer 411 of the device 400. In the embodiment shown in Figure 5, the substrate 401 may contain InP. In certain embodiments, any semiconductor material in the device 400 (i.e., disposed on the substrate 401) may be lattice-matched to InP. In the embodiment shown in Figure 5, the first contact layer 403 may contain InAlAs. In alternative embodiments, the first contact layer 403 may contain any one of InP, InGaAs, GaAsSb, InGaAsP, or InGaAlAs. In the embodiment shown in Figure 5, the second contact layer 402 may contain InGaAs. In alternative embodiments, the second contact layer 402 may contain InP, InGaAsP, InAlAs, or InGaAlAs. As shown in Figure 5, one or more electrodes 405 may be provided on each of the first contact layer 403 and the second contact layer 402.

[0154] The device 400 comprises an avalanche layer 406 containing antimony (Sb). The avalanche layer 406 is disposed between a second contact layer 402 and a first contact layer 403. The avalanche layer 406 may be intrinsic. The avalanche layer 406 may have a thickness of 75 to 4000 nm. In the embodiment shown in Figure 5, the avalanche layer 406 may contain AlGaAsSb. In certain embodiments, the avalanche layer 406 may contain Al x Ga 1-x As y S 1-y It may include, where x is 0.4 or more and 1.0 or less, and optionally 0.85 or more and 1.0 or less. In a particular embodiment, y may be selected to lattice match the avalanche layer 406 to the InP substrate 401. In a particular embodiment, the avalanche layer 406 is Al x Ga 1-x As y S 1-y It may include, where x is 0.85 and y is 0.56. In an alternative embodiment, the avalanche layer 406 may instead contain InAlAsSb or AlAsSb.

[0155] As shown in Figure 5, the p-type contact region 450 has a smaller cross-sectional area than the avalanche layer 406, and its cross-sectional area is perpendicular to the direction from the substrate 401 to the second contact layer 402.

[0156] The relative sizes of the p-type contact region 450 and the avalanche layer 406 ensure that, during use, the high-electric-field region of the device 400 is substantially confined to the area directly beneath the p-type contact region 450, as shown by the area between the dashed lines in Figure 5. The high-electric-field region does not extend to the sidewalls 410 of the avalanche layer 406. As a result, the device 400 has improved performance and reliability.

[0157] In certain embodiments, the distance between the edge 450a of the p-type contact region 450 and the sidewall 410 of the avalanche layer 406 in the direction from the substrate 401 to the second contact layer 403 may be at least 7.5 μm. At such a distance, the high-electric-field region can be sufficiently far from the sidewall of the avalanche layer 406 so that the risk of hot spots forming on the sidewall of the avalanche layer 406 due to irregularities is significantly reduced, and the resistance of the device 400 to defects is improved. This is shown in Figure 6. Figure 6 shows an example of the electric field within the avalanche layer 406 as a function of distance from the center of the avalanche layer 406. In Figure 6, the center of the avalanche layer 406 is at x=0 μm in Figure 6, and the sidewall 410 of the avalanche layer is at x=50 μm. In Figure 6, the location of the edge 450a of the p-type contact region 450 is indicated by the first dashed line 480. At distances greater than the position of the first dashed line 480, the electric field decreases sharply. The electric field reaches its minimum or stable value at the position of the second dashed line 481. The second dashed line 481 is located 7.5 μm away from the first dashed line 480. Therefore, by providing a distance of at least 7.5 μm between the edge 450a of the p-type contact region 450 and the sidewall 410 of the avalanche layer 406 in the direction from the substrate 401 to the second contact layer 403, a significant reduction in the electric field at the sidewall 410 of the avalanche layer 406 is ensured, thereby achieving optimal performance of the device 400. However, even at distances less than 7.5 μm from the edge 450a of the p-type contact region 450, the electric field within the avalanche layer 406 is still reduced. Therefore, while the optimal performance of device 400 can be achieved at a distance of at least 7.5 μm, improvements in device 400 performance can still be achieved at distances less than 7.5 μm. In certain embodiments, the distance between the wall 450a of the p-type contact region 450 and the side wall 410 of the avalanche layer 406 may be 30 μm or less to limit the size and capacitance of the device.

[0158] In a non-limiting specific embodiment shown in Figure 5, the device is a quasi-planar device. As shown in Figure 5, the second contact layer 402 may have substantially the same cross-sectional area as the avalanche layer 406, and the cross-sectional area is perpendicular to the direction from the substrate 401 to the second contact layer 402. The p-type contact region 450 may be located at the center on the avalanche layer 406. As shown in Figure 5, each layer between the second contact layer 402 and the first contact layer 403 may have substantially the same cross-sectional area as the other, and the cross-sectional area is perpendicular to the direction from the substrate 401 to the second contact layer 402.

[0159] In certain non-limiting examples, each layer within the device 400 may have a substantially circular cross-section, and the cross-section is oriented perpendicular to the direction from the substrate 401 to the second contact layer 402. Thus, each layer within the device 400 may have a substantially cylindrical shape. However, the present invention is not limited to each layer of the device 400 having a substantially circular cross-section. Each layer may have any preferred cross-section. In certain embodiments, each layer may have a substantially rectangular or substantially square cross-section, and each corner of the rectangle or square may be rounded.

[0160] In certain embodiments, the avalanche layer 406 may have a thickness of 300 nm to 1000 nm. As described above, a thick antimony avalanche layer can reduce the voltage sensitivity of the device 400 during use. The thick avalanche layer 406 can significantly reduce the peak electric field across the avalanche region required for avalanche gain. Thus, the impact of any defects in the device 400 on the device performance is reduced.

[0161] The device 400 in the embodiment shown in Figure 5 comprises an APD subassembly. The APD subassembly may comprise a subset of the features of the device 400 shown in Figure 5. In the embodiment shown in Figure 5, the APD subassembly comprises a substrate 401, a first contact layer 403 formed on the substrate 401, and a second contact layer 402. The subassembly also comprises an antimony-containing avalanche layer 406 disposed between the first contact layer 303 and the second contact layer 302. As described above, the first contact layer 403 is an n-type contact layer, and the second contact layer 502 includes a p-type contact region 450 formed by diffusing zinc. The p-type contact region 450 has a smaller cross-sectional area than the avalanche layer 406, and the cross-sectional area is perpendicular to the direction from the substrate 401 to the second contact layer 402. Thus, the APD subassembly is a component of the device 400. Device 400 may include further features in addition to the APD subassembly. The APD subassembly may optionally include one or more additional features of device 400 as shown and described with reference to Figure 5.

[0162] Device 400 may include one or more additional layers located between the avalanche layer 406 and the second contact layer 402.

[0163] The device 400 may include an absorption layer 417 disposed between the avalanche layer 406 and the second contact layer 402. The APD subassembly may include the absorption layer 417. In the embodiment shown in Figure 5, the absorption layer 417 may include InGaAs. In alternative embodiments, the absorption layer 417 may include any one of InGaAlAs, GaAsSb, InGaAsP, or InGaAs / GaAsSb type II superlattices. In certain embodiments, the absorption layer 417 may be intrinsic. The absorption layer 417 may have a thickness of approximately 500 nm to approximately 2500 nm.

[0164] The device 400 may include a transition section 418 disposed between the avalanche layer 406 and the absorption layer 417. The APD subassembly may include a transition section 118. The transition section 418 may include a first grading layer 419 and a charge sheet 420. The charge sheet 420 may be disposed between the first grading layer 419 and the avalanche layer 406. The charge sheet 420 may have a band gap between the band gap of the absorption layer 417 and the band gap of the avalanche layer 406. As shown in Figure 5, the charge sheet 420 may be formed on the avalanche layer 406. The absorption layer 417 may be formed on the first grading layer 419.

[0165] The charge sheet 420 in the embodiment of Figure 5 has substantially the same effect as the charge sheet 220 in the embodiment of Figure 3 described above. In certain embodiments, the charge sheet 420 may be p-doped. In certain embodiments, the charge sheet 420 may be 1 × 10 17 cm -3 ~1 × 10 18 cm -3 , and optionally 1 × 10 17 cm -3 ~5×10 17 cm -3 It can be p-doped at a concentration of [value]. In certain embodiments, the charge sheet 420 may have a thickness of 40 nm to 300 nm. In certain embodiments, the charge sheet 420 may contain InAlAs. In certain embodiments, the charge sheet 420 may have a band gap of 1 eV or more.

[0166] In certain embodiments, the first grading layer 419 may have a constant band gap over its thickness. In the embodiment shown in Figure 5, the first grading layer 419 may contain AlGaInAs. In alternative embodiments, the first grading layer 419 may contain InGaAsP. The first grading layer 419 may be intrinsic. The first grading layer 419 may have a thickness of approximately 25 nm to approximately 50 nm.

[0167] As shown in the embodiment in the figure, the transition layer 418 may include a second grading layer 421 disposed between the first grading layer 419 and the charge sheet 420. In certain embodiments, the second grading layer 421 may have a constant band gap over its thickness. In the embodiment shown in Figure 5, the second grading layer 421 may contain AlGaInAs. In alternative embodiments, the second grading layer 421 may contain InGaAsP. The second grading layer 421 may be intrinsic. The second grading layer 421 may have a thickness of approximately 25 nm to approximately 50 nm. The second grading layer 421 has a different band gap than that of the first grading layer 419. The second grading layer 421 may have a band gap between the band gap of the first grading layer 419 and the band gap of the avalanche layer 406.

[0168] The device 400 may include at least one stopper layer 460 disposed between the absorption layer 417 and the second contact layer 402. The APD subassembly may include at least one stopper layer 460. At least one stopper layer 460 may be on the opposite side of the absorption layer 417 from the transition portion 418. As shown in the embodiment of Figure 5, the device may include a first stopper layer 460a and a second stopper layer 460b. The first stopper layer 460a may be formed on the absorption layer 417. The second stopper layer 460a may be formed on the first stopper layer 460a.

[0169] Each stopper layer 460a, 460b has a lower zinc diffusion rate than the second contact layer. Therefore, the stopper layers 460a, 460b help prevent undesirable diffusion of zinc into the absorption layer 417 during manufacturing. In the embodiment shown in Figure 6, each of the stoppers 460a, 460b may contain InGaAlAs. In an alternative embodiment, each of the stoppers 460a, 460b may contain InGaAs or InGaAsP. Each of the stopper layers 460a, 460b may be intrinsic. Each of the stopper layers 460a, 460b may have the same thickness as the other. The first and second stopper layers 460a, 460b may each have a thickness of approximately 25 nm to approximately 100 nm.

[0170] Furthermore, the first and second stopper layers 460a and 460b may provide functions similar to those of the first and second layers 230a and 230b of the third grading layer 230 in the embodiment shown in Figure 3. Therefore, each stopper layer 460a and 460b may have different band gaps. The first stopper layer 460a may have a band gap between the band gap of the absorption layer 417 and the band gap of the second stopper layer 460b.

[0171] Device 400 may comprise a first cladding layer 414. The APD subassembly may comprise a first cladding layer 414. As shown in the embodiment of Figure 5, the first cladding layer 414 may be disposed between the absorption layer 417 and the second contact layer 402. The first cladding layer 414 may be formed on the second stopper layer 460b. The second contact layer 402 may be formed on the first cladding layer 414. In the embodiment shown in Figure 5, the first cladding layer 414 may comprise InAlAs. In an alternative embodiment, the first cladding layer 414 may comprise InP. In a particular embodiment, the first cladding layer 414 may be intrinsic.

[0172] As shown in Figure 5, the device 400 includes a zinc diffusion area 451, indicated by the area inside the dotted line in the figure. The zinc diffusion area 451 defines an area of ​​the device 400 where zinc has significantly diffused into the layer during manufacturing. Thus, the zinc diffusion area 451 includes a p-type contact region 450. As shown in Figure 5, the zinc diffusion area 451 may extend into the first cladding layer 414 and also into a stopper layer 460. In certain embodiments, the first cladding layer 414 may have a thickness of approximately 500 nm to approximately 5000 nm. The first cladding layer 414 may be thicker than typical of known SAMAPDs. A thicker cladding layer prolongs the zinc diffusion process in the manufacturing of the device 400. Therefore, the corners 452 of the zinc diffusion area 451 are rounded, thereby reducing the possibility of electric field hotspot formation during use. As described above, at least one stopper layer 460 can restrict the diffusion of zinc into the absorption layer 417. In certain embodiments, the first cladding layer 414 may have a thickness of approximately 1000 nm or more.

[0173] Figure 7 shows an example of zinc concentration across the zinc diffusion area 451 for an embodiment of device 400. Figure 7 shows 1 cm within the p-type contact area 450 of the second contact layer 402, the first cladding layer 414, and at least one stopper layer 460. 3 This shows the concentration of zinc atoms per unit area. In the embodiment shown in Figure 7, the second contact layer has a thickness of 50 nm, the first cladding layer has a thickness of 1000 nm, and at least one stopper layer has a thickness of 50 nm. As shown in Figure 7, the concentration of zinc atoms is highest in the second contact layer 402 where the p-type contact region 450 is formed. The concentration of zinc atoms in the second contact layer 402 is 4 × 10⁻¹⁶. 18 cm -3 ~2×10 20 cm -3 Therefore, the concentration of zinc atoms decreases within the first cladding layer 414. The concentration of zinc atoms within the first cladding layer 414 is 1.4 × 10⁻⁶. 18 cm -3 ~4.0×10 18 cm-3 As shown in Figure 7, the concentration of zinc atoms in the stopper layer 460 at the interface between the stopper layer and the absorption layer is significantly lower than the concentration of zinc atoms in the stopper layer 460 at the interface between the stopper layer and the first cladding layer 414. The concentration of zinc atoms in the stopper layer 460 at the interface between the stopper layer 460 and the absorption layer 417 is approximately 4.0 × 10⁻⁶. 16 cm -3 Therefore, the concentration of zinc atoms in the stopper layer 460 at the interface between the stopper layer 460 and the first cladding layer 414 is approximately 1.4 × 10⁻⁶. 18 cm -3 Therefore, Figure 7 shows that at least one stopper layer 460 is effective in helping to prevent the undesirable diffusion of zinc into the absorption layer 417 during manufacturing.

[0174] As shown in Figure 5, the zinc diffusion area 451 has a substantially uniform thickness. That is, except for the rounded corners 452, the thickness of the zinc diffusion area 451 is uniform. In the embodiment shown in Figure 5, the zinc diffusion area 451 has a substantially uniform width, and this width is perpendicular to the direction from the substrate 401 to the second contact layer 402. That is, except for the rounded corners 452, the width of the zinc diffusion area 451 is uniform. This uniform profile is a result of the device 400 being manufactured by a single zinc diffusion step. Therefore, the zinc diffusion area 452 does not have a stepped profile within the device 400 between the second contact layer 402 and the absorption layer 417.

[0175] As shown in Figure 5, the width of the p-type contact region 450 is substantially the same as the width of the zinc diffusion area in the first cladding layer 414 and at least one stopper layer 460.

[0176] In certain embodiments, the distance between the edge 450a of the p-type contact region 450 and the sidewall 410 of the avalanche layer 406 in the direction from the substrate 401 to the second contact layer 402 is substantially the same as the distance between the edge of the zinc diffusion area and the sidewall 410 of the avalanche layer 406 in the direction from the substrate 401 to the second contact layer 402. The edge of the zinc diffusion area is shown by a dotted line in Figure 5. Thus, in the same manner as described above for the p-type contact region 450 and the avalanche layer 406, the distance between the edge of the zinc diffusion area 451 and the sidewall 410 of the avalanche layer 406 in the direction from the substrate 401 to the second contact layer 402 may be at least 7.5 μm. The performance of the device 400 may be optimal when the distance between the edge of the zinc diffusion area and the sidewall 410 of the avalanche layer 406 is 7.5 μm or greater. At such distances, the high-electric-field region may be sufficiently far from the sidewall of the avalanche layer 406 so as to significantly reduce the risk of hot spots forming on the sidewall of the avalanche layer 406 due to irregularities, thereby improving the device 400's resistance to defects. In certain embodiments, the distance between the edge of the zinc diffusion area 451 and the sidewall 410 of the avalanche layer 406 may be 30 μm or less to limit the size and capacitance of the device.

[0177] Therefore, as shown in the embodiment of Figure 5, the device 400 may comprise a charge sheet 420, a second grading layer 421, a first grading layer 419, an absorption layer 417, at least one stopper layer 460, and a first cladding layer 414, located between the avalanche layer 406 and the second contact layer 402. However, the present invention is not limited to the specific layers or layer order shown in Figure 5.

[0178] Device 400 may include one or more additional layers located between the first contact layer 403 and the avalanche layer 406.

[0179] The device 400 may include a second cladding layer 431. The APD subassembly may include a second cladding layer 431. As shown in the embodiment of Figure 5, the second cladding layer 431 may be disposed between the first contact layer 403 and the avalanche layer 406. The second cladding layer 431 may be formed on the first contact layer 403.

[0180] In the embodiment shown in Figure 5, the second cladding layer 431 may contain InAlAs. In an alternative embodiment, the second cladding layer 431 may contain InP, InGaAlAs, InGaAsP, AlGaAsSb, AlAsSb, or InAlAsSb. The second cladding layer 431 may have a thickness of approximately 30 nm to approximately 250 nm. In a particular embodiment, the second cladding layer 431 may be n-doped. The concentration of the dopant in the second cladding layer 431 is approximately 1.0 × 10⁻¹⁶. 17 cm -3 ~Approximately 1.0 × 10 18 cm -3 This is possible. The concentration of the dopant in the second cladding layer 431 may be lower than the concentration of the dopant in the first contact layer 403.

[0181] Device 400 may include an electric field control layer 416. The APD subassembly may include an electric field control layer 416. The electric field control layer 416 may be disposed between the first contact layer 403 and the avalanche layer 406. As shown in the embodiment of Figure 5, the electric field control layer 416 may be formed on the second cladding layer 431. The avalanche layer 406 may be formed on the electric field control layer 431. Therefore, the electric field control layer 416 may be disposed on the opposite side of the avalanche layer 406 from the transition section 418.

[0182] The electric field control layer 416 can be doped with n. The concentration of the dopant in the electric field control layer 416 is 1.0 × 10⁻⁶. 17 cm -3 ~Approximately 1.0 × 10 19 cm -3This is possible. In certain embodiments, the electric field control layer 416 may contain antimony. In the embodiment shown in Figure 5, the electric field control layer 416 may contain AlGaAsSb. In certain embodiments, the electric field control layer 416 may contain Al x Ga 1-x As y S 1-y It may include, where x is 0.4 or more and 1.0 or less, and optionally 0.85 or more and 1.0 or less. In a particular embodiment, y may be selected to grid-match the electric field control layer 416 to the InP substrate 401. In a particular embodiment, the electric field control layer 416 is Al x Ga 1-x As y S 1-y It may include, where x is 0.85 and y is 0.56. In a particular embodiment, the electric field control layer 416 and the avalanche layer are each Al x Ga 1-x As y S 1-y It may include, where x and y are the same in both layers. In an alternative embodiment, the electric field control layer 416 may include InAlAsSb or AlAsSb. In a particular embodiment, the electric field control layer 416 may have a thickness of approximately 50 nm to approximately 200 nm.

[0183] Therefore, as shown in the embodiment of Figure 5, the device 400 may comprise a second cladding layer 431 and an electric field control layer 416 located between the first contact layer 403 and the avalanche layer 406. However, the present invention is not limited to the specific layers or layer order shown in Figure 5.

[0184] As described above, the second cladding layer 431 may be formed on the first contact layer 403. In the embodiment shown in Figure 5, the first contact layer 403 is formed on the substrate 401. As shown in the embodiment of Figure 5, the first contact layer 403 may have a larger cross-sectional area than the second cladding layer 431 and all subsequent layers laminated on the first contact layer 403, and the cross-sectional area is perpendicular to the direction from the substrate 401 to the second contact layer 402. In the embodiment shown in Figure 5, the second cladding layer 431, the field control layer 416, the charge sheet 420, the second grading layer 421, the first grading layer 419, the absorption layer 417, at least one stopper layer 460, the cladding layer 414, and the second contact layer 403 all have the same cross-sectional area, and the cross-sectional area is perpendicular to the direction from the substrate 401 to the second contact layer 402. One or more electrodes 405 may be formed on the first contact layer 403, as shown in Figure 5.

[0185] In another embodiment shown in Figure 8, a SAMAPD device 500 is provided. The SAMAPD device 500 and its APD subassembly in Figure 8 are identical to the SAMAPD device 400 in Figure 5, except for the configuration of the second contact layer 502 and the configuration of the p-type contact region 550. The reference numerals in Figure 8 correspond to those used in Figure 5 for the same features, but are replaced by 100.

[0186] In the embodiment shown in Figure 5, the second contact layer 402 is continuous and has the same width as the adjacent first cladding layer 414. The second contact layer 402 has substantially the same cross-sectional area as the avalanche layer 406, and the cross-sectional area is perpendicular to the direction from the substrate 401 to the second contact layer 402. The p-type contact region 450 includes a local region of the second contact layer 402. That is, the p-type contact region 450 extends over a portion of the second contact layer 402 but not over its entirety. However, in the embodiment shown in Figure 8, the second contact layer 502 has an alternative configuration.

[0187] As shown in the embodiment of Figure 8, the second contact layer 502 does not have to be continuous. The p-type contact region 550 includes a local region of the second contact layer 502 in the embodiment of Figure 8, while the portion of the second contact layer 502 including the p-type contact region 550 is separated from the rest of the second contact layer 502.

[0188] The second contact layer 502 may include an outer first portion 590 extending along the periphery of the device 500. As described above, each layer within the device 500 may have a substantially circular cross-section, and the cross-section is oriented perpendicular to the direction from the substrate 501 to the second contact layer 502. Thus, the first portion 590 of the second contact layer 502 may be ring-shaped. However, the present invention is not limited to each layer of the device 500 having a substantially circular cross-section. Each layer may have any preferred cross-section. In certain embodiments, each layer may have a substantially rectangular or substantially square cross-section, and each corner of the rectangle or square may be rounded.

[0189] The second contact layer 502 includes an inner second portion 591. As shown in Figure 8, the second portion 502 is a p-type contact region 550. The second portion 591 can be separated from the first portion 590 of the second contact layer 502. During manufacturing, the first portion 590 and the second portion 591 can be separated from each other by etching. The second portion 591 of the second contact layer 502 does not have to be at the center of the device 500. However, the distance between the sidewall of the second portion 591 (i.e., the p-type contact region 550) and the sidewall 510 of the avalanche layer 506 in a direction perpendicular to the direction from the substrate 501 to the second contact layer 503 can be at least 7.5 μm. As shown in Figure 8, the electrode 505 can be formed on the second portion 591 of the second contact layer 502.

[0190] In the embodiment shown in Figure 8, the cross-sectional area of ​​the zinc diffusion area 551 may be larger than the cross-sectional area of ​​the p-type contact area 550, and the cross-sectional area is defined to be perpendicular to the direction from the substrate 501 to the second contact layer 502.

[0191] The SAMAPD device 500 shown in Figure 8 can be manufactured using the following method according to embodiments of the present invention.

[0192] The method includes providing a substrate 501 and forming a first contact layer 503 on the substrate 501. The method also includes laminating a plurality of layers on the substrate. The plurality of layers include an avalanche layer 506 and a second contact layer 502. The plurality of layers may also include one or more of a second cladding layer 531, a charge sheet 520, a second grading layer 521, a first grading layer 519, an absorption layer 517, at least one stopper layer 560, and a first cladding layer 514, as shown in Figure 9. The plurality of layers are arranged on the substrate such that the avalanche layer 506 is disposed between the first contact layer 503 and the second contact layer 502.

[0193] The method may include etching the second contact layer 502 to divide it into a first portion 590 and a second portion 591. The etching may expose a portion of the first cladding layer 514, as shown in Figure 10. Thus, the second contact layer 502 may no longer be continuous. This etching may be performed to help define the boundary of the zinc diffusion area 550 formed within the device 500. The second contact layer 502 may be etched in the final device 500 such that the distance between the edge of the zinc diffusion area 550 and the sidewall 510 of the avalanche layer 506 in a direction perpendicular to the direction from the substrate 501 to the second contact layer 503 within the device 500 is at least 7.5 μm. In embodiments in which the second contact layer 502 may contain InGaAs, the second contact layer may be etched using citric acid.

[0194] The method may then include applying a first mask 601 over the exposed portions of the second contact layer 502 and the first cladding layer 514. The first mask 601 may be dry-etched to expose a window 602 for zinc diffusion, as shown in Figure 11. Thus, zinc may diffuse into multiple layers in the area directly below the window. The window 602 may have a width of 15 μm to 500 μm, and this width is perpendicular to the direction from the substrate 501 to the second contact layer 502. The window 602 may begin between the first portion 590 and the second portion 591 of the second contact layer 502. Thus, the first portion 590 of the second contact layer 502 may be covered by the first mask 601 after the dry etching is complete. Therefore, the first mask 601 may suppress zinc diffusion into the first portion 590 of the second contact layer 502. In certain embodiments, the first mask may contain silicon nitride. The first mask 601 may be applied by plasma deposition.

[0195] The method may then include creating a p-type contact region 550 within the second contact layer by diffusing zinc into the second contact layer 502. The zinc concentration in the second portion 591 of the second contact layer 502 is at least 4.0 × 10⁻¹⁴. 18 cm -3 It can diffuse until it reaches a certain point. When creating the p-type contact region 550, zinc can also diffuse into the first cladding layer 514 and one stopper layer 560. The stopper layer can substantially prevent zinc from diffusing into the absorption layer 517. Figure 12 shows the zinc diffusion area 551 resulting from the diffusion step. The zinc diffusion area 551 includes a second portion 591 of the second contact layer 502 and extends into the first cladding layer 514 and at least one stopper layer 560. The zinc diffusion area 551 is formed below the window 602. To create the p-type contact region 550, the method may include only a single zinc diffusion step. That is, the p-type contact region 550 can be created by diffusing zinc into the second contact layer 502 only once.

[0196] After the zinc diffusion step, the electrode 505 may be formed on the second portion 591 of the second contact layer 502, as shown in Figure 13. The electrode may be formed by deposition.

[0197] The method may include etching the second portion 590 of the second contact layer 502 to further reduce the size of the second portion 590, as shown in Figure 13, thereby providing the final shape of the p-type contact region 550. In certain embodiments, the second portion 590 of the second contact layer 502 may be etched using citric acid. Thus, as shown in Figure 8, the final shape of the p-type contact layer 500 may have a smaller cross-sectional area than the avalanche layer 506, and the cross-sectional area is defined to be perpendicular to the direction from the substrate 501 to the second contact layer 503. This can reduce the attenuation of light entering the device, thereby increasing the amount of light absorbed by the absorbing layer.

[0198] This method may include etching multiple layers. Multiple layers can be etched from the first mask 601 on the second contact layer 502 to the interface between the first contact layer 503 and the second cladding layer 531. Thus, the device has a sidewall 603 extending from the interface between the first contact layer 503 and the second cladding layer 531 to the top of the device 500. A portion of the sidewall 603 of the device 500 defines the sidewall 510 of the avalanche layer 506. Multiple layers can be etched such that the distance between the sidewall 510 of the avalanche layer 506 and the p-type contact region 550 in a direction perpendicular to the direction from the substrate 501 to the second contact layer 502 is at least 7.5 μm. Multiple layers can be etched such that the distance between the sidewall 510 of the avalanche layer 506 and the edge of the p-type contact region is 30 μm or less. Multiple layers can be etched within the device 500 such that the distance between the edge of the zinc diffusion area 550 in the first cladding layer 514 (and optionally in at least one stopper layer 560) and the sidewall 610 of the avalanche layer 506 is at least 7.5 μm in a direction perpendicular to the direction from the substrate 501 to the second contact layer 503. Multiple layers can be etched such that the distance between the edge of the zinc diffusion area 550 in the first cladding layer 514 (and optionally in at least one stopper layer 560) and the sidewall 610 of the avalanche layer 506 is 30 μm or less.

[0199] Etching multiple layers exposes a portion of the first contact layer 503. Therefore, once the etching of multiple layers is complete, the electrode 505 can be formed on the exposed portion of the first contact layer 503, as shown in Figure 14. The electrode can be formed by deposition.

[0200] In certain embodiments, the method may further include etching the first contact layer 503 to expose the substrate on which the first contact layer is formed, as shown in Figure 15. The first contact layer 503 may be etched using acid etching.

[0201] The method may include forming a second mask 604 on one surface of the device 500. The second mask 604 may cover the first mask 601, the exposed portion of the first cladding layer 514, the p-type contact region 550, the electrode 505, one surface of the device sidewall 603, the exposed portion of the first contact layer 503, and the exposed portion of the substrate 501. The device 500 may then be etched to remove a portion of the second mask 604 to expose the electrode 505 and the p-type contact region 550, as shown in Figure 16. In certain embodiments, the second mask 604 may contain silicon nitride. A remote adhesive pad 605 may be formed on the device. The remote adhesive pad 605 may extend from the electrode 505 on the p-type contact region 550 along the sidewall 603 of the device 550, as shown in Figure 16, and may terminate above the portion of the substrate 501 where the first contact layer 503 has been etched. The remote adhesive pad 605 may contain the same material as the electrode 505. The remote adhesive pad 605 may improve the ease of providing electrical connections to the device. Therefore, in certain embodiments, the device 500 may comprise one or more silicon nitride deposits 601, 604 and the remote adhesive pad 605.

[0202] The method described above may be adapted to provide the device shown in Figure 5. For example, when providing the device of Figure 5, the steps of etching the second contact layer to provide separate first and second portions of the second contact layer, and etching the second portion of the second contact layer to reduce the size of the second portion, may be omitted. Thus, the device 400 may have a continuous second contact layer 402. The method may still include applying a mask 601 to the periphery of the second contact layer and etching the mask 601 to expose a window 602 for zinc diffusion.

[0203] It should be understood that various changes and modifications can be made to the present invention without departing from the scope of this application.

[0204] In a particular non-limiting embodiment shown in Figure 1, the first stage 107 may include an n-type contact layer 103, a first cladding layer 114, a gradient cladding layer 115, and the upper part 113b of the spacer layer 113, and the second stage 108 may include the lower part 113a of the spacer layer 113, an electric field control layer 116, an avalanche layer 106, a transition layer 118, an absorption layer 117, a third grading layer 122, and the upper part 102b of the p-type contact layer 102. However, the present invention is not limited to two stages or the arrangement of layers within each stage of the embodiment of Figure 1. In alternative embodiments, the multi-stage structure may include two, three, or more stages. In such embodiments, each stage may have a different cross-sectional area, defined as being perpendicular to the direction from the substrate 101 to the n-type contact layer 103. The cross-sectional area of ​​each stage may decrease in the direction from the substrate 101 to the n-type contact layer 103. The layers within device 100 can be distributed across three or more stages in any preferred manner, provided that the n-type contact layer 103 is in a different stage from the avalanche layer 106, and that the stage containing the n-type contact layer 103 has a smaller cross-sectional area than the stage containing the avalanche layer 106. Additionally, the device or APD subassembly is not limited to the specific layers or layer order described in relation to the embodiment of Figure 1. Similarly, the present invention is not limited to the arrangement of stages and layers within each stage as shown in the specific non-limiting embodiments shown in Figures 3 and 4. In alternative embodiments to those of Figures 3 and 4, the multi-stage structure may include two, three, or more stages. In such embodiments, each stage may have a different cross-sectional area, defined as being perpendicular to the direction from the substrate to the p-type contact layer. The cross-sectional area of ​​each stage may decrease in the direction from the substrate to the p-type contact layer. The layers within devices 200, 300 can be distributed across two or more stages in any preferred manner, provided that the p-type contact layer is in a different stage from the avalanche layer, and the stage containing the p-type contact layer has a smaller cross-sectional area than the stage containing the avalanche layer. Additionally, the device or APD subassembly is not limited to the specific layers or layer order described in relation to the embodiments of Figures 3 and 4.

[0205] As described above, in the embodiment shown in Figure 3, the spacer layer does not have to contain antimony. In an alternative embodiment, the spacer layer of device 200 shown in Figure 3 may contain antimony. The spacer layer may contain AlGaAsSb. In such embodiments, the device may be manufactured using dry etching to avoid oxidation of the antimony caused by wet etching. The spacer layer does not have to contain the first and second portions. Rather, the spacer layer may have a uniform cross-sectional area in a direction perpendicular to the direction from the substrate to the p-type contact layer. Thus, the transition from the first stage to the second stage may occur at the interface between the spacer layer and the charge sheet formed on the spacer layer. To manufacture a device having an antimony-containing spacer layer, a selective etching solution may be used to remove the p-type contact layer and the layer between the spacer layer and the p-type contact layer without etching the spacer layer. Thus, a uniform etch can be formed. Providing the spacer layer in this manner may allow the use of a thinner spacer layer compared to a spacer layer having an upper and lower portion. This can be advantageous when the device is intended for high-speed applications such as telecommunications.

[0206] As described above, in the embodiment shown in Figure 4, one or both of the first and second spacer layers may not contain antimony. In an alternative embodiment, the first and / or second spacer layers of the device 300 shown in Figure 4 may contain antimony. Each spacer layer may contain AlGaAsSb. In such embodiments, the device may be manufactured using dry etching to avoid oxidation of antimony caused by wet etching. The first and second spacer layers may not contain first and second portions. Rather, the first and second spacer layers may have a uniform cross-sectional area in a direction perpendicular to the direction from the substrate to the p-type contact layer. Thus, the transition between the second and third stages may occur at the interface between the first spacer layer and the charge sheet formed on the first spacer layer. The transition between the third and first stages may occur at the interface between the second spacer layer and the gradient cladding layer formed on the second spacer layer. As described above, to manufacture a device having an antimony-containing spacer layer, a selective etching solution may be used to remove the p-type contact layer and the layer between the spacer layer and the p-type contact layer without etching the spacer layer. Thus, a uniform etch can be formed. Providing the spacer layer in this manner may allow the use of a thinner spacer layer compared to a spacer layer having an upper and lower layer. This may be advantageous when the device is to be used in high-speed applications such as telecommunications.

[0207] In certain non-limiting embodiments shown in Figures 5 and 8, the device comprises a substrate having a first contact layer, a second cladding layer, an avalanche layer, a charge sheet, a second grading layer, a first grading layer, an absorption layer, at least one stopper layer, a first cladding layer, and a second contact layer, these layers being laminated on the substrate in this order. However, the device or APD subassembly is not limited to such an order or combination of layers. Rather, any preferred combination and order of layers may be used.

[0208] Throughout this description and claims, the terms “equipped with” and “including” and their variations mean “including, but not limited to,” and they are not intended to exclude (or do not exclude) other forms, additives, components, integers, or steps. Throughout this description and claims, the singular encompasses the plural, unless the context requires otherwise. In particular, where the indefinite article is used, this specification should be understood to intend both the singular and the plural, unless the context requires otherwise.

[0209] Features, integers, properties, compounds, chemical parts, or groups described in conjunction with specific aspects, embodiments, or examples of the present invention should be understood to be applicable to any other aspects, embodiments, or examples described herein, unless incompatible therewith. All features disclosed herein (including the appended claims, abstract, and drawings) and / or all methods or processes disclosed herein may be combined in any combination, except for combinations in which at least some of such features and / or steps are mutually exclusive. The present invention is not limited to the details of any of the aforementioned embodiments. The present invention extends to any novel features or any novel combination of features disclosed herein (including the appended claims, abstract, and drawings), or any novel steps or any novel combination of steps of any methods or processes disclosed herein.

[0210] The reader's attention is directed to all papers and documents filed in connection with this application, either together with or prior to this specification, which are made publicly available together with this specification, and the contents of all such papers and documents are incorporated herein by reference.

Claims

1. an avalanche photodiode (APD) subassembly, circuit board and A first contact layer formed on the substrate, The second contact layer, An avalanche layer comprising AlGaAsSb or InAlAsSb, wherein the avalanche layer is disposed between the first contact layer and the second contact layer, The first contact layer is an n-type contact layer, The second contact layer includes a p-type contact region formed by diffusing zinc, The APD subassembly has a p-type contact region having a smaller cross-sectional area than the avalanche layer, and the cross-sectional area is perpendicular to the direction from the substrate to the second contact layer.

2. The APD subassembly according to claim 1, wherein the distance between the sidewall of the avalanche layer and the edge of the p-type contact region in a direction perpendicular to the direction from the substrate to the second contact layer is at least 7.5 μm.

3. The APD subassembly according to claim 1 or 2, wherein the avalanche layer has a thickness of 100 nm to 1500 nm or 300 nm to 1000 nm.

4. The APD subassembly according to any one of claims 1 to 3, comprising a first cladding layer having a thickness of at least 1 μm, disposed between the avalanche layer and the second contact layer, wherein the second contact layer is formed within the cladding layer.

5. The APD subassembly according to claim 4, wherein the first cladding layer includes a zinc diffusion area, the zinc diffusion area having a smaller cross-sectional area than the avalanche layer, and the cross-sectional area is perpendicular to the direction from the substrate to the second contact layer.

6. The APD subassembly according to claim 5, wherein the distance between the sidewall of the avalanche layer and the edge of the zinc diffusion area in the first cladding layer in a direction perpendicular to the direction from the substrate to the second contact layer is at least 7.5 μm.

7. The APD subassembly according to claim 5 or 6, wherein the zinc diffusion area includes a local region of the first cladding layer.

8. The APD subassembly according to any one of claims 1 to 7, comprising an absorption layer disclosed between the avalanche layer and the second contact layer.

9. The APD subassembly according to claim 8, wherein the absorbing layer comprises InGaAs, GaAsSb, InGaAlAs, InGaAsP, or an InGaAs / GaAsSb type II superlattice.

10. The APD subassembly according to claim 8 or 9, further comprising at least one stopper layer disposed between the absorption layer and the second contact layer, wherein the at least one stopper layer has a lower zinc diffusion rate than the second contact layer.

11. The APD subassembly according to claim 10, wherein the at least one stopper layer comprises InGaAs or InGaAlAs, and / or the at least one stopper layer is intrinsic.

12. A transition section disposed between the avalanche layer and the absorption layer, comprising a first grading layer of InAlGaAs or InGaAsP, A charge sheet disposed between the first grading layer and the avalanche layer, the charge sheet having a band gap between the band gap of the absorption layer and the band gap of the avalanche layer An APD subassembly according to any one of claims 8 to 11, comprising:

13. The APD subassembly according to claim 12, wherein the charge sheet is p-doped and / or comprises InAlAs or InP.

14. The APD subassembly according to claim 12 or 13, comprising a second grading layer of InAlGaAs or InGaAsP disposed between the charge sheet and the avalanche layer.

15. The APD subassembly according to any one of claims 1 to 14, wherein the APD subassembly is a quasi-planar subassembly.

16. The APD subassembly according to any one of claims 1 to 15, wherein the p-type contact region includes a local region of the second contact layer.

17. The APD subassembly according to any one of claims 1 to 16, wherein the second contact layer comprises an outer first portion and an inner second portion, the first portion being separated from the second portion, and the second portion comprising the p-type contact region.

18. An APD device comprising an APD subassembly according to any one of claims 1 to 17, wherein the APD device optionally comprises electrodes formed on each of the p-type contact layer and the n-type contact layer.

19. A method for manufacturing an APD subassembly, To provide a substrate, The first contact layer is formed on the substrate, wherein the first contact layer is an n-type contact layer. A plurality of layers, each including an avalanche layer containing AlGaAsSb or InAlAsSb and a second contact layer, are laminated on the first contact layer such that the avalanche layer is disposed between the first contact layer and the second contact layer, and A p-type contact region is created within the second contact layer by diffusing zinc into the second contact layer. Includes, The method wherein the p-type contact region has a smaller cross-sectional area than the avalanche layer, and the cross-sectional area is perpendicular to the direction from the substrate to the second contact layer.

20. The method according to claim 19, wherein the preparation of the p-type contact region includes a single zinc diffusion.

21. Before fabricating the p-type contact region, the second contact layer is etched to divide it into an outer first portion and an inner second portion, and Applying a mask over the first portion of the second contact layer to suppress zinc diffusion into the first portion. The method according to claim 19 or 20, including the method described in claim 19 or 20.

22. The method according to claim 21, wherein producing the p-type contact region includes etching the second portion of the second contact layer after zinc diffusion to provide the p-type contact region.

23. The method according to any one of claims 19 to 22, comprising etching the plurality of layers such that the distance between the sidewall of the avalanche layer and the edge of the p-type contact region in a direction perpendicular to the direction from the substrate to the second contact layer is at least 7.5 μm.

24. The plurality of layers include a first cladding layer disposed between the avalanche layer and the second contact layer. The method according to any one of claims 19 to 23, wherein the creation of the p-type contact region is to create a zinc diffusion area within the first cladding layer.

25. The method according to claim 14, as dependent on claim 23, wherein etching of the plurality of layers is such that the distance between the sidewall of the avalanche layer and the edge of the zinc diffusion area in the first cladding layer in a direction perpendicular to the direction from the substrate to the second contact layer is at least 7.5 μm.

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