Reducing voids in FINFET structures

Abstract

A method for forming transistors, such as FinFETs, is described. A conformal liner layer is formed within the trench. Metal nitride material is introduced at regular or semi-regular intervals during metal gap filling of the trench structure to prevent the formation of voids (gaps) within the structure. The metal nitride material and metal gap filling material can be deposited by atomic layer deposition.

Description

Technical Field

[0001]

[0001] Embodiments of the present disclosure relate to the field of semiconductor devices and semiconductor device manufacturing. More specifically, embodiments of the present disclosure relate to a method for reducing voids during a gap filling process.

Background Art

[0002]

[0002] Integrated circuits have evolved into complex devices that can incorporate millions of transistors, capacitors, and resistors on a single chip. In the process of the evolution of integrated circuits, the functional density (i.e., the number of interconnected devices per chip area) has generally increased while the feature size (i.e., the smallest component (or line) that can be fabricated using a manufacturing process) has decreased.

[0003]

[0003] Transistors are an important component of most integrated circuits. Since the drive current, and thus the speed, of a transistor is proportional to the gate width of the transistor, faster transistors generally require a larger gate width. Therefore, there is a trade-off between the size and speed of a transistor, and "fin" field effect transistors (FinFETs) have been developed to address the conflicting goals of transistors with the maximum drive current and the minimum size. FinFETs are characterized by a fin-shaped channel region that significantly increases the size of the transistor without significantly increasing the installation area of the transistor, and are currently applied to many integrated circuits. However, FinFETs have their own drawbacks.

[0004]

[0004] As the characteristic size of transistor devices continues to shrink in order to increase circuit density and improve performance, it is necessary to improve transistor device structures and reduce contact resistance. Examples of transistor device structures include planar structures, fin field-effect transistor (FinFET) structures, and gate-all-around (GAA) structures. Logic gate performance is related to the properties of the materials used, as well as the thickness and area of ​​the structural layers. However, challenges arise when some gate characteristics are adjusted to accommodate device scaling.

[0005]

[0005] As the semiconductor manufacturing industry moves to more advanced modes below the 2nm node, it is desirable to improve device speed and drive current by reducing trench variability. Therefore, improved methods for forming semiconductor devices such as FinFETs are needed. [Overview of the Initiative]

[0006]

[0006] One or more embodiments of the present disclosure relate to a method for forming a transistor. In one or more embodiments, the method includes performing a processing cycle which includes depositing a liner layer on a substrate having a plurality of features thereon, depositing a metal gap filler material on the liner layer, and depositing a metal material on the metal gap filler material.

[0007]

[0007] Other embodiments of the present disclosure relate to methods for forming a FinFET. In one or more embodiments, the method includes performing a processing cycle that includes exposing a substrate having at least one feature to a first titanium precursor and nitrogen-containing reactant to form a titanium nitride silicon liner, and exposing the substrate to a first molybdenum precursor and reactant to form a bulk molybdenum film, and alternately exposing the substrate to a second titanium precursor and nitrogen-containing reactant to form titanium nitride (TiN) within the bulk molybdenum film.

[0008]

[0008] To allow for a more detailed understanding of the above-described features of the Disclosure, a more detailed description of the Disclosure, which has been briefly summarized above, can be obtained by referring to embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings merely illustrate typical embodiments of the Disclosure and should not be considered to limit the scope of the Disclosure, as the Disclosure may also permit other equally valid embodiments. [Brief explanation of the drawing]

[0009] [Figure 1] A process flow diagram of one or more embodiments of the method is shown. [Figure 2] A cross-sectional view of a device according to one or more embodiments is shown. [Figure 3] A cross-sectional view of a device according to one or more embodiments is shown. [Figure 4] A cross-sectional view of a device according to one or more embodiments is shown. [Figure 5] A cross-sectional view of a device according to one or more embodiments is shown. [Figure 6] A cross-sectional view of a device according to one or more embodiments is shown. [Modes for carrying out the invention]

[0010]

[0015] Before describing some exemplary embodiments of this disclosure, it should be understood that this disclosure is not limited to the configuration or process step details described below. Other embodiments of this disclosure are possible and can be implemented or performed in various ways.

[0011]

[0016] As used herein and in the appended claims, the term “substrate” refers to a surface or portion of a surface on which a process is performed. Those skilled in the art will also understand that when a substrate is referred to, it may refer only to a portion of the substrate unless otherwise explicitly stated in the context. Furthermore, when a deposition on a substrate is referred to, it may mean both a bare substrate and a substrate on which one or more films or features are deposited or formed.

[0012]

[0017] As used herein, “substrate” refers to any substrate or material surface formed on a substrate on which a film treatment is performed during the manufacturing process. For example, substrate surfaces on which treatment can be performed include, depending on the application, materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials. Substrates include, but are not limited to, semiconductor wafers. Substrates can be exposed to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, electron beam cure, and / or bake the substrate surface. In addition to film treatment directly on the surface of the substrate itself, any of the film treatment steps disclosed herein may be performed on an underlying layer formed on the substrate, as disclosed in more detail below, and the term “substrate surface” is intended to include such underlying layers as indicated in the context.

[0013]

[0018] In one or more embodiments, the use of the term “on” in relation to a film or layer of film includes the presence of the film or layer directly on a surface (e.g., the substrate surface) and the presence of one or more underlying layers between the film or layer and the surface (e.g., the substrate surface). Thus, in one or more embodiments, the expression “on the substrate surface” is intended to include one or more underlying layers. In other embodiments, the expression “directly on” refers to a layer or film that is in contact with a surface (e.g., the substrate surface) but has no intervening layer. Thus, the expression “a layer directly on the substrate surface” refers to a layer that is in direct contact with the substrate surface and has no intervening layer.

[0014]

[0019] As used herein and in the appended claims, terms such as “precursor,” “reactant,” and “reactive gas” are used interchangeably to refer to any gas species that can react with the substrate surface.

[0015]

[0020] As used herein, “atomic layer deposition” or “periodic deposition” refers to the sequential exposure of two or more reactive compounds to deposit a layer of material on a substrate surface. The substrate or a portion of the substrate is exposed separately to two or more reactive compounds introduced into the reaction zone of a processing chamber. In a time-domain ALD process, exposure to each reactive compound is separated by a time delay, so that each compound adheres to and / or reacts on the substrate surface and is then purged from the processing chamber. These reactive compounds are said to be continuously exposed to the substrate. In a spatial ALD process, various portions of the substrate surface, or material on the substrate surface, are exposed simultaneously to two or more reactive compounds such that no given point on the substrate is substantially exposed to multiple reactive compounds at the same time. As used herein and in the appended claims, the term “substantially” as used in this regard means, as understood by those skilled in the art, that a small portion of the substrate may be simultaneously exposed to multiple reactive gases due to diffusion, but such simultaneous exposure is not intended.

[0016]

[0021] In one embodiment of time-domain ALD processing, a first reactive gas (i.e., a first precursor or compound A, e.g., an aluminum precursor) is pulsed into the reaction zone, followed by a first time delay. Next, a second precursor or compound B (e.g., an oxidizing agent) is pulsed into the reaction zone, followed by a second delay. At each time delay, a purge gas (e.g., argon) is introduced into the processing chamber to purge the reaction zone or to remove any residual reactive compounds or reaction byproducts from the reaction zone. Alternatively, the purge gas may flow continuously throughout the entire deposition process so that only the purge gas flows during the time delays between pulses of the reactive compounds. The reactive compounds are pulsed alternately until a desired film or thickness is formed on the substrate surface. In either case, one ALD process consists of pulsed supply of compound A, purge gas, compound B, and purge gas. A cycle can begin with either compound A or compound B, and each stage of the cycle may continue until a film of a predetermined thickness is achieved.

[0017]

[0022] In an embodiment of the spatial ALD process, a first reactive gas and a second reactive gas (e.g., nitrogen gas) are supplied simultaneously to the reaction zone but separated by an inert gas curtain and / or a vacuum curtain. By moving the substrate relative to the gas supply device, any given point on the substrate is exposed to the first and second reactive gases.

[0018]

[0023] As used herein, “chemical vapor deposition” refers to a process in which a substrate surface is exposed to precursors and / or co-reagents simultaneously or substantially simultaneously. As used herein, “substantially simultaneously” means either co-flow or when there is a majority overlap in the exposure of the precursors.

[0019]

[0024] As used throughout this specification, “substantially simultaneously” means that the majority of the duration of exposure to the first reactive compound overlaps with the exposure to the second reactive compound.

[0020]

[0025] As used herein, the term "purge" includes any suitable purge process for removing unreacted precursors, reaction products, and by-products from the processing region. Suitable purge processes include moving the substrate through a gas curtain to a portion or zone of the processing region that contains no or substantially no reactants. In one or more embodiments, purging the processing chamber includes applying a reduced pressure. In some embodiments, purging the processing chamber includes flowing a purge gas over the substrate. In some embodiments, the purge process includes flowing an inert gas. In one or more embodiments, the purge gas is selected from one or more of nitrogen (N2), helium (He), and argon (Ar). In some embodiments, the purge of the substrate surface or reaction chamber can occur for a duration in the range of 0.2 seconds to 30 seconds, 0.2 seconds to 10 seconds, 0.2 seconds to 5 seconds, 0.5 seconds to 30 seconds, 0.5 seconds to 10 seconds, 0.5 seconds to 5 seconds, 1 second to 30 seconds, 1 second to 10 seconds, 1 second to 5 seconds, 5 seconds to 30 seconds, 5 seconds to 10 seconds, or 10 seconds to 30 seconds.

[0021]

[0026] A transistor is a circuit component or circuit element that is often formed on a semiconductor device. Depending on the circuit design, in addition to capacitors, inductors, resistors, diodes, conductive lines, or other elements, transistors are formed on the semiconductor device. Typically, a transistor includes a gate formed between a source region and a drain region. In one or more embodiments, the source region and the drain region may include doped substrate regions and may exhibit a doping profile suitable for a particular application. The gate is positioned over the channel region and includes a gate dielectric interposed between the gate electrode of the substrate and the channel region.

[0022]

[0027] As used herein, the terms "field effect transistor" or "FET" refer to a transistor that uses an electric field to control the electrical behavior of a device. Enhancement-mode field effect transistors generally exhibit very high input impedance at low temperatures. The conductivity between the drain and source terminals is controlled by an electric field within the device generated by a voltage difference between the body of the device and the gate. The three terminals of a FET are the source (S) through which carriers enter the channel, the drain (D) through which carriers exit the channel, and the gate (G) which is the terminal that adjusts the conductivity of the channel. Conventionally, the current entering the channel at the source (S) has been called IS and the current entering the channel at the drain (D) has been called ID. The voltage between the drain and source is called VDS. By applying a voltage to the gate (G), the current entering the channel at the drain (i.e., ID) can be controlled.

[0023]

[0028] A metal-oxide-semiconductor field-effect transistor (MOSFET) is a type of field-effect transistor (FET). It has an insulated gate, and the voltage of the insulated gate determines the conductivity of the device. This ability to vary conductivity according to the amount of voltage applied is used to amplify or switch an electronic signal. The MOSFET is based on the modulation of charge concentration by the metal-oxide-semiconductor (MOS) capacitance between the body electrode and the gate electrode located on the body and insulated from all other device regions by a gate dielectric layer. Compared to a MOS capacitor, a MOSFET includes two additional terminals (source and drain), each connected to an individual highly doped region separated by the body region. These regions can be either p-type or n-type, but both are of the same type and of the opposite type to the body region. The source and drain are (unlike the body) highly doped and are suffixed with a "+" symbol after the type of doping.

[0024]

[0029] When a MOSFET is an n-channel or nMOSFET, the source and drain are in the n+ region, and the body is in the p region. When a MOSFET is a p-channel type, i.e., a pMOSFET, the source and drain are in the p+ region, and the body is in the n region. The source is so named because it is the source of charge carriers (electrons in n-channels, holes in p-channels) flowing through the channel, and similarly, the drain is so named because it is where the charge carriers leave the channel.

[0025]

[0030] As used herein, the term "Fin-field-effect transistor (FinFET)" refers to a MOSFET transistor built on a substrate in which the gate is located on two or three sides of the channel, forming a double-gate or triple-gate structure. FinFET devices are given the general name FinFET because the channel region forms "fins" on the substrate. FinFET devices have fast switching times and high current density.

[0026]

[0031] As used herein, the term “Dynamic Random Access Memory” or “DRAM” refers to a memory cell that stores data bits by storing packets of charge (i.e., binary 1) or uncharged (i.e., binary 0) in a capacitor. Charge is transferred via capacitor vias through an access transistor, and this charge is sensed by turning on the same transistor and observing the voltage perturbation caused by dumping the charge packets onto the interconnection lines of the transistor output. Thus, a single DRAM cell consists of one transistor and one capacitor. A DRAM device is formed by an array of DRAM cells. Rows on the access transistors are linked by word lines, and the inputs and outputs of the transistors are linked by bit lines. Historically, DRAM capacitors have evolved from planar polycrystalline silicon-oxide-substrate plate capacitors to three-dimensional structures, which have branched into “stacked” capacitors where both plates are on top of the substrate, and “trench” capacitors that use a cavity etched into the substrate as a shared plate.

[0027]

[0032] Current transistor processes, such as the DRAM embedded word line (bWL) process, involve a liner and a metal (e.g., tungsten (W)) stack. However, due to poor adhesion between the metal and the trench structure, voids and delamination of the metal filling are often observed during high-temperature post-annealing ring processing. Furthermore, during subsequent metal etching, voids can cause variations between trenches. Such voids and delamination are undesirable as they cause electrical contact and device yield losses. Voids and delamination also contribute to increased stacking resistance. Therefore, embodiments of this disclosure relate to improving gap-filling performance to favorably reduce void formation while maintaining a high metal percentage within the trenches. This should provide lower resistance than previous approaches. In one or more embodiments, fewer processing steps are required.

[0028]

[0033] The choice of metal used as the gate electrode can significantly impact device performance. While not intended to be theoretically bound, the use of low-resistance metals is considered advantageous, as it provides a transistor structure with reduced resistance. However, when exposed to the heat treatment requirements used in transistor manufacturing, these materials often delaminate from their surfaces. Delamination can affect the final array resistance and lead to reliability issues.

[0029]

[0034] Current approaches to filling semiconductor structures, when using molybdenum (Mo), cannot have low void filling. Void formation increases resistance, and poor electrical contact leads to device yield losses. During metal etch-back, voids cause variations between trenches. One or more embodiments of this disclosure relate to methods for forming semiconductor devices. Some embodiments of this disclosure incorporate thin titanium nitride (TiN) films introduced at regular or semi-regular intervals during molybdenum filling of a FinFET structure to prevent void formation within the structure. In some embodiments, cycles of alternately depositing void-filling material onto thin metallic material films can be repeated so that multiple thin layers of metallic material are deposited and stacked within the void-filling material.

[0030]

[0035] One or more embodiments reduce void formation while maintaining a high metal percentage within the trench of a semiconductor device. In one or more embodiments, this provides lower resistance than previous approaches.

[0031]

[0036] Further embodiments of the present disclosure relate to memory transistors (e.g., DRAMs) having thin titanium nitride (TiN) films introduced at regular or semi-regular intervals during molybdenum filling.

[0032]

[0037] Embodiments of the present disclosure are illustrated by drawings showing processes and substrates according to one or more embodiments of the present disclosure. The illustrated processes, schemes, and resulting substrates are illustrative of the disclosed processes, and those skilled in the art will recognize that the disclosed processes are not limited to the illustrated applications.

[0033]

[0038] Figure 1 shows a process flow diagram of a method according to one or more embodiments of the present disclosure. Figures 2-5 show cross-sectional views of a device being processed by the method of Figure 1.

[0034]

[0039] Referring to Figure 1, one or more embodiments of this disclosure relate to a method 10 for depositing a film. The method shown in Figure 1 represents an atomic layer deposition (ALD) process in which a substrate or substrate surface is sequentially exposed to a reactive gas in a manner that prevents or minimizes the gas-phase reaction of the reactive gas. In some embodiments, the method includes a chemical vapor deposition (CVD) process in which the reactive gas is mixed in a processing chamber to enable the gas-phase reaction of the reactive gas and the deposition of a thin film.

[0035]

[0040] In one or more embodiments, step 12 of Method 10 includes forming a conformal liner layer. The liner layer may be formed by any suitable means, including but not limited to ALD and CVD. In step 14, the Method includes cycles to form a metal nitride film and bulk metal gap filler. In one or more embodiments, the metal nitride film (step 16) is introduced at regular or semi-regular intervals during the metal gap filler of the trench structure (step 18) to prevent the formation of voids within the structure. At decision point 20, the thickness of the deposited film or the number of cycles of the metal nitride film and bulk metal gap filler is taken into consideration. If the deposited film has reached a predetermined thickness or a predetermined number of processing cycles have been performed, Method 10 proceeds to step 22, where the substrate is optionally annealed.

[0036]

[0041] Referring to Figure 2, a substrate 102 having a plurality of trenches 104 is provided. As used herein and in the appended claims, the term “provided” means that the substrate is made available for processing (e.g., placed in a processing chamber). The trenches 104 form recessed channels. In one or more embodiments, the trenches have a bottom 106 and at least one side wall 108. The plurality of trenches 104 may be formed to have a width in the range of about 10 to about 100 nm (including, but not limited to, the ranges of about 10 nm to about 80 nm, about 10 nm to about 70 nm, about 10 nm to about 60 nm, about 10 nm to about 50 nm, or about 10 nm to about 40 nm). As will be recognized by those skilled in the art, the width of the plurality of trenches 104 is defined by the distance W1 from one side wall 108 to another side wall 108.

[0037]

[0042] Multiple trenches 104 may be formed to have depths in the range of approximately 120 nm to approximately 250 nm. This depth is not limited to the ranges of approximately 120 nm to approximately 150 nm, approximately 150 nm to approximately 200 nm, approximately 200 nm to approximately 250 nm, or approximately 120 nm to approximately 200 nm. As will be recognized by those skilled in the art, the depth of the multiple trenches 104 is defined by the distance D1 from the substrate surface 103 to the bottom 106 of the multiple trenches 104.

[0038]

[0043] To form multiple trenches 104, a buffer insulating layer (e.g., a silicon oxide layer, not shown) may be formed on the substrate surface 103, and / or a hard mask layer (e.g., a nitride layer, not shown). Such techniques are well known to those skilled in the art and are therefore not shown.

[0039]

[0044] Referring to Figures 1 and 3, in step 12, the liner layer 110 is deposited conformally on the substrate 102, on the substrate surface 103, and along the side walls 108 and bottom 106 of the multiple trenches 104. As used herein, the term “conformal” means that the liner layer 110 conforms to the feature or the contour of the feature. The conformality of a layer is typically quantified by the ratio of the average thickness of the layer deposited on the side walls of the feature to the average thickness of the same deposited layer on the field (or top surface) of the substrate.

[0040]

[0045] The liner layer 110 may contain any suitable material. In one or more embodiments, the liner layer 110 contains one or more of titanium nitride (TiN), tantalum nitride (Ta), and titanium silicon nitride (TiSiN). In a particular embodiment, the liner layer contains titanium silicon nitride (TiSiN).

[0041]

[0046] The liner layer 110 can be formed by any suitable means. In one or more embodiments, the liner layer 110 is formed by atomic layer deposition (ALD). Thus, in one or more embodiments, the liner layer 110 can be formed by immersing a substrate in a solution of a metal precursor, such as a titanium precursor. In some embodiments, the metal precursor may include titanium chloride (TiCl4), titanium fluoride (TiF4), titanium iodide (TiI4), titanium bromide (TiBr4), or tantalum bromide (TaBr4), which may include titanium halides selected from one or more of tantalum chloride (TaCl4), tantalum fluoride (TaF4), and tantalum iodide (TaI4). In some embodiments, the substrate can be immersed in the metal precursor for a time ranging from above 0 seconds to 60 seconds. In some embodiments, the substrate can be immersed in the metal precursor at a pressure ranging from 3 Torr to 50 Torr and a temperature ranging from 300°C to 600°C or 400°C to 550°C.

[0042]

[0047] The substrate surface or processing chamber may optionally be purged from the metal precursor. When used in this way, the term “processing chamber” includes portions of the processing chamber adjacent to the substrate surface, without encompassing the entire internal space of the processing chamber. For example, in a spatially separated sector of the processing chamber, the portion of the processing chamber adjacent to the substrate surface is purged of the molybdenum precursor by any suitable technique, including but not limited to moving the substrate through a gas curtain into a portion or sector of the processing chamber that contains no or substantially no molybdenum precursor. In one or more embodiments, purging the processing chamber includes applying reduced pressure. In some embodiments, purging the processing chamber includes flowing a purge gas over the substrate. In some embodiments, a portion of the processing chamber refers to a minute volume or small volume processing station within the processing chamber. The term “adjacent” when referring to the substrate surface means the physical space adjacent to the substrate surface that can provide sufficient space for a surface reaction (e.g., precursor adsorption) to occur. In one or more embodiments, the purge gas is selected from one or more of nitrogen (N2), helium (He), and argon (Ar).

[0043]

[0048] In one or more embodiments, the substrate can then be exposed to the reactants to form a liner layer 110 on the substrate, which can then be conformally deposited on a plurality of features 104. The substrate surface or the processing chamber may be optionally purged from the reactants.

[0044]

[0049] In one or more embodiments, the liner layer 110 has a thickness in the range of about 1 Å to about 20 Å, or in the range of 1 Å to 15 Å, or in the range of about 1 Å to 10 Å, and includes about 1 Å, about 2 Å, about 3 Å, about 4 Å, about 5 Å, about 6 Å, about 7 Å, about 8, about 9 Å, about 10 Å, about 11 Å, about 12 Å, about 13 Å, about 14 Å, about 15 Å, about 16 Å, about 17 Å, about 18 Å, about 19 Å, and about 20 Å.

[0045]

[0050] Referring to Figures 1, 4, and 5, in one or more embodiments, in the deposition 14, the metal gap-filling material 114 and the metal material 112 are introduced at regular or semi-regular intervals during gap-filling of the transistor structure (e.g., FinFET structure) to prevent the formation of voids within the multiple features 104 of the structure 100. The metal material 112 may be in the form of a thin layer. In one or more embodiments, the thin layer of metal material 112 may be conformal.

[0046]

[0051] In some embodiments, the regular or semi-regular spacing in the gap filling of the transistor structure can provide a cycle of alternating deposition of metal gap-filling material 114 and thin layers of metal material 112. In one or more embodiments, the cycle can be repeated so that multiple thin layers of metal material 112 are deposited and stacked within the metal gap-filling material 114.

[0047]

[0052] In one or more embodiments, introducing metallic material 112 at regular or semi-regular intervals during gap filling with metallic gap-filling material 114 is called the nanolaminate approach. The nanolaminate approach in one or more embodiments allows for the advantageous use of a liner layer 110, for example, TiSiN, and provides advantages in interfacial trap density (Dit) and flat-band voltage (VFB). Furthermore, although not intended to be bound by theory, the nanolaminate approach in one or more embodiments is thought to offer resistivity advantages because the gap-filling material 114 has a high proportion of material in the structure.

[0048]

[0053] In one or more embodiments, the metallic material 112 includes any suitable metallic material or metallic nitride material known to those skilled in the art. In one or more embodiments, the metallic material 112 includes one or more of the following: cobalt (Co), titanium (Ti), tungsten (W), tantalum (Ta), molybdenum (Mo), titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), molybdenum nitride (MoN), TaN / TiN, or WN / TiN. In one or more embodiments, the metallic material 112 is selected from the group consisting of titanium (Ti), tungsten (W), tantalum nitride (WN), tantalum nitride (TaN), molybdenum nitride (MoN), TaN / TiN, WN / TiN, and combinations thereof. In one or more embodiments, the metallic material 112 includes titanium nitride.

[0049]

[0054] The metallic material 112 can be deposited by any suitable means. In one or more embodiments, the metallic material 112 is deposited by atomic layer deposition (ALD). In one or more embodiments, a substrate is exposed to a metal precursor and then to reactants to form the metallic material 112. The substrate may be exposed to the metal precursor and reactants sequentially or simultaneously.

[0050]

[0055] In one or more embodiments, the metallic material 112 has a thickness ranging from about >0 Å to about 15 Å, including about 1 Å, about 2 Å, about 3 Å, about 4 Å, about 5 Å, about 6 Å, about 7 Å, about 8 Å, about 9 Å, about 10 Å, about 11 Å, about 12 Å, about 13 Å, about 14 Å, and about 15 Å.

[0051]

[0056] Referring to Figures 1, 4, and 5, in step 16, the metal gap-filling material 114 is deposited in a plurality of trenches 104 on the liner layer 110 at regular or semi-regular intervals with the metal material 112. The metal gap-filling material 114 and the metal material 112 may be deposited simultaneously or alternately. In one or more embodiments, the metal gap-filling material 114 is formed by depositing the bulk gap-filling using atomic layer deposition (ALD).

[0052]

[0057] In one or more embodiments, the metal gap filler material 114 may include any suitable metal known to those skilled in the art. In one or more embodiments, the metal gap filler material 114 includes one or more of molybdenum (Mo), tungsten (W), and cobalt (Co), and in certain embodiments, the metal gap filler material 114 includes molybdenum (Mo).

[0053]

[0058] In one or more embodiments, the metal gap-filling material 114 in step 18 may include any suitable gap-filling process known to those skilled in the art. In some embodiments, the gap-filling process includes exposing the substrate to a metal precursor and reactants. In one or more embodiments, the gap-filling process includes exposing the substrate to a molybdenum precursor (e.g., molybdenum dichloride dioxide (MoO2Cl2)) and reactants (e.g., hydrogen (H2)) to form a bulk molybdenum film.

[0054]

[0059] The molybdenum precursor can be any suitable molybdenum-containing compound. In one or more embodiments, the molybdenum precursor includes one or more of the following: molybdenum chloride (MoCl5), molybdenum fluoride (MoF6), molybdenum iodide (MoI6), molybdenum bromide (MoBr3), hexacarbonyl (Mo(CO)6), molybdenum dichloride (MoO2Cl2), oxy tetrachloride (MoOCl4), tetrakis(dimethylamino)molybdenum(IV), and bis(tert-butyllimide)-bis(dimethylamide)molybdenum. In some embodiments, the substrate (or substrate surface) is exposed to the molybdenum precursor at a pressure in the range of 10 Torr to 50 Torr and a temperature in the range of 400°C to 550°C.

[0055]

[0060] In some embodiments, the gap-filling process in step 18 may be a bottom-up gap-filling process. In other embodiments, the gap-filling process may be a conventional gap-filling process.

[0056]

[0061] In some embodiments, the thickness T1 of the metal gap filler material 114 is controlled. In some embodiments, the thickness T1 of the metal gap filler material 114 is controlled relative to the depth D1 of the multiple trenches 104. In some embodiments, the thickness T1 is about 90% or more of the depth D1 of the multiple trenches 104. Referring to Figures 4 and 5, in some embodiments, the thickness T1 of the metal gap filler material 114 exceeds the depth D1 of the trenches 104, and overfilling of the metal gap filler material 114 can be formed on the substrate.

[0057]

[0062] While not intended to be theoretically binding, alternating deposition of metallic material 112 and metallic void-filling material 114 by the methods of one or more embodiments is considered to advantageously result in no delamination of the metallic void-filling material 114 during annealing, substantially no void formation, and in particular, substantially no void formation at the interface between the liner layer 110 and the metallic void-filling material 14. In some embodiments, the metallic void-filling material 114 contains small particles of metallic material 112, reducing the proportion of voids present in the metallic void-filling material 114. In addition, interrupting the void-filling process of the metallic void-filling material 114 with regular or semi-regular deposition of metallic material 112 is considered to reduce the particle size of the metal in the metallic void-filling material 114, and thus contribute to a reduction in voids. When used in this manner, a material that is substantially free of seams or voids has voids, seams, or voids occupying less than 2%, less than 1%, or less than 0.5% of the volume of the described material.

[0058]

[0063] Referring to Figure 1, at the decision point 20, the thickness of the deposited film or the number of cycles of the metal material 112 and the metal gap filler material 114 is taken into consideration. If the deposited film reaches a predetermined thickness or a predetermined number of processing cycles have been performed, method 10 moves to the annealing step 22. If the thickness of the deposited film or the number of processing cycles has not reached a predetermined threshold, method 10 returns to the deposition 14 forming the metal material 112 and the metal gap filler material 114 and continues.

[0059]

[0064] In one or more embodiments, the substrate is annealed in step 22 after the gap-filling process. Annealing may include any suitable annealing process known to those skilled in the art. In one or more embodiments, annealing is carried out at a temperature in the range of 600°C to 1200°C in one or more atmospheres of argon (Ar), nitrogen (N2), or hydrogen (H2) gas. In some embodiments, annealing may be carried out in one or more steps.

[0060]

[0065] Referring to Figures 1 and 6, in step 24, in one or more embodiments, the metal gap filler material 114 is recessed (embedded) by chemical mechanical polishing (CMP) and etch-back, so that the metal gap filler material 114 and the metal material 112 do not protrude beyond the substrate surface 103 (for example, the metal layer 114 is completely embedded in the substrate 102).

[0061]

[0066] In one or more embodiments, an embedded word line 115 (i.e., a recessed metal gap-filling material 114) may be formed. In some embodiments, as shown in Figure 6, the metal material 112 is recessed to the same level as the embedded word line 115. The upper surface 117 of the embedded word line 115 and the metal material 112 is the recess depth or distance D2 from the substrate surface 103 within a plurality of trenches 104. After the formation of the word line 115, the substrate processing can continue to form a FinFET, for example, a memory device. Such processes are known to those skilled in the art.

[0062]

[0067] Spatially relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” may be used here to describe the relationship between one element or feature shown in the drawing and another, for the sake of clarity. It will be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation shown in the drawing. For example, if the device in the drawing is upside down, an element described as being “below” or “directly below” another element or feature will be oriented “above” the other element or feature. Thus, the exemplary term “below” may encompass both up and down orientations. The device may be oriented in ways other than those described (it may be rotated 90 degrees or rotated to other orientations), and the spatially relative descriptions used herein shall be interpreted accordingly.

[0063]

[0068] In the context of describing the materials and methods discussed herein (in particular in the context of the following claims), the use of “a” and “an,” “the,” and similar references should be interpreted as encompassing both singular and plural, unless otherwise indicated herein or unless the context clearly contradicts this interpretation. Enumerations of numerical ranges herein are intended merely as abbreviations to refer individually to each distinct value falling within that range, unless otherwise indicated herein, and each distinct value is incorporated into the specification as if it were individually enumerated herein. All methods described herein may be performed in any appropriate order, unless otherwise indicated herein or unless the context clearly contradicts this interpretation. Any and all examples or exemplary language provided herein (e.g., “such as”) is intended merely to better describe the materials and methods and does not limit their scope unless otherwise requested. No language herein should be interpreted as indicating an element that is not claimed as essential to the implementation of the disclosed materials and methods.

[0064]

[0069] Throughout this specification, any reference to “one embodiment,” “a particular embodiment,” “one or more embodiments,” or “embodiment” means that a particular feature, structure, material, or property described in relation to an embodiment is included in at least one embodiment of this disclosure. Therefore, the appearance of phrases such as “in one or more embodiments,” “a particular embodiment,” “in one embodiment,” or “in an embodiment” in various places throughout this specification does not necessarily refer to the same embodiment of this disclosure. In one or more embodiments, a particular feature, structure, material, or property may be combined in any suitable manner.

[0065]

[0070] Although the disclosures herein have been described with reference to specific embodiments, these embodiments should be understood as merely illustrative examples of the principles and uses of the disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the methods and apparatus of the disclosure without departing from the spirit and scope of the disclosure. Accordingly, the disclosure is intended to include modifications and variations that fall within the scope of the appended claims and their equivalents.

Claims

1. A method for forming a transistor, Depositing a liner layer on a substrate containing multiple features, The process involves performing a processing cycle that includes depositing a metal gap-filling material on the liner layer and depositing a metal material on the metal gap-filling material. A method that includes this.

2. The method according to claim 1, wherein the liner layer comprises one or more of titanium nitride (TiN), tantalum nitride (Ta), and titanium silicon nitride (TiSiN).

3. The method according to claim 2, wherein the liner layer comprises titanium silicon nitride (TiSiN).

4. The method according to claim 1, wherein the liner layer has a thickness in the range of about 1 Å to about 20 Å.

5. The method according to claim 1, wherein the metal gap-filling material comprises one or more of molybdenum (Mo), tungsten (W), and cobalt (Co).

6. The method according to claim 5, wherein the metal gap filling material contains molybdenum (Mo).

7. The method according to claim 1, wherein the metallic material comprises one or more of the following: cobalt (Co), titanium (Ti), tungsten (W), tantalum (Ta), molybdenum (Mo), titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), molybdenum nitride (MoN), TaN / TiN, or WN / TiN.

8. The method according to claim 7, wherein the metal material includes titanium nitride (TiN).

9. The method according to claim 1, wherein the metal material has a thickness in the range of about >0 Å to about 15 Å.

10. The method according to claim 1, wherein depositing the metal gap-filling material includes exposing the substrate to a first metal precursor and a first reactant.

11. The deposition of the aforementioned metal gap-filling material is performed on the substrate, which contains a molybdenum precursor and hydrogen (H ２ The method according to claim 10, comprising exposing the plurality of features to a bulk molybdenum film.

12. The method according to claim 1, wherein depositing the metal material includes exposing the substrate to a second metal precursor and reactants.

13. The method according to claim 1, further comprising repeating the processing cycle to form a metal gap-filling material having a thickness of 90% or more of the depth of the plurality of features.

14. The method according to claim 1, further comprising annealing the substrate, wherein there is substantially no delamination of the metal gap filler material and the metal gap filler material is substantially void-free.

15. The method according to claim 14, further comprising recessing a portion of the metal gap filling material and the metal material in order to form an embedded word line.

16. The method according to claim 1, wherein the metal material includes a thin film within the metal gap-filling material.

17. The method according to claim 16, further comprising repeating the processing cycle to form a plurality of layers of the metal material within the metal gap filling material.

18. A method for forming a FinFET, A substrate having at least one feature is exposed to a first titanium precursor and a nitrogen-containing reactant to form a titanium nitride silicon liner, The process cycle includes exposing the substrate to a first molybdenum precursor and reactant to form a bulk molybdenum film, and alternately exposing the substrate to a second titanium precursor and nitrogen-containing reactant to form a titanium nitride (TiN) layer within the bulk molybdenum film. A method that includes this.

19. The method according to claim 18, wherein the bulk molybdenum film and the titanium nitride (TiN) layer are formed sequentially.

20. The method according to claim 18, wherein the bulk molybdenum film and the titanium nitride (TiN) layer are formed simultaneously.

Images