In-situ etching and inhibition in plasma-enhanced atomic layer deposition

Abstract

Exemplary semiconductor processing methods may include methods for non-conformally depositing silicon-oxygen-containing materials. In this method, the top of a feature is preferentially filled at a slower rate than the bottom of the feature. Such methods may include iterative non-conformal etching steps and / or iterative non-conformal inhibition steps. For example, after depositing a layer containing silicon-oxygen-containing material, the layer may be non-conformally etched before depositing another layer containing silicon-oxygen-containing material. In another example, during layer deposition, an inhibitor may be preferentially introduced to the top of the feature and its vicinity to provide non-conformal deposition of the silicon-oxygen-containing material.

Description

Technical Field

[0001] Cross - Reference to Related Applications

[0001] This application claims the benefit and priority of U.S. Non - Provisional Application No. 18 / 209,711, filed on June 14, 2023, entitled "IN - SITU ETCH AND INHIBITION IN PLASMA ENHANCED ATOMIC LAYER DEPOSITION", the content of which is hereby incorporated by reference in its entirety for all purposes.

[0002]

[0002] This technology relates to methods and components for semiconductor processing. More specifically, this technology relates to systems and methods for depositing silicon - containing materials with reduced void or seam formation.

Background Art

[0003]

[0003] Integrated circuits are enabled by a process that creates a complexly patterned layer of material on a substrate surface. To fabricate the patterned material on the substrate, a controlled method for forming and removing the material is required. As device miniaturization progresses, the features within the integrated circuit become smaller, and the aspect ratio of the structures can increase, making it difficult to maintain the dimensions of these structures during the processing steps. Depending on the process, voids or seams can occur in the material, which can cause undesirable or unwanted effects in further processing. Developing materials with controllable void or seam formation can become more difficult as device miniaturization progresses.

[0004]

[0004] Therefore, there is a need for improved systems and methods that can be used in the manufacture of high - quality devices and structures. This technology addresses these and other needs.

Summary of the Invention

[0005]

[0005] An exemplary method of semiconductor processing may include a method for nonconformally depositing a silicon-oxygen-containing material to fill features on a substrate. The method may include iteratively repeating a deposition cycle on a substrate placed in a processing area of ​​a semiconductor processing chamber to deposit a silicon-oxygen-containing material of about 100 Å to about 1000 Å on one or more features. The substrate may define one or more features along the substrate. Each feature has a top, a bottom, and side walls connecting the top and bottom. The silicon-containing precursor may be deposited within one or more features. The deposition cycle may include purging the processing area after depositing the silicon-containing material on the substrate. The deposition cycle may further include exposing the silicon-containing material to an oxygen plasma to convert the silicon-containing material into a silicon-oxygen-containing material, and then purging the processing area. After iteratively repeating the deposition cycle, the method may include exposing the silicon-oxygen-containing material to an etching agent to non-conformally remove a portion of the silicon-oxygen-containing material. Non-conformal removal may occur to a greater extent at the top of a feature compared to the bottom of the feature. The deposition cycle and subsequent exposure to an etching agent may be iteratively repeated to fill one or more features with silicon-oxygen-containing material. In some embodiments, non-conformal removal removes approximately 10 Å to approximately 100 Å of silicon-oxygen-containing material from the top of the feature.

[0006]

[0006] In some embodiments, the sidewalls of one or more features may be tapered sidewalls. In some embodiments, after each exposure to the etchant, the angle of the sidewall of the silicon-oxygen-containing material may increase compared to the previous exposure to the etchant. The increase in angle may be about 5° or more. The etchant may include the products of a plasma generated using a halogen-containing precursor. The halogen-containing precursor may include one or more of nitrogen trifluoride (NF3), hydrogen bromide (HBr), fluoromethane (CH3F), difluoromethane (CH2F2), trifluoromethane (CHF3), carbon tetrafluoride (CF4), and boron trichloride (BCl3). The distance between the substrate and the position where the etchant enters the processing area may be about 4 mm to about 50 mm. The plasma may have a plasma output of about 500 W or less. The exposure time to the plasma may be about 60 seconds or less.

[0007]

[0007] Some embodiments of the present technology may encompass a semiconductor processing method. The method may include supplying a nitrogen-containing inhibitor to a processing area of ​​a semiconductor processing chamber. A substrate may be placed within the processing area of ​​the semiconductor processing chamber. The substrate may define one or more features along the substrate. Each of the one or more features has a top, a bottom, and a side wall connecting the top and bottom. The method may further include absorbing the nitrogen-containing inhibitor more at the top of one or more features than at the bottom of one or more features. The method may further include depositing a silicon-containing material on the substrate. The method may further include exposing the silicon-containing material to an oxygen plasma in order to convert the silicon-containing material into a silicon-oxygen-containing material. The above steps may be repeated iteratively to fill one or more features with the silicon-oxygen-containing material.

[0008]

[0008] In some embodiments, the nitrogen-containing inhibitor is a product of the plasma of the nitrogen-containing precursor. The nitrogen-containing precursor may include ammonia, nitrogen, or a combination thereof. The gas used to generate the plasma may contain 5 mol% to 75 mol% of the nitrogen-containing precursor. The distance between the substrate and the position where the nitrogen-containing inhibitor enters the processing area may be about 4 mm to about 50 mm. The plasma output may be about 500 W or less. The exposure time to the plasma may be about 60 seconds or less.

[0009]

[0009] Some embodiments of the present technology may encompass a semiconductor processing method. The method may include supplying a nitrogen-containing inhibitor to a processing area of ​​a semiconductor processing chamber. A substrate may be placed within the processing area of ​​the semiconductor processing chamber. The substrate may define one or more features along the substrate. Each of the one or more features has a top, a bottom, and a side wall connecting the top and bottom. The method may further include adsorbing the nitrogen-containing inhibitor more at the top of one or more features than at the bottom of one or more features. The method may further include depositing a silicon-containing material on the substrate after such absorption. The method may further include exposing the silicon-containing material to an oxygen plasma to convert the silicon-containing material into a silicon-oxygen-containing material. The method may further include iteratively repeating the above steps to deposit a silicon-oxygen-containing material of about 50 Å to about 500 Å on one or more features on the substrate. Subsequently, after the repeated deposition of silicon-oxygen-containing material, the method may include exposing the silicon-oxygen-containing material to an etching agent to remove approximately 10 Å to approximately 100 Å of the silicon-oxygen-containing material. The cycle of depositing silicon-oxygen-containing material and then removing it using an etching agent may be repeated iteratively to fill one or more features with silicon-oxygen-containing material.

[0010]

[0010] In some embodiments, the etching agent may include products of the plasma generated using a halogen-containing precursor. The nitrogen-containing inhibitor may be a product of the plasma of a nitrogen-containing precursor.

[0011]

[0011] Such technologies can offer many advantages over conventional systems and techniques. For example, embodiments of the technology can reduce void or seam sizes applicable to a large number of substrate features. Furthermore, the technology can produce silicon-containing films intended not only for gap-filling applications but also for other applications where a deposited film characterized by reduced void or seam size is advantageous. Along with these numerous advantages and features, these embodiments and other embodiments will be described in more detail below with reference to the accompanying drawings.

[0012]

[0012] Further understanding of the nature and advantages of the technology of this disclosure can be obtained by referring to the remainder of this specification and the drawings. [Brief explanation of the drawing]

[0013] [Figure 1]

[0013] A schematic cross-sectional view of an exemplary plasma system according to several embodiments of the present technology is shown. [Figure 2]

[0014] The process steps in a semiconductor processing method according to several embodiments of this technology are shown. [Figure 3A]

[0015] The following shows an exemplary schematic cross-sectional structure in which a material layer is contained and manufactured according to several embodiments of this technology. [Figure 3B] The following shows an exemplary schematic cross-sectional structure in which a material layer is contained and manufactured according to several embodiments of this technology. [Figure 3C] The following shows an exemplary schematic cross-sectional structure in which a material layer is contained and manufactured according to several embodiments of this technology. [Figure 3D] The following shows an exemplary schematic cross-sectional structure in which a material layer is contained and manufactured according to several embodiments of this technology. [Figure 3E] The following shows an exemplary schematic cross-sectional structure in which a material layer is contained and manufactured according to several embodiments of this technology. [Figure 3F]An exemplary schematic cross-sectional structure in which a material layer is included and manufactured according to some embodiments of the present technology is shown. [Figure 3G] An exemplary schematic cross-sectional structure in which a material layer is included and manufactured according to some embodiments of the present technology is shown. [Figure 3H] An exemplary schematic cross-sectional structure in which a material layer is included and manufactured according to some embodiments of the present technology is shown. [Figure 4]

[0016] Steps in a semiconductor processing method according to some embodiments of the technology are shown. [Figure 5A]

[0017] An exemplary schematic cross-sectional structure in which a material layer is included and manufactured according to some embodiments of the present technology is shown. [Figure 5B] An exemplary schematic cross-sectional structure in which a material layer is included and manufactured according to some embodiments of the present technology is shown. [Figure 5C] An exemplary schematic cross-sectional structure in which a material layer is included and manufactured according to some embodiments of the present technology is shown. [Figure 5D] An exemplary schematic cross-sectional structure in which a material layer is included and manufactured according to some embodiments of the present technology is shown. [Figure 5E] An exemplary schematic cross-sectional structure in which a material layer is included and manufactured according to some embodiments of the present technology is shown. [Figure 5F] An exemplary schematic cross-sectional structure in which a material layer is included and manufactured according to some embodiments of the present technology is shown. [Figure 5G] [[ID=三十二]]An exemplary schematic cross-sectional structure in which a material layer is included and manufactured according to some embodiments of the present technology is shown. [Figure 5H] An exemplary schematic cross-sectional structure in which a material layer is included and manufactured according to some embodiments of the present technology is shown.

Mode for Carrying Out the Invention

[0014]

[0018] Some of the drawings are included as schematic diagrams. It should be understood that the figures are for illustrative purposes and should not be considered to be to scale unless expressly stated to be so. Further, as schematic diagrams, the drawings are provided to aid understanding and may not include all aspects or information compared to a realistic depiction, and may include material emphasized for illustrative purposes.

[0015]

[0019] In the accompanying drawings, similar components and / or features may have the same reference numerals. Further, various components of the same type can be distinguished according to the reference numerals by letters that distinguish between similar components. Where only a first reference numeral is used in this specification, the description is applicable to any of the similar components having the same first reference numeral, regardless of the letter.

[0016]

[0020] As the size of the device continues to shrink, the thickness and size of many material layers can be reduced to adjust the device. As features across the semiconductor structure are reduced, the aspect ratio of the features can increase. As the aspect ratio of the features increases, pinch-off can occur near the top of the feature before the feature is completely filled, so voids or seams may occur in the feature in a chemical vapor deposition process.

[0017]

[0021] Conventional techniques, such as gate-all-around (GAA) and processes related to 3D NAND, have struggled to produce films that fill high-aspect-ratio features in underlying structures where void or seam formation is controlled. Depositing silicon-containing materials into underlying structures containing high-aspect-ratio trenches can be incomplete because many silicon-containing film depositions produce conformal films. The filling process can result in voids in the filler near the top of a feature or seams in the center of the feature before the feature is filled. These seams can extend into the upper part of the structure. In some manufacturing processes, subsequent polishing can expose voids or seams, allowing access to the feature. This can lead to oxidation of the material when exposed to the atmosphere, or the infiltration of slurry or other materials along the voids or seams. Therefore, many conventional techniques have limited ability to prevent structural defects in the final device.

[0018]

[0022] This technology overcomes these problems by incorporating in-situ etching and / or inhibition steps into the plasma-enhanced atomic layer deposition method. These additional steps enable non-conformal deposition of silicon-oxygen-containing materials, allowing the top of the feature to be filled preferentially at a slower rate compared to the bottom. This suppresses pinch-off near the top of the feature before the feature is completely filled.

[0019]

[0023] By filling features or high aspect ratio structures with silicon-oxygen-containing material from which voids or seams have been reduced or removed, this technique can prevent problems in subsequent integration processes and / or defects in the final device. The remainder of the disclosure routinely identifies specific deposition processes that utilize the disclosed technique and describes one type of semiconductor processing chamber, but it will be readily apparent that the processes described can be carried out in any number of semiconductor processing chambers. Therefore, this technique should not be considered to be limited to use in only these specific deposition processes or chambers. Before describing the method of semiconductor processing by this technique, this disclosure will describe one possible chamber that may be used to carry out the process according to embodiments of this technique.

[0020]

[0024] Figure 1 shows a cross-sectional view of an exemplary semiconductor processing chamber 100 according to several embodiments of the present technology. The figure may illustrate an overview of a system that incorporates one or more aspects of the present technology and / or can be specifically configured to perform one or more steps according to embodiments of the present technology. Additional details of the chamber 100 or the method performed may be described further below. While the chamber 100 may be used to form a film layer according to several embodiments of the present technology, it should be understood that the method can be similarly performed in any chamber in which film formation may be performed. The semiconductor processing chamber 100 may include a chamber body 102, a substrate support 104 disposed inside the chamber body 102, and a lid assembly 106 coupled to the chamber body 102 and sealing the substrate support 104 in the processing space 120. A substrate 103 is supplied to the processing space 120 through an opening 126, which can be conventionally sealed for processing using a slit valve or door. The substrate 103 can be placed on the surface 105 of the substrate support 104 during processing. The substrate support 104 may be rotatable along an axis 147 in which the shaft 144 of the substrate support 104 may be located, as indicated by the arrow 145. Alternatively, the substrate support 104 may be lifted and rotated as needed during the deposition process.

[0021]

[0025] The plasma profile modulator 111 may be located within the semiconductor processing chamber 100 to control the plasma distribution across the substrate 103 placed on the substrate support 104. The plasma profile modulator 111 may include a first electrode 108. This first electrode 108 is located adjacent to the chamber body 102, which can isolate the chamber body 102 from other components of the lid assembly 106. The first electrode 108 may be part of the lid assembly 106 or a separate sidewall electrode. The first electrode 108 may be an annular or ring-shaped member or a ring electrode. The first electrode 108 may be a continuous loop around the outer periphery of the semiconductor processing chamber 100 surrounding the processing space 120, or may be discontinuous at selected locations if desired. The first electrode 108 may also be a perforated electrode, such as a perforated ring or mesh electrode, or a planar electrode, such as a secondary gas distributor.

[0022]

[0026] One or more isolators 110a, 110b, which may be dielectric materials such as ceramics or metal oxides (e.g., aluminum oxide and / or aluminum nitride), may be in contact with the first electrode 108 to electrically and thermally isolate the first electrode 108 from the gas distributor 112 and the chamber body 102. The gas distributor 112 may define openings 118 for distributing process precursors into the processing space 120. The gas distributor 112 may be connected to a first power supply 142, which may be an RF generator, an RF power supply, a DC power supply, a pulsed DC power supply, a pulsed RF power supply, or any other power supply that can be connected to the semiconductor processing chamber 100. In some embodiments, the first power supply 142 may be an RF power supply.

[0023]

[0027] The gas distributor 112 may be a conductive or non-conductive gas distributor. Furthermore, the gas distributor 112 may also be formed from conductive and non-conductive components. For example, the body of the gas distributor 112 may be conductive, while the faceplate of the gas distributor 112 is non-conductive. The gas distributor 112 may be powered by a first power supply 142, such as shown in Figure 1, or in some embodiments, the gas distributor 112 may be connected to earth.

[0024]

[0028] The first electrode 108 may be coupled to a first tuning circuit 128 that can control the ground path of the semiconductor processing chamber 100. The first tuning circuit 128 may include a first electronic sensor 130 and a first electronic controller 134. The first electronic controller 134 may be a variable capacitor or other circuit element, or may include such elements. The first tuning circuit 128 may be one or more inductors 132, or may include such elements. The first tuning circuit 128 may be any circuit that enables a variable or controllable impedance under plasma conditions present in the processing space 120 during processing. In some embodiments as illustrated, the first tuning circuit 128 may include a first circuit leg and a second circuit leg connected in parallel between ground and the first electronic sensor 130. The first circuit leg may include a first inductor 132a. The second circuit leg may include a second inductor 132b connected in series with the first electronic controller 134. A second inductor 132b may be positioned between the first electronic controller 134 and a node connecting both the first and second circuit legs to the first electronic sensor 130. The first electronic sensor 130 is a voltage or current sensor and is connected to the first electronic controller 134, thereby providing some degree of closed-loop control over the plasma conditions inside the processing space 120.

[0025]

[0029] The second electrode 122 may be connected to the substrate support 104. The second electrode 122 may be embedded within the substrate support 104 or connected to the surface 105 of the substrate support 104. The second electrode 122 may be a plate, a perforated plate, a mesh, a wire screen, or any other distributed configuration of conductive elements. The second electrode 122 is a tuning electrode and may be connected to a second tuning circuit 136 by a conduit 146 (e.g., a cable with a selected resistance, such as 50 ohms, located within the shaft 144 of the substrate support 104). The second tuning circuit 136 may have a second electronic sensor 138 and a second electronic controller 140 (which may be a second variable capacitor). The second electronic sensor 138 is a voltage or current sensor and may be connected to the second electronic controller 140 to provide further control over plasma conditions in the processing space 120.

[0026]

[0030] A third electrode 124 (which may be a bias electrode and / or an electrostatic chuck electrode) may be connected to the substrate support 104. The third electrode may be connected to a second power supply 150 through a filter 148 (which may be an impedance matching circuit). The second power supply 150 may be a DC power supply, a pulsed DC power supply, an RF bias power supply, a pulsed RF source or bias power supply, or a combination of these or other power supplies. In some embodiments, the second power supply 150 may be an RF bias power supply. The substrate support 104 may also include one or more heating elements configured to heat the substrate to a processing temperature which may be between about 25°C and about 800°C or higher.

[0027]

[0031] The lid assembly 106 and substrate support 104 in Figure 1 can be used with any processing chamber for plasma processing or heat processing. During operation, the semiconductor processing chamber 100 can control the plasma conditions in the processing space 120 in real time. The substrate 103 is placed on the substrate support 104, and process gas can flow through the lid assembly 106 using the inlet 114 according to any desired flow plan. The gas can be discharged from the semiconductor processing chamber 100 through the outlet 152. Power can be coupled to the gas distributor 112 to form plasma in the processing space 120. In some embodiments, the substrate can be electrically biased using a third electrode 124.

[0028]

[0032] When the plasma in the processing space 120 is excited, a potential difference can be established between the plasma and the first electrode 108. A potential difference can also be established between the plasma and the second electrode 122. Electronic controllers 134, 140 can then be used to adjust the flow characteristics of the ground path, which are represented by two tuning circuits 128, 136. Setpoints can be provided for the first tuning circuit 128 and the second tuning circuit 136 to provide separate control over the deposition rate and the uniformity of plasma density from the center to the edge. In embodiments where both electronic controllers are variable capacitors, electronic sensors can separately adjust the variable capacitors to maximize the deposition rate and minimize thickness non-uniformity.

[0029]

[0033] Each of the tuning circuits 128 and 136 may have a variable impedance that can be adjusted using their respective electronic controllers 134 and 140. If the electronic controllers 134 and 140 are variable capacitors, the capacitance range of each variable capacitor and the inductances of the first inductor 132A and the second inductor 132B may be selected to provide an impedance range. This range depends on the frequency and voltage characteristics of the plasma and may have a minimum value within the capacitance range of each variable capacitor. Thus, when the capacitance of the first electronic controller 134 is at its minimum or maximum, the impedance of the first tuning circuit 128 becomes high, which may result in a plasma shape with minimal air or lateral coverage over the substrate support 104. As the capacitance of the first electronic controller 134 approaches the value that minimizes the impedance of the first tuning circuit 128, the air coverage of the plasma grows to its maximum, effectively covering the entire working area of ​​the substrate support 104. If the capacitance of the first electronic controller 134 deviates from the minimum impedance setting, the plasma shape may contract away from the chamber wall, and the air coverage of the substrate support 104 may decrease. The second electronic controller 140 has a similar effect, and since the capacitance of the second electronic controller 140 can be changed, the air coverage of the plasma on the substrate support 104 can be increased or decreased.

[0030]

[0034] Electronic sensors 130 and 138 may be used to tune their respective circuits 128 and 136 in a closed loop. Depending on the type of sensor used, a current or voltage setpoint may be set for each sensor, and control software may be provided to the sensors to determine the adjustments to their respective electronic controllers 134 and 140 to minimize deviations from the setpoint. Thus, the plasma shape can be selected and dynamically controlled during processing. Although the above considerations are based on electronic controllers 134 and 140 (which may be variable capacitors), it will be understood that any electronic component with adjustable characteristics may be used to provide tuning circuits 128 and 136 with adjustable impedance.

[0031]

[0035] Figure 2 shows exemplary steps in processing method 200 according to several embodiments of the present technology. Method 200 may be performed in various processing chambers, including the semiconductor processing chamber 100 described above. Method 200 may include one or more operations, including front-end processing, deposition, etching, polishing, cleaning, or any other operations that may be performed before the operations described, prior to the commencement of Method 200. Method 200 may include a number of optional steps, which may or may not be particularly relevant to some embodiments of the method according to embodiments of the present technology. For example, many of the steps are described to provide a broader range of processes to be performed, but are not critical to the present technology or may be performed by alternative methods, which will be discussed further below. Method 200 may describe the steps schematically shown in Figures 3A–3H. These illustrations will be described in conjunction with the steps of Method 200. It should be understood that only partial schematic diagrams are shown in the figures, and the substrate may include any number of additional materials and features having various properties and characteristics as shown in the figures.

[0032]

[0036] Method 200 may or may not include optional steps for developing the semiconductor structure into a specific manufacturing process. It should be understood that Method 200 can be performed on any number of semiconductor structures or substrates 305, including exemplary structures 300 on which one or more silicon-containing materials may be formed. As shown in Figure 3A, the substrate 305 may be processed to form one or more concave features 315, such as trenches, openings, or any other structures in the semiconductor process. The substrate 305 may be any number of materials, including a base wafer or substrate 305 made from silicon or a silicon-containing material, other substrate 305 materials, and one or more materials that may be layered and formed on top of the substrate 305 during the semiconductor process. For example, in some embodiments, the substrate 305 may be processed to include one or more materials or structures for semiconductor processing. The substrate 305 may be or include dielectric materials, such as oxides or nitrides of any number of materials. In embodiments, one or more material layers 310 may be deposited on the substrate 305. In the embodiment, one or more material layers 310 may be or may contain a silicon-containing material. The silicon-containing material may be amorphous silicon, doped silicon, silicon oxide, silicon nitride, silicon carbide, or silicon.

[0033]

[0037] As illustrated, one or more features 315 may be defined by one or more material layers 310 and / or substrate 305, such as trenches, openings, or other recessed features. Feature 315 may include a top 320, a bottom 325, and a side wall 330 connecting the top 320 and the bottom 325.

[0034]

[0038] The illustrated feature 315 features vertical sidewalls, but feature 315 may alternatively feature tapered sidewalls. In embodiments of tapered sidewalls, the feature may feature a larger diameter or width at the top of the feature than at the bottom of the feature. The aspect ratio of the feature, i.e., the ratio of the depth of the feature to the width or diameter of the feature being formed, is about 1:1 or greater and may be about 2:1 or greater, about 3:1 or greater, about 4:1 or greater, about 5:1 or greater, about 6:1 or greater, about 7:1 or greater, about 8:1 or greater, about 9:1 or greater, about 10:1 or greater, or greater.

[0035]

[0039] Although only one feature 315 is shown in the figure, it should be understood that the exemplary structure may have any number of features 315 defined in accordance with the structure according to the embodiment of this technology.

[0036]

[0040] Method 200 includes a deposition cycle 205 which comprises a series of steps that are repeated x times iteratively to deposit a layer 335a containing silicon-oxygen material, as shown in Figure 3B. In embodiments, x may be about 3 or more, about 5 or more, about 10 or more, about 20 or more, about 30 or more, about 40 or more, about 50 or more, about 250 or less, about 225 or less, about 200 or less, about 175 or less, about 150 or less, about 3 to about 250, about 10 to about 250, about 50 to about 250, about 3 to about 200, about 3 to about 150, about 10 to about 200, about 10 to about 150, or about 50 to about 200 or more.

[0037]

[0041] After repeating the series of steps in the deposition cycle 205 x times, method 200 includes step 215 of exposing layer 335a containing silicon-oxygen material to an etching agent that removes at least a portion of the silicon-oxygen material from layer 335a. The etching in step 215 may selectively remove the silicon-oxygen material from layer 335a to a greater extent at the top 320 and / or sidewalls 330 of feature 315 compared to the bottom 325 of feature 315. Thus, as shown in Figure 3C, the resulting etched layer 335b (containing silicon-oxygen material) may have tapered sidewalls 340a within feature 315.

[0038]

[0042] Following step 215, the deposition cycle 205 is repeated 220 times to increase the thickness of the silicon-oxygen-containing material, as shown in Figure 3D, to produce a layer 335c with tapered sidewalls 340b within the feature 315. Another step 215 is then performed to preferentially etch layer 335c at the top 320 and / or sidewalls 330 of the feature 315 compared to the bottom 325 of the feature 315. As a result, the resulting etched layer 335d (containing the silicon-oxygen-containing material) produces a layer 335d with tapered sidewalls 340c. The deposition cycle 205 and subsequent steps 215 are repeated again to produce (a) a layer 335e containing the silicon-oxygen-containing material with tapered sidewalls 340d after the deposition cycle 205, and (b) an etched layer 335f containing the silicon-oxygen-containing material with tapered sidewalls 340e after step 215. The deposition cycle 205 and subsequent steps 215 are carried out iteratively y times by repeats 220, filling one or more features 315 with silicon-oxygen-containing material 335 g, as shown in Figure 3H. In embodiments, y may be about 2 or more, about 3 or more, about 4 or more, about 5 or more, about 10 or more, about 15 or more, about 50 or less, about 40 or less, about 30 or less, about 20 or less, about 10 or less, about 2 to about 50, about 2 to about 30, about 3 to about 50, about 3 to about 30, about 3 to about 10, about 5 to about 25, about 10 to about 40, or about 15 to about 50 or more.

[0039]

[0043] The illustrated deposition cycle 205 comprises four steps. The first step 225 involves depositing a silicon-containing material onto a substrate. This can be achieved by supplying a silicon-containing precursor to a processing area in a semiconductor processing chamber. Prior to the start of Method 200, a silicon-containing precursor may be supplied to the same processing area in the semiconductor processing chamber to perform the processing. The silicon-containing precursor that can be used in Method 200 may be any number of silicon-containing precursors or may comprise any number of silicon-containing precursors. For example, the silicon-containing precursor may be or comprise silane (SiH4), disilane (Si2H6), silicon tetrachloride (SiCl4), tetraethyl orthosilicate (TEOS), diisopropylaminosilane (DIPAS), bis(diethylamino)silane (BDEAS), bis(t-butylamino)silane (BTBAS), or any other precursor that can form, for example, silicon oxide (SiO), silicon nitride (SiN), or silicon carbide (SiC) materials. In some embodiments, along with the silicon-containing precursor, one or more additional precursors may be supplied, such as one or more carrier gases or inert gases, including argon or helium, in addition to the hydrogen-containing precursor.

[0040]

[0044] The silicon-containing precursor is deposited on the substrate as a silicon-containing material. It should be noted that "deposited on the substrate" includes deposition on features, layers (e.g., layers of silicon-oxygen-containing material or high-density layers of silicon-oxygen-containing material) that already exist on the substrate. That is, the silicon-containing material, if exposed, may extend along any and / or all exposed surfaces along the substrate, and also along any other incorporated material (e.g., previously formed silicon-oxygen-containing material or high-density silicon-oxygen-containing material). During step 225, deposition of the silicon-containing material may occur, if present, from, for example, the sidewalls defining the feature toward the interior of the feature.

[0041]

[0045] The deposition of the silicon-containing material onto the substrate in step 225 can be carried out as a non-plasma process. By performing step 225 without plasma, the deposition of the silicon-containing material can be highly conformal. In embodiments, the deposition of the silicon-containing material may be characterized by conformality of about 80% or more, about 85% or more, about 90% or more, about 95% or more, about 97% or more, about 99% or more, or about 100%.

[0042]

[0046] Step 225 may be performed for approximately 5 seconds or less, approximately 4 seconds or less, approximately 3 seconds or less, approximately 2 seconds or less, approximately 1 second or less, approximately 0.5 seconds or less, approximately 0.1 seconds to approximately 5 seconds, approximately 0.1 seconds to approximately 0.5 seconds, approximately 0.25 seconds to approximately 1 second, approximately 0.25 seconds to approximately 1.5 seconds, approximately 1 second to approximately 3 seconds, or approximately 2 seconds to approximately 5 seconds.

[0043]

[0047] After step 225, step 230 may be performed to purge the processing area to remove excess silicon-containing precursor. Purging can be achieved by reducing the pressure in the semiconductor processing chamber or by flowing a gas (e.g., an inert gas such as argon or nitrogen) through the semiconductor processing chamber.

[0044]

[0048] Step 230 can be performed for approximately 5 seconds or less, approximately 4 seconds or less, approximately 3 seconds or less, approximately 2 seconds or less, approximately 1 second or less, approximately 0.5 seconds or less, approximately 0.1 seconds to approximately 5 seconds, approximately 0.1 seconds to approximately 0.5 seconds, approximately 0.25 seconds to approximately 1 second, approximately 0.25 seconds to approximately 1.5 seconds, approximately 1 second to approximately 3 seconds, or approximately 2 seconds to approximately 5 seconds.

[0045]

[0049] Following step 230, method 200 may include step 235, in which the silicon-containing material is exposed to an oxygen plasma to convert the silicon-containing material into a silicon-oxygen-containing material. The plasma may be formed from an oxygen-containing precursor. The oxygen-containing precursor that can be used in method 200 may be any number of oxygen-containing precursors or may include these. For example, the oxygen-containing precursor may be nitrous oxide (N2O), water (H2O), diatomic oxygen (O2), ozone (O3), a combination of one or more of these, or any other oxygen-containing substance or may include these. An inert gas such as argon may also be present.

[0046]

[0050] The plasma output in process 235 may be approximately 2500 watts (W) or less, approximately 2000 W or less, approximately 1750 W or less, approximately 1500 W or less, approximately 1250 W or less, approximately 1000 W or less, approximately 1 W to approximately 2500 W, approximately 1 W to approximately 500 W, approximately 100 W to approximately 2500 W, approximately 100 W to approximately 1000 W, approximately 500 W to approximately 2500 W, or approximately 1000 W to approximately 2500 W.

[0047]

[0051] The exposure time (or the length of time for which step 235 is performed) may be approximately 5 seconds or less, approximately 4 seconds or less, approximately 3 seconds or less, approximately 2 seconds or less, approximately 1 second or less, approximately 0.5 seconds or less, approximately 0.1 seconds to approximately 5 seconds, approximately 0.1 seconds to approximately 0.5 seconds, approximately 0.25 seconds to approximately 1 second, approximately 0.25 seconds to approximately 1.5 seconds, approximately 1 second to approximately 3 seconds, or approximately 2 seconds to approximately 5 seconds.

[0048]

[0052] In some embodiments, the oxygen-containing precursor may include either or both N2O and O2.

[0049]

[0053] After step 235, step 240 may be performed to purge the processing area to remove residues from the oxygen plasma and by-products from the conversion of silicon-containing material to silicon-oxygen-containing material. Purging can be achieved by reducing the pressure in the semiconductor processing chamber or by flowing a gas (e.g., an inert gas such as argon or nitrogen) through the semiconductor processing chamber.

[0050]

[0054] Step 240 can be performed for approximately 5 seconds or less, approximately 4 seconds or less, approximately 3 seconds or less, approximately 2 seconds or less, approximately 1 second or less, approximately 0.5 seconds or less, approximately 0.1 seconds to approximately 5 seconds, approximately 0.1 seconds to approximately 0.5 seconds, approximately 0.25 seconds to approximately 1 second, approximately 0.25 seconds to approximately 1.5 seconds, approximately 1 second to approximately 3 seconds, or approximately 2 seconds to approximately 5 seconds.

[0051]

[0055] The illustrated sedimentation cycle 205 illustrates four steps 225, 230, 235, and 240, but the sedimentation cycle may include other steps, or may not include one or more of the illustrated steps 225, 230, 235, and 240.

[0052]

[0056] Each deposition cycle 205 (e.g., four iterative processes 225, 230, 235, 240, in which 210 is repeated) can be characterized by the amount of silicon-oxygen-containing material deposited. This amount may be approximately 50 Å or more, approximately 75 Å or more, approximately 100 Å or more, approximately 150 Å or more, approximately 200 Å or more, approximately 50 Å to approximately 100 Å, approximately 50 Å to approximately 200 Å, approximately 100 Å to approximately 500 Å, or approximately 250 Å to approximately 500 Å. The amount of deposited silicon-oxygen-containing material can be measured at the top of the feature.

[0053]

[0057] Following the deposition cycle 205, the method includes a step 215 for selectively etching the deposited layer containing silicon-oxygen material. Etching can be achieved by exposing the silicon-oxygen material to an etchant. The etchant may include plasma products generated using halogen-containing precursors. Examples of halogen-containing precursors include nitrogen trifluoride (NF3), hydrogen bromide (HBr), and hydrofluorocarbon (CH3). x F y This may include, but is not limited to, fluoromethane (CH3F), difluoromethane (CH2F2), trifluoromethane (CHF3), carbon tetrafluoride (CF4), boron trichloride (BCl3), and any combination thereof.

[0054]

[0058] The halogen-containing precursor can be present in concentrations of approximately 5 mol% or more, approximately 10 mol% or more, approximately 25 mol% or more, approximately 50 mol% or more, approximately 75 mol% or more, approximately 5 mol% to approximately 90 mol%, approximately 5 mol% to approximately 75 mol%, approximately 5 mol% to approximately 50 mol%, or approximately 10 mol% to approximately 75 mol%, based on the total number of moles of gas used to generate the plasma. The remaining gas may be an inert gas such as N2 and / or Ar. Although not constrained by theory, it is thought that lower concentrations of the halogen-containing precursor will result in less generation of etching-causing species, thus increasing preferential etching at the top 520 of feature 515 and its vicinity. Therefore, the etchant is used before reaching the bottom 525 of feature 515.

[0055]

[0059] Selective etching (or etching of silicon-oxygen-containing material near the top or sidewalls of a feature compared to the bottom of the feature) can be achieved by controlling the distance between the substrate and the etching agent inlet to the processing area (shorter distances may increase etching at the bottom of the feature), controlling the plasma output (higher plasma output may increase etching at the bottom of the feature), controlling the etching duration, controlling the pressure within the processing area, controlling the concentration of the etching agent within the processing area, selecting the plasma source and / or conditions (e.g., radio frequency (RF) plasma or remote plasma source (RPS), pulsing, etc.), and any combination thereof.

[0056]

[0060] The distance between the substrate and the etching agent inlet to the processing area can be controlled by adjusting the distance between the substrate support 104 and the gas distributor 112 of the semiconductor processing chamber 100. Those skilled in the art will recognize that this distance can be applied and adjusted to other semiconductor processing chambers with different configurations.

[0057]

[0061] While not theoretically constrained, it is generally believed that the conformality of etching increases with decreasing distance. However, if the distance is too great, sufficient etching may not be achieved even on the upper part of the layer containing silicon and oxygen-containing material. The distance between the substrate and the inlet of the etching agent (or its plasma) into the processing area can be approximately 150 mil or more, approximately 200 mil or more, approximately 250 mil or more, approximately 300 mil or more, approximately 150 mil to approximately 2000 mil, approximately 150 mil to approximately 1500 mil, approximately 300 mil to approximately 1500 mil, approximately 300 mm to approximately 1200 mm, or approximately 500 mil to approximately 2000 mil.

[0058]

[0062] While not theoretically constrained, when plasma generated from an etching agent is used, the conformality of etching may increase as the plasma power increases. When the etching agent is used to generate the plasma, the plasma power in step 215 may be approximately 500W or less, approximately 400W or less, approximately 300W or less, approximately 200W or less, approximately 100W or less, approximately 1W to approximately 500W, approximately 1W to approximately 250W, approximately 1W to approximately 100W, approximately 50W to approximately 250W, approximately 50W to approximately 300W, approximately 100W to approximately 300W, or approximately 250W to approximately 500W.

[0059]

[0063] The plasma source may be a capacitively coupled plasma (CCP) formed in a remote region or remote plasma unit (RPS unit) separate from the processing chamber. A CPC plasma source may be preferred in some embodiments.

[0060]

[0064] Furthermore, the RF power supply (e.g., power supply 142) can generate power at frequencies above approximately 100 kHz, above approximately 500 kHz, above approximately 1 MHz, above approximately 10 MHz, above approximately 20 MHz, above approximately 50 MHz, and above approximately 100 MHz, among other frequency ranges. Specific examples of power frequencies generated by the RF power supply include, among other frequencies, 350 kHz, 2 MHz, 13.56 MHz, 27 MHz, 40 MHz, 60 MHz, 100 MHz, and 162 MHz. The plasma may be a dual-frequency plasma or a single-frequency plasma. A dual-frequency plasma may include low frequencies (e.g., below 500 kHz or 350 kHz) and high frequencies (e.g., above 10 MHz or 27 MHz).

[0061]

[0065] While not theoretically constrained, when plasma generated from an etching agent is used, longer exposure times may increase the conformality of the etching. The exposure time to the etching agent or the plasma generated therefrom (or the length of time that step 215 is performed) may be approximately 60 seconds or less, approximately 45 seconds or less, approximately 30 seconds or less, approximately 15 seconds or less, approximately 5 seconds or less, approximately 1 second or less, approximately 0.1 seconds to approximately 60 seconds, approximately 1 second to approximately 30 seconds, approximately 5 seconds to approximately 30 seconds, approximately 10 seconds to approximately 60 seconds, or approximately 30 seconds to approximately 60 seconds.

[0062]

[0066] When selective etching is desired, the distance between the substrate and the etching agent (or its plasma) inlet, the plasma power, and the exposure time may be selected to provide selective etching of silicon-oxygen-containing material near the top of the feature compared to the bottom of the feature. Selective etching results in a taper on the sidewalls of the layer containing the silicon-oxygen-containing material.

[0063]

[0067] After each step 215, the degree of tapering of the sidewalls of the silicon-oxygen-containing material layer may increase. As described above, voids or seams in the silicon-oxygen-containing material located within a feature may be formed by pinching off near the top of the feature before the silicon-oxygen-containing material completely fills the feature. Advantageously, method 200 illustrated in Figures 2 and 3A-3H increases the degree of taper of the sidewalls of the silicon-oxygen-containing material layer, preferentially filling the feature 315 from the bottom 325 of the feature toward the top 320 of the feature 315. Thus, for each deposition cycle 205, the formation of voids or seams may be suppressed by leaving a sufficiently large opening at the top 320 of the feature 315.

[0064]

[0068] The degree of taper can be characterized by an angle 340 with respect to the perpendicular of the tapered sidewall of the layer. In Figures 3C, 3E, and 3G, the angles are labeled 345a, 345b, and 345c, respectively. Since the sidewall 330 of feature 315 is shown perpendicularly, angles 345a, 345b, and 345c are shown as being measured from the feature sidewall 330 to the tapered sidewalls 340a, 340c, and 340e of layers 335b, 335d, and 335f, respectively. Those skilled in the art will recognize that if feature 315 is tapered, the angle is measured relative to a perpendicular line from the top 320 of feature 315, not from the sidewall of feature 315.

[0065]

[0069] After an etching step (e.g., step 215), the degree of taper of the sidewalls of the layer containing the silicon-oxygen material may be characterized by an angle from the vertical of about 5° or more, about 20° or more, about 40° or more, about 5° to about 90°, about 5° to about 30°, about 20° to about 60°, about 40° to about 75°, or about 60° to about 90°. The increase in the degree of taper of the sidewalls of the layer between two consecutive etching steps (e.g., from Figure 3C to Figure 3E, or from Figure 3E to Figure 3G) may be characterized by an increase in angle of about 1° or more, about 5° or more, about 10° or more, about 1° to about 30°, about 5° to about 20°, or about 10° to about 30°.

[0066]

[0070] Each etching step (e.g., step 215) may be characterized by the amount of silicon-oxygen-containing material removed. This amount may be approximately 10 Å or more, approximately 20 Å or more, approximately 30 Å or more, approximately 10 Å to approximately 100 Å, approximately 10 Å to approximately 50 Å, approximately 25 Å to approximately 75 Å, or approximately 50 Å to approximately 100 Å. The amount of silicon-oxygen-containing material removed is measured at the top of the feature.

[0067]

[0071] During each step of Method 200, the semiconductor processing chamber may be maintained at various pressures. For example, the pressure inside the semiconductor processing chamber may be maintained between approximately 1 Torr and above, approximately 2 Torr and above, approximately 3 Torr and above, approximately 4 Torr and above, approximately 5 Torr and above, between approximately 1 Torr and approximately 100 Torr, between approximately 1 Torr and approximately 10 Torr, or between approximately 1 Torr and approximately 5 Torr.

[0068]

[0072] During each step of Method 200, the semiconductor processing chamber may be maintained at various temperatures. For example, the temperature inside the semiconductor processing chamber may be maintained at approximately 450°C or higher, approximately 500°C or higher, approximately 550°C or higher, approximately 600°C or higher, or higher. The temperature may be maintained at approximately 650°C or lower, approximately 600°C or lower, approximately 550°C or lower, approximately 500°C or lower, or lower.

[0069]

[0073] Figure 4 shows exemplary steps in processing method 400 according to several embodiments of the present technology. Method 400 can be performed in various processing chambers, including the semiconductor processing chamber 100 described above. Method 400 may include one or more operations, including front-end processing, deposition, etching, polishing, cleaning, or any other operations that may be performed before the operations described, prior to the commencement of Method 400. Method 400 may include a number of optional steps, which may or may not be particularly relevant to some embodiments of the method according to embodiments of the present technology. For example, many of the steps are described to provide a broader range of processes to be performed, but are not critical to the present technology or may be performed by alternative methods, which will be discussed further below. Method 400 may describe the steps schematically shown in Figures 5A–5H. These illustrations will be described in conjunction with the steps of Method 400. It should be understood that only partial schematic diagrams are shown in the figures, and the substrate may include any number of additional materials and features having various properties and characteristics as shown in the figures.

[0070]

[0074] Method 400 may include or may not include optional steps for developing the semiconductor structure into a specific manufacturing process. It should be understood that Method 400 can be performed on any number of semiconductor structures or substrates 505, including exemplary structures 500 on which one or more silicon-containing materials may be formed. As shown in Figure 5A, the substrate 505 may be processed to form one or more concave features 515, such as trenches, openings, or any other structures in the semiconductor process. The substrate 505 may be any number of materials, including a base wafer or substrate 505 made from silicon or a silicon-containing material, other substrate 505 materials, and one or more materials that may be layered and formed on top of the substrate 505 during the semiconductor process. For example, in some embodiments, the substrate 505 may be processed to include one or more materials or structures for semiconductor processing. The substrate 505 may be or include dielectric materials, such as oxides or nitrides of any number of materials. In embodiments, one or more material layers 510 may be deposited on the substrate 505. In the embodiment, one or more material layers 510 may be or may contain silicon-containing materials. The silicon-containing material may be amorphous silicon, doped silicon, silicon oxide, silicon nitride, silicon carbide, or silicon.

[0071]

[0075] As illustrated, one or more features 515 may be defined by one or more material layers 510 and / or substrate 505, such as trenches, openings, or other recessed features. Feature 515 has an upper part 520, a lower part 525, and a side wall 530 connecting the upper part 520 and the lower part 525.

[0072]

[0076] The illustrated feature 515 is characterized by vertical sidewalls, but the feature may alternatively be characterized by tapered sidewalls. In embodiments of tapered sidewalls, the feature may have a larger diameter or width at the top of the feature than at the bottom of the feature. The aspect ratio of the feature, i.e., the ratio of the depth of the feature to the width or diameter of the feature being formed, is about 1:1 or greater and may be about 2:1 or greater, about 3:1 or greater, about 4:1 or greater, about 5:1 or greater, about 6:1 or greater, about 7:1 or greater, about 8:1 or greater, about 9:1 or greater, about 10:1 or greater, or greater.

[0073]

[0077] Although only one feature 515 is shown in the figure, it should be understood that the exemplary structure may have any number of features 515 defined in accordance with the structure according to the embodiment of this technology.

[0074]

[0078] Method 400 includes step 405 of exposing the substrate 505 to a nitrogen-containing inhibitor 535. The nitrogen-containing inhibitor 535 is preferentially absorbed at or near the top 520 of the feature 515 compared to the bottom 525 of the feature 515, as shown in Figure 5B. Next, in step 410, the treated area is purged to remove excess nitrogen-containing inhibitor 535. After step 410, Method 400 includes step 415 of depositing a silicon-containing material 540a onto the substrate. The disclosure relating to step 225 in Figure 2 also applies to step 410 in Figure 4.

[0075]

[0079] The nitrogen-containing inhibitor 535 reduces or suppresses the deposition of the silicon-containing material 540a. Therefore, because the nitrogen-containing inhibitor 535 is on the surface near the top 520 of feature 515, the silicon-containing material 540a preferentially deposits at or near the bottom 525 of feature 515 compared to the top 520 of feature 515, as shown in Figure 5C.

[0076]

[0080] Following step 415, step 420 may be performed to purge the processing area to remove excess silicon-containing precursor. The disclosure regarding step 230 in Figure 2 also applies to step 420 in Figure 4. Following step 420, method 200 includes step 425 of exposing the silicon-containing material to an oxygen plasma, converting the silicon-containing material 540a to a silicon-oxygen-containing material 545a, as shown in Figure 5D. Although Figure 5D does not show the presence of a nitrogen-containing inhibitor 535, the nitrogen inhibitor 535 may still be present. The disclosure regarding step 235 in Figure 2 also applies to step 425 in Figure 4.

[0077]

[0081] Next, following step 425, the method includes step 430, in which the processing area is purged to remove residues from the oxygen plasma and by-products from the conversion of silicon-containing material 540a to silicon-oxygen-containing material 545a. The disclosure relating to step 240 in Figure 2 also applies to step 430 in Figure 4.

[0078]

[0082] The method includes iteratively repeating steps 405, 410, 415, 420, 425, and 430 z times until feature 315 is filled with silicon-oxygen-containing material 435. Figure 5E shows a second iteration of step 405, where the nitrogen-containing inhibitor 535 is preferentially absorbed in the upper part 520 of feature 515 and its vicinity. Figure 5F shows a second iteration of step 415 in which silicon-containing material 540b is preferentially deposited in the bottom part 325 of feature 315 and its vicinity. Figure 5G shows the conversion from silicon-containing material 540b to silicon-oxygen-containing material 545b. Figure 5H shows feature 515 being filled with silicon-oxygen-containing material 545c after iteratively repeating steps 405, 410, 415, 420, 425, and 430.

[0079]

[0083] As shown in Figures 3A–3H, the silicon-oxygen-containing material is deposited over 435 iterative cycles of the method, and the non-conformal deposition of the silicon-containing material forms tapered sidewalls 550a and 550b. Advantageously, method 400, shown in Figures 4 and 5A–5H, increases the degree of tapering of the sidewalls of the silicon-oxygen-containing material, filling the feature 515. Thus, for each method 400, the upper part 520 of the feature 515 can be opened sufficiently large to suppress the formation of voids or seams.

[0080]

[0084] Referring again to step 405, the nitrogen-containing inhibitor 535 may be a product of the plasma generated using the nitrogen-containing precursor. Examples of nitrogen-containing precursors may include, but are not limited to, ammonia (NH3), nitrogen (N2), or a combination thereof. The nitrogen-containing precursor may be present in concentrations of approximately 5 mol% or more, approximately 10 mol% or more, approximately 25 mol% or more, approximately 50 mol% or more, approximately 75 mol% or more, approximately 5 mol% to approximately 90 mol%, approximately 5 mol% to approximately 75 mol%, approximately 5 mol% to approximately 50 mol%, or approximately 10 mol% to approximately 75 mol%, based on the total number of moles of gas used to generate the plasma. The remaining gas may be an inert gas such as N2 and / or Ar. Although not constrained by theory, it is thought that lower concentrations of the nitrogen-containing precursor would result in lower abundance of the nitrogen-containing inhibitor 535, and therefore increased preferential absorption of the nitrogen-containing inhibitor 535 in and near the top 520 of feature 515, as it would be absorbed before reaching the bottom 525 of feature 515. Dilution with an inert gas is not necessarily required for upper inhibition, but dilution may preferably result in depth-selective inhibition.

[0081]

[0085] Furthermore, similar to step 215 in Figure 2, non-conformal absorption of the nitrogen-containing inhibitor 535 can be achieved by controlling the distance between the substrate and the inhibitor inlet to the processing area (shorter distances may increase absorption at the bottom of features), controlling the plasma output (higher plasma output may increase absorption at the bottom of features), controlling the duration of absorption, controlling the pressure during absorption, controlling the pressure within the processing area, controlling the concentration of the nitrogen-containing inhibitor within the processing area, selecting the plasma source and / or conditions (e.g., radio frequency (RF) plasma or remote plasma source (RPS), pulsing, etc.), and any combination thereof.

[0082]

[0086] The distance between the substrate and the inhibitor inlet to the processing area can be controlled by adjusting the distance between the substrate support 104 and the gas distributor 112 of the semiconductor processing chamber 100. Those skilled in the art will recognize that this distance can be applied and adjusted to other semiconductor processing chambers with different configurations.

[0083]

[0087] While not theoretically constrained, it is thought that the conformality of nitrogen-containing inhibitor 535 absorption increases with decreasing distance. However, if the distance is too great, sufficient absorption of nitrogen-containing inhibitor 535 may not be obtained, even at the top of the feature. The distance between the substrate and the inhibitor inlet to the processing area can be approximately 150 mils or more, approximately 200 mils or more, approximately 250 mils or more, approximately 300 mils or more, approximately 150 mils to approximately 2000 mils, approximately 150 mils to approximately 1500 mils, approximately 300 mils to approximately 1500 mils, approximately 300 mm to approximately 1200 mm, or approximately 500 mils to approximately 2000 mils.

[0084]

[0088] While not theoretically constrained, higher plasma power may increase conformity of absorption of nitrogen-containing inhibitor 535 and increase faceting. The plasma power in step 215 may be approximately 1000W or less, approximately 750W or less, approximately 500W or less, approximately 400W or less, approximately 300W or less, approximately 200W or less, approximately 100W or less, approximately 1W to approximately 1000W, approximately 1W to approximately 750W, approximately 1W to approximately 500W, approximately 1W to approximately 250W, approximately 1W to approximately 100W, approximately 50W to approximately 250W, approximately 50W to approximately 300W, approximately 100W to approximately 300W, approximately 250W to approximately 500W, approximately 250W to approximately 1000W, or approximately 500W to approximately 1000W. Depth-selective inhibition may preferably occur at power levels of approximately 500W or less.

[0085]

[0089] While not theoretically constrained, longer exposure times may increase conformity of absorption of the nitrogen-containing inhibitor 535. The exposure time to the nitrogen-containing inhibitor 535 (or the length of time that step 215 is performed) may be approximately 60 seconds or less, approximately 45 seconds or less, approximately 30 seconds or less, approximately 15 seconds or less, approximately 5 seconds or less, approximately 1 second or less, approximately 0.1 seconds to approximately 60 seconds, approximately 1 second to approximately 30 seconds, or approximately 5 seconds to approximately 30 seconds.

[0086]

[0090] While not theoretically constrained, increased pressure within the semiconductor processing chamber during absorption of the nitrogen-containing inhibitor 535 may increase the conformality of the absorption. However, in plasma-based methods, non-conformality may be observed even at high pressures. The pressure within the semiconductor processing chamber during absorption of the nitrogen-containing inhibitor 535 can be maintained between approximately 1 Torr and above, approximately 2 Torr and above, approximately 3 Torr and above, approximately 4 Torr and above, approximately 5 Torr and above, between approximately 1 Torr and approximately 30 Torr, between approximately 1 Torr and approximately 10 Torr, between approximately 1 Torr and approximately 5 Torr, or between approximately 5 Torr and approximately 20 Torr.

[0087]

[0091] When non-conformal absorption of the nitrogen-containing inhibitor 535 is desired, the concentration of the nitrogen-containing precursor used to generate the plasma, the distance between the substrate and the inhibitor inlet, the plasma power, exposure time, and pressure may be selected to provide selective absorption of the nitrogen-containing inhibitor 535 on or near the top 520 of feature 515 compared to the bottom 525 of feature 515. As the silicon-oxygen-containing material 545 is deposited, the degree of taper of the sidewalls 550 of the silicon-oxygen-containing material 545 may increase.

[0088]

[0092] During each step of Method 400, the semiconductor processing chamber may be maintained at various pressures. For example, the pressure inside the semiconductor processing chamber may be maintained between approximately 1 Torr or more, approximately 2 Torr or more, approximately 3 Torr or more, approximately 4 Torr or more, approximately 5 Torr or more, between approximately 1 Torr and approximately 100 Torr, between approximately 1 Torr and approximately 10 Torr, between approximately 1 Torr and approximately 5 Torr, between approximately 5 Torr and approximately 50 Torr, or between approximately 25 Torr and approximately 100 Torr.

[0089]

[0093] During each step of Method 400, the semiconductor processing chamber may be maintained at various temperatures. For example, the temperature inside the semiconductor processing chamber may be maintained at approximately 450°C or higher, approximately 500°C or higher, approximately 550°C or higher, approximately 600°C or higher, or higher. The temperature may be maintained at approximately 650°C or lower, approximately 600°C or lower, approximately 550°C or lower, approximately 500°C or lower, or lower.

[0090]

[0094] The method of the present disclosure includes a hybrid of method 200 and method 400, where method 400 is used in place of deposition cycle 205 of method 200. That is, steps 405, 410, 415, 420, 425, and 430 may be repeated iteratively. After repeating the steps in method 400 iteratively x times, the hybrid method may include step 215, which involves exposing the silicon-oxygen-containing material to an etching agent. Thereafter, the steps of method 400 and the subsequent step 215 may be repeated iteratively again, where the iterative repeats of method 400 and the subsequent step 215 may be performed y times.

[0091]

[0095] The above description includes numerous details for illustrative purposes to facilitate understanding of the various embodiments of this technology. However, it will be apparent to those skilled in the art that certain embodiments can be implemented without some of these details, or with additional details.

[0092]

[0096] While several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative structures, and equivalents can be used without departing from the spirit of the embodiments. Furthermore, many well-known processes and elements have not been described in order to avoid unnecessarily obscuring the art of the present invention. Therefore, the above description should not be construed as limiting the scope of the art.

[0093]

[0097] Where a range of values ​​is given, unless explicitly stated otherwise in the context, each intervening value between the upper and lower limits of that range is understood to be specifically disclosed down to the smallest unit of the lower limit. Any narrow range between any stated or unstated intervening values ​​within the stated range, and any other stated or intervening values ​​within that stated range, are also included. The upper and lower limits of such narrower ranges may be individually included in or excluded from that range. Each range in which one, neither, or both of the limit values ​​are included is also included in the Art, provided that there are any limit values ​​specifically excluded within the stated range. Where a stated range includes one or both limit values, it also includes ranges that exclude one or both of the included limit values.

[0094]

[0098] As used herein and in the appended claims, the singular forms "a," "an," and "the" include multiple references unless otherwise explicitly stated in the context. For example, where “silicon-containing precursors” is mentioned, it includes multiple such precursors; where “silicon-containing materials” is mentioned, it includes references to one or more materials and equivalents well known to those skilled in the art, and so on.

[0095]

[0099] Furthermore, the terms “comprise(s),” “comprising,” “contain(s),” “containing,” “include(s),” and “including,” as used herein and in the claims, are intended to identify the presence of the described feature, integer, component, or action, but not to exclude the presence or addition of one or more other features, integers, components, actions, or groups.

Claims

1. A semiconductor processing method, i) Repeatedly performing a deposition cycle on a substrate placed in the processing area of ​​a semiconductor processing chamber in order to deposit a silicon-oxygen-containing material of about 100 Å to about 1000 Å on one or more features, wherein the substrate defines the one or more features along the substrate, a silicon-containing precursor is deposited within the one or more features, each of the one or more features has an upper part, a bottom part, and a side wall connecting the upper part and the bottom part, and the deposition cycle is performed i-a) Depositing a silicon-containing material on the substrate, i-b) Purging the processing area after step i-a, i-c) Exposing the silicon-containing material to an oxygen plasma in order to convert the silicon-containing material to the silicon-oxygen-containing material, i-d) Purge the processing area after step i-c. This includes the repeated cycle of deposition, ii) Exposing the silicon-oxygen-containing material to an etching agent in order to non-conformally remove a portion of the silicon-oxygen-containing material, wherein the non-conformal removal is performed to a greater extent at the top of the feature compared to the bottom of the feature, iii) Repeating steps i to ii iteratively in order to fill one or more features with the silicon-oxygen-containing material. A semiconductor processing method, including the following.

2. The semiconductor processing method according to claim 1, wherein the side wall of one or more features is a tapered side wall.

3. The semiconductor processing method according to claim 1, wherein after each step ii, the angle of the side wall of the silicon-oxygen-containing material increases from that of the previous step ii.

4. The semiconductor processing method according to claim 3, wherein the angle increases by approximately 5° or more from the previous step ii.

5. The semiconductor processing method according to claim 1, wherein the etching agent includes a product of plasma generated using a halogen-containing precursor.

6. The halogen-containing precursor is nitrogen trifluoride (NF ３ ), hydrogen bromide (HBr), fluoromethane (CH ３ F), difluoromethane (CH ２ F ２ ), trifluoromethane (CHF ３ ), carbon tetrafluoride (CF ４ ), and boron trichloride (BCl ３ The semiconductor processing method according to claim 5, comprising one or more of the following:

7. The semiconductor processing method according to claim 5, wherein the distance between the substrate and the position where the etching agent enters the processing area is approximately 4 mm to approximately 50 mm.

8. The semiconductor processing method according to claim 5, wherein the plasma has a plasma output of approximately 500 W or less.

9. The semiconductor processing method according to claim 5, wherein the exposure time to the plasma is approximately 60 seconds or less.

10. The semiconductor processing method according to claim 1, wherein the non-conformal removal removes the silicon-oxygen-containing material in an area of ​​about 10 Å to about 100 Å from the upper part of the feature.

11. A semiconductor processing method, i) Supplying a nitrogen-containing inhibitor to a processing area of ​​a semiconductor processing chamber, wherein a substrate is placed within the processing area of ​​the semiconductor processing chamber, the substrate defines one or more features along the substrate, and each of the one or more features has an upper part, a bottom part, and a side wall connecting the upper part and the bottom part, ii) The nitrogen-containing inhibitor is absorbed more at the top of one or more features than at the bottom of one or more features, iii) After step ii, deposit a silicon-containing material onto the substrate, iv) In order to convert the silicon-containing material into a silicon-oxygen-containing material, the silicon-containing material is exposed to an oxygen plasma, v) Repeatedly performing steps i to iv in order to fill one or more features with the silicon-oxygen-containing material. A semiconductor processing method, including the following.

12. The semiconductor processing method according to claim 11, wherein the nitrogen-containing inhibitor is a product of plasma of a nitrogen-containing precursor.

13. The semiconductor processing method according to claim 12, wherein the nitrogen-containing precursor comprises ammonia, nitrogen, or a combination thereof.

14. The semiconductor processing method according to claim 12, wherein the gas used to generate the plasma contains 5 mol% to 75 mol% of the nitrogen-containing precursor.

15. The semiconductor processing method according to claim 12, wherein the distance between the substrate and the position where the nitrogen-containing inhibitor enters the processing area is approximately 4 mm to approximately 50 mm.

16. The semiconductor processing method according to claim 12, wherein the plasma has a plasma output of approximately 500 W or less.

17. The semiconductor processing method according to claim 12, wherein the exposure time to the plasma is approximately 60 seconds or less.

18. A semiconductor processing method, i) Supplying a nitrogen-containing inhibitor to a processing area of ​​a semiconductor processing chamber, wherein a substrate is placed within the processing area of ​​the semiconductor processing chamber, the substrate defines one or more features along the substrate, and each of the one or more features has an upper part, a bottom part, and a side wall connecting the upper part and the bottom part, ii) The nitrogen-containing inhibitor is absorbed more at the top of one or more features than at the bottom of one or more features, iii) After step ii, deposit a silicon-containing material onto the substrate, iv) In order to convert the silicon-containing material into a silicon-oxygen-containing material, the silicon-containing material is exposed to an oxygen plasma, v) Repeatedly repeating steps i to iv in order to deposit the silicon-oxygen-containing material of about 50 Å to about 500 Å on one or more features on the substrate, vi) In order to remove the silicon-oxygen-containing material of approximately 10 Å to approximately 100 Å, the silicon-oxygen-containing material is exposed to an etching agent, vii) In order to fill one or more features with the silicon-oxygen-containing material, steps v to vi are repeated iteratively, ending in step v. A semiconductor processing method, including the following.

19. The semiconductor processing method according to claim 18, wherein the etching agent includes a product of plasma generated using a halogen-containing precursor.

20. The semiconductor processing method according to claim 18, wherein the nitrogen-containing inhibitor is a product of plasma of a nitrogen-containing precursor.

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