Multi-gate silicon carbide MOSFET transistor and its manufacturing method, chip
The multi-gate silicon carbide MOSFET transistor addresses low channel mobility and etching challenges by employing a comb-shaped gate structure, improving mobility and yield while maintaining compatibility with conventional processes, suitable for high-voltage applications.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- PN JUNCTION SEMICON (HANGZHOU) CO LTD
- Filing Date
- 2024-08-19
- Publication Date
- 2026-07-01
AI Technical Summary
Conventional silicon carbide MOSFET transistors face challenges such as low channel mobility, difficulty in etching trenches deeper than 1.5 μm, and high process yield issues, particularly in large-scale production, due to the unique crystallographic properties of silicon carbide and the structural limitations of planar and trench gate designs.
A multi-gate silicon carbide MOSFET transistor with a comb-shaped gate structure is developed, featuring comb-tooth side walls perpendicular to the substrate plane, enhancing channel mobility and reducing etching complexity by allowing shallower trench depths, while maintaining compatibility with conventional planar gate processes.
The multi-gate design improves channel mobility, reduces conduction losses, and enhances process yield by optimizing trench etching, making it suitable for high-voltage applications with reduced leakage current and lower production costs.
Smart Images
Figure 2026521786000001_ABST
Abstract
Description
[Technical Field]
[0001] The present invention relates to a semiconductor method, and more specifically to a multi-gate silicon carbide MOSFET transistor, a method for manufacturing the same, and a chip. [Background technology]
[0002] Silicon carbide power devices are increasingly being used in new energy fields such as charging systems, electric vehicles, solar inverters, and energy storage. Conventional silicon carbide MOSFET transistor structures mainly include planar gate and trench gate structures.
[0003] Conventional silicon carbide MOSFET transistors, whether planar gate or trench gate, each have their own drawbacks. For example, while planar gate silicon carbide MOSFET transistors offer excellent reliability, the plane in which the channel is located is perpendicular to the c-axis of 4H-SiC, resulting in low channel mobility in that plane (generally around 30 cm²). 2 This results in additional conduction losses due to the value being smaller than / V·s. Also, the plane on which the channel of a trench gate silicon carbide MOSFET transistor is located is parallel to the c-axis, and its channel mobility is high (120 cm²). 2 While it is possible to reach / V·s, etching silicon carbide materials is extremely difficult, and it is generally difficult to etch trenches deeper than 1.5 μm. The yield of the process steps poses a significant challenge in large-scale device production, and the protection of the gate oxide at the bottom of the trench due to the high breakdown field of silicon carbide (>2.5 MV / cm) becomes the main difficulty in structural design and process implementation. [Overview of the project] [Problems that the invention aims to solve]
[0004] To solve the problems mentioned in the background technology, embodiments of the present invention provide a multi-gate silicon carbide MOSFET transistor, a method for manufacturing the same, and a chip that is compatible with conventional planar-gate silicon carbide MOSFET processes and is advantageous in maintaining high yield and reliability at the application end during large-scale mass production, as well as having high channel mobility. [Means for solving the problem]
[0005] A multi-gate silicon carbide MOSFET transistor, A semiconductor substrate, a silicon carbide drift region located on the first surface of the semiconductor substrate, and a drain electrode located on the second surface of the semiconductor substrate, A well region located within the silicon carbide drift region, and a source region located within the well region, A source electrode located on the surface of the source region, A gate mechanism located on the surface of the source region, well region, and silicon carbide drift region, wherein a portion of the well region in contact with the gate structure is designated as a channel region, The semiconductor substrate, silicon carbide drift region, and source region are of the first doping type, and the well region is of the second doping type. The gate structure includes a comb-shaped first gate structure, the comb-shaped first gate structure is located within the source region, the corresponding well region, and the silicon carbide drift region, the comb-tooth length direction of the comb-tooth first gate structure coincides with the current direction of the channel region, and the channel mobility of the channel corresponding to the comb-tooth side wall surface of the comb-tooth first gate structure is greater than the channel mobility of the channel corresponding to the comb-tooth top surface and comb-tooth bottom surface of the comb-tooth first gate structure.
[0006] Optionally, the side walls of the comb teeth are perpendicular to the substrate plane, or they are inclined to form an angle with the substrate plane.
[0007] Optionally, the comb tooth sidewalls may be silicon carbide m-face, a-face or
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[0008] Optionally, the side wall surface of the comb teeth
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[0009] The number of comb teeth is optional; it may be one or more.
[0010] Optionally, the depth of the comb teeth is in the range of 0.1 micrometers to 1.5 micrometers, and the depth of the comb teeth is smaller than the depth of the well region.
[0011] The invention optionally further includes a JFET current enhancement layer located within the silicon carbide drift region and adjacent to the well region, wherein the JFET current enhancement layer has a first doping type and a doping concentration greater than that of the silicon carbide drift region.
[0012] Optionally, the system further includes a low-concentration doping channel of a first doping type located in the channel region.
[0013] The embodiments of the present invention further provide a method for manufacturing a multi-gate silicon carbide MOSFET transistor. A semiconductor substrate is provided, a silicon carbide drift region is formed on the first surface of the semiconductor substrate, and the semiconductor substrate and the silicon carbide drift region have a first doping concentration. The steps include forming a drain electrode on the second surface of the semiconductor substrate, The steps include forming a well region and a source region within the silicon carbide drift region, wherein the well region is located within the silicon carbide drift region, the source region is located within the well region, the source region is of a first doping type, and the well region is of a second doping type, Etching the source region, well region, and silicon carbide drift region to form comb-shaped trenches; Forming a gate structure on the surface of the comb-shaped trenches, designating a part of the well region in contact with the gate structure as a channel region, the gate structure including a comb-shaped first gate structure located within the comb-shaped trenches, the comb tooth length direction of the comb-shaped first gate structure being consistent with the current direction of the channel region, and the channel mobility of the channel region corresponding to the comb tooth side wall surface of the comb-shaped first gate structure being greater than the channel mobility of the channel regions corresponding to the comb tooth top surface and comb tooth bottom surface of the comb-shaped first gate structure; Forming a source electrode on the surface of the source region.
[0014] An embodiment of the present invention further provides a chip having the multi-gate silicon carbide MOSFET transistor.
Advantages of the Invention
[0015] In summary, the present application has the following advantages.
[0016] Comb-shaped trenches are formed in the source region, corresponding well region, and silicon carbide drift region of the multi-gate silicon carbide MOSFET transistor, and a corresponding comb-shaped first gate structure is formed. The comb-shaped first gate structure has three surfaces, namely, a comb tooth side wall surface, a comb tooth top surface, and a comb tooth bottom surface, which contact the channel region, increasing the width of the channel region. The comb tooth side wall surface is perpendicular to the conventional substrate plane or forms a certain inclination angle. By reasonably adjusting the crystal plane of the comb tooth side wall surface, the channel mobility of the channel region corresponding to the comb tooth side wall surface is made greater than the channel mobility of the channel regions corresponding to the comb tooth top surface and comb tooth bottom surface of the comb-shaped first gate structure, improving the overall comprehensive mobility.
[0017] Moreover, the multi-gate silicon carbide MOSFET transistor is compatible with the process of the conventional planar gate silicon carbide MOSFET transistor and has a low cost. [Brief explanation of the drawing]
[0018] [Figure 1] This figure shows the cross-sectional structure along the AA' plane of a multi-gate silicon carbide MOSFET transistor according to one embodiment of the present invention. [Figure 2] This figure shows the cross-sectional structure along the BB' plane of a multi-gate silicon carbide MOSFET transistor according to one embodiment of the present invention. [Figure 3] This is a three-dimensional structural diagram (with the gate structure removed) of a multi-gate silicon carbide MOSFET transistor according to one embodiment of the present invention. [Figure 4] This figure shows the cross-sectional structure along the CC' plane of a multi-gate silicon carbide MOSFET transistor according to one embodiment of the present invention. [Figure 5] This figure shows the cross-sectional structure along the DD' plane of a multi-gate silicon carbide MOSFET transistor according to one embodiment of the present invention. [Figure 6] This figure shows the cross-sectional structure along the EE' plane of a multi-gate silicon carbide MOSFET transistor according to one embodiment of the present invention. [Figure 7] This figure shows the cross-sectional structure along the FF' plane of a multi-gate silicon carbide MOSFET transistor according to another embodiment of the present invention. [Figure 8] This figure shows the cross-sectional structure along the GG' plane of a multi-gate silicon carbide MOSFET transistor according to another embodiment of the present invention. [Figure 9] This figure shows the cross-sectional structure along the HH' plane of a multi-gate silicon carbide MOSFET transistor according to another embodiment of the present invention. [Figure 10] This figure shows a cross-sectional structure of a multi-gate silicon carbide MOSFET transistor according to yet another embodiment of the present invention. [Figure 11] This figure shows the cross-sectional structure along the II' plane of a multi-gate silicon carbide MOSFET transistor according to another embodiment of the present invention. [Figure 12] This figure shows the cross-sectional structure along the JJ' plane of a multi-gate silicon carbide MOSFET transistor according to another embodiment of the present invention. [Figure 13] This figure shows the cross-sectional structure along the KK' plane of a multi-gate silicon carbide MOSFET transistor according to another embodiment of the present invention. [Modes for carrying out the invention]
[0019] The technical solutions in embodiments of the present invention will be described clearly and completely below with reference to the drawings of the embodiments; however, it will be clear that the embodiments described are only a subset of the embodiments of the present invention, not all embodiments. All other embodiments obtained by those skilled in the art without creative effort based on the embodiments of the present invention are all within the scope of protection of the present invention.
[0020] Referring to Figures 1 to 6, these figures show the structure of a multi-gate silicon carbide MOSFET transistor according to one embodiment of the present invention. Figure 1 shows the cross-sectional structure along the AA' plane of the multi-gate silicon carbide MOSFET transistor according to one embodiment of the present invention. Figure 2 shows the cross-sectional structure along the BB' plane of the multi-gate silicon carbide MOSFET transistor according to one embodiment of the present invention. Figure 3 is a three-dimensional structure diagram (with the gate structure removed) of the multi-gate silicon carbide MOSFET transistor according to one embodiment of the present invention. Figure 4 shows the cross-sectional structure along the CC' plane of the multi-gate silicon carbide MOSFET transistor according to one embodiment of the present invention. Figure 5 shows the cross-sectional structure along the DD' plane of the multi-gate silicon carbide MOSFET transistor according to one embodiment of the present invention. Figure 6 shows the cross-sectional structure along the EE' plane of the multi-gate silicon carbide MOSFET transistor according to one embodiment of the present invention.
[0021] The multi-gate silicon carbide MOSFET transistor in the embodiment of the present invention is A semiconductor substrate 10, a silicon carbide drift region 20 located on the first surface of the semiconductor substrate 10, and a drain electrode 30 located on the second surface of the semiconductor substrate 10, A well region 40 located within the silicon carbide drift region 20, and a source region 50 located within the well region 40, A source electrode 70 located on the surface of the source region 50, A gate mechanism 60 located on the surface of the source region 50, the well region 40, and the silicon carbide drift region 20, wherein a portion of the well region that contacts the gate structure 60 is designated as a channel region 55, The semiconductor substrate 10, silicon carbide drift region 20, and source region 50 are of the first doping type, and the well region 40 is of the second doping type. The gate structure 60 includes a comb-shaped first gate structure 65, which is located within the source region 50, the corresponding well region 40, and the silicon carbide drift region 20. The comb-tooth length direction of the comb-tooth first gate structure 65 coincides with the current direction of the channel region, and the channel mobility of the channel region corresponding to the comb-tooth side wall surface 61 of the comb-tooth first gate structure 65 is greater than the channel mobility of the channel region corresponding to the comb-tooth top surface 63 and comb-tooth bottom surface 62 of the comb-tooth first gate structure, with the comb-tooth length direction being, i.e., direction aa'.
[0022] Because silicon carbide materials exhibit very large differences in channel mobility across different crystal planes, the plane in which the channel of a conventional planar-gate silicon carbide MOSFET transistor is located is perpendicular to the c-axis of 4H-SiC, resulting in low channel mobility in that plane (generally around 30 cm²). 2 This results in additional conduction losses (smaller than / V·s). Furthermore, the channel of a silicon carbide MOSFET transistor employing a trench gate structure is parallel to the c-axis, resulting in high channel mobility of 120 cm². 2 / V·s can be reached, but due to the large trench depth of the trench gate structure, etching the silicon carbide material is extremely difficult, and it is generally difficult to etch trenches deeper than 1.5 μm, making the yield of the process steps a major challenge in large-scale device production.
[0023] In addition, in the embodiment of the present invention, comb-shaped trenches 21 are formed in the source region 50, the corresponding well region 40, and the silicon carbide drift region 20, and a comb-shaped first gate structure 65 is correspondingly formed. The comb-shaped first gate structure has three surfaces, namely a comb-tooth side wall surface 61, a comb-tooth top surface 63, and a comb-tooth bottom surface 62, and contacts the channel region. Among them, the comb-tooth top surface 63 and the comb-tooth bottom surface 62 are parallel to the conventional substrate plane, and the comb-tooth side wall surface 61 is perpendicular to the conventional substrate plane or forms a certain inclination angle. By reasonably adjusting the crystal direction of the comb-tooth side wall surface 61, the channel mobility of the channel region corresponding to the comb-tooth side wall surface 61 is made larger than the channel mobility of the channel regions corresponding to the comb-tooth top surface 63 and the comb-tooth bottom surface 62 of the comb-shaped first gate structure.
[0024] In this embodiment, the plane where the comb-tooth top surface 63 and the comb-tooth bottom surface 62 of the multi-gate silicon carbide MOSFET transistor are located is perpendicular to the c-axis of 4H-SiC, and the plane where the comb-tooth side wall surface 61 is located is parallel to the c-axis of 4H-SiC.
[0025] Silicon carbide has a low channel mobility in the substrate plane (~25 cm 2 / V·s), but the channel mobilities of the a-face and m-face in the vertical direction parallel to the c-axis of 4H-SiC are high (50 - 120 cm 2 / V·s). Therefore, the comprehensive mobility obtained in the multi-channel of the multi-gate silicon carbide MOSFET transistor in the embodiment of the present invention is higher than that of the conventional planar gate structure.
[0026] Moreover, since the comb-shaped first gate structure 65 of the present invention has three surfaces, namely the comb-tooth side wall surface 61, the comb-tooth top surface 63, and the comb-tooth bottom surface 62, compared with introducing the side MOS interface by introducing the prior art, the effective channel width-to-length ratio (W ch / L ch ) of the multi-gate silicon carbide MOSFET transistor in the embodiment of the present invention is higher than the channel width-to-length ratio of the conventional planar gate. (If the ratio of the depth to the width of the trench 21 is 1, the W ch / L chThe ratio is twice that of a conventional planar gate, which results in a channel resistance (its reciprocal is 1 / R). ch =μ n *W ch / L ch *C ox *(V G -V TH It can significantly reduce )).
[0027] Embodiments of the present invention improve the channel resistance by adjusting the ratio of the comb tooth sidewall surface 61 to the comb tooth top surface 63 and comb tooth bottom surface 62 by adjusting the ratio of the trench depth to width, and also improve the overall channel mobility of the multi-gate silicon carbide MOSFET transistor of the present invention by adjusting the crystal plane corresponding to the comb tooth sidewall surface 61.
[0028] Furthermore, since the current direction in the channel region of the present invention is generally within a horizontal direction parallel to the substrate plane, it can still be considered a planar structure, is compatible with conventional planar gate processes (simply etching strip-shaped trenches perpendicular to the gate placement direction into the silicon carbide before forming the gate structure), and is low-cost.
[0029] In an embodiment of the present invention, the height of the comb teeth of the comb-shaped first gate structure 65 (i.e., the height of the comb tooth side wall) is less than the depth of the well region 40 but greater than the depth of the source region 50. In one embodiment, the height of the comb teeth is 0.2 micrometers, the depth of the well region is 0.8 micrometers, and the depth of the source region is 0.3 micrometers or 0.15 micrometers.
[0030] In other embodiments, the height range of the comb teeth is 0.1 micrometers to 1.5 micrometers, preferably 0.1 micrometers to 0.5 micrometers.
[0031] Compared to conventional trench gate structures, the depth of the well region in the present invention is deeper than the bottom of the comb-tooth trench, and the deeper PN junction formed between the bottom of the well region and the silicon carbide drift region can effectively protect the gate oxygen, reducing the high electric field formed by the drain high-voltage bias and improving the service life of the gate oxygen. From a process realization standpoint, the trench etching depth of conventional trench gates must be strictly controlled, generally around 1 to 1.5 μm, and the channel etching depth must be deeper than where the channel current is at the exit of the well region, but shallower than the deep PN junction used in avalanche clamps. The process difficulties faced here include the high difficulty of the trench gate etching process and the very high difficulty of the deep junction process that provides clamp protection. Since the trench depth of the present invention can be controlled to within 0.5 micrometers, the present invention can operate even at a depth of as little as 0.1 micrometers by controlling the ratio of the depth to width of the trench structure to ensure a sufficient side gate width. The silicon carbide etching process has low requirements, and the process difficulty of forming a high-quality gate oxygenation layer in shallow trenches is also low. This significantly reduces process difficulty, which is advantageous for forming a high-quality gate structure and ensures that the product has a high yield during mass production.
[0032] In high-voltage applications, the channel current direction of conventional trench gate MOSFET structures is perpendicular to the substrate plane and parallel to the electric field direction of the drift region. When the power is turned off, the channel region is affected by the Drain-Induced Barrier Lowering (DIBL) effect introduced at the drain end, causing high channel leakage current under a high-voltage drain bias. The channel current direction of the present invention remains parallel to the substrate plane and perpendicular to the electric field of the drift region, making the channel less susceptible to the DIBL effect and significantly reducing leakage current in high-voltage applications.
[0033] In other embodiments, referring to Figures 7 to 9, the height of the comb teeth of the comb-shaped first gate structure 65 is less than the depth of the well region 40 and less than the depth of the source region 50. Since it is not important whether the trench depth is greater than the source region, the present invention has high process redundancy with respect to the trench etching depth.
[0034] In this embodiment, the number of comb teeth is one or more, and the appropriate number of comb teeth can be rationally set according to the width of the channel.
[0035] In this embodiment, the gate structure 60 includes a comb-shaped first gate structure 65 located within the source region, the corresponding well region, and the silicon carbide drift region, and a second gate structure located on the surface of the comb-shaped first gate structure.
[0036] Referring to Figures 1 and 2, in this embodiment, one cell structure includes two multi-gate silicon carbide MOSFET transistors, of which carriers must pass through a JFET region formed by two adjacent well regions in order to reach the silicon carbide drift region after leaving the channel.
[0037] In other embodiments, a single cell structure may include only one multi-gate silicon carbide MOSFET transistor, for example, as shown in Figure 3.
[0038] In this embodiment, the semiconductor substrate is a silicon carbide substrate with high concentration doping. In other embodiments, the semiconductor substrate may be any other suitable substrate, such as a silicon substrate, a diamond substrate, an aluminum nitride substrate, or a gallium nitride substrate.
[0039] In this embodiment, the multi-gate silicon carbide MOSFET transistor is an N-type channel MOSFET transistor, the first doping type is N-type, the second doping type is P-type, the semiconductor substrate 10 is an N-type high-concentration doped substrate, the silicon carbide drift region 20 is an N-type low-concentration doped drift region, the well region 40 is a P-type low-concentration doped well region, and the source region 50 is an N-type high-concentration doped source region.
[0040] In other embodiments, the multi-gate silicon carbide MOSFET transistor may be a P-type channel MOSFET transistor, the first doping type is P-type, the second doping type is N-type, the semiconductor substrate 10 is a P-type high-concentration doped substrate, the silicon carbide drift region 20 is a P-type low-concentration doped drift region, the well region 40 is an N-type low-concentration doped well region, and the source region 50 is a P-type high-concentration doped source region.
[0041] Referring to Figure 10, similar to conventional planar gate structures, after carriers leave the channel region, they must pass through the JFET region, which is formed by two adjacent well regions, to reach the drift region. To reduce the resistance of the JFET region, the silicon carbide MOSFET can introduce a first-type doping higher than that of the drift region into the JFET region, forming a JFET current enhancement layer 25.
[0042] Furthermore, the depth of the N-type doping in the JFET current enhancement layer 25 is greater than the depth of the well region, which is advantageous for lateral current diffusion within the drift region.
[0043] Referring to Figure 11, the channel region of the multi-gate silicon carbide MOSFET transistor may be a first-doping type low-concentration doped channel 45. The comb-like first gate structure improves gate control capability by forming a three-sided ring gate structure in the silicon carbide channel body, thereby allowing the low-concentration first-doping type channel doping to still operate the device in enhancement mode (i.e., if the device is an N-channel enhancement MOSFET, its threshold voltage Vth > 0). The threshold voltage can be adjusted by selecting gate materials with different work functions and adjusting the concentration of N-type doping in the channel.
[0044] Referring to Figures 12 and 13, these figures show the structure of two other embodiments of the present invention, and the plane in which the comb-tooth side wall surface 61 is located is
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[0045] Referring to Figure 12, the cross-sectional shape of the comb teeth is an inverted triangle, and the two side walls of the inverted triangle are,
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[0046] Referring to Figure 13, the cross-sectional shape of the comb teeth is an inverted trapezoid, and the two side walls of the inverted trapezoid are,
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[0047] Embodiments of the present invention further provide a chip having the above-mentioned multi-gate silicon carbide MOSFET transistor.
[0048] The embodiments of the present invention further provide a method for manufacturing a multi-gate silicon carbide MOSFET transistor. A semiconductor substrate is provided, a silicon carbide drift region is formed on the first surface of the semiconductor substrate, and the semiconductor substrate and the silicon carbide drift region have a first doping concentration. The steps include forming a well region and a source region within the silicon carbide drift region, wherein the well region is located within the silicon carbide drift region, the source region is located within the well region, the source region is of a first doping type, and the well region is of a second doping type, The steps include etching the source region, well region and silicon carbide drift region to form a comb-shaped trench, A gate structure is formed on the surface of the comb-shaped trench, a portion of the well region in contact with the gate structure is defined as a channel region, the gate structure includes a comb-shaped first gate structure located within the comb-shaped trench, the comb-tooth length direction of the comb-tooth first gate structure coincides with the current direction of the channel region, and the channel mobility of the channel region corresponding to the comb-tooth side wall surface of the comb-tooth first gate structure is greater than the channel mobility of the channel region corresponding to the comb-tooth top surface and comb-tooth bottom surface of the comb-tooth first gate structure. The steps include forming a source electrode on the surface of the source region, The process includes the step of forming a drain electrode on the second surface of the semiconductor substrate.
[0049] The multi-gate silicon carbide MOSFET transistor of the embodiment of the present invention is compatible with conventional planar gate processes, and only requires etching into the silicon carbide to form comb-shaped trenches in the gate placement direction before forming the gate structure, which are then filled to form the gate structure, resulting in low process costs.
[0050] The etching process that forms the comb-shaped trenches can be manufactured using a conventional silicon carbide etching process, and will not be explained here.
[0051] As will be explained in the last part, by relying on the apparatus structure of the present invention and the technical solutions of the embodiments described above, some or all of the technical features may be modified or replaced by equivalents, and the resulting essence will fall within the patentable scope of the apparatus structure and the embodiments of the present invention without departing from the corresponding technical solutions of the present invention.
Claims
1. A semiconductor substrate, a silicon carbide drift region located on the first surface of the semiconductor substrate, and a drain electrode located on the second surface of the semiconductor substrate, A well region located within the silicon carbide drift region, and a source region located within the well region, A source electrode located on the surface of the source region, A gate mechanism located on the surface of the source region, well region, and silicon carbide drift region, wherein a portion of the well region in contact with the gate structure is designated as a channel region, The semiconductor substrate, silicon carbide drift region, and source region are of the first doping type, and the well region is of the second doping type. The gate structure includes a comb-shaped first gate structure, the comb-shaped first gate structure is located within the source region, the corresponding well region, and the silicon carbide drift region, the comb-tooth length direction of the comb-tooth first gate structure coincides with the current direction of the channel region, and the channel mobility of the channel corresponding to the comb-tooth side wall surface of the comb-tooth first gate structure is greater than the channel mobility of the channel corresponding to the comb-tooth top surface and comb-tooth bottom surface of the comb-tooth first gate structure. A multi-gate silicon carbide MOSFET transistor characterized by the following features.
2. The side walls of the comb teeth are perpendicular to the substrate plane, or the side walls of the comb teeth are inclined to form an angle with the substrate plane. The multi-gate silicon carbide MOSFET transistor according to feature 1.
3. The comb tooth side wall surface is made of silicon carbide m-face, a-face or [Number 7] It is a slope. The multi-gate silicon carbide MOSFET transistor according to feature 1.
4. The side wall surface of the comb teeth [Number 8] If the surface is sloped, the cross-sectional shape of the comb teeth is an inverted triangle or an inverted trapezoid. The multi-gate silicon carbide MOSFET transistor according to feature 4.
5. The number of comb teeth is one or more. The multi-gate silicon carbide MOSFET transistor according to feature 1.
6. The depth of the comb teeth is in the range of 0.1 micrometers to 1.5 micrometers, and the depth of the comb teeth is smaller than the depth of the well region. The multi-gate silicon carbide MOSFET transistor according to feature 1.
7. The JFET current enhancement layer is located within the silicon carbide drift region and adjacent to the well region, and the JFET current enhancement layer has a first doping type and a doping concentration greater than that of the silicon carbide drift region. The multi-gate silicon carbide MOSFET transistor according to feature 1.
8. Further comprising a first-type low-concentration doping channel located in the channel region, The multi-gate silicon carbide MOSFET transistor according to feature 1.
9. A semiconductor substrate is provided, a silicon carbide drift region is formed on the first surface of the semiconductor substrate, and the semiconductor substrate and the silicon carbide drift region have a first doping concentration. The steps include forming a well region and a source region within the silicon carbide drift region, wherein the well region is located within the silicon carbide drift region, the source region is located within the well region, the source region is of a first doping type, and the well region is of a second doping type. The steps include etching the source region, well region and silicon carbide drift region to form a comb-shaped trench, A gate structure is formed on the surface of the comb-shaped trench, a portion of the well region in contact with the gate structure is defined as a channel region, the gate structure includes a comb-shaped first gate structure located within the comb-shaped trench, the comb-tooth length direction of the comb-tooth first gate structure coincides with the current direction of the channel region, and the channel mobility of the channel region corresponding to the comb-tooth side wall surface of the comb-tooth first gate structure is greater than the channel mobility of the channel region corresponding to the comb-tooth top surface and comb-tooth bottom surface of the comb-tooth first gate structure. The steps include forming a source electrode on the surface of the source region, The step includes forming a drain electrode on the second surface of the semiconductor substrate, A method for manufacturing a multi-gate silicon carbide MOSFET transistor, characterized by the following features.
10. A chip having a multi-gate silicon carbide MOSFET transistor according to any one of claims 1 to 8.