Stacked transistor with dielectric insulator layer

Abstract

The semiconductor structure comprises a first stacked device having a first field-effect transistor comprising one or more first nanosheet layers, a second field-effect transistor comprising one or more second nanosheet layers, and a first dielectric insulator layer positioned between the first and second field-effect transistors, wherein the first dielectric insulator layer has a first width. The semiconductor structure further comprises a second stacked device adjacent to the first stacked device. The second stacked device has a third field-effect transistor comprising one or more third nanosheet layers, a fourth field-effect transistor comprising one or more fourth nanosheet layers, and a second dielectric insulator layer positioned between the third and fourth field-effect transistors. The second dielectric insulator layer has a second width smaller than the first width of the first dielectric insulator layer.

Description

Technical Field

[0001] A field-effect transistor (FET) is a transistor having a source, a gate, and a drain, and its operation depends on the flow of carriers (electrons or holes) along a channel extending between the source and the drain. The current flowing through the channel between the source and the drain can be controlled by a transverse electric field under the gate. FETs are widely used for switching, amplification, filtering, and other tasks.

Summary of the Invention

[0002] Exemplary embodiments of the present disclosure include techniques used in semiconductor manufacturing. In an exemplary embodiment, a semiconductor structure includes a first field-effect transistor including one or more first nanosheet layers, a second field-effect transistor vertically stacked above the first field-effect transistor, the second field-effect transistor including one or more second nanosheet layers, and a first dielectric insulating layer positioned between the first field-effect transistor and the second field-effect transistor, the first dielectric insulating layer having a first width. The semiconductor structure further includes a second stacked device adjacent to the first stacked device. The second stacked device includes a third field-effect transistor including one or more third nanosheet layers, a fourth field-effect transistor vertically stacked above the third field-effect transistor, the fourth field-effect transistor including one or more fourth nanosheet layers, and a second dielectric insulating layer positioned between the third field-effect transistor and the fourth field-effect transistor. The second dielectric insulating layer has a second width smaller than the first width of the first dielectric insulating layer.

[0003] Advantageously, the semiconductor structure of the exemplary embodiment allows for the formation of a first dielectric insulator layer of a first stacked device having a different width from the second dielectric insulator layer of a second stacked device adjacent to the first stacked device, thereby resulting in both shared gate integration and independent gate devices.

[0004] In one or more additional exemplary embodiments that may be combined with the preceding paragraphs, the first width of the first dielectric insulator layer is equal to the third width of the one or more second nanosheet layers, and the second width of the second dielectric insulator layer is equal to the fourth width of the one or more third nanosheet layers.

[0005] In one or more additional exemplary embodiments that may be combined with the preceding paragraphs, the semiconductor structure further comprises a third dielectric insulator layer located on the bottom surface of the first stacked device, and a fourth dielectric insulator layer located on the bottom surface of the second stacked device.

[0006] In one or more additional exemplary embodiments that may be combined with the preceding paragraphs, the first stacked device and the second stacked device are separated by isolation dielectric pillars.

[0007] In one or more additional exemplary embodiments that may be combined with the preceding paragraphs, the first field-effect transistor further includes a first gate structure, and the second field-effect transistor further includes a second gate structure separated from the first gate structure by the first dielectric insulator layer.

[0008] In one or more additional exemplary embodiments that may be combined with the preceding paragraphs, the semiconductor structure further comprises the first gate structure and a first front gate contact connected to a front back-end-of-the-line layer.

[0009] In one or more additional exemplary embodiments that may be combined with the preceding paragraphs, the semiconductor structure further comprises the second gate structure and a back-side gate contact connected to a back-side back-of-the-line layer.

[0010] In one or more additional exemplary embodiments that may be combined with the preceding paragraphs, the second stacked device further comprises a third gate structure positioned over the third and fourth field-effect transistors.

[0011] In one or more additional exemplary embodiments that may be combined with the preceding paragraphs, the semiconductor structure further comprises the third gate structure and a second front gate contact connected to the front back-end-of-the-line layer.

[0012] In another exemplary embodiment, the semiconductor structure comprises a first stacked device structure having a first field-effect transistor arranged to include a first source / drain region, and a second field-effect transistor vertically stacked above the first field-effect transistor, the second field-effect transistor including a second source / drain region. The first stacked device further comprises a front-facing source / drain contact located on the sidewall and a first portion of the top surface of the second source / drain region, and a first metal via connected to the front-facing source / drain contact and a first back-facing power line. The semiconductor structure further comprises a second stacked device structure adjacent to the first stacked device structure. The second stacked device structure has a third field-effect transistor including a third source / drain region, and a fourth field-effect transistor vertically stacked above the third field-effect transistor, the fourth field-effect transistor including a fourth source / drain region. The second stacked device structure further comprises a first back-side source / drain contact located on the second portion of the sidewall and bottom surface of the third source / drain region, the second metal being a via connected to the first back-side source / drain contact and the back-end ob-the-line layer.

[0013] Advantageously, the semiconductor structure of the exemplary embodiment allows for the formation of a first dielectric insulator layer of a first stacked device having a different width from the second dielectric insulator layer of a second stacked device adjacent to the first stacked device, thereby resulting in both shared gate integration and independent gate devices.

[0014] In one or more additional exemplary embodiments that may be combined with the preceding paragraphs, the third gate structure is a shared gate structure between the third stacked device and the fourth stacked device.

[0015] In one or more additional exemplary embodiments that may be combined with the preceding paragraphs, the semiconductor structure further comprises the third gate structure and a first front gate contact connected to the front back-end-of-the-line layer.

[0016] In one or more additional exemplary embodiments that may be combined with the preceding paragraphs, the semiconductor structure further comprises the first gate structure and a second front gate contact connected to the front back-end-of-the-line layer.

[0017] In one or more additional exemplary embodiments that may be combined with the preceding paragraphs, the semiconductor structure further comprises the second gate structure and a back-side gate contact connected to a back-side back-of-the-line layer.

[0018] In one or more additional exemplary embodiments that may be combined with the preceding paragraphs, the first dielectric insulator layer has a first width, and the second dielectric insulator layer has a second width that is smaller than the first width of the first dielectric insulator layer.

[0019] In one or more additional exemplary embodiments that may be combined with the preceding paragraphs, the first stacked device and the second stacked device are separated by isolation dielectric pillars.

[0020] Another exemplary embodiment comprises an integrated circuit comprising one or more semiconductor structures. At least one of the one or more semiconductor structures is a semiconductor structure described in one or more of the embodiments described above.

[0021] These and other exemplary embodiments will be described in, or will become apparent from, the following detailed description of exemplary embodiments, which will be read in conjunction with the accompanying drawings. [Brief explanation of the drawing]

[0022] Exemplary embodiments will be described in more detail below with reference to the accompanying drawings:

[0023] [Figure 1-1] FIG. 1A is a top view showing a semiconductor structure for use in a first intermediate fabrication stage according to an exemplary embodiment.

[0024] FIG. 1B is a cross-sectional view of the semiconductor structure taken along the X-X axis of FIG. 1A in a first intermediate fabrication stage according to an exemplary embodiment.

[0025] [Figure 1-2] FIG. 1C is a cross-sectional view of the semiconductor structure taken along the Y1-Y1 axis of FIG. 1A in a first intermediate fabrication stage according to an exemplary embodiment.

[0026] FIG. 1D is a cross-sectional view of the semiconductor structure taken along the Y2-Y2 axis of FIG. 1A in a first intermediate fabrication stage according to an exemplary embodiment.

[0027] [Figure 2-1] FIG. 2A is a cross-sectional view of the semiconductor structure taken along the X-X axis of FIG. 1A in a second intermediate fabrication stage according to an exemplary embodiment.

[0028] FIG. 2B is a cross-sectional view of the semiconductor structure taken along the Y1-Y1 axis of FIG. 1A in a second intermediate fabrication stage according to an exemplary embodiment.

[0029] [Figure 2-2] FIG. 2C is a cross-sectional view of the semiconductor structure taken along the Y2-Y2 axis of FIG. 1A in a second intermediate fabrication stage according to an exemplary embodiment.

[0030] [Figure 3-1] FIG. 3A is a cross-sectional view showing the semiconductor structure taken along the X-X axis of FIG. 1A in a third intermediate fabrication stage according to an exemplary embodiment.

[0031] [Figure 3-2] Figure 3B is a cross-sectional view showing a semiconductor structure taken along the Y1-Y1 axis of Figure 1A during a third intermediate fabrication stage, according to an exemplary embodiment.

[0032] Figure 3C is a cross-sectional view showing a semiconductor structure taken along the Y2-Y2 axis of Figure 1A during a third intermediate fabrication stage, according to an exemplary embodiment.

[0033] [Figure 4-1] Figure 4A is a cross-sectional view showing a semiconductor structure taken along the XX axis of Figure 1A during a fourth intermediate fabrication stage, according to an exemplary embodiment.

[0034] Figure 4B is a cross-sectional view showing a semiconductor structure taken along the Y1-Y1 axis of Figure 1A during a fourth intermediate fabrication stage, according to an exemplary embodiment.

[0035] [Figure 4-2] Figure 4C is a cross-sectional view showing a semiconductor structure taken along the Y2-Y2 axis of Figure 1A during a fourth intermediate fabrication stage, according to an exemplary embodiment.

[0036] [Figure 5-1] Figure 5A is a cross-sectional view showing a semiconductor structure taken along the XX axis of Figure 1A during a fifth intermediate fabrication stage, according to an exemplary embodiment.

[0037] [Figure 5-2] Figure 5B is a cross-sectional view showing a semiconductor structure taken along the Y1-Y1 axis of Figure 1A during a fifth intermediate fabrication stage, according to an exemplary embodiment.

[0038] Figure 5C is a cross-sectional view showing a semiconductor structure taken along the Y2-Y2 axis of Figure 1A during a fifth intermediate fabrication stage, according to an exemplary embodiment.

[0039] [Figure 6-1]Figure 6A is a cross-sectional view of a semiconductor structure taken along the XX axis of Figure 1A during the sixth intermediate fabrication stage, according to an exemplary embodiment.

[0040] Figure 6B is a cross-sectional view of a semiconductor structure taken along the Y1-Y1 axis in Figure 1A during the sixth intermediate fabrication stage, according to an exemplary embodiment.

[0041] [Figure 6-2] Figure 6C is a cross-sectional view of a semiconductor structure taken along the Y2-Y2 axis in Figure 1A during the sixth intermediate fabrication stage, according to an exemplary embodiment.

[0042] [Figure 7-1] Figure 7A is a cross-sectional view showing a semiconductor structure taken along the XX axis of Figure 1A during the seventh intermediate fabrication stage, according to an exemplary embodiment.

[0043] [Figure 7-2] Figure 7B is a cross-sectional view showing a semiconductor structure taken along the Y1-Y1 axis of Figure 1A during the seventh intermediate fabrication stage, according to an exemplary embodiment.

[0044] Figure 7C is a cross-sectional view showing a semiconductor structure taken along the Y2-Y2 axis of Figure 1A during the seventh intermediate fabrication stage, according to an exemplary embodiment.

[0045] [Figure 8-1] Figure 8A is a cross-sectional view of a semiconductor structure taken along the XX axis of Figure 1A during the eighth intermediate fabrication stage, according to an exemplary embodiment.

[0046] Figure 8B is a cross-sectional view of a semiconductor structure taken along the Y1-Y1 axis in Figure 1A during the eighth intermediate fabrication stage, according to an exemplary embodiment.

[0047] [Figure 8-2]Figure 8C is a cross-sectional view of a semiconductor structure taken along the Y2-Y2 axis of Figure 1A during the eighth intermediate fabrication stage, according to an exemplary embodiment.

[0048] [Figure 9-1] Figure 9A is a cross-sectional view showing a semiconductor structure taken along the XX axis of Figure 1A during the ninth intermediate fabrication stage, according to an exemplary embodiment.

[0049] [Figure 9-2] Figure 9B is a cross-sectional view showing a semiconductor structure taken along the Y1-Y1 axis of Figure 1A during the ninth intermediate fabrication stage, according to an exemplary embodiment.

[0050] Figure 9C is a cross-sectional view showing a semiconductor structure taken along the Y2-Y2 axis of Figure 1A during the ninth intermediate fabrication stage, according to an exemplary embodiment.

[0051] [Figure 10-1] Figure 10A is a cross-sectional view showing a semiconductor structure taken along the XX axis of Figure 1A during the 10th intermediate fabrication stage, according to an exemplary embodiment.

[0052] Figure 10B is a cross-sectional view showing a semiconductor structure taken along the Y1-Y1 axis of Figure 1A during a tenth intermediate fabrication stage, according to an exemplary embodiment.

[0053] [Figure 10-2] Figure 10C is a cross-sectional view showing a semiconductor structure taken along the Y2-Y2 axis of Figure 1A during a tenth intermediate fabrication stage, according to an exemplary embodiment.

[0054] [Figure 11-1] Figure 11A is a cross-sectional view showing a semiconductor structure taken along the XX axis of Figure 1A during the 11th intermediate fabrication stage, according to an exemplary embodiment.

[0055] [Figure 11-2]Figure 11B is a cross-sectional view showing a semiconductor structure taken along the Y1-Y1 axis of Figure 1A during an eleventh intermediate fabrication stage, according to an exemplary embodiment.

[0056] Figure 11C is a cross-sectional view showing a semiconductor structure taken along the Y2-Y2 axis of Figure 1A during the 11th intermediate fabrication stage, according to an exemplary embodiment.

[0057] [Figure 12-1] Figure 12A is a cross-sectional view showing a semiconductor structure taken along the XX axis of Figure 1A during a twelfth intermediate fabrication stage, according to an exemplary embodiment.

[0058] Figure 12B is a cross-sectional view showing a semiconductor structure taken along the Y1-Y1 axis of Figure 1A during a twelfth intermediate fabrication stage, according to an exemplary embodiment.

[0059] [Figure 12-2] Figure 12C is a cross-sectional view showing a semiconductor structure taken along the Y2-Y2 axis of Figure 1A during a twelfth intermediate fabrication stage, according to an exemplary embodiment.

[0060] [Figure 13-1] Figure 13A is a cross-sectional view showing a semiconductor structure taken along the XX axis of Figure 1A during a thirteenth intermediate fabrication stage, according to an exemplary embodiment.

[0061] [Figure 13-2] Figure 13B is a cross-sectional view showing a semiconductor structure taken along the Y1-Y1 axis of Figure 1A during a thirteenth intermediate fabrication stage, according to an exemplary embodiment.

[0062] Figure 13C is a cross-sectional view showing a semiconductor structure taken along the Y2-Y2 axis of Figure 1A during a thirteenth intermediate fabrication stage, according to an exemplary embodiment.

[0063] [Figure 14-1]Figure 14A is a cross-sectional view showing a semiconductor structure taken along the XX axis of Figure 1A during the 14th intermediate fabrication stage, according to an exemplary embodiment.

[0064] Figure 14B is a cross-sectional view showing a semiconductor structure taken along the Y1-Y1 axis of Figure 1A during a 14th intermediate fabrication stage, according to an exemplary embodiment.

[0065] [Figure 14-2] Figure 14C is a cross-sectional view showing a semiconductor structure taken along the Y2-Y2 axis of Figure 1A during a 14th intermediate fabrication stage, according to an exemplary embodiment.

[0066] [Figure 15-1] Figure 15A is a cross-sectional view showing a semiconductor structure taken along the XX axis of Figure 1A during the 15th intermediate fabrication stage, according to an exemplary embodiment.

[0067] [Figure 15-2] Figure 15B is a cross-sectional view showing a semiconductor structure taken along the Y1-Y1 axis of Figure 1A during a 15th intermediate fabrication stage, according to an exemplary embodiment.

[0068] Figure 15C is a cross-sectional view showing a semiconductor structure taken along the Y2-Y2 axis of Figure 1A during the 15th intermediate fabrication stage, according to an exemplary embodiment.

[0069] [Figure 16-1] Figure 16A is a cross-sectional view showing a semiconductor structure taken along the XX axis of Figure 1A during the 16th intermediate fabrication stage, according to an exemplary embodiment.

[0070] Figure 16B is a cross-sectional view showing a semiconductor structure taken along the Y1-Y1 axis of Figure 1A during the 16th intermediate fabrication stage, according to an exemplary embodiment.

[0071] [Figure 16-2]Figure 16C is a cross-sectional view showing a semiconductor structure taken along the Y2-Y2 axis of Figure 1A during the 16th intermediate fabrication stage, according to an exemplary embodiment.

[0072] [Figure 17-1] Figure 17A is a cross-sectional view showing a semiconductor structure taken along the XX axis of Figure 1A during the 17th intermediate fabrication stage, according to an exemplary embodiment.

[0073] [Figure 17-2] Figure 17B is a cross-sectional view showing a semiconductor structure taken along the Y1-Y1 axis of Figure 1A during the 17th intermediate fabrication stage, according to an exemplary embodiment.

[0074] Figure 17C is a cross-sectional view showing a semiconductor structure taken along the Y2-Y2 axis of Figure 1A during the 17th intermediate fabrication stage, according to an exemplary embodiment. [Modes for carrying out the invention]

[0075] Exemplary embodiments of the present invention can be described herein, in conjunction with exemplary apparatus, structures, and devices formed using such methods, in the context of an exemplary method of forming a first dielectric insulator layer of a first stacked device having a different width from the second dielectric insulator layer of a second stacked device adjacent to a first stacked device, thereby resulting in both a shared gate integration and independent gate devices. However, it will be understood that embodiments of the present invention are not limited to exemplary methods, apparatus, structures, and devices, but are rather more broadly applicable to other suitable methods, apparatus, structures, and devices.

[0076] Please understand that the various layers, structures, and regions shown in the attached drawings are schematic diagrams and not drawn to scale. Furthermore, for the sake of simplicity, one or more types of layers, structures, and regions commonly used to form semiconductor devices or structures may not be explicitly shown in the given drawings. This does not imply that any layers, structures, and regions not explicitly shown are omitted from actual semiconductor structures.

[0077] Furthermore, the same or similar reference numerals are used throughout the drawings to indicate the same or similar features, elements, or structures, and therefore, detailed descriptions of the same or similar features, elements, or structures are not repeated for each of the drawings. In addition, the terms “exemplary” and “illustrative,” as used herein, mean “serving as an example, case, or illustration.” Any embodiment or design described herein as “exemplary” or “illustrative” should not be construed as being preferable or advantageous to other embodiments or designs.

[0078] Furthermore, it should be understood that the embodiments discussed herein are not limited to the specific materials, features, and processing steps shown and described herein. In particular, with respect to semiconductor processing steps, it should be emphasized that the descriptions provided herein are not intended to encompass all processing steps that may be required to form a functional semiconductor integrated circuit device. Rather, some processing steps commonly used in forming semiconductor devices, such as wet cleaning and annealing steps, are intentionally omitted herein for the sake of brevity. It should be understood that the terms “about” or “substantially” used herein with respect to thickness, width, percentage, range, etc., mean that they are close or approximate, but not exact. For example, the terms “about” or “substantially” used herein suggest that there may be small errors, such as 1% or less of the stated quantity.

[0079] In this specification, any reference to “one embodiment” or “an embodiment” of the Principle and any other variations thereof means that certain features, structures, properties, etc., described in relation to that embodiment are included in at least one embodiment of the Principle. Accordingly, the appearance of the phrases “in one embodiment” or “in an embodiment” and any other variations, which appear in various places throughout this specification, does not necessarily all refer to the same embodiment. The term “positioned on top” means that a first element, such as a first structure, is located on a second element, such as a second structure, and an intervening element, such as an interface structure or interface layer, may be located between the first and second elements. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected at the interface between the two elements without any intermediate conductive, insulating, or semiconductor layer.

[0080] The terms "first," "second," etc., may be used in this specification to describe various elements, but it will be understood that these elements should not be limited by these terms. These terms are used solely to distinguish one element from another. Thus, the first element discussed below may be referred to as the second element without deviating from the scope of this concept.

[0081] As used herein, “height” refers to the vertical size of an element (e.g., a layer, trench, hole, opening, etc.) in a cross-sectional view, measured from the bottom to the top of the element and / or relative to the surface on which the element is located. Conversely, “depth” refers to the vertical size of an element (e.g., a layer, trench, hole, opening, etc.) in a cross-sectional view, measured from the top to the bottom of the element. Terms such as “thick,” “thickness,” “thin,” or their derivatives may be used instead of “height” when explicitly stated.

[0082] As used herein, “width” or “length” refers to the size of an element in a drawing (e.g., a layer, trench, hole, opening, etc.) measured from one side to the opposite surface of that element. Terms such as “thick,” “thickness,” “thin,” or their derivatives may be used instead of “width” or “length” if explicitly stated.

[0083] In the IC chip manufacturing industry, there are three sections typically mentioned in IC chip construction: the front-end-of-line (FEOL), the back-end-of-line (BEOL), and the middle-of-line (MOL), which connects these two sections to each other. The FEOL consists of semiconductor devices, such as transistors; the BEOL consists of interconnects and wiring; and the MOL is the interconnect between the FEOL and the BEOL, including materials to prevent the diffusion of BEOL metal into the FEOL devices. Therefore, the exemplary embodiments described herein may focus on BEOL semiconductor processing and construction. The BEOL is the second part of IC fabrication, where individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring on the wafer, such as a metallization layer or multiple metallization layers. The BEOL includes contacts, insulating layers (dielectrics), metal levels, and junctions for connecting the chip to the package. In the BEOL, fabrication stage contacts (pads), interconnect wires, vias, and parts of the dielectric structure are formed. For the latest IC processes, more than 10 metal layers can be added within the BEOL (Below-Earth Layer).

[0084] The embodiments described below may be applicable to FEOL processing and structure, BEOL processing and structure, or both FEOL and BEOL processing and structure. In particular, exemplary processing schemes may be shown using FEOL processing scenarios, but such methods may also be applicable to BEOL processing. Similarly, exemplary processing schemes may be shown using BEOL processing scenarios, but such methods may also be applicable to FEOL processing.

[0085] Current stacked FETs utilize a dielectric insulator layer of uniform width between transistors. Consequently, current stacked FETs do not enable both shared-gate integration and independent-gate devices. Therefore, there is a need to form a stacked FET that does not suffer from the above drawbacks. Accordingly, the non-limiting exemplary embodiments described herein overcome the drawbacks discussed above by forming a first dielectric insulator layer of a first stacked device having a different width from the second dielectric insulator layer of a second stacked device adjacent to the first stacked device, thereby enabling both shared-gate integration and independent-gate devices.

[0086] Referring to Figures 1A to 17C, Figure 1A shows a top view of semiconductor structure 100. The first side section view in Figure 1B is taken along line XX in the top view of Figure 1A, the second side section view in Figure 1C is taken along line Y1-Y1 in the top view of Figure 1A, and the third side section view in Figure 1D is taken along line Y2-Y2 in the top view of Figure 1A.

[0087] The semiconductor structure 100 shows a substrate 102. The substrate 102 can be formed with any suitable semiconductor structure, including, but not limited to, various silicon-containing materials such as silicon (Si), silicon germanium (SiGe), silicon germanium carbide (SiGeC), silicon carbide (SiC), and multilayers thereof. Although silicon is the semiconductor material primarily used in wafer fabrication, alternative semiconductor materials such as, but not limited to, germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), SiGe, cadmium telluride (CdTe), and zinc selenide (ZnSe) may be used as additional layers. In one exemplary embodiment, the substrate 102 is silicon.

[0088] An etching stop layer 104 is formed within the substrate 102. The etching stop layer 104 may include another suitable material such as a buried oxide (BOX) layer, silicon germanium (SiGe), or a III-V semiconductor epitaxial layer.

[0089] Nanosheet stacks 116-1 and 116-2 are formed on a substrate 102, each containing nanosheet devices 112-1 and 112-2. Nanosheet devices 112-1 and 112-2 include sacrificial layers 106-1 and 106-2 (collectively, sacrificial layer 106), sacrificial layers 108-1 and 108-2 (collectively, sacrificial layer 108), and nanosheet channel layers 110-1 and 110-2 (collectively, nanosheet channel layer 110).

[0090] Sacrificial layers 106 and 108 are, exemplary, formed of different sacrificial materials so that they can be selectively etched or otherwise removed relative to each other. In some embodiments, both sacrificial layers 106 and 108 are formed from SiGe, but having different proportions of Ge. For example, sacrificial layer 106 may have a relatively high proportion of Ge (e.g., 55% Ge), and sacrificial layer 108 may have a relatively low proportion of Ge (e.g., 25% Ge). In other embodiments, other combinations of different sacrificial materials may be used.

[0091] In non-limiting exemplary embodiments, the nanosheet channel layer 110-1 has a first width, and the nanosheet channel layer 110-2 has a second width smaller than the first width (see Figures 1C and 1D).

[0092] The nanosheet channel layer 110 may be formed of Si or another suitable material (for example, a material similar to that used for the substrate 102).

[0093] Nanosheet stacks 116-1 and 116-2 are formed by depositing a hard mask (HM) layer 114, followed by lithography and etching. The HM layer 114 may consist of a multilayer of silicon nitride (SiN), SiN and SiO2, or another suitable material.

[0094] Figures 2A to 2C illustrate the semiconductor structure 100 in the second intermediate fabrication stage. During this stage, a mask layer 118 (e.g., an organic planarization layer (OPL) or spin-on-carbon (SOC)) is deposited on the semiconductor structure 100 using any conventional deposition process, such as spin-on coating or any other suitable deposition process. Next, the mask layer 118 is patterned to remove the exposed portions of the sacrificial layer 106-2 of the nanosheet stack 116-2, and then selectively etched using, for example, reactive ion etching (RIE).

[0095] Figures 3A to 3C show the semiconductor structure 100 in the third intermediate fabrication stage. During this stage, the mask layer 118 is removed using any conventional technique such as ashing. Next, as shown in Figures 3B and 3C, isolation dielectric pillars 120 are formed by first depositing dielectric material on the semiconductor structure 100 using any conventional deposition technique such as physical vapor deposition (PVD), atomic layer deposition (ALD), or chemical vapor deposition (CVD). Then, an etch-back process such as wet etching is performed to remove the dielectric material from the semiconductor structure 100, leaving the isolation dielectric pillars 120 between the nanosheet stacks 116-1 and 116-2. Suitable dielectric materials include, for example, SiN, SiO2, SiOC, SiOCN, SiBCN, SiC, etc.

[0096] Figures 4A to 4C show the semiconductor structure 100 in the fourth intermediate fabrication stage. During this stage, shallow trench isolation (STI) regions 122 may be formed on the substrate 102. The STI regions 122 comprise a dielectric material such as silicon oxide or silicon oxynitride and are formed by methods known in the art. For example, in one exemplary embodiment, the STI region 122 is a shallow trench isolation oxide layer. The HM layer 114 can then be removed by any suitable etching technique.

[0097] Figures 5A to 5C show the semiconductor structure 100 in the fifth intermediate fabrication stage. During this stage, a dummy gate 124 can be filled onto the structure, after which patterning is performed using a gate hard mask (HM) layer 126. The dummy gate 124 may be formed by blanket deposition of the dummy gate material (e.g., amorphous silicon (a-Si) or amorphous silicon germanium (a-SiGe) on a thin SiO2 or titanium nitride (TiN) layer, or another suitable material) and the material for the gate HM layer 126 (e.g., silicon nitride (SiN), a multilayer of SiN and SiO2, or another suitable material) followed by lithography, thereby producing the patterned gate HM layer 126 and the underlying dummy gate 124 as shown in Figures 5A and 5C.

[0098] Figures 6A to 6C show the semiconductor structure 100 in the sixth intermediate fabrication stage. During this stage, the sacrificial layer 106 is removed using any suitable selective etching process. For example, first, the sacrificial layer 106-1 can be removed to form an opening 128, and then the sacrificial layer 106-2 can be removed to form an opening 130.

[0099] Figures 7A to 7C show the semiconductor structure 100 in the seventh intermediate fabrication stage. During this stage, a bottom dielectric insulator (BDI) layer 132-1, a middle dielectric insulator (MDI) layer 132-2, and a sidewall spacer 134 are formed. The BDI layer 132-1 and the MDI layer 132-2 (collectively, the dielectric insulator layer 132) can be formed from any suitable insulator or dielectric material such as SiN, silicon boron carbide nitride (SiBCN), or silicon oxycarbonite (SiOCN). The BDI layer 132-1 is formed in the region previously occupied by the sacrificial layer 106-1, and the MDI layer 132-2 is formed in the region previously occupied by the sacrificial layer 106-2, and may have similar sizing to the sacrificial layer.

[0100] In a non-limiting exemplary embodiment, as shown in Figure 7C, the MDI layer 132-2 between nanosheet devices 112-1 and 112-2 of the nanosheet stack 116-1 is formed with a first width, and the MDI layer 132-2 between nanosheet devices 112-1 and 112-2 of the nanosheet stack 116-2 is formed with a second width smaller than the first width. In an exemplary embodiment, the first width of the MDI layer 132-2 between nanosheet devices 112-1 and 112-2 of the nanosheet stack 116-1 is the same width as the nanosheet channel layer 110-1 of nanosheet device 112-1, and the second width of the MDI layer 132-2 between nanosheet devices 112-1 and 112-2 of the nanosheet stack 116-2 is the same width as the nanosheet channel layer 110-2 of nanosheet device 112-2.

[0101] The sidewall spacer 134 may be formed from the same material as that of the BDI layer 132-1. In one embodiment, the sidewall spacer 134 is formed from the same insulating or dielectric material as the BDI layer 132-1, such as SiN or SiBCN.

[0102] Figures 8A to 8C show the semiconductor structure 100 in the eighth intermediate fabrication stage. During this stage, the lower source / drain region 136, the lower interlevel dielectric (ILD) layer 138, the upper source / drain region 140, the upper ILD layer 142, and the inner spacer 144 are formed. In an exemplary embodiment, the lower source / drain region 136 is first formed on the substrate 102, then the lower ILD layer 138 is deposited on the lower source / drain region 136 and the STI region 122, then the upper source / drain region 140 is formed, then the upper ILD layer 142 is deposited on the upper source / drain region 140, the lower ILD layer 138, and covering the isolation dielectric pillar 120, and then polyopen CMP is performed to expose the dummy gate 124.

[0103] The lower source / drain region 136 and the upper source / drain region 140 may be formed using an epitaxial growth process. The lower source / drain region 136 and the upper source / drain region 140 may be appropriately doped using methods such as ion implantation, gas-phase doping, plasma doping, plasma immersion ion implantation, cluster doping, infusion doping, liquid-phase doping, and solid-phase doping. The N-type dopant may be selected from the group consisting of phosphorus (P), arsenic (As), and antimony (Sb), and the p-type dopant may be selected from the group consisting of boron (B), boron fluoride (BF2), gallium (Ga), indium (In), and thallium (Tl). In some embodiments, the epitaxy process includes in-situ doping (the dopant is incorporated into the epitaxy material during epitaxy).

[0104] Epitaxial materials can be grown from gaseous or liquid precursors. Epitaxial materials can be grown using vapor-phase epitaxy (VPE), molecular-beam epitaxy (MBE), liquid-phase epitaxy (LPE), rapid thermal chemical vapor deposition (RTCVD), metal organic chemical vapor deposition (MOCVD), ultra-high vacuum chemical vapor deposition (UHVCVD), low-pressure chemical vapor deposition (LPCVD), limited reaction processing CVD (LRPCVD), or other suitable processes. Epitaxial silicon, silicon germanium (SiGe), germanium (Ge), and / or carbon-doped silicon (Si:C) can be doped in situ during deposition by adding dopants such as n-type dopants (e.g., phosphorus or arsenic) or p-type dopants (e.g., boron or gallium), depending on the type of transistor being formed. The dopant concentration in the source / drain region is 1 x 10⁻¹⁶. 19 cm -3 From 3x10 21 cm -3 up to, or preferably 2x10 20 cm -3 From 3x10 21 cm -3 It could be within a range of [something].

[0105] The lower ILD layer 138 and the upper ILD layer 142 can be formed separately from any suitable separating material such as SiO2, SiOC, or SiON.

[0106] The inner spacers 144 may be formed to fill in indent spaces (for example, resulting from indent etching them before removing the sacrificial layers 108). The inner spacers 144 may be formed from silicon nitride (SiN), or another suitable material such as SiBCN, silicon carbide (SiCO), or SiOCN.

[0107] Figures 9A to 9C show the semiconductor structure 100 in the ninth intermediate fabrication stage. During this stage, the dummy gate 124 and sacrificial layer 108 are removed, and then a replacement gate 146 is formed (for example, using a replacement HKMG process). The replacement gate 146 includes a gate stack layer which may comprise a gate dielectric layer and a gate conductor layer. The gate dielectric layer may be formed from a high-k dielectric material. Examples of high-k materials include, but are not limited to, metal oxides such as HfO2, hafnium silicon oxide (Hf-Si-O), hafnium silicon oxynitride (HfSiON), lanthanum oxide (La2O3), aluminum lanthanum oxide (LaAlO3), zirconium oxide (ZrO2), zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide (Ta2O5), titanium oxide (TiO2), barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide (Y2O3), aluminum oxide (Al2O3), lead scandium tantalum oxide, and lead zinc niobate. High-k materials may further include dopants such as lanthanum (La), aluminum (Al), and magnesium (Mg). The gate dielectric layer may have a uniform thickness in the range of 1 nm to 3 nm.

[0108] The gate conductor layer may include a metallic gate or a work function metal (WFM). WFMs for the gate conductor layer may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), aluminum (Al), titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), combinations of Ti and Al alloys, or stacks containing a barrier layer (e.g., TiN, TaN, etc.) followed by one or more of the aforementioned WFM materials. It should be understood that various other materials may be used for the gate conductor layer as desired.

[0109] Figures 10A to 10C show the semiconductor structure 100 in the tenth intermediate fabrication stage. During this stage, a first gate cut is performed through the replacement gate 146 to expose a portion of the STI region 122 (see Figure 10C). The gate cut is performed using a standard lithography and etching process, such as RIE.

[0110] Figures 11A-11C show the semiconductor structure 100 in the 11th intermediate fabrication stage. During this stage, a second gate cut is performed through the replacement gate 146 to expose a portion of the MDI layer 132-2 between the nanosheet devices 112-1 and 112-2 of the nanosheet stack 116-1, leaving the MDI layer 132-2 between the nanosheet devices 112-1 and 112-2 of the nanosheet stack 116-2 within the replacement gate 146 (see Figure 11C). The gate cut is performed using a standard lithography and etching process, such as RIE.

[0111] Figures 12A to 12C show the semiconductor structure 100 in the twelfth intermediate fabrication stage. During this stage, a dielectric fill 148 is deposited in the opening, followed by a planarization process such as CMP. The dielectric fill 148 can be deposited using any conventional deposition technique such as PVD, ALD, or CVD. Suitable dielectric materials for the dielectric fill 148 include, for example, SiO2.

[0112] Figures 13A to 13C show the semiconductor structure 100 in the 13th intermediate fabrication stage. During this stage, the front upper source / drain contact 150, the front lower source / drain contact 152, and the front gate contact 154 are formed. For example, in an exemplary embodiment, a mask layer is first deposited on the semiconductor structure 100, and then the upper source / drain contact opening and the lower source / drain contact opening are formed in at least one mask layer using a conventional lithography and etching process such as RIE. Next, a high-conductance metal is deposited in the upper source / drain contact opening and the lower source / drain contact opening to form the front upper source / drain contact 150 and the front lower source / drain contact 152, respectively. Suitable high-conductance metals may include, for example, silicide liners such as Ti, Ni, NiPt, followed by adhesive metal liners such as TiN, and metal filler materials such as tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), ruthenium (Ru), molybdenum (Mo), or any other suitable conductive material. In various embodiments, the high-conductance metal may be deposited by ALD, CVD, PVD, and / or plating. The high-conductance metal may be planarized using a planarization process such as CMP. Other planarization processes may include grinding and polishing.

[0113] The front gate contact 154 can be formed by utilizing conventional lithography and etching processes at least within the upper ILD layer 142, followed by the deposition of a high-conductance metal as discussed above. The high-conductance metal can be planarized using a planarization process such as CMP. Other planarization processes may include grinding and polishing.

[0114] Next, a front-side back-end obline (BEOL) structure 156 is formed on the semiconductor structure 100, and then the structure (e.g., the front-side BEOL structure 156) is bonded to the carrier wafer 158. The front-side BEOL structure 156 includes various BEOL interconnection structures. The carrier wafer 158 may be formed from a material similar to that of the substrate 102 and may be formed on the front-side BEOL structure 156 using a wafer bonding process such as dielectric-dielectric bonding.

[0115] Figures 14A to 14C show the semiconductor structure 100 in the 14th intermediate fabrication stage. During this stage, a portion of the substrate 102 may be selectively removed from the back side by using, for example, substrate grinding, CMP and wet etching until the etching stop layer 104 is reached. This can be achieved, for example, by inverting the semiconductor structure 100 using the carrier wafer 158 so that the back side (i.e., the back surface) of the substrate 102 is facing upwards.

[0116] Figures 15A to 15C illustrate the semiconductor structure 100 in the 15th intermediate fabrication stage. During this stage, the etching stop layer 104 is selectively removed by selectively removing the etching stop layer 104 until the substrate 102 is reached, for example using wet etching. Next, the remaining portion of the substrate 102 is removed to expose the BDI layer 132-1, the isolation dielectric pillar 120, the STI region 122, and the lower source / drain region 136. The remaining portion of the substrate 102 may be removed using a selective etching process such as wet etching.

[0117] Figures 16A to 16C show the semiconductor structure 100 in the 16th intermediate fabrication stage. During this stage, the back ILD layer 160, the back source / drain contacts 162, and the back gate contacts 164 are formed. The back ILD layer 160 may be formed using the same material and process as the lower ILD layer 138. The material for the back ILD layer 160 may be overfilled first and then planarized (e.g., using CMP).

[0118] Next, for example, a mask layer may be deposited on the semiconductor structure 100, and then a source / drain contact opening may be formed in the back surface ILD layer 160 using a conventional lithography and etching process such as RIE within at least one mask layer, thereby forming a back surface source / drain contact 162. Next, a high-conductance metal may be deposited in the source / drain contact opening to form each back surface source / drain contact 162. The suitable conductive metal may be any of the metals discussed above. The high-conductance metal may be planarized using a planarization process such as CMP. Other planarization processes may include grinding and polishing.

[0119] The back gate contact 164 can be formed by utilizing conventional lithography and etching processes at least within the back ILD layer 160, followed by the deposition of a high-conductance metal as discussed above. The high-conductance metal can be planarized using a planarization process such as CMP. Other planarization processes may include grinding and polishing.

[0120] Figures 17A to 17C show the semiconductor structure 100 in the 17th intermediate fabrication stage. During this stage, a back-end ob-line (BEOL) structure 166 is formed on the semiconductor structure 100, including back-end source / drain contacts 162 and back-end gate contacts 164, based on the creation of a wiring scheme that is arranged on both sides of the device layer (front-end ob-line structure).

[0121] The semiconductor devices and methods for forming them using the techniques described above can be employed in a variety of applications, hardware, and / or electronic systems. Suitable hardware and systems for implementing embodiments of the present invention may include, but are not limited to, personal computers, communication networks, e-commerce systems, portable communication devices (e.g., mobile phones and smartphones), solid-state media storage devices, and functional circuits. Systems and hardware incorporating semiconductor devices are intended embodiments of the present invention. Given the teachings provided herein, those skilled in the art will be able to envision other implementations and applications of embodiments of the present invention.

[0122] In some embodiments, the techniques described above are used in relation to semiconductor devices that require, or may utilize, CMOS, MOSFET, and / or FinFET technology, for example. As a non-limiting example, the semiconductor devices may include, but are not limited to, CMOS, MOSFET, and FinFET devices, and / or semiconductor devices that utilize CMOS, MOSFET, and / or FinFET technology.

[0123] The various structures described above may be implemented in integrated circuits. The resulting integrated circuit chips may be distributed by the manufacturer in the form of raw wafers (i.e., as a single wafer with multiple unpackaged chips), as bare dies, or in packaged form. In the latter case, the chips are mounted in a single chip package (e.g., a plastic carrier with leads attached to a motherboard or other higher-level carrier) or in a multi-chip package (e.g., a ceramic carrier with either or both surface interconnects or embedded interconnects). In either case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of either: (a) an intermediate product, e.g., a motherboard, or (b) a final product. The final product may be any product containing integrated circuit chips, ranging from toys and other low-end applications to displays, keyboards or other input devices, and advanced computer products with central processing units.

[0124] The descriptions of various embodiments of the present invention are presented for illustrative purposes only and are not intended to be exhaustive or limitful to the disclosed embodiments. Many modifications and variations will become apparent to those skilled in the art without departing from the scope of the embodiments described. The terminology used herein has been selected to best describe the principles, practical applications, or technical improvements to the technologies available on the market, or to enable other those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A first stack-type device, A first field-effect transistor comprising one or more first nanosheet layers; A second field-effect transistor vertically stacked above the first field-effect transistor, the second field-effect transistor comprising one or more second nanosheet layers; and A first dielectric insulator layer is positioned between the first field-effect transistor and the second field-effect transistor, and the first dielectric insulator layer has a first width. A first stacked device having; and A second stack-type device adjacent to the first stack-type device, wherein the second stack-type device is A third field-effect transistor comprising one or more third nanosheet layers; A fourth field-effect transistor vertically stacked above the third field-effect transistor, the fourth field-effect transistor comprising one or more fourth nanosheet layers; and A second dielectric insulator layer is positioned between the third field-effect transistor and the fourth field-effect transistor, and the second dielectric insulator layer has a second width smaller than the first width of the first dielectric insulator layer. A second stack-type device having A semiconductor structure comprising the features described above.

2. The semiconductor structure according to claim 1, wherein the first width of the first dielectric insulator layer is equal to the third width of the one or more second nanosheet layers, and the second width of the second dielectric insulator layer is equal to the fourth width of the one or more third nanosheet layers.

3. The semiconductor structure according to claim 1 or claim 2, further comprising a third dielectric insulator layer disposed on the bottom surface of the first stacked device, and a fourth dielectric insulator layer disposed on the bottom surface of the second stacked device.

4. The semiconductor structure according to any prior claim, wherein the first stacked device and the second stacked device are separated by isolation dielectric pillars.

5. The semiconductor structure according to any prior claim, wherein the first field-effect transistor further comprises a first gate structure, and the second field-effect transistor further comprises a second gate structure separated from the first gate structure by a first dielectric insulator layer.

6. The semiconductor structure according to claim 5, further comprising the first gate structure and a first front gate contact connected to the front back-end-of-the-line layer.

7. The semiconductor structure according to claim 6, further comprising the second gate structure and a back-side gate contact connected to the back-side back-of-the-line layer.

8. The semiconductor structure according to any prior claim, wherein the second stacked device further comprises a third gate structure arranged to cover the third field-effect transistor and the fourth field-effect transistor.

9. The semiconductor structure according to claim 8, further comprising the third gate structure and a second front gate contact connected to the front back-end-of-the-line layer.

10. A first stack-type device, A first field-effect transistor including a first gate structure; A second field-effect transistor is stacked vertically above the first field-effect transistor, the second field-effect transistor including a second gate structure; and A first dielectric insulator layer positioned between the first field-effect transistor and the second field-effect transistor, separating the first gate structure from the second gate structure; A first stack-type device having, A second stack-type device adjacent to the first stack-type device, wherein the second stack-type device is The third field-effect transistor; A fourth field-effect transistor stacked vertically above the third field-effect transistor; A second dielectric insulator layer positioned between the third field-effect transistor and the fourth field-effect transistor; and The third field-effect transistor, the fourth field-effect transistor, and the third gate structure arranged to cover the second dielectric insulator layer. A second stack-type device having A semiconductor structure comprising the features described above.

11. The semiconductor structure according to claim 10, wherein the third gate structure is a shared gate structure between the third field-effect transistor and the fourth field-effect transistor.

12. The semiconductor structure according to claim 11, further comprising the third gate structure and a first front gate contact connected to the front back-end-of-the-line layer.

13. The semiconductor structure according to claim 12, further comprising the first gate structure and a second front gate contact connected to the front back-end-of-the-line layer.

14. The semiconductor structure according to claim 13, further comprising the second gate structure and a back-side gate contact connected to the back-side back-of-the-line layer.

15. The semiconductor structure according to any one of claims 10 to 14, wherein the first dielectric insulator layer has a first width, and the second dielectric insulator layer has a second width smaller than the first width of the first dielectric insulator layer.

16. The semiconductor structure according to any one of claims 10 to 15, wherein the first stacked device and the second stacked device are separated by an isolation dielectric pillar.

17. The first field-effect transistor comprises one or more first nanosheet layers; The second field-effect transistor comprises one or more second nanosheet layers; The third field-effect transistor comprises one or more third nanosheet layers; and The fourth field-effect transistor comprises one or more fourth nanosheet layers. The semiconductor structure according to any one of claims 10 to 16.

18. One or more semiconductor structures, wherein at least one of the one or more semiconductor structures is A first stack-type device, A first field-effect transistor including a first gate structure; A second field-effect transistor is stacked vertically above the first field-effect transistor, the second field-effect transistor including a second gate structure; and A first dielectric insulator layer positioned between the first field-effect transistor and the second field-effect transistor, separating the first gate structure from the second gate structure; A first stacked device, and A second stack-type device adjacent to the first stack-type device, wherein the second stack-type device is The third field-effect transistor; A fourth field-effect transistor stacked vertically above the third field-effect transistor; A second dielectric insulator layer positioned between the third field-effect transistor and the fourth field-effect transistor; and The third field-effect transistor, the fourth field-effect transistor, and the third gate structure arranged to cover the second dielectric insulator layer. A second stacked device including One or more semiconductor structures having An integrated circuit comprising:

19. The integrated circuit according to claim 18, wherein at least one of the one or more semiconductor structures further comprises a first front gate contact connected to the third gate structure and a front back-end-of-the-line layer.

20. The integrated circuit according to claim 19, wherein at least one of the one or more semiconductor structures further comprises a second front gate contact connected to the first gate structure and the front back-end-of-the-line layer, and a back gate contact connected to the second gate structure and the back back-end-of-the-line layer.

21. The integrated circuit according to any one of claims 18 to 20, wherein the first dielectric insulator layer has a first width, and the second dielectric insulator layer has a second width smaller than the first width of the first dielectric insulator layer.

22. The first field-effect transistor comprises one or more first nanosheet layers; The second field-effect transistor comprises one or more second nanosheet layers; The third field-effect transistor comprises one or more third nanosheet layers; and The fourth field-effect transistor comprises one or more fourth nanosheet layers. The semiconductor structure according to any one of claims 18 to 21.

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