Semiconductor structure and method for manufacturing the same, electronic device
The described method simplifies the manufacturing of vertical-channel transistors by using mask layers to pattern sacrificial layers and etch grooves, reducing complexity and costs while improving performance through precise channel control.
JP2026521882APending Publication Date: 2026-07-02BEIJING SUPERSTRING ACAD OF MEMORY TECH
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- BEIJING SUPERSTRING ACAD OF MEMORY TECH
- Filing Date
- 2023-12-01
- Publication Date
- 2026-07-02
AI Technical Summary
Technical Problem
The manufacturing process of vertical-channel transistors is complex and costly due to the need for retaining mandrels and spacers during the formation of the gate electrode layer, which complicates the etching process and increases production costs.
Method used
A method for manufacturing semiconductor structures involves forming a first mask layer on a stacked structure, using it to pattern a sacrificial layer, and then etching to create grooves and gate electrode layers, simplifying the process and reducing material requirements.
Benefits of technology
This method reduces process complexity and costs by minimizing the number of etching cycles and material needs, while allowing precise control over channel length and electrode alignment, enhancing semiconductor performance.
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Figure 2026521882000001_ABST
Abstract
This application relates to semiconductor structures and methods for manufacturing the same, and electronic devices, as disclosed herein, and relates to the semiconductor technology field. The method involves providing a base, forming a first stacked structure (104) on the base, forming a first mask layer (112) on the first stacked structure (104), forming a first sacrificial layer (218) on the first stacked structure (104) using the first mask layer (112) as a mask, and removing the first mask layer (112) and alternately forming a second mask layer (114) on the first sacrificial layer (218). The process includes removing the exposed first sacrificial layer (218) using the second mask layer (114) as a mask, removing a portion of the channel sacrificial layer (204) by lateral etching to form the first groove (306) and the channel layer (116), removing the second mask layer (114), removing the remaining channel sacrificial layer (204) by lateral etching to form the second groove (310) and the gate electrode layer (120) surrounding the channel layer (116). This reduces the requirements for mask layer material, is cost-effective, and simplifies the manufacturing process.
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