Electronic Devices

Abstract

Provided is an electronic device that increases the impedance value by increasing the distance between a signal processing circuit in a semiconductor die and a reference voltage terminal, thereby preventing a decrease in the choke effect and thereby reducing harmonics. [Solution] The electronic device includes a substrate (100), a semiconductor die (110), an adhesive layer (120), and a first wiring layer (130). The substrate has a first surface (s1) and a second surface (s2). The semiconductor die is bonded to the first surface of the substrate and includes a signal processing circuit (111). The adhesive layer is disposed between the semiconductor die and the first surface of the substrate. The first wiring layer is disposed between the adhesive layer and the first surface of the substrate, and an orthogonal projection of the signal processing circuit onto the first surface may or may not overlap the first wiring layer.

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor technology, and more particularly to electronic devices. [Background technology]

[0002] In semiconductor dies, the choke effect of the bulk of the transistor has a significant impact on harmonics. If the bulk choke performance is reduced by the parasitic capacitance of the base supporting the semiconductor die (including, for example, the buried oxide layer, trap rich layer, handle wafer, etc.), harmonics increase, which in turn reduces the linearity of the transistor. Summary of the Invention

[0003] The electronic device of the present disclosure includes a substrate, a semiconductor die, an adhesive layer, and a first wiring layer. The substrate has a first surface and a second surface. The semiconductor die is bonded to the first surface of the substrate. The semiconductor die includes a signal processing circuit. The adhesive layer is disposed between the semiconductor die and the first surface of the substrate. The first wiring layer is disposed between the adhesive layer and the first surface of the substrate, and an orthogonal projection of the signal processing circuit onto the first surface may or may not overlap the first wiring layer.

[0004] To make the features and advantages of the present disclosure more readily understandable, specific embodiments will now be described in detail with reference to the drawings. [Brief explanation of the drawings]

[0005] [Figure 1] FIG. 1 is a top view of an electronic device according to a first embodiment of the present disclosure. [Figure 2] FIG. 2 is a schematic cross-sectional view taken along line XX′ in FIG. 1. [Figure 3] FIG. 2 is a top view of an electronic device according to a second embodiment of the present disclosure. [Figure 4] FIG. 4 is a schematic cross-sectional view taken along line XX′ in FIG. 3. [Figure 5] FIG. 10 is a top view of an electronic device according to a third embodiment of the present disclosure. [Figure 6]FIG. 6 is a schematic cross-sectional view taken along line XX′ in FIG. 5. [Figure 7] FIG. 10 is a top view of an electronic device according to a fourth embodiment of the present disclosure. [Figure 8] FIG. 10 is a top view of an electronic device according to a fifth embodiment of the present disclosure. [Figure 9] 1 is a schematic diagram of a cross section of a substrate in an electronic device according to some embodiments of the present disclosure. [Figure 10] 10A to 10C are diagrams illustrating a manufacturing process of an electronic device according to a sixth embodiment of the present disclosure. [Figure 11] FIG. 10 is a schematic diagram of a circuit effect according to a comparative example. [Figure 12] FIG. 1 is a schematic diagram of a circuit effect according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0006] Fig. 1 is a top view of an electronic device according to a first embodiment of the present disclosure, with some components omitted for simplicity. Fig. 2 is a schematic cross-sectional view taken along line X-X' in Fig. 1. Fig. 11 is a schematic diagram of a circuit effect according to a comparative example. Fig. 12 is a schematic diagram of a circuit effect according to one embodiment of the present disclosure.

[0007] See FIGS. 1 and 2. The electronic device of the first embodiment includes at least one substrate 100, a semiconductor die 110, an adhesive layer 120, and a first wiring layer 130. The substrate 100 has a first surface s1 and a second surface s2. In the first embodiment, the substrate 100 may be a single-layer structure such as, but not limited to, a printed circuit board core, a land grid array core, or other non-conductive substrate such as a fiberglass substrate or a ceramic substrate. The semiconductor die 110 is bonded to the first surface s1 of the substrate 100, and the semiconductor die 110 includes a signal processing circuit 111. In some embodiments, the signal processing circuit 111 may include a single transistor or multiple transistors, such as transistor M2 shown in FIG. 12. In some embodiments, the signal processing circuit 111 is used primarily for processing AC signals, and may be, for example, a switch, a power amplifier, a low-noise amplifier, a mixer, a voltage-controlled oscillator, or a combination thereof. The other portion of the semiconductor die 110 is used, for example, primarily to process non-AC signals (e.g., DC signals) and may include, but is not limited to, digital circuits, bias circuits, and other circuits (e.g., control or logic circuits). Next, an adhesive layer 120 is disposed between the semiconductor die 110 and the first surface s1 of the substrate 100. A protective layer 140, such as a solder mask made of a polymer insulating material, may also be disposed between the adhesive layer 120 and the first surface s1 of the substrate 100. The protective layer 140 is used to protect a first wiring layer 130 on the first surface s1 of the substrate 100. The first wiring layer 130 is disposed between the adhesive layer 120 and the first surface s1, and the material of the first wiring layer 130 is a conductor, such as a metal, such as gold, copper, or silver. In other words, the portion of the substrate 100 not covered by the first wiring layer 130 is the insulating region 102. The orthogonal projection of the signal processing circuit 111 onto the first surface s1 does not overlap with the first wiring layer .

[0008] Generally, a transistor included in a signal processing circuit (e.g., transistor M1 in FIG. 11 or transistor M2 in FIG. 12) processes (e.g., amplifies, blocks / conducts, etc.) a fundamental frequency signal in the form of an alternating current and also generates unwanted harmonics. See FIG. 11. In a typical architecture, the signal processing circuit of a semiconductor die includes, for example, transistor M1. Transistor M1 has, for example, a gate G, a drain D, a source S, and a bulk B. Bulk B may have a choke effect that blocks current. Furthermore, the base of the semiconductor die (which may include, for example, a buried oxide layer, a trap rich layer, a handle wafer, etc., though not shown) may have parasitic effects such as parasitic capacitance CP and parasitic resistance RP connected in parallel between bulk B of transistor M1 and the reference voltage terminal shown in FIG. 11. The impedance value generated by such parasitic effects is insufficient to block current. As a result, current easily flows into the reference voltage terminal along path P, worsening the choke effect and thus increasing harmonics.

[0009] Next, please refer to FIGS. 2 and 12. In the architecture of the embodiment of FIG. 2, the signal processing circuit 111 of the semiconductor die 110 includes, for example, a transistor M2. The transistor M2 has, for example, a gate G, a drain D, a source S, and a bulk B. To address the problem of excessive reduction in impedance value due to parasitic effects leading to an increase in harmonics, the embodiment of FIG. 2 is configured such that the orthogonal projections of the first wiring layer 130, which can essentially be considered a reference voltage terminal, and the signal processing circuit 111 onto the first surface s1 do not overlap. In other words, because the first wiring layer 130 is not located directly below the signal processing circuit 111 in the embodiment of FIG. 2, the distance between the signal processing circuit 111 and the reference voltage terminal in the semiconductor die 110 is increased, thereby increasing the overall impedance value. Furthermore, the equivalent impedance generated by the configuration of the embodiment of FIG. 2 is R', as shown in FIG. 12. In the configuration of the embodiment of FIG. 2, a capacitor CE and a resistor RE are connected in parallel, as shown in FIG. 12. At frequencies in the megahertz (MHz) range, the parallel-connected parasitic capacitance C P and parasitic resistance R P can be approximated as a capacitor, and the parallel-connected capacitors C E and R E can also be approximated as a capacitor. In other words, the impedance value is dominated by the capacitor. Therefore, in the architecture of FIG. 12 , the parasitic capacitance C P, parasitic resistance R P, capacitor C E, and resistor R E can be approximated as two capacitors connected in series, which reduces the overall capacitance value and potentially increases the equivalent impedance R′. For example, when the area of ​​a single transistor is 15.96 μm × 645.16 μm, the total impedance value generated by a single transistor using a typical architecture, including parasitic effects, is approximately 450 kΩ. However, the total impedance value generated by a transistor using the architecture of the embodiment of FIG. 2 and FIG. 12 can be greater than 450 kΩ, e.g., 1 MΩ. Furthermore, when the area of ​​a single transistor is 15.96 μm × 645.16 μm, the total impedance value generated by a single transistor using the architecture of the embodiment of FIG. 2 and FIG. 12 can be greater than 450 kΩ, e.g., 1 MΩ. 2 Impedance per unit is 43.7Ω / μm 2, which may be larger than the reference impedance. An increase in the total impedance value indicates a reduction in the influence of parasitic capacitance, preventing the choke effect and thereby reducing harmonics. The electronic device of the present disclosure is suitable for applications at relatively low frequencies in the megahertz range, such as radio frequency (RF) architectures, for example, applications with a fundamental frequency of 170 MHz or less. In other embodiments, the electronic device of the present disclosure can also be applied to frequencies above 170 MHz. In the first embodiment, when the fundamental frequency is 65 MHz, in terms of the absolute power of harmonic energy, the second harmonic energy generated by the general architecture (in which the orthogonal projections of the first wiring layer 130 and the signal processing circuit 111 onto the first surface s1 completely overlap) is 12 times or more greater than the second harmonic energy generated by the architecture of the embodiment of FIG. 2. When the fundamental frequency is 170 MHz, in terms of the absolute power of harmonic energy, the second harmonic energy generated by the general architecture is 5 times or more greater than the second harmonic energy generated by the architecture of the embodiment of FIG. 2.

[0010] In some embodiments, the adhesive layer 120 is typically an insulating material such as epoxy, die attach film (DAF), or other insulating material. The thickness of the semiconductor die 110 may be 100 μm or more. In some embodiments, the thickness t1 of the adhesive layer 120 may be set to 30 μm or more, such as 35 μm or more, or 50 μm or more. Compared to a semiconductor die with a typical structure (e.g., an adhesive layer 120 having a thickness of less than 30 μm), the distance between the signal processing circuit 111 and the reference voltage terminal in a semiconductor die with a thicker adhesive layer 120 (e.g., a thickness of 30 μm or more) is also increased, resulting in the formation of a capacitor CE and a resistor RE, as shown in FIG. 12 . Referring to the above description, the overall capacitance value may decrease, which may increase the equivalent impedance R′.

[0011] Referring again to FIG. 2 , in some embodiments, the second wiring layer 150 may be disposed on the second surface s2 of the substrate 100, and the material of the second wiring layer 150 may be a conductor, such as a metal, such as gold, copper, or silver. At least a portion of the second wiring layer 150 may function as a reference voltage terminal. Note that in the embodiment of FIG. 2 , the orthogonal projections of the first wiring layer 130 and the signal processing circuit 111 onto the first surface s1 do not overlap. Therefore, in the embodiment of FIG. 2 , the first wiring layer 130 does not function as a reference voltage terminal, and at least a portion of the second wiring layer 150 functions as a reference voltage terminal. Compared to the first wiring layer 130 functioning as a reference voltage terminal, the second wiring layer 150 functioning as a reference voltage terminal increases the distance between the signal processing circuit 111 and the reference voltage terminal, thereby increasing the overall impedance value.

[0012] 2 , a plurality of vias 152 may be disposed in the substrate 100 to connect the first wiring layer 130 and the second wiring layer 150. Electrical connection between the semiconductor die 110 and the underlying first wiring layer 130 may be achieved by connecting a plurality of lead wires 112 from the semiconductor die 110 to the first wiring layer 130 by wire bonding, and the first wiring layer 130 may be electrically connected to the second wiring layer 150 through the vias 152. However, the present disclosure is not limited thereto. Furthermore, an encapsulation layer 160 may be formed on the first surface s1 of the substrate 100 to cover at least the lead wires 112 and the semiconductor die 110, and further cover the adhesive layer 120, the first wiring layer 130, and the protective layer 140. The encapsulation layer 160 may be formed using a molding material such as epoxy resin or other suitable material.

[0013] Fig. 3 is a top view of an electronic device according to a second embodiment of the present disclosure, with some components omitted for simplification. Fig. 4 is a schematic cross-sectional view taken along line X-X' in Fig. 3. In Figs. 3 and 4, the same reference symbols as in the first embodiment are used to indicate the same or similar components, and the omitted technical descriptions, such as the position, material, and formation method of each layer or space, can be found in the relevant content of the first embodiment, and will not be repeated here.

[0014] See Figures 3 and 4. The electronic device of the second embodiment differs from the electronic device of the first embodiment in that the first wiring layer 130 further includes a first wiring layer 300 located below the semiconductor die 110. As a result, the orthogonal projection of the signal processing circuit 111 onto the first surface s1 partially overlaps with the first wiring layer 300. Note that "partial overlap" means that the overlapping area between the orthogonal projection of the signal processing circuit 111 onto the first surface s1 and the first wiring layer 300 accounts for more than 0% but not more than 90% of the area of ​​the orthogonal projection of the signal processing circuit 111 onto the first surface s1. Because the region directly below the signal processing circuit 111 is not completely blocked by the first wiring layer 300, the overall impedance value can still be increased, and the effect of reducing harmonics can still be achieved.

[0015] Fig. 5 is a top view of an electronic device according to a third embodiment of the present disclosure, with some components omitted for simplification. Fig. 6 is a schematic cross-sectional view taken along line X-X' in Fig. 5. In Figs. 5 and 6, the same reference numerals as in the first embodiment are used to indicate the same or similar components. For omitted technical descriptions such as the position, material, and formation method of each layer or space, please refer to the relevant content of the first embodiment, and they will not be repeated here.

[0016] 5 and 6. The electronic device of the third embodiment differs from the first embodiment in that the protective layer 140 has a cavity 600. The cavity 600 at least partially overlaps the orthogonal projection of the signal processing circuit 111 onto the first surface s1. The cavity 600 contains air or vacuum, and the relative permittivity (ε r) is lower than the relative permittivity of a solid medium, reducing the capacitance and increasing the overall impedance value, thereby helping to reduce harmonics. In the third embodiment, when the fundamental frequency is 65 MHz, in terms of absolute power of harmonic energy, the second harmonic energy generated by the general architecture (a configuration in which the orthogonal projections of the first wiring layer 130 and the signal processing circuit 111 onto the first surface s1 completely overlap) is 79 times or more greater than the second harmonic energy generated by the architecture of the embodiment of FIG. 6. When the fundamental frequency is 170 MHz, in terms of absolute power of harmonic energy, the second harmonic energy generated by the general architecture is 1.9 times or more greater than the second harmonic energy generated by the architecture of the embodiment of FIG. 6.

[0017] 7 is a top view of an electronic device according to a fourth embodiment of the present disclosure. Here, the same reference numerals as those in the third embodiment are used to denote the same or similar components. Regarding omitted technical descriptions such as the position, material, and formation method of each layer or space, please refer to the relevant content of the third embodiment, and therefore will not be repeated here.

[0018] See Figure 7. The electronic device of the fourth embodiment differs from the first embodiment in that the substrate 100 has a cavity 700 recessed inward from the first surface s1, the cavity 700 at least partially overlaps the orthogonal projection of the signal processing circuit 111 onto the first surface s1, and the cavity 700 can be connected to the cavity 600 of the protective layer 140. Since the cavity 700 contains air or vacuum, its relative dielectric constant (ε r ) is lower than the relative permittivity of the solid medium, reducing capacitance and increasing the overall impedance value, thereby helping to reduce harmonics.

[0019] 8 is a top view of an electronic device according to a fifth embodiment of the present disclosure. Here, the same reference numerals as those in the third embodiment are used to denote the same or similar components. Regarding omitted technical descriptions such as the position, material, and formation method of each layer or space, please refer to the relevant content of the third embodiment, and therefore will not be repeated here.

[0020] See Figure 8. The electronic device of the fifth embodiment differs from the third embodiment in that the substrate 100 includes a plurality of air vias 800 penetrating the first surface s1 and the second surface s2, and these air vias 800 are connected to the cavities 600 of the protective layer 140. This further reduces the capacitance, increases the overall impedance value, improves the choke effect, and reduces harmonics.

[0021] FIG. 9 is a schematic diagram of a cross section of a substrate in an electronic device according to some embodiments of the present disclosure.

[0022] Please refer to FIG. 9. A substrate in the present invention may have a multilayer structure such as the illustrated substrate 900. The substrate 900 has a first surface s1 and a second surface s2. The positional relationship with other components in the electronic device can be referenced from the above-described embodiment, and will not be repeated here. The substrate 900 includes multiple sublayers 9001-9004, multiple intermediate wiring layers 910, and multiple intermediate material layers 920 provided between the sublayers 9001-9004. The intermediate wiring layer 910 is made of a conductive material such as a metal, such as gold, copper, or silver, and the intermediate material layer 920 is made of an insulating material (e.g., prepreg). The positions of the intermediate wiring layer 910 and the first wiring layer 930 when orthogonally projected onto the first surface s1 are approximately the same, but the intermediate material layer 920 is configured to correspond to the insulating region 902. In other words, the orthogonal projection of the signal processing circuit 111 (see also FIG. 2 ) onto the first surface s1 may or may not overlap with the first wiring layer 930, and the orthogonal projection of the signal processing circuit 111 onto the first surface s1 may or may not overlap with the orthogonal projection onto the first surface s1 of the intermediate wiring layer 910. In this way, instead of regarding the first wiring layer 930 or the intermediate wiring layer 910 as the reference voltage terminal, the signal processing circuit 111 regards the second wiring layer 950 directly below as the reference voltage terminal, which increases the distance between the signal processing circuit 111 and the reference voltage terminal, which may increase the overall impedance value.

[0023] FIG. 10 is a manufacturing process diagram of an electronic device according to the sixth embodiment of the present disclosure.

[0024] Referring to step S100, a substrate is provided, such as substrate 100 having a first surface s1 and a second surface s2, as shown in Figure 2. In some embodiments, to further increase the impedance value, the first surface s1 of substrate 100 can be etched to form a cavity 700, as shown in Figure 7. In some embodiments, to further increase the impedance value, air vias 800 can be formed in substrate 100, as shown in Figure 8, which can be formed by, but are not limited to, laser drilling or mechanical drilling.

[0025] Referring to step S102 and FIG. 2 , a first wiring layer 130 is formed on a first surface s1 of the substrate 100, the first surface s1 having an insulating region 102 that is not covered by the first wiring layer 130. The position of the first wiring layer 130 is offset from or does not overlap with the position of the signal processing circuitry in the semiconductor die to be subsequently bonded. In another embodiment, the step of forming the first wiring layer 130 includes simultaneously forming a first wiring layer 300, as shown in FIG. 4 . For example, a conductive layer may be deposited over the entire surface of the first surface s1, and then the conductive layer may be patterned by etching or other means to obtain the first wiring layer 130 and the first wiring layer 300. In some embodiments, as shown in FIG. 2 , a via 152 may be formed in the substrate 100, and a second wiring layer 150 may be formed on a second surface s2 of the substrate 100.

[0026] See step S104 and FIG. 1. An adhesive layer is formed on the insulating region 102 and the first wiring layer 130. The adhesive layer is formed, for example, by repeatedly applying an adhesive. In some embodiments, the thickness t1 of the adhesive layer 120 may be 30 μm or more, as shown in FIG. 2, for example. In some embodiments, a thinner adhesive layer 120 can be formed when the adhesive is applied only once.

[0027] Before the bonding step, a protective layer 140 can be formed on the first wiring layer 130 with reference to FIG. 2, or a protective layer 140 having a cavity 600 can be formed on the first wiring layer 130 with reference to FIG. 6.

[0028] 1 and 2. The semiconductor die 110 is bonded to the first wiring layer 130 of the substrate 100, and the orthogonal projection of the signal processing circuit 111 included in the semiconductor die 110 onto the first surface s1 may completely overlap the insulating region 102. In other embodiments, the orthogonal projection of the signal processing circuit 111 partially overlaps the insulating region 102.

[0029] 2 may be formed by wire bonding. Additionally, an encapsulation layer 160 may be formed on the first surface s1 of the substrate 100 to encapsulate the underlying structure.

[0030] In summary, the electronic device and the manufacturing method thereof according to the embodiments of the present disclosure can increase the impedance value by increasing the distance between the signal processing circuitry in the semiconductor die and the reference voltage terminal, thereby preventing a decrease in the choke effect and thereby reducing harmonics.

Claims

1. An electronic device, the electronic device comprising: a substrate having a first surface and a second surface; a semiconductor die bonded to the first surface of the substrate, the semiconductor die including signal processing circuitry; an adhesive layer disposed between the semiconductor die and the first surface of the substrate; a first wiring layer disposed between the adhesive layer and the first surface of the substrate; an orthogonal projection of the signal processing circuit onto the first surface partially overlaps or does not overlap the first wiring layer; Electronic devices.

2. The electronic device of claim 1 , wherein an orthogonal projection of the semiconductor die onto the first surface does not overlap the first wiring layer.

3. The electronic device of claim 1 , wherein an orthogonal projection of the semiconductor die onto the first surface partially overlaps the first wiring layer.

4. The electronic device of claim 1 , wherein the substrate has a cavity recessed inward from the first surface, the cavity at least partially overlapping an orthogonal projection of the signal processing circuitry onto the first surface.

5. 2. The electronic device of claim 1, further comprising a protective layer disposed on the first wiring layer, the protective layer having a cavity, the cavity at least partially overlapping an orthogonal projection of the signal processing circuit onto the first surface.

6. The electronic device of claim 5 , wherein the substrate further includes a plurality of air vias penetrating the first surface and the second surface, the air vias connecting to the cavity.

7. The electronic device according to claim 1 , wherein the adhesive layer has a thickness of 30 μm or more.

8. The electronic device of claim 1 , wherein the signal processing circuitry comprises a switch, a power amplifier, a low noise amplifier, a mixer, a voltage controlled oscillator, or a combination thereof.

9. a second wiring layer disposed on the second surface of the substrate; The electronic device according to claim 1 , further comprising: a via disposed in the substrate and connecting the first wiring layer and the second wiring layer.

10. 10. The electronic device of claim 9, wherein the semiconductor die is electrically connected to the second wiring layer through a plurality of leads wire-bonded to the first wiring layer, the first wiring layer, and the vias.

11. The electronic device according to claim 9 , wherein at least a portion of the second wiring layer functions as a reference voltage terminal.

12. The electronic device of claim 1 , wherein the substrate comprises a single layer structure or a multi-layer structure.

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