Memory module

Abstract

This memory module offers improved compatibility with small outline dual inline memory modules, reducing costs while maintaining signal integrity and high-frequency operation, improving fit into low-power compressed-connectivity memory modules, and increasing motherboard space. [Solution] The present invention is a memory module 1 including a main board 10, the main board including a first pin area 20 having a plurality of pins electrically connected to a first double data rate memory chip 30. The first operating voltage of the first double data rate memory chip is 1.05 volts or less, and the first transfer speed of the first double data rate memory chip is 6400 MT / s or more.

Description

Technical Field

[0001] The present invention relates to a memory module, and more particularly to a memory module suitable for a Small Outline Dual In-line Memory Module (SO-DIMM) and a Low Power Compression Attached Memory Module (LPCAMM), which includes double data rate memory chips with an operating voltage of 1.05 volts or less and a transfer speed of 6400 MT / s or more.

Background Art

[0002] LPDDR5 (Low Power Double Data Rate 5) is a memory specification specially designed for mobile devices and other similar platforms with low power consumption and high performance. The advantages of low voltage and energy-saving operation of the LPDDR series also lead to a significant improvement in data transfer speed, and can support applications that require high-bandwidth data transfer, such as mobile phones, thin and light notebook computers, embedded systems, and edge computing devices.

[0003] LPDDR5 memory has a low operating voltage and adopts a plurality of power-saving mechanisms such as deep sleep mode and dynamic bandwidth adjustment, so that it is possible to suppress power consumption while simultaneously requiring higher performance.

[0004] Since LPDDR5 memory is extremely sensitive to signal integrity and wiring distance, LPDDR5 memory in existing common implementation methods is packaged in a ball grid array package and soldered directly to the main circuit board of a mobile device for implementation to ensure optimal performance. However, in existing common implementation methods, compatibility is sacrificed, resulting in limitations in memory maintenance and expansion.

[0005] SO-DIMM (Small Outline Dual In-Line Memory Module) is a miniaturized dual in-line memory module commonly used in computers with limited space, such as laptops, minicomputers, and industrial control equipment. The slot-type design of SO-DIMMs allows users to easily install and replace memory modules in their systems, increasing system maintainability and upgrade flexibility.

[0006] SO-DIMMs typically conform to DDR memory standards, employing fixed pin definitions and module sizes to ensure better compatibility. While SO-DIMM wiring distances are longer than those of memory directly soldered to the motherboard, SO-DIMMs maintain high-frequency operational stability by strictly defining signal specifications.

[0007] Therefore, if LPDDR5 memory can be mounted on a SO-DIMM printed circuit board, the problems associated with LPDDR5 memory directly soldered to the mainboard can be solved, providing not only interchangeability but also maintenance and expansion options. Thus, providing a memory module that allows LPDDR5 memory to be mounted on a SO-DIMM memory circuit board via a customized pin configuration while maintaining signal integrity and high-frequency operation is a problem that those skilled in the art would like to solve. [Overview of the project] [Problems that the invention aims to solve]

[0008] The objective of this invention is to provide a memory module that enhances compatibility with small outline dual inline memory modules by combining a fifth-generation low-power double data rate (LPDDR5) memory chip with a customized pin configuration. By simply bringing the motherboard wiring as close as possible to the central processing unit (CPU), interchangeability can be improved, costs reduced, and signal integrity and high-frequency operation can be maintained. Furthermore, by combining the LPDDR5 memory chip with a customized pin configuration, the ability to accommodate low-power compressed-connectivity memory modules can be improved, increasing the space available on the motherboard. [Means for solving the problem]

[0009] To achieve the above objective, the present invention provides a memory module including a main board. The main board includes a first pin area, a first double data rate (DDR) memory chip, and a positioning notch. The first pin area is located at the edge of the main board and comprises a plurality of first data pins and a plurality of first command control pins adjacent to the plurality of first data pins. The first double data rate (DDR) memory chip is electrically connected to the plurality of first data pins and the plurality of first command control pins. The positioning notch is located at the edge of the main board. The first DDR memory chip has a first operating voltage of 1.05 volts or less and a first transfer speed of 6400 MT / s or more. By combining the LPDDR5 memory chip with a customized pin configuration, the memory module according to the present invention has improved compatibility with small outline dual inline memory modules and improved convenience for module assembly and disassembly.

[0010] In one embodiment of the present invention, the main board is a main circuit board corresponding to a small outline dual inline memory module.

[0011] In one embodiment of the present invention, the main board further comprises a plurality of first power pins located at the end of the main board and a plurality of first clock pins located at the end of the main board.

[0012] In one embodiment of the present invention, the main board further includes a second pin region and a second DDR memory chip. The second pin region is located at the end of the main board and is positioned opposite the positioning notch to the first pin region, and comprises a plurality of second data pins and a plurality of second command control pins adjacent to the plurality of second data pins. The second DDR memory chip is electrically connected to the plurality of second data pins and the plurality of second command control pins. The second DDR memory chip has a second operating voltage of 1.05 volts or less and a second transfer speed of 6400 MT / s or more.

[0013] In one embodiment of the present invention, the main board further includes a third pin region and a first universal flash storage (UFS) memory chip. The third pin region is located at the end of the main board and is positioned opposite the second pin region with respect to the positioning notch, and comprises a plurality of second power pins, a plurality of third data pins adjacent to the plurality of second power pins, and a plurality of second clock pins adjacent to the plurality of third data pins. The first universal flash storage (UFS) memory chip is located adjacent to the second DDR memory chip and is electrically connected to the plurality of second power pins, the plurality of third data pins, and the plurality of second clock pins.

[0014] To achieve the above objective, the present invention provides a memory module including a main board. The main board includes a first pin area and a first double data rate memory chip. The first pin area is located on the surface of the main board and comprises a plurality of first data pins and a plurality of first command control pins adjacent to the plurality of first data pins. The first double data rate memory chip is located on another surface of the main board and is electrically connected to the plurality of first data pins and the plurality of first command control pins. The first double data rate memory chip has a first operating voltage of 1.05 volts or less and a first transfer rate of 6400 MT / s or more. By combining the LPDDR5 memory chip with a customized pin configuration, the memory module according to the present invention has improved compatibility with low-power compressed connection memory modules and improved convenience for module assembly and disassembly.

[0015] In one embodiment of the present invention, the main board is the main circuit board of a low-power compressed connection memory module.

[0016] In one embodiment of the present invention, the main board further includes a fourth pin region and a second UFS memory chip. The fourth pin region is located on the surface of the main board and comprises a plurality of third power pins, a plurality of fourth data pins adjacent to the plurality of third power pins, and a plurality of third clock pins adjacent to the plurality of fourth data pins. The second UFS memory chip is located adjacent to the first DDR memory chip and is electrically connected to the plurality of third power pins, the plurality of fourth data pins, and the plurality of third clock pins.

[0017] In one embodiment of the present invention, the main board further includes a plurality of fourth power pins arranged on the surface of the main board, and a power management integrated circuit (PMIC) chip arranged adjacent to the first DDR memory chip and electrically connected to the fourth power pins.

[0018] Therefore, the present invention provides a memory module that can be mounted on a small outline dual inline memory module or a low power compression connection memory module, overcoming the problems that those skilled in the art desire to solve.

Brief Description of the Drawings

[0019] [Figure 1] It is a schematic structural diagram of the memory module according to the present invention.

[0020] [Figure 2] It is a schematic structural diagram of the memory module according to the present invention.

[0021] [Figure 3] It is a schematic structural diagram of the memory module according to the present invention.

[0022] [Figure 4] It is a schematic structural diagram of the memory module according to the present invention.

Modes for Carrying Out the Invention

[0023] In order to better understand the features and effects achieved by the present invention, preferred embodiments and detailed descriptions are shown below.

[0024] Since the low power double data rate (LPDDR) memory chip is designed for mobile devices, it is currently used in mobile devices and other similar platforms with low power consumption and high performance. The currently used LPDDR5 memory chip has a significantly improved data transfer speed compared to previous generations, especially exceeding 6400 MT / s, so the LPDDR5 memory chip can support applications that require high bandwidth.

[0025] The memory module according to the present invention can be used for a small outline dual inline memory module (SO-DIMM) and a low power compression connection memory module (LPCAMM) by having a customized pin arrangement. The memory module according to the present invention can further enhance the storage capacity and further expand the application range of the LPDDR memory chip by combining with a flash memory chip. Furthermore, the SO-DIMM eliminates the need to adhere or screw the memory module to the motherboard, facilitates the replacement of the memory module, and facilitates the modification of the hardware.

[0026] Hereinafter, the present invention will be described in detail based on the drawings showing various embodiments. However, the concept of the present invention can be implemented in many different forms and should not be construed as being limited to the exemplary embodiments described herein.

[0027] First, the structure of the memory module according to the present invention will be described. Refer to FIG. 1. FIG. 1 is a schematic structural diagram of the memory module according to the present invention. As shown in the figure, the memory module 1 according to the present invention will be described in detail. The memory module 1 is used to connect to a socket adjacent to the central processing unit and includes a main board 10. The main board 10 includes a first pin region 20 arranged at an end of the main board 10, the first pin region 20 including a plurality of first data pins 22 and a plurality of first command control pins 24 adjacent to the first data pins 22, and a first double data rate (DDR) memory chip 30 electrically connected to the first data pins 22 and the first command control pins 24. The first DDR memory chip 30 has a first operating voltage of 1.05 volts or less and a first transfer speed of 6400 MT / s or more. In this embodiment, the first DDR memory chip 30 is an LPDDR5 memory chip.

[0028] Continuing from the above, in this embodiment, the main board 10 is a main circuit board for a 262-pin SO-DIMM. By mounting the LPDDR5 memory chip on the main circuit board of the SO-DIMM, the SO-DIMM allows for easy installation of the LPDDR5 memory on the motherboard without the use of fasteners such as screws or adhesives. The LPDDR5 memory can be installed and removed using clips specifically designed for SO-DIMMs. Furthermore, the cost of SO-DIMMs is lower, and signal integrity and high-frequency operation can be maintained simply by bringing the wiring on the motherboard as close to the CPU as possible.

[0029] Continuing from the above, in this embodiment, the main board 10 further comprises a plurality of first power supply pins 13 located at the edge of the main board 10 and a plurality of first clock pins 15 located at the edge of the main board 10. The first power supply pins 13 are used to provide power signals to the memory module 1, and the first clock pins 15 are used to provide clock signals to the memory module 1. In this embodiment, the positions of these pins are for illustrative purposes only and do not necessarily indicate that they are arranged in the same order.

[0030] Next, another embodiment will be described below. Refer to Figure 2. Figure 2 is a schematic diagram of the structure of a memory module according to the present invention. As shown in the figure, the memory module 1 according to the present invention will be described in detail below. The memory module 1 includes a main board 10, the main board 10 and includes a first pin area 20 located at the end of the main board 10, which has a plurality of first data pins 22 and a plurality of first command control pins 24 located adjacent to the first data pins 22; a second pin area 40 located at the end of the main board 10, which has a plurality of second data pins 42 and a plurality of second command control pins 44 located adjacent to the second data pins 42; a first DDR memory chip 30 electrically connected to the first data pins 22 and the first command control pins 24; and a second DDR memory chip 50 located adjacent to the first DDR memory chip 30 and electrically connected to the second data pins 42 and the second command control pins 44. The first DDR memory chip 30 has a first operating voltage of 1.05 volts or less and a first transfer speed of 6400 MT / s or more. The second DDR memory chip 50 has a second operating voltage of 1.05 volts or less and a second transfer speed of 6400 MT / s or more. In this embodiment, both the first and second DDR memory chips 30 and 50 are LPDDR5 memory chips.

[0031] Continuing from the above, in this embodiment, the main board 10 is the main circuit board for a 262-pin small outline dual inline memory (SO-DIMM). By mounting the LPDDR5 memory chip on the main circuit board of the SO-DIMM for mounting to the motherboard, the main circuit board of the SO-DIMM can be attached to the motherboard more easily without the need for screws or adhesive. In other words, SO-DIMM eliminates the need to glue or screw the memory module to the motherboard. It can be attached and removed using a clip specifically designed for SO-DIMM. Furthermore, SO-DIMM is less expensive and can maintain signal integrity and high-frequency operation simply by bringing the wiring on the motherboard as close to the CPU as possible.

[0032] Continuing from the above, in this embodiment, the main board 10 further comprises a plurality of first power supply pins 13 located at the edge of the main board 10 and a plurality of first clock pins 15 located at the edge of the main board 10. The first power supply pins 13 are used to provide the respective power signals to the memory module 1, and the first clock pins 15 are used to provide the respective clock signals to the memory module 1. In this embodiment, the positions of these pins are for illustrative purposes only and do not necessarily indicate that they are arranged in the same order.

[0033] Next, another embodiment will be described below. Refer to Figure 3. Figure 3 is a schematic diagram of the structure of a memory module according to the present invention. As shown in the figure, the memory module 1 according to the present invention will be described in detail below. The memory module 1 includes a main board 10. The main board 10 includes a first pin area 20 located at the end of the main board 10, which has a plurality of first data pins 22 and a plurality of first command control pins 24 adjacent to the first data pins 22; a second pin area 40 located at the end of the main board 10, which has a plurality of second data pins 42 and a plurality of second command control pins 44 adjacent to the second data pins 42; a positioning notch 17 located between the first pin area 20 and the second pin area 40; and a third pin area 60 located on the side of the second pin area 40, opposite to the positioning notch 17, which has a plurality of second power supply pins 62, second The memory includes a third pin area 60 having a plurality of third data pins 64 adjacent to the power supply pin 62, and a plurality of second clock pins 66 adjacent to the third data pins 64; a first DDR memory chip 30 electrically connected to the first data pin 22 and the first command control pin 24; a second DDR memory chip 50 adjacent to the first DDR memory chip 30 and electrically connected to the second data pin 42 and the second command control pin 44; and a first universal flash storage (UFS) memory chip 70 adjacent to the second DDR memory chip 50 and electrically connected to the second power pin 62, the third data pin 64, and the second clock pin 66. The first DDR memory chip 30 has a first operating voltage of 1.05 volts or less and a first transfer speed of 6400 MT / s or more. The second DDR memory chip 50 has a second operating voltage of 1.05 volts or less and a second transfer speed of 6400 MT / s or more. In this embodiment, the first DDR memory chip 30 and the second DDR memory chip 50 are LPDDR5 memory chips.

[0034] Following the above, in this embodiment, the first UFS memory chip 70 refers to a solid-state drive (SSD) using ball grid array (BGA) packaging technology. A single chip consisting of a complete SSD controller and non-volatile flash memory chips is included within the scope of the first UFS memory chip 70, and the first UFS memory chip 70 may further include an embedded multimedia card (EMMC) in which the flash memory and controller are integrated.

[0035] Continuing from the above, in this embodiment, the main board 10 is a SO-DIMM board having 262 pins. By combining LPDDR5 memory chips and UFS memory chips on the SO-DIMM motherboard, the LPDDR5 memory can be attached to the motherboard more easily without requiring screws or adhesive. In other words, SO-DIMM eliminates the need to glue or screw memory modules to the motherboard. It can be attached and removed using SO-DIMM-specific clips. Furthermore, SO-DIMM is less expensive and can maintain signal integrity and high-frequency operation simply by bringing the motherboard wiring as close as possible to the central processing unit (CPU).

[0036] Continuing from the above, in this embodiment, the main board 10 further comprises a plurality of first power supply pins 13 located at the edge of the main board 10 and a plurality of first clock pins 15 located at the edge of the main board 10. The first power supply pins 13 are used to provide the respective power signals to the memory module 1, and the first clock pins 15 are used to provide the respective clock signals to the memory module 1. In this embodiment, the positions of these pins are for illustrative purposes only and do not necessarily indicate that they are arranged in the same order.

[0037] Next, another embodiment will be described below. Refer to Figure 4. Figure 4 is a schematic diagram of the structure of a memory module according to the present invention. As shown in the figure, the memory module 1 according to the present invention will be described in detail. The memory module 1 includes a main board 10. The main board 10 includes a first pin area 20 located on the surface of the main board 10, which has a plurality of first data pins 22 and a plurality of first command control pins 24 adjacent to the first data pins 22, and a first DDR memory chip 30 located on another surface of the main board 10, which is electrically connected to the first data pins 22 and the first command control pins 24. The first DDR memory chip 30 has a first operating voltage of 1.05 volts or less and a first transfer speed of 6400 MT / s or more. In this embodiment, the first DDR memory chip 30 is an LPDDR5 memory chip.

[0038] Continuing from the above, in this embodiment, the main board 10 is the main circuit board for the low-power compressed connection memory module 2 (LPCAMM2) having 408 pins. By mounting the LPDDR5 memory chip on the main circuit board of the LCAMM2, further space on the motherboard of the entire system can be saved.

[0039] Continuing from the above, in this embodiment, the main board 10 further includes a fourth pin area 80 located on the surface of the main board 10, the fourth pin area 80 comprising a plurality of third power pins 82, a plurality of fourth data pins 84 adjacent to the third power pins 82, and a plurality of third clock pins 86 adjacent to the fourth data pins 84, and a second UFS memory chip 90 adjacent to the first DDR memory chip 30 and electrically connected to the third power pins 82, the fourth data pins 84, and the third clock pins 86. In this embodiment, the positions of these pins are for illustrative purposes only and do not necessarily indicate that they are arranged in the same order. The second UFS memory chip 90 is an SSD packaged by BGA packaging technology for storing data. All complete SSD controllers and single chips consisting of non-volatile flash memory chips are included within the scope of the second UFS memory chip 90, and the second UFS memory chip 90 may further include an EMMC in which the flash memory and controller are integrated.

[0040] Continuing from the above, in this embodiment, the main board 10 further comprises a plurality of fourth power supply pins 102 arranged on the surface of the main board 10, and a power management integrated circuit chip (PMIC) 100 arranged adjacent to the first DDR memory chip 30 and electrically connected to the fourth power supply pins 102. The PMIC 100 is used to perform power management on the main board 10 and integrates a plurality of power management functions.

[0041] In summary, through the embodiments described above, the present invention provides a memory module that employs an LPDDR5 memory chip mounted on a SO-DIMM or LPCAM main circuit board, and further uses a UFS memory chip as a storage unit. This makes it easier to combine LPDDR5 memory chips with SO-DIMMs and use customized pin configurations. Module assembly and disassembly are simplified, and costs are reduced. Furthermore, by combining LPDDR5 memory chips with LPCAMs and enabling the use of customized pin configurations, space on the motherboard is increased, and the range of applications for LPDDR5 memory chips is broadened.

[0042] The above description is merely a preferred embodiment of the present invention, and equivalent modifications and alterations made within the scope of the utility model registration claims of the present invention shall be included within the scope of the present invention.

Claims

1. A memory module used to connect to a socket adjacent to a central processing unit, The aforementioned memory module includes the main board, The main board includes a first pin area, a first double data rate memory chip, and a positioning notch. The first pin region is located at the edge of the main board. The first pin region is, Multiple first data pins, A plurality of first command control pins adjacent to the plurality of first data pins, Equipped with, The first double data rate memory chip is electrically connected to the plurality of first data pins and the plurality of first command control pins, The positioning notch is located at the end of the main board, The first double data rate memory chip has a first operating voltage of 1.05 volts or less and a first transfer speed of 6400 MT / s or more. Memory module.

2. The memory module according to claim 1, wherein the main board is a main circuit board corresponding to a small outline dual inline memory module.

3. The aforementioned main board is A plurality of first power pins located at the end of the main board, A plurality of first clock pins located at the end of the main board, Furthermore, The memory module according to claim 2.

4. The main board further includes a second pin area and a second double data rate memory chip. The second pin region is located at the end of the main board and is positioned opposite the positioning notch to the first pin region. The aforementioned second pin region is, Multiple second data pins, A plurality of second command control pins adjacent to the plurality of second data pins, Equipped with, The second double data rate memory chip is adjacent to the first double data rate memory chip and is electrically connected to the plurality of second data pins and the plurality of second command control pins. The second double data rate memory chip has a second operating voltage of 1.05 volts or less and a second transfer speed of 6400 MT / s or more. The memory module according to claim 2.

5. The main board further includes a third pin area and a first universal flash storage memory chip. The third pin region is located at the end of the main board and is positioned opposite the second pin region with respect to the positioning notch. The pin area of ​​BADD 3 is, Multiple second power pins, A plurality of third data pins adjacent to the plurality of second power pins, A plurality of second clock pins adjacent to the plurality of third data pins, Equipped with, The first universal flash storage memory chip is positioned adjacent to the second double data rate memory chip and is electrically connected to the plurality of second power pins, the plurality of third data pins, and the plurality of second clock pins. The memory module according to claim 4.

6. A memory module including a main board, The main board includes a first pin area and a first double data rate memory chip. The first pin region is located on the surface of the main board. The first pin region is, Multiple first data pins, A plurality of first command control pins adjacent to the plurality of first data pins, Equipped with, The first double data rate memory chip is located on another surface of the main board and is electrically connected to the plurality of first data pins and the plurality of first command control pins. The first double data rate memory chip has a first operating voltage of 1.05 volts or less and a first transfer speed of 6400 MT / s or more. Memory module.

7. The memory module according to claim 6, wherein the main board corresponds to the main board of a low-power compressed connection memory module.

8. The main board further includes a fourth pin area and a second universal flash storage memory chip. The fourth pin region is located on the surface of the main board, The fourth pin region is, Multiple third power pins, A plurality of fourth data pins adjacent to the plurality of third power pins, A plurality of third clock pins adjacent to the plurality of fourth data pins, Equipped with, The second universal flash storage memory chip is positioned adjacent to the first double data rate memory chip and is electrically connected to the plurality of third power pins, the plurality of fourth data pins, and the plurality of third clock pins. The memory module according to claim 7.

9. The aforementioned main board is A plurality of fourth power pins arranged on the surface of the main board, A power management integrated circuit chip is positioned adjacent to the first double data rate memory chip and electrically connected to the plurality of fourth power pins, Furthermore, The memory module according to claim 7.

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