Processor and error detection method - Patents.com

Abstract

To provide a processor and an error detection method configured to detect an error generated in the processor more appropriately with a simple configuration.SOLUTION: A processor includes a pipeline control circuit which performs processing in accordance with an input instruction, and an ECC circuit which detects an error on the pipeline control circuit. The ECC circuit selects whether or not to execute error detection on the pipeline control circuit in accordance with the processing executed by the pipeline control circuit. Whether or not the ECC circuit executes error detection is defined for each instruction code which indicates processing to be executed by the pipeline control circuit.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a processor and an error detection method. [Background technology]

[0002] 2. Description of the Related Art In processors equipped with memories, as disclosed in Patent Document 1, error checking and correcting (ECC) for detecting abnormalities in the memory is widely used.

[0003] For example, Patent Document 1 discloses an electronic control device that includes an arithmetic unit including a CPU and a memory, and a memory error detection unit that is an ECC that detects memory errors. The memory and the memory error detection unit exchange data via a bus, and the CPU reads and writes data from and to the memory via the memory error detection unit 11E. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2018-10362 A Summary of the Invention [Problem to be solved by the invention]

[0005] 6 shows a processor 100 in which a pipeline control circuit 114 performs processing in response to an instruction from a memory 112. Conventionally, as shown in FIG 6, an ECC circuit 116 is disposed between the memory 112 and the pipeline control circuit 114, and the ECC circuit 116 detects a fault (ECC error) present in the memory 112. Meanwhile, a fault in the pipeline control circuit 114 is detected by comparing outputs from the duplicated pipeline control circuits 114 with a comparator 120.

[0006] However, in such a conventional configuration, the circuit scale increases because the pipeline control circuit 114 is duplicated. Also, in the conventional configuration, the ECC circuit 116 performs error detection processing on the memory 112 before performing error detection processing on the pipeline control circuit 114, which may result in poor processing timing in the pipeline control circuit 114. Furthermore, if error detection is performed on a process that requires a high processing speed, the required processing speed may not be satisfied.

[0007] In view of the above background, an object of the present invention is to provide a processor and an error detection method that can more appropriately detect errors occurring in a processor with a simpler configuration. [Means for solving the problem]

[0008] The present invention employs the following technical means to solve the above problems. The reference characters in the claims and in this section are merely examples showing the corresponding relationship with the specific means described in the embodiments below as one aspect, and do not limit the technical scope of the present invention.

[0009] A processor (10) according to one embodiment of the present invention comprises a processing means (14) which performs processing in accordance with an input command, and an error detection means (16) which detects errors in the processing means, the error detection means switching between performing and not performing error detection for the processing means depending on the processing executed by the processing means, and the switching between performing and not performing error detection by the error detection means is defined for each command indicating the processing to be executed by the processing means. Effect of the Invention

[0010] According to the present invention, it is possible to more appropriately detect errors occurring in a processor with a simpler configuration. [Brief description of the drawings]

[0011] [Figure 1] FIG. 2 is a schematic configuration diagram of a processor according to the first embodiment. [Diagram 2] 4 is a schematic diagram showing an instruction code of a pipeline control circuit according to the first embodiment; FIG. [Diagram 3] 4 is a flowchart showing the flow of instruction processing executed by the processor of the first embodiment. [Figure 4] FIG. 11 is a schematic configuration diagram of a processor according to a second embodiment. [Diagram 5] 10 is a flowchart showing the flow of instruction processing executed by a processor according to a second embodiment. [Figure 6] FIG. 1 is a schematic diagram of a processor equipped with a conventional ECC circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. Note that the embodiment described below shows an example of a case where the present invention is implemented, and the present invention is not limited to the specific configuration described below. In implementing the present invention, a specific configuration according to the embodiment may be appropriately adopted.

[0013] (First embodiment) 1 is a schematic diagram of a processor 10 according to the present embodiment. The processor 10 according to the present embodiment includes a memory 12, a pipeline control circuit 14, an ECC circuit 16, and a register 18. In addition, the processor 10 according to the present embodiment applies RISC-V as an example of an instruction set architecture.

[0014] The memory 12 stores data, ECC codes, etc., which are read out and used in processing by the pipeline control circuit 14, and the results of this processing are stored in a register 18.

[0015] The pipeline control circuit 14 is an example of a processing means that performs processing (tasks) according to input instructions (hereinafter also referred to as "instruction codes"). In the pipeline control circuit 14 of this embodiment, instruction execution units, which are processing elements, are connected in series, and the output of the previous instruction execution unit is used as the input of the next instruction execution unit, so that the multiple instruction execution units perform parallel processing.

[0016] In FIG. 1, the instruction execution units include an instruction fetch 14A, an instruction decoder 14B, and an ALU (Arithmetic Logic Unit) 14C, but this is just one example, and the pipeline control circuit 14 also includes other instruction execution units for performing addition, subtraction, multiplication, etc.

[0017] The ECC circuit 16 is hardware provided at a subsequent stage of the pipeline control circuit 14, and detects errors that occur in either the pipeline control circuit 14 or the memory 12. The ECC circuit 16 of this embodiment switches between performing and not performing error detection for the pipeline control circuit 14 depending on the process executed by the pipeline control circuit 14.

[0018] In this embodiment, switching between execution and non-execution of error detection by the ECC circuit 16 is defined for each instruction code indicating a process to be executed by the pipeline control circuit 14. Fig. 2 is a schematic diagram showing an example of an instruction code in this embodiment.

[0019] The instruction code shown in FIG. 2 is an instruction (Memrory[rs1+imm] → rd) for loading the contents (data) of the address “rs1+imm” of the memory 12 into the register 18, and shows a normal instruction code and an instruction code with ECC.

[0020] As shown in Fig. 2, the normal instruction code and the ECC-added instruction code are different in the underlined portion, for example. This different portion defines whether or not to execute error detection for the pipeline control circuit 14, and in this embodiment, is defined by an extension field (Custom-0 Field) of the instruction set in RISC-V. That is, the ECC-added instruction code includes an instruction to execute error detection by the ECC circuit 16 as well as a processing instruction to the pipeline control circuit 14. This further simplifies the instruction to switch between executing and not executing error detection.

[0021] In this way, the ECC circuit 16 of this embodiment is enabled when the instruction code is an ECC instruction code, but disabled when the instruction code is a normal instruction code, switching between performing and not performing error detection for the pipeline control circuit 14.

[0022] Note that instruction codes that require error detection are for performing processing that requires functional safety, whereas instruction codes that do not require error detection are for performing processing that requires, for example, processing speed rather than functional safety. In this way, whether the instruction code is with ECC or is normal depends on the processing content executed by the pipeline control circuit 14. Therefore, the processor 10 of this embodiment can perform appropriate error detection according to the processing content.

[0023] Furthermore, since the ECC circuit 16 is provided after the pipeline control circuit 14, it is possible to detect an error even if the error occurs in the memory 12 or in the pipeline control circuit 14. Therefore, the circuit scale of the processor 10 can be reduced compared to the case where the ECC circuit 16 is provided between the memory 12 and the pipeline control circuit 14 and the pipeline control circuit 14 is duplicated.

[0024] FIG. 3 is a flowchart showing the flow of instruction processing executed by the processor 10 of this embodiment.

[0025] First, in step S100, an instruction code is output from the memory 12 to the pipeline control circuit 14.

[0026] In the next step S102, the pipeline control circuit 14 executes processing based on the instruction code. When the processing by the pipeline control circuit 14 is completed, the instruction code and the processing result by the pipeline control circuit 14 are input to the ECC circuit 16 via the pipeline control circuit 14.

[0027] Then, in the next step S106, the ECC circuit 16 judges whether the input instruction code is an ECC-added instruction code, and if the judgment is positive, the process proceeds to step S106. On the other hand, if the judgment is negative, the ECC circuit 16 does not perform error detection, the processing result by the pipeline control circuit 14 is stored in the register 18, and the instruction processing ends.

[0028] In step S106, the ECC circuit 16 performs error detection based on the processing result of the pipeline control circuit 14, outputs the error detection result, and ends this instruction processing. Note that the ECC circuit 16 outputs an error signal only when an error is detected, but does not have to output any signal when no error is detected.

[0029] As described above, in the processor 10 of this embodiment, when an instruction to the pipeline control circuit 14 includes an instruction to execute error detection by the ECC circuit 16, the ECC circuit 16 executes error detection for the pipeline control circuit 14 after processing by the pipeline control circuit 14 is completed.

[0030] That is, depending on the processing contents executed by the pipeline control circuit 14, there are cases where error detection for the pipeline control circuit 14 is unnecessary or execution of error detection is undesirable. In anticipation of such cases, the processor 10 of the present embodiment switches between enabling and disabling the ECC circuit 16 depending on the processing executed by the pipeline control circuit 14, and therefore can perform more appropriately with a simpler configuration.

[0031] Second embodiment A second embodiment of the present invention will now be described.

[0032] Fig. 4 shows the configuration of a processor 10 according to the second embodiment. Note that the same components in Fig. 4 as those in Fig. 1 are denoted by the same reference numerals as in Fig. 1, and the description thereof will be omitted.

[0033] The processor 10 of this embodiment includes a comparison unit 20 that compares the results of a plurality of identical processes performed in the pipeline control circuit 14. That is, the comparison unit 20 functions as an error detection means that detects an error that occurs in the pipeline control circuit 14. Note that the comparison unit 20 of this embodiment is executed by software processing, for example.

[0034] In the processor 10 of this embodiment, when the instruction code is an instruction code with ECC, the pipeline control circuit 14 performs the same process multiple times based on the instruction code, and the comparison unit 20 compares the process results. If the multiple process results are the same, no error has occurred, and if the multiple process results are different, an error signal is output indicating that an error has occurred.

[0035] FIG. 5 is a flowchart showing the flow of instruction processing executed by the processor 10 of this embodiment.

[0036] First, in step 200 , an instruction code is output from the memory 12 to the pipeline control circuit 14 .

[0037] In the next step 202, it is determined whether or not the instruction code is an instruction code with ECC. If the determination is affirmative, the process proceeds to step 208, and if the determination is negative, the process proceeds to step 206.

[0038] In step 206, the pipeline control circuit 14 executes processing based on the instruction code, and the processing result is stored in the register 18, after which the instruction processing ends. That is, if the determination in step 202 is negative, no error detection is performed.

[0039] On the other hand, in step 208, which is reached when the determination in step 202 is affirmative, the pipeline control circuit 14 performs a first process based on the instruction code. The result of this first process is output to the comparison unit 20.

[0040] In the next step 210 , the pipeline control circuit 14 performs a second process based on the instruction code, and the result of the second process is also output to the comparison section 20 .

[0041] In the next step 212, the comparison unit 20 compares the first processing result with the second processing result, and this instruction processing ends. If the comparison results by the comparison unit 20 are different, it is determined that an error has occurred in the pipeline control circuit 14, and the comparison unit 20 outputs an error signal. On the other hand, if the comparison results by the comparison unit 20 are the same, no error has occurred in the pipeline control circuit 14, and therefore the comparison unit 20 does not output a signal, or outputs a signal indicating that no error has occurred.

[0042] In the present embodiment, the presence or absence of an error is detected by comparing the results of performing the same process twice in the pipeline control circuit 14, but the present embodiment is not limited to this.

[0043] For example, the processing based on the ECC-added instruction code may also be executed by other instruction execution units included in the pipeline control circuit 14, and the comparison unit 20 may compare the execution results to detect errors. For example, the pipeline control circuit 14 may include a plurality of adders, subtractors, multipliers, etc. as instruction execution units. In such a case, the same arithmetic instruction is executed multiple times using different adders, subtractors, multipliers, etc., and the comparison unit 20 compares the results of the multiple arithmetic operations. As a result, if an error (fault) occurs in any of the instruction execution units that performed the operation, the comparison results will be different, and an error signal will be output from the comparison unit 20.

[0044] In addition, the input contents to the pipeline control circuit 14 based on the ECC instruction code and the inverted data of the processing result may be stored in a buffer, and the pipeline control circuit 14 may again execute processing based on the data stored in the buffer, and the comparison unit 20 may compare this processing result with the data stored in the buffer to detect errors.

[0045] Although the present invention has been described above using the above embodiment, the technical scope of the present invention is not limited to the scope described in the above embodiment. Various modifications or improvements can be made to the above embodiment without departing from the gist of the invention, and the forms with such modifications or improvements are also included in the technical scope of the present invention. In addition, the first and second embodiments may be combined.

[0046] In the above embodiment, RISC-V is applied as the architecture of the processor 10, and the execution or non-execution of error detection is defined by an extension field of the instruction set in RISC-V, but the present invention is not limited to this. Other architectures may be used as long as the execution or non-execution of error detection can be defined by the instruction set.

[0047] In the above embodiment, the switching between execution and non-execution of error detection is described as being defined for each instruction code to the pipeline control circuit 14, but the present invention is not limited to this. For example, the switching between execution and non-execution of error detection may be switched according to the processing mode of the processor 10. That is, the processing mode of the processor 10 can be set to a mode in which error detection is executed and a mode in which error detection is not executed.

[0048] In the above embodiment, a configuration in which a processor 10 that performs pipeline processing has been described, but the present invention is not limited to this, and the processor 10 does not necessarily have to perform pipeline processing. For example, the processor 10 may have a configuration including a plurality of CPUs (Central Processing Units). In this case, when the same processing is performed a plurality of times as in the second embodiment and the comparison unit 20 compares the processing results, the comparison unit 20 compares the processing results of the processing performed by the plurality of CPUs. [Explanation of symbols]

[0049] 10 processor; 14 pipeline control circuit; 16 ECC circuit; 20. Comparison section

Claims

1. A processing means (14) for performing processing according to instructions input from a memory; an ECC circuit (16) provided downstream of the processing means for detecting an error in the processing means and switching between execution and non-execution of error detection; Equipped with The switching between execution and non-execution of error detection by the ECC circuit is defined for each instruction indicating a process to be executed by the processing means, There is no detection means between the memory and the processing means for performing error detection on data output from the memory. Processor (10).

2. a processing means for performing processing in response to an instruction input from a memory; an error detection means (20) for detecting an error by comparing the results of a plurality of identical processes performed by the processing means, and for switching between execution and non-execution of error detection; Equipped with switching between execution and non-execution of error detection by said error detection means is defined for each instruction indicating a process to be executed by said processing means; There is no detection means between the memory and the processing means for performing error detection on data output from the memory. Processor.

3. 3. The processor according to claim 2, wherein execution or non-execution of error detection by said error detection means is defined in an extension field of an instruction set in RISC-V.

4. An error detection method for a processor comprising: a processing means for performing processing in accordance with an instruction input from a memory; and an ECC circuit provided downstream of the processing means for detecting an error in the processing means and for switching between execution and non-execution of error detection; and no detection means provided between the memory and the processing means for performing error detection on data output from the memory, comprising: a first step in which the processing means performs processing in accordance with an input command; a second step in which the ECC circuit performs error detection after the first step is completed in response to a process performed by the processing means; having The execution or non-execution of the error detection by the second step is defined for each command indicating a process to be executed by the processing means. Error detection methods.

5. 1. An error detection method for a processor comprising a processing means for performing processing in accordance with an instruction input from a memory, and an error detection means for detecting an error by comparing results of a plurality of identical processes performed by the processing means, and no detection means for detecting an error in data output from the memory between the memory and the processing means, comprising: a first step in which the processing means performs processing in accordance with an input command; a second step in which the error detection means performs error detection after the first step is completed, in accordance with the processing performed by the processing means; having The execution or non-execution of the error detection by the second step is defined for each command indicating a process to be executed by the processing means. Error detection methods.

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