Semiconductor Device

Abstract

To realize overcurrent protection with a simpler configuration.SOLUTION: For example, a semiconductor device includes: a split-gate power transistor configured to have a plurality of channel regions that are controlled individually in accordance with a plurality of gate control signals; a gate control circuit configured to generate the plurality of gate control signals; and an overcurrent protection circuit configured to turn off at least one of the plurality of channel regions when an output current that passes through the power transistor exceeds a threshold voltage.SELECTED DRAWING: Figure 9

Description

[Technical field]

[0001] The invention disclosed in this specification relates to a semiconductor device. [Background technology]

[0002] Conventionally, most semiconductor devices are equipped with an overcurrent protection circuit as one of the abnormality protection circuits. For example, an in-vehicle IPD (intelligent power device) is equipped with an overcurrent protection circuit that limits the output current flowing through a power transistor to a set overcurrent value or less so that the device is not destroyed even if a load connected to the power transistor is shorted.

[0003] As an example of the related art, Patent Document 1 can be mentioned. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2015-46954 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, in conventional semiconductor devices, there is still room for further study on reducing the scale of the overcurrent protection circuit (and thus reducing the product price).

[0006] In view of the above problems found by the inventors of the present application, the invention disclosed in this specification has an object to provide a semiconductor device that can easily achieve overcurrent protection. [Means for solving the problem]

[0007] For example, the semiconductor device disclosed in this specification has a configuration (first configuration) including a gate-split type power transistor configured to individually control a plurality of channel regions in response to a plurality of gate control signals, a gate control circuit configured to generate the plurality of gate control signals, and an overcurrent protection circuit configured to turn off at least one of the plurality of channel regions when an output current flowing through the power transistor exceeds a threshold value.

[0008] In addition, in the semiconductor device having the above-mentioned first configuration, the power transistor may be configured (second configuration) to include a first electrode formed on a first main surface side of a semiconductor substrate and a second electrode formed on a second main surface side of the semiconductor substrate.

[0009] Furthermore, in the semiconductor device having the above-mentioned second configuration, the overcurrent protection circuit may be configured (third configuration) to include a comparator configured to compare a predetermined threshold voltage with the terminal voltage of the first electrode to generate an overcurrent protection signal, and a first transistor configured to establish / cut off conduction between at least one of a plurality of gate control wirings and the first electrode in response to the overcurrent protection signal.

[0010] In addition, in the semiconductor device having the above-mentioned third configuration, the overcurrent protection circuit may be configured (fourth configuration) to further include a second transistor connected between the second electrode or the first electrode and the threshold voltage application terminal and configured to generate the threshold voltage by a constant current flowing through the second transistor.

[0011] In the semiconductor device having the above-mentioned fourth configuration, the second transistor may be configured (fifth configuration) to be turned on / off in synchronization with the power transistor.

[0012] In addition, in the semiconductor device having the fourth or fifth configuration, the second transistor may be configured (sixth configuration) to be a split-gate transistor formed to have a pair with the power transistor.

[0013] In addition, in a semiconductor device having any one of the first to sixth configurations, the power transistor may be configured (seventh configuration) to function as a high-side switch in which the first electrode is connected to a load and the second electrode is connected to a power supply terminal.

[0014] In addition, in a semiconductor device having any one of the first to sixth configurations, the power transistor may be configured (eighth configuration) to function as a low-side switch in which the first electrode is connected to a ground terminal and the second electrode is connected to a load.

[0015] Also, for example, the electronic device disclosed in this specification has a configuration (ninth configuration) including a semiconductor device having any one of the first to eighth configurations above and a load connected to the semiconductor device.

[0016] Also, for example, the vehicle disclosed in this specification has a configuration (tenth configuration) including the electronic device having the ninth configuration described above. Effect of the Invention

[0017] According to the invention disclosed in this specification, it is possible to provide a semiconductor device that can easily achieve overcurrent protection. [Brief description of the drawings]

[0018] [Figure 1] A perspective view of a semiconductor device seen from one direction. [Diagram 2] A block circuit diagram showing the electrical structure of a semiconductor device. [Diagram 3] A circuit diagram for explaining normal operation and active clamp operation of a semiconductor device. [Figure 4] Waveforms of main electrical signals [Diagram 5] FIG. 2 is a cross-sectional perspective view of an area V shown in FIG. [Figure 6] A graph showing the relationship between active clamp resistance and sheet resistivity based on actual measurements [Figure 7] FIG. 1 is a cross-sectional perspective view for explaining a normal operation of a semiconductor device; [Figure 8] FIG. 1 is a cross-sectional perspective view for explaining an active clamp operation of a semiconductor device; [Figure 9] A diagram showing a first configuration example of an overcurrent protection circuit. [Figure 10] FIG. 13 is a diagram showing an example of an overcurrent protection operation in the first configuration example. [Figure 11] FIG. 2 shows a second example of the configuration of an overcurrent protection circuit. [Figure 12] FIG. 13 is a diagram showing an example of an overcurrent protection operation in the second configuration example. [Figure 13] FIG. 1 is an external view showing an example of a vehicle configuration. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] <Semiconductor device> Various embodiments of a semiconductor device will be described below with reference to the accompanying drawings.

[0020] 1 is a perspective view of the semiconductor device 1 seen from one direction. In the following, an embodiment in which the semiconductor device 1 is a high-side switching device will be described, but the semiconductor device 1 is not limited to being a high-side switching device. The semiconductor device 1 can also be provided as a low-side switching device by adjusting the electrical connection forms and functions of various structures.

[0021] 1, the semiconductor device 1 includes a semiconductor layer 2. The semiconductor layer 2 includes silicon. The semiconductor layer 2 is formed in the shape of a rectangular parallelepiped chip. The semiconductor layer 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and side surfaces 5A, 5B, 5C, and 5D connecting the first main surface 3 and the second main surface 4.

[0022] The first main surface 3 and the second main surface 4 are formed in a rectangular shape in a plan view (hereinafter simply referred to as "plan view") as viewed from their normal direction Z. The side surface 5A and the side surface 5C extend along the first direction X and face each other in the second direction Y intersecting the first direction X. The side surface 5B and the side surface 5D extend along the second direction Y and face each other in the first direction X. More specifically, the second direction Y is orthogonal to the first direction X.

[0023] An output region 6 and an input region 7 are set in the semiconductor layer 2. The output region 6 is set in the region on the side surface 5C side. The input region 7 is set in the region on the side surface 5A side. In a plan view, the area SOUT of the output region 6 is equal to or larger than the area SIN of the input region 7 (SIN≦SOUT).

[0024] The ratio SOUT / SIN of the area SOUT to the area SIN may be 1 or more and 10 or less (1<SOUT / SIN≦10). The ratio SOUT / SIN may be 1 or more and 2 or less, 2 or more and 4 or less, 4 or more and 6 or less, 6 or more and 8 or less, or 8 or more and 10 or less. The planar shape of the input region 7 and the planar shape of the output region 6 are arbitrary and are not limited to a specific shape. Of course, the ratio SOUT / SIN may be more than 0 and less than 1.

[0025] The output region 6 includes a power MISFET (Metal Insulator Semiconductor Field Effect Transistor) 9 as an example of an insulated gate type power transistor. The power MISFET 9 includes a gate, a drain, and a source.

[0026] The input area 7 includes a control IC (Integrated Circuit) 10 as an example of a control circuit. The control IC 10 includes a plurality of types of functional circuits that realize various functions. The plurality of types of functional circuits includes a circuit that generates a gate control signal that drives and controls the power MISFET 9 based on an electrical signal from the outside. The control IC 10 and the power MISFET 9 form a so-called IPD (Intelligent Power Device). The IPD is also called an IPM (Intelligent Power Module).

[0027] The input region 7 is electrically insulated from the output region 6 by a region isolation structure 8. In Fig. 1, the region isolation structure 8 is indicated by hatching. Although a detailed description is omitted, the region isolation structure 8 may have a trench isolation structure in which an insulator is buried in a trench.

[0028] A plurality of electrodes (six in this example) 11, 12, 13, 14, 15, and 16 are formed on the semiconductor layer 2. In Fig. 1, the plurality of electrodes 11-16 are indicated by hatching. The plurality of electrodes 11-16 are formed as terminal electrodes that are connected to the outside by conductive wires (e.g., bonding wires) or the like. The number, arrangement, and planar shape of the plurality of electrodes 11-16 are arbitrary and are not limited to the form shown in Fig. 1.

[0029] The number, arrangement and planar shape of the multiple electrodes 11-16 are adjusted according to the specifications of the power MISFET 9 and the specifications of the control IC 10. In this embodiment, the multiple electrodes 11-16 include a drain electrode 11 (power supply electrode), a source electrode 12 (output electrode), an input electrode 13, a reference voltage electrode 14, an ENABLE electrode 15 and a SENSE electrode 16.

[0030] The drain electrode 11 is formed on the second main surface 4 of the semiconductor layer 2. The drain electrode 11 is electrically connected to the second main surface 4 of the semiconductor layer 2. The drain electrode 11 transmits a power supply voltage VB to the drain of the power MISFET 9 and various circuits of the control IC 10.

[0031] The drain electrode 11 may include at least one of a Ti layer, a Ni layer, an Au layer, an Ag layer, and an Al layer. The drain electrode 11 may have a single layer structure including a Ti layer, a Ni layer, an Au layer, an Ag layer, or an Al layer. The drain electrode 11 may have a laminated structure in which at least two of a Ti layer, a Ni layer, an Au layer, an Ag layer, and an Al layer are laminated in any manner.

[0032] The source electrode 12 is formed on the first main surface 3 on the output region 6. The source electrode 12 is electrically connected to the source of the power MISFET 9. The source electrode 12 transmits an electrical signal generated by the power MISFET 9 to the outside.

[0033] The input electrode 13, the reference voltage electrode 14, the ENABLE electrode 15, and the SENSE electrode 16 are each formed on the input region 7 on the first main surface 3. The input electrode 13 transmits an input voltage for driving the control IC 10.

[0034] The reference voltage electrode 14 transmits a reference voltage (for example, a ground voltage) to the control IC 10. The ENABLE electrode 15 transmits an electrical signal for enabling or disabling some or all of the functions of the control IC 10. The SENSE electrode 16 transmits an electrical signal for detecting an abnormality in the control IC 10.

[0035] A gate control wiring 17 as an example of a control wiring is further formed on the semiconductor layer 2. The gate control wiring 17 is selectively routed to the output region 6 and the input region 7. The gate control wiring 17 is electrically connected to the gate of the power MISFET 9 in the output region 6, and is electrically connected to the control IC 10 in the input region 7.

[0036] The gate control wiring 17 transmits the gate control signal generated by the control IC 10 to the gate of the power MISFET 9. The gate control signal includes an on signal Von and an off signal Voff, and controls the on state and off state of the power MISFET 9.

[0037] The on signal Von is higher than the gate threshold voltage Vth of the power MISFET 9 (Vth < Von). The off signal Voff is lower than the gate threshold voltage Vth of the power MISFET 9 (Voff < Vth). The off signal Voff may be a reference voltage (for example, a ground voltage).

[0038] In this form, the gate control wiring 17 includes a first gate control wiring 17A, a second gate control wiring 17B, and a third gate control wiring 17C. The first gate control wiring 17A, the second gate control wiring 17B, and the third gate control wiring 17C are electrically insulated from each other.

[0039] In this form, two first gate control wirings 17A are routed in different regions. Also, two second gate control wirings 17B are routed in different regions. Also, two third gate control wirings 17C are routed in different regions.

[0040] The first gate control wiring 17A, the second gate control wiring 17B, and the third gate control wiring 17C transmit the same or different gate control signals to the gate of the power MISFET 9. The number, arrangement, shape, etc. of the gate control wiring 17 are arbitrary and are adjusted according to the transmission distance of the gate control signal and the number of gate control signals to be transmitted.

[0041] The source electrode 12, the input electrode 13, the reference voltage electrode 14, the ENABLE electrode 15, the SENSE electrode 16, and the gate control wiring 17 may each contain at least one of nickel, palladium, aluminum, copper, aluminum alloy, and copper alloy.

[0042] The source electrode 12, the input electrode 13, the reference voltage electrode 14, the ENABLE electrode 15, the SENSE electrode 16 and the gate control wiring 17 may each contain at least one of an Al-Si-Cu (aluminum-silicon-copper) alloy, an Al-Si (aluminum-silicon) alloy, and an Al-Cu (aluminum-copper) alloy.

[0043] The source electrode 12, the input electrode 13, the reference voltage electrode 14, the ENABLE electrode 15, the SENSE electrode 16 and the gate control wiring 17 may contain the same type of electrode material, or may contain different electrode materials.

[0044] Fig. 2 is a block circuit diagram showing an electrical structure of the semiconductor device 1 shown in Fig. 1. In the following, an example will be described in which the semiconductor device 1 is mounted on a vehicle.

[0045] The semiconductor device 1 includes a drain electrode 11 , a source electrode 12 , an input electrode 13 , a reference voltage electrode 14 , an ENABLE electrode 15 , a SENSE electrode 16 , a gate control wiring 17 , a power MISFET 9 and a control IC 10 .

[0046] The drain electrode 11 is connected to a power supply. The drain electrode 11 provides a power supply voltage VB to the power MISFET 9 and the control IC 10. The power supply voltage VB may be 10 V or more and 20 V or less. The source electrode 12 is connected to a load.

[0047] The input electrode 13 may be connected to an MCU (Micro Controller Unit), a DC / DC converter, an LDO (Low Drop Out), or the like. The input electrode 13 provides an input voltage to the control IC 10. The input voltage may be 1 V or more and 10 V or less. The reference voltage electrode 14 is connected to a reference voltage wiring. The reference voltage electrode 14 provides a reference voltage to the power MISFET 9 and the control IC 10.

[0048] The ENABLE electrode 15 may be connected to the MCU. An electrical signal for enabling or disabling a part or all of the functions of the control IC 10 is input to the ENABLE electrode 15. The SENSE electrode 16 may be connected to a resistor.

[0049] The gate of the power MISFET 9 is connected to a control IC 10 (a gate control circuit 25 described later) via a gate control wiring 17. The drain of the power MISFET 9 is connected to a drain electrode 11. The source of the power MISFET 9 is connected to the control IC 10 (a current detection circuit 27 described later) and a source electrode 12.

[0050] The control IC 10 includes a sensor MISFET 21 , an input circuit 22 , a current / voltage control circuit 23 , a protection circuit 24 , a gate control circuit 25 , an active clamp circuit 26 , a current detection circuit 27 , a power supply reverse connection protection circuit 28 and an abnormality detection circuit 29 .

[0051] The gate of the sensor MISFET 21 is connected to the gate control circuit 25. The drain of the sensor MISFET 21 is connected to the drain electrode 11. The source of the sensor MISFET 21 is connected to the current detection circuit 27.

[0052] The input circuit 22 is connected to the input electrode 13 and the current / voltage control circuit 23. The input circuit 22 may include a Schmitt trigger circuit. The input circuit 22 shapes the waveform of the electrical signal applied to the input electrode 13. The signal generated by the input circuit 22 is input to the current / voltage control circuit 23.

[0053] The current / voltage control circuit 23 is connected to the protection circuit 24, the gate control circuit 25, the power supply reverse connection protection circuit 28, and the abnormality detection circuit 29. The current / voltage control circuit 23 may include a logic circuit.

[0054] The current / voltage control circuit 23 generates various voltages in response to an electrical signal from the input circuit 22 and an electrical signal from the protection circuit 24. In this embodiment, the current / voltage control circuit 23 includes a drive voltage generation circuit 30, a first constant voltage generation circuit 31, a second constant voltage generation circuit 32, and a reference voltage / reference current generation circuit 33.

[0055] The drive voltage generation circuit 30 generates a drive voltage for driving the gate control circuit 25. The drive voltage may be set to a value obtained by subtracting a predetermined value from the power supply voltage VB. The drive voltage generation circuit 30 may generate a drive voltage in the range of 5V to 15V obtained by subtracting 5V from the power supply voltage VB. The drive voltage is input to the gate control circuit 25.

[0056] The first constant voltage generating circuit 31 generates a first constant voltage for driving the protection circuit 24. The first constant voltage generating circuit 31 may include a Zener diode or a regulator circuit (here, a Zener diode). The first constant voltage may be 1 V or more and 5 V or less. The first constant voltage is input to the protection circuit 24 (more specifically, the load open detection circuit 35 described later, etc.).

[0057] The second constant voltage generating circuit 32 generates a second constant voltage for driving the protection circuit 24. The second constant voltage generating circuit 32 may include a Zener diode or a regulator circuit (here, a regulator circuit). The second constant voltage may be 1 V or more and 5 V or less. The second constant voltage is input to the protection circuit 24 (more specifically, an overheat protection circuit 36 ​​and an undervoltage malfunction suppression circuit 37, which will be described later).

[0058] The reference voltage / reference current generating circuit 33 generates a reference voltage and a reference current for various circuits. The reference voltage may be 1 V or more and 5 V or less. The reference current may be 1 mA or more and 1 A or less. The reference voltage and the reference current are input to the various circuits. If the various circuits include a comparator, the reference voltage and the reference current may be input to the comparator.

[0059] The protection circuit 24 is connected to the current / voltage control circuit 23, the gate control circuit 25, the abnormality detection circuit 29, the source of the power MISFET 9, and the source of the sensor MISFET 21. The protection circuit 24 includes an overcurrent protection circuit 34, an open load detection circuit 35, an overheat protection circuit 36, and an undervoltage malfunction suppression circuit 37.

[0060] The overcurrent protection circuit 34 protects the power MISFET 9 from an overcurrent. The overcurrent protection circuit 34 is connected to the gate control circuit 25 and the source of the sensor MISFET 21. The overcurrent protection circuit 34 may include a current monitor circuit. A signal generated by the overcurrent protection circuit 34 is input to the gate control circuit 25 (more specifically, a drive signal output circuit 40 described later).

[0061] The load open detection circuit 35 detects a short state or an open state of the power MISFET 9. The load open detection circuit 35 is connected to the current / voltage control circuit 23 and the source of the power MISFET 9. A signal generated by the load open detection circuit 35 is input to the current / voltage control circuit 23.

[0062] The overheat protection circuit 36 ​​monitors the temperature of the power MISFET 9 and protects the power MISFET 9 from an excessive temperature rise. The overheat protection circuit 36 ​​is connected to the current / voltage control circuit 23. The overheat protection circuit 36 ​​may include a temperature sensing device such as a temperature sensing diode or a thermistor. A signal generated by the overheat protection circuit 36 ​​is input to the current / voltage control circuit 23.

[0063] The low voltage malfunction suppression circuit 37 suppresses malfunction of the power MISFET 9 when the power supply voltage VB is less than a predetermined value. The low voltage malfunction suppression circuit 37 is connected to the current / voltage control circuit 23. A signal generated by the low voltage malfunction suppression circuit 37 is input to the current / voltage control circuit 23.

[0064] The gate control circuit 25 controls the on and off states of the power MISFET 9 and the on and off states of the sensor MISFET 21. The gate control circuit 25 is connected to the current / voltage control circuit 23, the protection circuit 24, the gate of the power MISFET 9, and the gate of the sensor MISFET 21.

[0065] The gate control circuit 25 generates a plurality of gate control signals according to the number of gate control wirings 17 in response to the electrical signal from the current / voltage control circuit 23 and the electrical signal from the protection circuit 24. The plurality of gate control signals are input to the gate of the power MISFET 9 and the gate of the sensor MISFET 21 via the gate control wirings 17, respectively.

[0066] Specifically, the gate control circuit 25 has the function of turning the power MISFET 9 on / off by collectively controlling a plurality of gate control signals in response to an electrical signal (input signal) applied to the input electrode 13, while also having the function of individually controlling a plurality of gate control signals so as to increase the on-resistance of the power MISFET 9 when the active clamp circuit 26 is in operation (details will be described later).

[0067] More specifically, the gate control circuit 25 includes an oscillation circuit 38, a charge pump circuit 39, and a drive signal output circuit 40. The oscillation circuit 38 oscillates in response to an electric signal from the current / voltage control circuit 23 to generate a predetermined electric signal. The electric signal generated by the oscillation circuit 38 is input to the charge pump circuit 39. The charge pump circuit 39 boosts the electric signal from the oscillation circuit 38. The electric signal boosted by the charge pump circuit 39 is input to the drive signal output circuit 40.

[0068] The drive signal output circuit 40 generates a plurality of gate control signals in response to an electric signal from the charge pump circuit 39 and an electric signal from the protection circuit 24 (more specifically, the overcurrent protection circuit 34). The plurality of gate control signals are input to the gate of the power MISFET 9 and the gate of the sensor MISFET 21 via the gate control wiring 17. The sensor MISFET 21 and the power MISFET 9 are simultaneously controlled by the gate control circuit 25.

[0069] The active clamp circuit 26 protects the power MISFET 9 from a counter electromotive force. The active clamp circuit 26 is connected to the drain electrode 11, the gate of the power MISFET 9, and the gate of the sensor MISFET 21. The active clamp circuit 26 may include a plurality of diodes.

[0070] The active clamp circuit 26 may include a plurality of diodes connected in a forward bias to each other. The active clamp circuit 26 may include a plurality of diodes connected in a reverse bias to each other. The active clamp circuit 26 may include a plurality of diodes connected in a forward bias to each other and a plurality of diodes connected in a reverse bias to each other.

[0071] The multiple diodes may include pn junction diodes, or Zener diodes, or pn junction diodes and Zener diodes. The active clamp circuit 26 may include multiple Zener diodes connected to each other in a biased manner. The active clamp circuit 26 may include a Zener diode and a pn junction diode connected to each other in a reverse biased manner.

[0072] The current detection circuit 27 detects the current flowing through the power MISFET 9 and the sensor MISFET 21. The current detection circuit 27 is connected to the protection circuit 24, the abnormality detection circuit 29, the source of the power MISFET 9, and the source of the sensor MISFET 21. The current detection circuit 27 generates a current detection signal in response to the electric signal generated by the power MISFET 9 and the electric signal generated by the sensor MISFET 21. The current detection signal is input to the abnormality detection circuit 29.

[0073] The power supply reverse connection protection circuit 28 protects the current / voltage control circuit 23, the power MISFET 9, etc. from reverse voltage when the power supply is reverse connected. The power supply reverse connection protection circuit 28 is connected to the reference voltage electrode 14 and the current / voltage control circuit 23.

[0074] Abnormality detection circuit 29 monitors the voltage of protection circuit 24. Abnormality detection circuit 29 is connected to current / voltage control circuit 23, protection circuit 24, and current detection circuit 27. If an abnormality (such as a voltage fluctuation) occurs in any of overcurrent protection circuit 34, open load detection circuit 35, overheat protection circuit 36, and low voltage malfunction suppression circuit 37, abnormality detection circuit 29 generates an abnormality detection signal according to the voltage of protection circuit 24 and outputs it to the outside.

[0075] More specifically, the abnormality detection circuit 29 includes a first multiplexer circuit 41 and a second multiplexer circuit 42. The first multiplexer circuit 41 includes two input parts, one output part, and one selection control input part. The protection circuit 24 and the current detection circuit 27 are respectively connected to the input parts of the first multiplexer circuit 41. The second multiplexer circuit 42 is connected to the output part of the first multiplexer circuit 41. The current / voltage control circuit 23 is connected to the selection control input part of the first multiplexer circuit 41.

[0076] The first multiplexer circuit 41 generates an abnormality detection signal in response to the electrical signal from the current / voltage control circuit 23, the voltage detection signal from the protection circuit 24, and the current detection signal from the current detection circuit 27. The abnormality detection signal generated by the first multiplexer circuit 41 is input to the second multiplexer circuit 42.

[0077] The second multiplexer circuit 42 includes two inputs and one output. The inputs of the second multiplexer circuit 42 are connected to the output of the second multiplexer circuit 42 and the ENABLE electrode 15. The output of the second multiplexer circuit 42 is connected to the SENSE electrode 16.

[0078] When an MCU is connected to ENABLE electrode 15 and a resistor is connected to SENSE electrode 16, an ON signal is input from the MCU to ENABLE electrode 15, and an abnormality detection signal is extracted from SENSE electrode 16. The abnormality detection signal is converted into an electrical signal by the resistor connected to SENSE electrode 16. An abnormal state of semiconductor device 1 is detected based on this electrical signal.

[0079] Fig. 3 is a circuit diagram for explaining the active clamp operation of the semiconductor device 1 shown in Fig. 1. Fig. 4 is a waveform diagram of main electric signals in the circuit diagram shown in Fig. 3.

[0080] Here, normal operation and active clamp operation of the semiconductor device 1 will be described using a circuit example in which an inductive load L is connected to a power MISFET 9. Devices using a winding (coil), such as a solenoid, a motor, a transformer, and a relay, are exemplified as the inductive load L. The inductive load L is also referred to as an L load.

[0081] Referring to FIG. 3, the source of the power MISFET 9 is connected to the inductive load L. The drain of the power MISFET 9 is electrically connected to the drain electrode 11. The gate and drain of the power MISFET 9 are connected to the active clamp circuit 26. The active clamp circuit 26 includes, in this circuit example, m (m is a natural number) Zener diodes DZ and n (n is a natural number) pn junction diodes D. The pn junction diode D is connected in reverse bias to the Zener diode DZ.

[0082] Referring to FIGS. 3 and 4, when an on signal Von is input to the gate of the off-state power MISFET 9, the power MISFET 9 switches from the off state to the on state (normal operation). The on signal Von has a voltage equal to or higher than the gate threshold voltage Vth (Vth ≦ Von). The power MISFET 9 is maintained in the on state for a predetermined on time TON.

[0083] When the power MISFET 9 switches to the on state, the drain current ID starts to flow from the drain to the source of the power MISFET 9. The drain current ID increases from zero to a predetermined value and saturates. The inductive load L accumulates inductive energy due to the increase in the drain current ID.

[0084] When an off signal Voff is input to the gate of the power MISFET 9, the power MISFET 9 switches from the on state to the off state. The off signal Voff has a voltage lower than the gate threshold voltage Vth (Voff < Vth). The off signal Voff may be a reference voltage (e.g., ground voltage).

[0085] During the transition when the power MISFET 9 switches from the on state to the off state, the inductive energy of the inductive load L is applied to the power MISFET 9 as a back electromotive force. As a result, the power MISFET 9 enters the active clamp state (active clamp operation). When the power MISFET 9 enters the active clamp state, the source voltage VSS rapidly drops to a negative voltage lower than the reference voltage (ground voltage).

[0086] At this time, the source voltage VSS is limited to a voltage equal to or higher than the voltage obtained by subtracting the limiting voltage VL and the clamp-on voltage VCLP from the power supply voltage VB due to the operation of the active clamp circuit 26 (VSS≧VB - VL - VCLP).

[0087] In other words, when the power MISFET 9 enters the active clamp state, the drain voltage VDS between the drain and source of the power MISFET 9 rapidly rises to the clamp voltage VDSSCL. The clamp voltage VDSSCL is limited to a voltage equal to or lower than the voltage obtained by adding the clamp-on voltage VCLP and the limiting voltage VL by the power MISFET 9 and the active clamp circuit 26 (VDS≦VCLP + VL).

[0088] In this embodiment, the limiting voltage VL is the sum of the terminal voltage VZ of the Zener diode DZ and the terminal voltage VF of the pn junction diode in the active clamp circuit 26 (VL = m·VZ + n·VF).

[0089] The clamp-on voltage VCLP is the positive voltage applied between the gate and source of the power MISFET 9 (i.e., the gate voltage VGS). The clamp-on voltage VCLP is equal to or higher than the gate threshold voltage Vth (Vth≦VCLP). Therefore, the power MISFET 9 maintains the on state in the active clamp state.

[0090] When the clamp voltage VDSSCL exceeds the maximum rated drain voltage VDSS (VDSS < VDSSCL), the power MISFET 9 will be damaged. The power MISFET 9 is designed such that the clamp voltage VDSSCL is equal to or lower than the maximum rated drain voltage VDSS (VDSSCL≦VDSS).

[0091] When the clamp voltage VDSSCL is equal to or lower than the maximum rated drain voltage VDSS (VDSSCL≦VDSS), the drain current ID continues to flow from the drain to the source of the power MISFET 9 , and the inductive energy of the inductive load L is consumed (absorbed) in the power MISFET 9 .

[0092] The drain current ID decreases to zero from a peak value IAV immediately before the power MISFET 9 is turned off, after an active clamp time TAV has elapsed. This causes the gate voltage VGS to become a reference voltage (for example, ground voltage), and the power MISFET 9 is switched from an on state to an off state.

[0093] The active clamp withstand capability Eac of the power MISFET 9 is defined by the withstand capability of the power MISFET 9 during active clamp operation. More specifically, the active clamp withstand capability Eac is defined by the withstand capability of the power MISFET 9 against a back electromotive force caused by the inductive energy of the inductive load L when the power MISFET 9 transitions from an on state to an off state.

[0094] More specifically, the active clamp withstand capability Eac is defined by the withstand capability of the power MISFET 9 against the energy caused by the clamp voltage VDSSCL. For example, the active clamp withstand capability Eac is expressed by the formula Eac=(VL+VCLP)×ID×TAV using the clamp voltage VL, the clamp-on voltage VCLP, the drain current ID, and the active clamp time TAV.

[0095] Fig. 5 is a cross-sectional perspective view of region V shown in Fig. 1. For ease of explanation, the upper structure of the first main surface 3 (such as the source electrode 12 and the gate control wiring 17, and the interlayer insulating layer) is omitted in this figure.

[0096] In the semiconductor device 1 shown in the figure, the semiconductor layer 2 is, in this embodiment, +It has a stacked structure including a p-type semiconductor substrate 51 and an n-type epitaxial layer 52. The second main surface 4 of the semiconductor layer 2 is formed by the semiconductor substrate 51. The first main surface 3 of the semiconductor layer 2 is formed by the epitaxial layer 52. The side surfaces 5A to 5D of the semiconductor layer 2 are formed by the semiconductor substrate 51 and the epitaxial layer 52.

[0097] The epitaxial layer 52 has an n-type impurity concentration lower than the n-type impurity concentration of the semiconductor substrate 51. The n-type impurity concentration of the semiconductor substrate 51 is 1×10 18 cm -3 or more and 1×10 20 cm -3 or less. The n-type impurity concentration of the epitaxial layer 52 is 1×10 15 cm -3 or more and 1×10 18 cm -3 or less.

[0098] The epitaxial layer 52 has a thickness Tepi (Tepi < Tsub) less than the thickness Tsub of the semiconductor substrate 51. The thickness Tsub may be 50 μm or more and 450 μm or less. The thickness Tsub may be 50 μm or more and 150 μm or less, 150 μm or more and 250 μm or less, 250 μm or more and 350 μm or less, or 350 μm or more and 450 μm or less.

[0099] By reducing the thickness Tsub, the resistance value can be reduced. The thickness Tsub is adjusted by grinding. In this case, the second main surface 4 of the semiconductor layer 2 may be a ground surface having grinding marks.

[0100] The thickness Tepi of the epitaxial layer 52 is preferably 1 / 10 or less of the thickness Tsub. The thickness Tepi may be 5 μm or more and 20 μm or less. The thickness Tepi may be 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, or 15 μm or more and 20 μm or less. The thickness Tepi is preferably 5 μm or more and 15 μm or less.

[0101] The semiconductor substrate 51 is formed on the second main surface 4 side of the semiconductor layer 2 as a drain region 53. The epitaxial layer 52 is formed in a surface layer portion of the first main surface 3 of the semiconductor layer 2 as a drift region 54 (drain drift region). The bottom of the drift region 54 is formed by the boundary between the semiconductor substrate 51 and the epitaxial layer 52. Hereinafter, the epitaxial layer 52 will be referred to as the drift region 54.

[0102] In the output region 6, a p-type body region 55 is formed in a surface layer portion of the first main surface 3 of the semiconductor layer 2. The body region 55 is a region that serves as the base of the power MISFET 9. The p-type impurity concentration of the body region 55 is 1×10 16 cm -3 More than 1×10 18 cm -3 It may be the following.

[0103] Body region 55 is formed in a surface layer portion of drift region 54. The bottom of body region 55 is formed in a region on the first main surface 3 side with respect to the bottom of drift region 54. The thickness of body region 55 may be 0.5 μm or more and 2 μm or less. The thickness of body region 55 may be 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, or 1.5 μm or more and 2 μm or less.

[0104] The power MISFET 9 includes a first MISFET 56 (first transistor) and a second MISFET 57 (second transistor). The first MISFET 56 is electrically isolated from the second MISFET 57 and is independently controlled. The second MISFET 57 is electrically isolated from the first MISFET 56 and is independently controlled.

[0105] That is, the power MISFET 9 is configured to operate with both the first MISFET 56 and the second MISFET 57 in the on state (Full-ON control). Also, the power MISFET 9 is configured to operate with the first MISFET 56 in the on state while the second MISFET 57 is in the off state (first Half-ON control). Furthermore, the power MISFET 9 is configured to operate with the first MISFET 56 in the off state while the second MISFET 57 is in the on state (second Half-ON control).

[0106] In the case of the Full-ON control, the power MISFET 9 is driven with all current paths open. Therefore, the on-resistance in the semiconductor layer 2 is relatively decreased. On the other hand, in the case of the first Half-ON control or the second Half-ON control, the power MISFET 9 is driven with some of the current paths blocked. Therefore, the on-resistance in the semiconductor layer 2 is relatively increased.

[0107] The first MISFET 56 specifically includes a plurality of first FET (Field Effect Transistor) structures 58. The plurality of first FET structures 58 are arranged at intervals along a first direction X in a plan view, and each extends in a strip shape along a second direction Y. The plurality of first FET structures 58 are formed in a stripe shape as a whole in a plan view.

[0108] 5 illustrates a region on one end side of the first FET structure 58, and omits illustrating a region on the other end side of the first FET structure 58. The structure of the region on the other end side of the first FET structure 58 is substantially similar to the structure of the region on one end side of the first FET structure 58. In the following, the structure of the region on one end side of the first FET structure 58 will be described as an example, and a description of the structure of the region on the other end side of the first FET structure 58 will be omitted.

[0109] In this embodiment, each first FET structure 58 includes a first trench gate structure 60. A first width WT1 of the first trench gate structure 60 may be 0.5 μm or more and 5 μm or less. The first width WT1 is the width in a direction (first direction X) perpendicular to the direction in which the first trench gate structure 60 extends (second direction Y).

[0110] The first width WT1 may be 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, or 4.5 μm to 5 μm. The first width WT1 is preferably 0.8 μm to 1.2 μm.

[0111] The first trench gate structure 60 penetrates the body region 55 and reaches the drift region 54. The first depth DT1 of the first trench gate structure 60 may be 1 μm or more and 10 μm or less. The first depth DT1 may be 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less. The first depth DT1 is preferably 2 μm or more and 6 μm or less.

[0112] The first trench gate structure 60 includes a first sidewall 61 on one side, a second sidewall 62 on the other side, and a bottom wall 63 connecting the first sidewall 61 and the second sidewall 62. Hereinafter, the first sidewall 61, the second sidewall 62, and the bottom wall 63 may be collectively referred to as an "inner wall" or an "outer wall."

[0113] The absolute value of the angle (taper angle) formed by the first sidewall 61 and the first main surface 3 in the semiconductor layer 2 may be more than 90° and not more than 95° (for example, about 91°). The absolute value of the angle (taper angle) formed by the second sidewall 62 and the first main surface 3 in the semiconductor layer 2 may be more than 90° and not more than 95° (for example, about 91°). The first trench gate structure 60 may be formed in a tapered shape in which the first width WT1 narrows from the first main surface 3 side toward the bottom wall 63 side in a cross-sectional view.

[0114] A bottom wall 63 of the first trench gate structure 60 is located in a region on the first main surface 3 side with respect to the bottom of the drift region 54. The bottom wall 63 of the first trench gate structure 60 is formed in a convex curved shape (U-shape) toward the bottom of the drift region 54.

[0115] The bottom wall 63 of the first trench gate structure 60 is located in a region on the first main surface 3 side with a first interval IT1 of 1 μm to 10 μm from the bottom of the drift region 54. The first interval IT1 may be 1 μm to 2 μm, 2 μm to 4 μm, 4 μm to 6 μm, 6 μm to 8 μm, or 8 μm to 10 μm. The first interval IT1 is preferably 1 μm to 5 μm.

[0116] In this embodiment, the second MISFET 57 includes a plurality of second FET structures 68. The plurality of second FET structures 68 are arranged at intervals along the first direction X in a plan view, and each extends in a strip shape along the second direction Y.

[0117] The second FET structures 68 extend in the same direction as the first FET structures 58. The second FET structures 68 are generally formed in a striped pattern in a plan view. In this embodiment, the second FET structures 68 are arranged alternately with the first FET structures 58, with one first FET structure 58 sandwiched between them.

[0118] 5 illustrates a region on one end side of the second FET structure 68, and omits illustrating a region on the other end side of the second FET structure 68. The structure of the region on the other end side of the second FET structure 68 is substantially similar to the structure of the region on one end side of the second FET structure 68. In the following, the structure of the region on one end side of the second FET structure 68 will be described as an example, and a description of the structure of the region on the other end side of the second FET structure 68 will be omitted.

[0119] Each second FET structure 68, in this embodiment, includes a second trench gate structure 70. A second width WT2 of the second trench gate structure 70 may be 0.5 μm or more and 5 μm or less. The second width WT2 is the width in a direction (first direction X) perpendicular to the direction in which the second trench gate structure 70 extends (second direction Y).

[0120] The second width WT2 may be 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, or 4.5 μm to 5 μm. The second width WT2 is preferably 0.8 μm to 1.2 μm.

[0121] The second width WT2 of the second trench gate structure 70 may be equal to or greater than the first width WT1 of the first trench gate structure 60 (WT1≦WT2). The second width WT2 may be equal to or smaller than the first width WT1 (WT1≧WT2). It is preferable that the second width WT2 is equal to the first width WT1 (WT1=WT2).

[0122] The second trench gate structure 70 penetrates the body region 55 and reaches the drift region 54. The second depth DT2 of the second trench gate structure 70 may be 1 μm or more and 10 μm or less. The second depth DT2 may be 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less. The second depth DT2 is preferably 2 μm or more and 6 μm or less.

[0123] The second depth DT2 of the second trench gate structure 70 may be equal to or greater than the first depth DT1 of the first trench gate structure 60 (DT1≦DT2). The second depth DT2 may be equal to or less than the first depth DT1 (DT1≧DT2). It is preferable that the second depth DT2 is equal to the first depth DT1 (DT1=DT2).

[0124] The second trench gate structure 70 includes a first sidewall 71 on one side, a second sidewall 72 on the other side, and a bottom wall 73 connecting the first sidewall 71 and the second sidewall 72. Hereinafter, the first sidewall 71, the second sidewall 72, and the bottom wall 73 may be collectively referred to as the "inner wall" or the "outer wall."

[0125] The absolute value of the angle (taper angle) formed by the first sidewall 71 and the first main surface 3 in the semiconductor layer 2 may be more than 90° and not more than 95° (for example, about 91°). The absolute value of the angle (taper angle) formed by the second sidewall 72 and the first main surface 3 in the semiconductor layer 2 may be more than 90° and not more than 95° (for example, about 91°). The second trench gate structure 70 may be formed in a tapered shape in which the second width WT2 narrows from the first main surface 3 side toward the bottom wall 73 side in a cross-sectional view.

[0126] A bottom wall 73 of the second trench gate structure 70 is located in a region on the first main surface 3 side with respect to the bottom of the drift region 54. The bottom wall 73 of the second trench gate structure 70 is formed in a convex curved shape (U-shape) toward the bottom of the drift region 54.

[0127] The bottom wall 73 of the second trench gate structure 70 is located in a region on the first main surface 3 side with a second interval IT2 of 1 μm to 10 μm from the bottom of the drift region 54. The second interval IT2 may be 1 μm to 2 μm, 2 μm to 4 μm, 4 μm to 6 μm, 6 μm to 8 μm, or 8 μm to 10 μm. The second interval IT2 is preferably 1 μm to 5 μm.

[0128] Cell regions 75 are defined in the regions between the first trench gate structures 60 and the second trench gate structures 70. The cell regions 75 are arranged at intervals along the first direction X in a plan view, and each extends in a strip shape along the second direction Y. The cell regions 75 extend in the same direction as the first trench gate structures 60 and the second trench gate structures 70. The cell regions 75 are formed in a stripe shape as a whole in a plan view.

[0129] A first depletion layer extends from the outer wall of the first trench gate structure 60 into the drift region 54. The first depletion layer extends from the outer wall of the first trench gate structure 60 in a direction along the first main surface 3 and in the normal direction Z. Similarly, a second depletion layer extends from the outer wall of the second trench gate structure 70 into the drift region 54. The second depletion layer extends from the outer wall of the second trench gate structure 70 in a direction along the first main surface 3 and in the normal direction Z.

[0130] The second trench gate structure 70 is arranged at a distance from the first trench gate structure 60, with the second depletion layer overlapping the first depletion layer. That is, the second depletion layer overlaps the first depletion layer in a region on the first main surface 3 side with respect to the bottom wall 73 of the second trench gate structure 70 in the cell region 75. With such a structure, it is possible to suppress the concentration of the electric field in the first trench gate structure 60 and the second trench gate structure 70, thereby suppressing a decrease in the breakdown voltage.

[0131] The second depletion layer preferably overlaps with the first depletion layer in a region on the bottom side of the drift region 54 with respect to the bottom wall 73 of the second trench gate structure 70. With such a structure, it is possible to suppress the electric field from concentrating on the bottom wall 63 of the first trench gate structure 60 and the bottom wall 73 of the second trench gate structure 70, and therefore it is possible to appropriately suppress a decrease in the breakdown voltage.

[0132] The pitch PS between the sidewalls of the first trench gate structure 60 and the second trench gate structure 70 may be not less than 0.2 μm and not more than 2 μm. The pitch PS is the distance in a direction (first direction X) perpendicular to the direction in which the first trench gate structure 60 and the second trench gate structure 70 extend (second direction Y) between the first sidewall 61 (second sidewall 62) of the first trench gate structure 60 and the second sidewall 72 (first sidewall 71) of the second trench gate structure 70.

[0133] The pitch PS may be 0.2 μm to 0.4 μm, 0.4 μm to 0.6 μm, 0.6 μm to 0.8 μm, 0.8 μm to 1.0 μm, 1.0 μm to 1.2 μm, 1.2 μm to 1.4 μm, 1.4 μm to 1.6 μm, 1.6 μm to 1.8 μm, or 1.8 μm to 2.0 μm. The pitch PS is preferably 0.3 μm to 1.5 μm.

[0134] The pitch PC between the central portions of the first trench gate structure 60 and the second trench gate structure 70 may be 1 μm or more and 7 μm or less. The pitch PC is the distance in a direction (first direction X) perpendicular to the direction in which the first trench gate structure 60 and the second trench gate structure 70 extend (second direction Y) between the central portion of the first trench gate structure 60 and the central portion of the second trench gate structure 70.

[0135] The pitch PC may be 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 5 μm or less, 5 μm or more and 6 μm or less, or 6 μm or more and 7 μm or less. The pitch PC is preferably 1 μm or more and 3 μm or less.

[0136] More specifically, the first trench gate structure 60 includes a first gate trench 81, a first insulating layer 82, and a first electrode 83. The first gate trench 81 is formed by digging down the first main surface 3 toward the second main surface 4.

[0137] The first gate trench 81 defines a first sidewall 61, a second sidewall 62, and a bottom wall 63 of the first trench gate structure 60. Hereinafter, the first sidewall 61, the second sidewall 62, and the bottom wall 63 of the first trench gate structure 60 are also referred to as the first sidewall 61, the second sidewall 62, and the bottom wall 63 of the first gate trench 81.

[0138] The first insulating layer 82 is formed in the form of a film along the inner wall of the first gate trench 81. The first insulating layer 82 defines a concave space within the first gate trench 81. A portion of the first insulating layer 82 covering the bottom wall 63 of the first gate trench 81 is formed following the shape of the bottom wall 63 of the first gate trench 81. As a result, the first insulating layer 82 defines a U-shaped space recessed in a U-shape within the first gate trench 81.

[0139] The first insulating layer 82 includes at least one of silicon oxide (SiO2), silicon nitride (SiN), aluminum oxide (Al2O3), zirconium oxide (ZrO2), and tantalum oxide (Ta2O3).

[0140] The first insulating layer 82 may have a laminated structure including a SiN layer and a SiO2 layer laminated in this order from the semiconductor layer 2 side. The first insulating layer 82 may have a laminated structure including a SiO2 layer and a SiN layer laminated in this order from the semiconductor layer 2 side. The first insulating layer 82 may have a single layer structure made of a SiO2 layer or a SiN layer. In this embodiment, the first insulating layer 82 has a single layer structure made of a SiO2 layer.

[0141] The first insulating layer 82 includes a first bottom side insulating layer 84 and a first opening side insulating layer 85 formed in this order from the bottom wall 63 side of the first gate trench 81 toward the first main surface 3 side.

[0142] The first bottom side insulating layer 84 covers the inner wall of the first gate trench 81 on the bottom wall 63 side. More specifically, the first bottom side insulating layer 84 covers the inner wall of the first gate trench 81 on the bottom wall 63 side with respect to the bottom of the body region 55. The first bottom side insulating layer 84 defines a U-shaped space on the bottom wall 63 side of the first gate trench 81. The first bottom side insulating layer 84 has a smooth inner wall surface that defines the U-shaped space. The first bottom side insulating layer 84 is in contact with the drift region 54. A part of the first bottom side insulating layer 84 may be in contact with the body region 55.

[0143] The first opening-side insulating layer 85 covers the inner wall on the opening side of the first gate trench 81. More specifically, the first opening-side insulating layer 85 covers the first side wall 61 and the second side wall 62 of the first gate trench 81 in the region on the opening side of the first gate trench 81 with respect to the bottom of the body region 55. The first opening-side insulating layer 85 is in contact with the body region 55. A part of the first opening-side insulating layer 85 may be in contact with the drift region 54.

[0144] The first bottom-side insulating layer 84 has a first thickness T1. The first opening-side insulating layer 85 has a second thickness T2 (T2 < T1) less than the first thickness T1. The first thickness T1 is the thickness along the normal direction of the inner wall of the first gate trench 81 in the first bottom-side insulating layer 84. The second thickness T2 is the thickness along the normal direction of the inner wall of the first gate trench 81 in the first opening-side insulating layer 85.

[0145] Note that the first ratio T1 / WT1 of the first thickness T1 to the first width WT1 of the first gate trench 81 may be 0.1 or more and 0.4 or less. Also, the first ratio T1 / WT1 may be 0.1 or more and 0.15 or less, 0.15 or more and 0.2 or less, 0.2 or more and 0.25 or less, 0.25 or more and 0.3 or less, 0.3 or more and 0.35 or less, or 0.35 or more and 0.4 or less. The first ratio T1 / WT1 is preferably 0.25 or more and 0.35 or less.

[0146] Note that the first thickness T1 of the first bottom-side insulating layer 84 may be 1500 Å or more and 4000 Å or less. The first thickness T1 may be 1500 Å or more and 2000 Å or less, 2000 Å or more and 2500 Å or less, 2500 Å or more and 3000 Å or less, 3000 Å or more and 3500 Å or less, or 3500 Å or more and 4000 Å or less. The first thickness T1 is preferably 1800 Å or more and 3500 Å or less.

[0147] The first thickness T1 may be adjusted to 4000 Å or more and 12000 Å or less according to the first width WT1 of the first gate trench 81. The first thickness T1 may be 4000 Å or more and 5000 Å or less, 5000 Å or more and 6000 Å or less, 6000 Å or more and 7000 Å or less, 7000 Å or more and 8000 Å or less, 8000 Å or more and 9000 Å or less, 9000 Å or more and 10000 Å or more and 11000 Å or less, or 11000 Å or more and 12000 Å or less. In this case, the withstand voltage of the semiconductor device 1 can be increased by thickening the first bottom-side insulating layer 84.

[0148] The second thickness T2 of the first opening-side insulating layer 85 may be 1 / 100 or more and 1 / 10 or less of the first thickness T1 of the first bottom-side insulating layer 84. The second thickness T2 may be 100 Å or more and 500 Å or less. The second thickness T2 may be 100 Å or more and 200 Å or less, 200 Å or more and 300 Å or less, 300 Å or more and 400 Å or less, or 400 Å or more and 500 Å or less. The second thickness T2 is preferably 200 Å or more and 400 Å or less.

[0149] The first bottom side insulating layer 84 is formed in a manner such that the first thickness T1 decreases from the portion covering the first sidewall 61 and the second sidewall 62 of the first gate trench 81 toward the portion covering the bottom wall 63 of the first gate trench 81.

[0150] The thickness of the portion of the first bottom side insulating layer 84 covering the bottom wall 63 of the first gate trench 81 is smaller than the thickness of the portion of the first bottom side insulating layer 84 covering the first side wall 61 and the second side wall 62 of the first gate trench 81. The opening width on the bottom wall side of the U-shaped space partitioned by the first bottom side insulating layer 84 is expanded by the reduction in the first thickness T1. This prevents the U-shaped space from tapering. Such a U-shaped space is formed, for example, by etching the inner wall of the first bottom side insulating layer 84 (for example, wet etching).

[0151] The first electrode 83 is embedded in the first gate trench 81 with a first insulating layer 82 sandwiched therebetween. A first gate control signal (first control signal) including an on signal Von and an off signal Voff is applied to the first electrode 83. In this embodiment, the first electrode 83 has an insulating and separated split electrode structure including a first bottom side electrode 86, a first opening side electrode 87, and a first intermediate insulating layer 88.

[0152] The first bottom side electrode 86 is embedded on the bottom wall 63 side of the first gate trench 81 with the first insulating layer 82 sandwiched therebetween. More specifically, the first bottom side electrode 86 is embedded on the bottom wall 63 side of the first gate trench 81 with the first bottom side insulating layer 84 sandwiched therebetween. The first bottom side electrode 86 faces the drift region 54 with the first bottom side insulating layer 84 sandwiched therebetween. A portion of the first bottom side electrode 86 may face the body region 55 with the first bottom side insulating layer 84 sandwiched therebetween.

[0153] The first bottom side electrode 86 defines an inverted concave recess in a cross-sectional view between the first bottom side insulating layer 84 and the first opening side insulating layer 85 at the opening side of the first gate trench 81. With this structure, local electric field concentration on the first bottom side electrode 86 can be suppressed, thereby suppressing a decrease in the breakdown voltage. In particular, by embedding the first bottom side electrode 86 in the expanded U-shaped space of the first bottom side insulating layer 84, it is possible to appropriately suppress the first bottom side electrode 86 from becoming tapered from the upper end to the lower end. This makes it possible to appropriately suppress local electric field concentration on the lower end of the first bottom side electrode 86.

[0154] The first bottom side electrode 86 may include at least one of conductive polysilicon, tungsten, aluminum, copper, an aluminum alloy, and a copper alloy. In this embodiment, the first bottom side electrode 86 includes conductive polysilicon. The conductive polysilicon may include n-type impurities or p-type impurities. It is preferable that the conductive polysilicon includes n-type impurities.

[0155] The first opening-side electrode 87 is embedded on the opening side of the first gate trench 81 with the first insulating layer 82 interposed therebetween. More specifically, the first opening-side electrode 87 is embedded in a reverse concave-shaped recess partitioned on the opening side of the first gate trench 81 with the first opening-side insulating layer 85 interposed therebetween. The first opening-side electrode 87 faces the body region 55 with the first opening-side insulating layer 85 interposed therebetween. A part of the first opening-side electrode 87 may face the drift region 54 with the first opening-side insulating layer 85 interposed therebetween.

[0156] The first opening-side electrode 87 may contain at least one of conductive polysilicon, tungsten, aluminum, copper, aluminum alloy, and copper alloy. The first opening-side electrode 87 preferably contains the same type of conductive material as the first bottom-side electrode 86. In this form, the first opening-side electrode 87 contains conductive polysilicon. The conductive polysilicon may contain an n-type impurity or a p-type impurity. The conductive polysilicon preferably contains an n-type impurity.

[0157] The first intermediate insulating layer 88 is interposed between the first bottom-side electrode 86 and the first opening-side electrode 87 and electrically insulates the first bottom-side electrode 86 and the first opening-side electrode 87. More specifically, the first intermediate insulating layer 88 covers the first bottom-side electrode 86 exposed from the first bottom-side insulating layer 84 in the region between the first bottom-side electrode 86 and the first opening-side electrode 87. The first intermediate insulating layer 88 covers the upper end portion (more specifically, the protruding portion) of the first bottom-side electrode 86. The first intermediate insulating layer 88 is continuous with the first insulating layer 82 (the first bottom-side insulating layer 84).

[0158] The first intermediate insulating layer 88 has a third thickness T3. The third thickness T3 is less than the first thickness T1 of the first bottom-side insulating layer 84 (T3 < T1). The third thickness T3 may be 1 / 100 or more and 1 / 10 or less of the first thickness T1. The third thickness T3 may be 100 Å or more and 500 Å or less. The third thickness T3 may be 100 Å or more and 200 Å or less, 200 Å or more and 300 Å or less, 300 Å or more and 400 Å or less, or 400 Å or more and 500 Å or less. The third thickness T3 is preferably 200 Å or more and 400 Å or less.

[0159] The first intermediate insulating layer 88 includes at least one of silicon oxide (SiO2), silicon nitride (SiN), aluminum oxide (Al2O3), zirconium oxide (ZrO2), and tantalum oxide (Ta2O3). In this embodiment, the first intermediate insulating layer 88 has a single-layer structure made of a SiO2 layer.

[0160] In this embodiment, the exposed portion of the first opening side electrode 87 exposed from the first gate trench 81 is located on the bottom wall 63 side of the first gate trench 81 with respect to the first main surface 3. The exposed portion of the first opening side electrode 87 is formed in a curved shape toward the bottom wall 63 of the first gate trench 81.

[0161] The exposed portion of the first opening side electrode 87 is covered with a first cap insulating layer formed in a film shape. The first cap insulating layer is continuous with the first insulating layer 82 (first opening side insulating layer 85) in the first gate trench 81. The first cap insulating layer may contain silicon oxide (SiO2).

[0162] Each first FET structure 58 further includes a p-type first channel region 91 (first channel). The first channel region 91 is formed in a region in the body region 55 facing the first electrode 83 (first opening side electrode 87) with the first insulating layer 82 (first opening side insulating layer 85) interposed therebetween.

[0163] The first channel region 91 is formed along the first sidewall 61 or the second sidewall 62, or the first sidewall 61 and the second sidewall 62, of the first trench gate structure 60. In this embodiment, the first channel region 91 is formed along the first sidewall 61 and the second sidewall 62 of the first trench gate structure 60.

[0164] Each of the first FET structures 58 is an n-type FET formed in the surface layer of the body region 55. +The first source region 92 defines a first channel region 91 between the drift region 54 and the body region 55. The n-type impurity concentration of the first source region 92 exceeds the n-type impurity concentration of the drift region 54. The n-type impurity concentration of the first source region 92 is 1×10 19 cm -3 More than 1×10 21 cm -3 It may be the following.

[0165] In this embodiment, each first FET structure 58 includes a plurality of first source regions 92. The plurality of first source regions 92 are formed at intervals along the first trench gate structure 60 in the surface layer portion of the body region 55. More specifically, the plurality of first source regions 92 are formed along the first sidewall 61 or the second sidewall 62, or the first sidewall 61 and the second sidewall 62, of the first trench gate structure 60. In this embodiment, the plurality of first source regions 92 are formed at intervals along the first sidewall 61 and the second sidewall 62 of the first trench gate structure 60.

[0166] The bottoms of the multiple first source regions 92 are located in a region on the first main surface 3 side with respect to the bottom of the body region 55. As a result, the multiple first source regions 92 face the first electrode 83 (first opening side electrode 87) with the first insulating layer 82 (first opening side insulating layer 85) sandwiched therebetween. In this manner, the first channel region 91 of the first MISFET 56 is formed in a region in the body region 55 sandwiched between the multiple first source regions 92 and the drift region 54.

[0167] Each of the first FET structures 58 is a p + The p-type impurity concentration of the first contact region 93 exceeds the p-type impurity concentration of the body region 55. The p-type impurity concentration of the first contact region 93 is, for example, 1×10 19 cm -3 More than 1×10 21 cm -3 It may be the following.

[0168] In this embodiment, each first FET structure 58 includes a plurality of first contact regions 93. The plurality of first contact regions 93 are formed at intervals along the first trench gate structure 60 in a surface layer portion of the body region 55. More specifically, the plurality of first contact regions 93 are formed along the first sidewall 61 or the second sidewall 62, or the first sidewall 61 and the second sidewall 62, of the first trench gate structure 60.

[0169] In this embodiment, the multiple first contact regions 93 are formed at intervals along the first sidewall 61 and the second sidewall 62 of the first trench gate structure 60. More specifically, the multiple first contact regions 93 are formed in a surface layer portion of the body region 55 in an alternating arrangement with the multiple first source regions 92. The bottoms of the multiple first contact regions 93 are located in a region on the first main surface 3 side with respect to the bottom of the body region 55.

[0170] The second trench gate structure 70 includes a second gate trench 101, a second insulating layer 102, and a second electrode 103. The second gate trench 101 is formed by digging down the first main surface 3 toward the second main surface 4.

[0171] The second gate trench 101 defines a first sidewall 71, a second sidewall 72, and a bottom wall 73 of the second trench gate structure 70. Hereinafter, the first sidewall 71, the second sidewall 72, and the bottom wall 73 of the second trench gate structure 70 are also referred to as the first sidewall 71, the second sidewall 72, and the bottom wall 73 of the second gate trench 101.

[0172] The second insulating layer 102 is formed in the form of a film along the inner wall of the second gate trench 101. The second insulating layer 102 defines a concave space within the second gate trench 101. A portion of the second insulating layer 102 covering the bottom wall 73 of the second gate trench 101 is formed following the shape of the bottom wall 73 of the second gate trench 101. As a result, the second insulating layer 102 defines a U-shaped space recessed in a U-shape within the second gate trench 101.

[0173] The second insulating layer 102 includes at least one of silicon oxide (SiO2), silicon nitride (SiN), aluminum oxide (Al2O3), zirconium oxide (ZrO2), and tantalum oxide (Ta2O3).

[0174] The second insulating layer 102 may have a laminated structure including a SiN layer and a SiO2 layer laminated in this order from the semiconductor layer 2 side. The second insulating layer 102 may have a laminated structure including a SiO2 layer and a SiN layer laminated in this order from the semiconductor layer 2 side. The second insulating layer 102 may have a single layer structure made of a SiO2 layer or a SiN layer. In this embodiment, the second insulating layer 102 has a single layer structure made of a SiO2 layer.

[0175] The second insulating layer 102 includes a second bottom side insulating layer 104 and a second opening side insulating layer 105 formed in this order from the bottom wall 73 side of the second gate trench 101 toward the first main surface 3 side.

[0176] The second bottom side insulating layer 104 covers the inner wall of the second gate trench 101 on the bottom wall 73 side. More specifically, the second bottom side insulating layer 104 covers the inner wall of the second gate trench 101 on the bottom wall 73 side with respect to the bottom of the body region 55. The second bottom side insulating layer 104 defines a U-shaped space on the bottom wall 73 side of the second gate trench 101. The second bottom side insulating layer 104 has a smooth inner wall surface that defines the U-shaped space. The second bottom side insulating layer 104 is in contact with the drift region 54. A part of the second bottom side insulating layer 104 may be in contact with the body region 55.

[0177] The second opening-side insulating layer 105 covers the inner wall on the opening side of the second gate trench 101. More specifically, the second opening-side insulating layer 105 covers the first side wall 71 and the second side wall 72 of the second gate trench 101 in a region on the opening side of the second gate trench 101 relative to the bottom of the body region 55. The second opening-side insulating layer 105 is in contact with the body region 55. A portion of the second opening-side insulating layer 105 may be in contact with the drift region 54.

[0178] The second bottom-side insulating layer 104 has a fourth thickness T4. The second opening-side insulating layer 105 has a fifth thickness T5 (T5 < T4) less than the fourth thickness T4. The fourth thickness T4 is the thickness along the normal direction of the inner wall of the second gate trench 101 in the second bottom-side insulating layer 104. The fifth thickness T5 is the thickness along the normal direction of the inner wall of the second gate trench 101 in the second opening-side insulating layer 105.

[0179] The second ratio T4 / WT2 of the fourth thickness T4 to the second width WT2 of the second gate trench 101 may be 0.1 or more and 0.4 or less. For example, the second ratio T4 / WT2 may be 0.1 or more and 0.15 or less, 0.15 or more and 0.2 or less, 0.2 or more and 0.25 or less, 0.25 or more and 0.3 or less, 0.3 or more and 0.35 or less, or 0.35 or more and 0.4 or less. It is preferable that the second ratio T4 / WT2 is 0.25 or more and 0.35 or less.

[0180] The second ratio T4 / WT2 may be less than or equal to the first ratio T1 / WT1 (T4 / WT2 ≦ T1 / WT1). The second ratio T4 / WT2 may be greater than or equal to the first ratio T1 / WT1 (T4 / WT2 ≧ T1 / WT1). Also, the second ratio T4 / WT2 may be equal to the first ratio T1 / WT1 (T4 / WT2 = T1 / WT1).

[0181] The fourth thickness T4 of the second bottom-side insulating layer 104 may be 1500 Å or more and 4000 Å or less. The fourth thickness T4 may be 1500 Å or more and 2000 Å or less, 2000 Å or more and 2500 Å or less, 2500 Å or more and 3000 Å or less, 3000 Å or more and 3500 Å or less, or 3500 Å or more and 4000 Å or less. It is preferable that the fourth thickness T4 is 1800 Å or more and 3500 Å or less.

[0182] The fourth thickness T4 may be 4000 Å or more and 12000 Å or less according to the second width WT2 of the second gate trench 101. The fourth thickness T4 may be 4000 Å or more and 5000 Å or less, 5000 Å or more and 6000 Å or less, 6000 Å or more and 7000 Å or less, 7000 Å or more and 8000 Å or less, 8000 Å or more and 9000 Å or less, 9000 Å or more and 10000 Å or less, 10000 Å or more and 11000 Å or less, or 11000 Å or more and 12000 Å or less. In this case, the breakdown voltage of the semiconductor device 1 can be increased by thickening the second bottom insulating layer 104.

[0183] The fourth thickness T4 may be less than or equal to the first thickness T1 (T4≦T1). The fourth thickness T4 may be greater than or equal to the first thickness T1 (T4≧T1). The fourth thickness T4 may be equal to the first thickness T1 (T4=T1).

[0184] The fifth thickness T5 of the second opening side insulating layer 105 is less than the fourth thickness T4 of the second bottom side insulating layer 104 (T5<T4). The fifth thickness T5 may be 1 / 100 or more and 1 / 10 or less of the fourth thickness T4. It may be 100 Å or more and 500 Å or less. The fifth thickness T5 may be 100 Å or more and 200 Å or less, 200 Å or more and 300 Å or less, 300 Å or more and 400 Å or less, or 400 Å or more and 500 Å or less. The fifth thickness T5 is preferably 200 Å or more and 400 Å or less.

[0185] The fifth thickness T5 may be less than or equal to the second thickness T2 (T5≦T2). The fifth thickness T5 may be greater than or equal to the second thickness T2 (T5≧T2). The fifth thickness T5 may be equal to the second thickness T2 (T5=T2).

[0186] The second bottom side insulating layer 104 is formed in such a manner that the fourth thickness T4 decreases from the portion covering the first side wall 71 and the second side wall 72 of the second gate trench 101 toward the portion covering the bottom wall 73 of the second gate trench 101.

[0187] The thickness of the portion of the second bottom side insulating layer 104 covering the bottom wall 73 of the second gate trench 101 is smaller than the thickness of the portion of the second bottom side insulating layer 104 covering the first side wall 71 and the second side wall 72 of the second gate trench 101. The opening width on the bottom wall side of the U-shaped space partitioned by the second bottom side insulating layer 104 is expanded by the reduction in the fourth thickness T4. This prevents the U-shaped space from tapering. Such a U-shaped space is formed, for example, by etching the inner wall of the second bottom side insulating layer 104 (for example, wet etching).

[0188] The second electrode 103 is embedded in the second gate trench 101 with the second insulating layer 102 sandwiched therebetween. A predetermined second gate control signal (second control signal) including an on signal Von and an off signal Voff is applied to the second electrode 103.

[0189] The second electrode 103, in this embodiment, has an insulated split electrode structure including a second bottom side electrode 106, a second aperture side electrode 107, and a second intermediate insulating layer 108. The second bottom side electrode 106, in this embodiment, is electrically connected to the first bottom side electrode 86. The second aperture side electrode 107 is electrically insulated from the first aperture side electrode 87.

[0190] The second bottom side electrode 106 is embedded on the bottom wall 73 side of the second gate trench 101 with the second insulating layer 102 in between. More specifically, the second bottom side electrode 106 is embedded on the bottom wall 73 side of the second gate trench 101 with the second bottom side insulating layer 104 in between. The second bottom side electrode 106 faces the drift region 54 with the second bottom side insulating layer 104 in between. A part of the second bottom side electrode 106 may face the body region 55 with the second bottom side insulating layer 104 in between.

[0191] The second bottom side electrode 106 defines an inverted concave recess in a cross-sectional view between the second bottom side insulating layer 104 and the second opening side insulating layer 105 at the opening side of the second gate trench 101. With this structure, local electric field concentration on the second bottom side electrode 106 can be suppressed, so that a decrease in the breakdown voltage can be suppressed. In particular, by embedding the second bottom side electrode 106 in the expanded U-shaped space of the second bottom side insulating layer 104, it is possible to appropriately suppress the second bottom side electrode 106 from becoming tapered from the upper end to the lower end. This allows the local electric field concentration on the lower end of the second bottom side electrode 106 to be appropriately suppressed.

[0192] The second bottom side electrode 106 may include at least one of conductive polysilicon, tungsten, aluminum, copper, an aluminum alloy, and a copper alloy. In this embodiment, the second bottom side electrode 106 includes conductive polysilicon. The conductive polysilicon may include n-type impurities or p-type impurities. The conductive polysilicon preferably includes n-type impurities.

[0193] The second opening side electrode 107 is embedded in the opening side of the second gate trench 101 with the second insulating layer 102 sandwiched therebetween. More specifically, the second opening side electrode 107 is embedded in an inverted concave recess defined on the opening side of the second gate trench 101 with the second opening side insulating layer 105 sandwiched therebetween. The second opening side electrode 107 faces the body region 55 with the second opening side insulating layer 105 sandwiched therebetween. A part of the second opening side electrode 107 may face the drift region 54 with the second opening side insulating layer 105 sandwiched therebetween.

[0194] The second opening side electrode 107 may contain at least one of conductive polysilicon, tungsten, aluminum, copper, an aluminum alloy, and a copper alloy. The second opening side electrode 107 preferably contains the same type of conductive material as the second bottom side electrode 106. In this embodiment, the second opening side electrode 107 contains conductive polysilicon. The conductive polysilicon may contain n-type impurities or p-type impurities. The conductive polysilicon preferably contains n-type impurities.

[0195] The second intermediate insulating layer 108 is interposed between the second bottom-side electrode 106 and the second opening-side electrode 107, and electrically insulates the second bottom-side electrode 106 and the second opening-side electrode 107. More specifically, the second intermediate insulating layer 108 covers the second bottom-side electrode 106 exposed from the second bottom-side insulating layer 104 in the region between the second bottom-side electrode 106 and the second opening-side electrode 107. The second intermediate insulating layer 108 covers the upper end portion (more specifically, the protruding portion) of the second bottom-side electrode 106. The second intermediate insulating layer 108 is continuous with the second insulating layer 102 (the second bottom-side insulating layer 104).

[0196] The second intermediate insulating layer 108 has a sixth thickness T6. The sixth thickness T6 is less than the fourth thickness T4 of the second bottom-side insulating layer 104 (T6 < T4). The sixth thickness T6 may be 1 / 100 or more and 1 / 10 or less of the fourth thickness T4. The sixth thickness T6 may be 100 Å or more and 500 Å or less. The sixth thickness T6 may be 100 Å or more and 200 Å or less, 200 Å or more and 300 Å or less, 300 Å or more and 400 Å or less, or 400 Å or more and 500 Å or less. It is preferable that the sixth thickness T6 is 200 Å or more and 400 Å or less.

[0197] The sixth thickness T6 may be less than or equal to the third thickness T3 (T6 ≤ T3). The sixth thickness T6 may be greater than or equal to the third thickness T3 (T6 ≥ T3). The sixth thickness T6 may be equal to the third thickness T3 (T6 = T3).

[0198] The second intermediate insulating layer 108 contains at least one of silicon oxide (SiO2), silicon nitride (SiN), aluminum oxide (Al2O3), zirconium oxide (ZrO2), and tantalum oxide (Ta2O3). In this form, the second intermediate insulating layer 108 has a single-layer structure composed of a SiO2 layer.

[0199] In this form, the exposed portion of the second opening-side electrode 107 exposed from the second gate trench 101 is located on the bottom wall 73 side of the second gate trench 101 with respect to the first main surface 3. The exposed portion of the second opening-side electrode 107 is formed in a curved shape toward the bottom wall 73 of the second gate trench 101.

[0200] The exposed portion of the second opening side electrode 107 is covered with a second cap insulating layer formed in a film shape. The second cap insulating layer is continuous with the second insulating layer 102 (second opening side insulating layer 105) in the second gate trench 101. The second cap insulating layer may contain silicon oxide (SiO2).

[0201] Each second FET structure 68 further includes a p-type second channel region 111 (second channel). More specifically, the second channel region 111 is formed in a region in the body region 55 facing the second electrode 103 (second opening side electrode 107) with the second insulating layer 102 (second opening side insulating layer 105) interposed therebetween.

[0202] More specifically, the second channel region 111 is formed along the first sidewall 71 or the second sidewall 72, or the first sidewall 71 and the second sidewall 72, of the second trench gate structure 70. In this embodiment, the second channel region 111 is formed along the first sidewall 71 and the second sidewall 72 of the second trench gate structure 70.

[0203] Each of the second FET structures 68 is an n-type FET formed in the surface layer of the body region 55. + The second source region 112 defines a second channel region 111 between the drift region 54 and the body region 55.

[0204] The n-type impurity concentration of the second source region 112 exceeds the n-type impurity concentration of the drift region 54. The n-type impurity concentration of the second source region 112 is 1×10 19 cm -3 More than 1×10 21 cm -3 The n-type impurity concentration of the second source region 112 is preferably equal to the n-type impurity concentration of the first source region 92.

[0205] In this embodiment, each second FET structure 68 includes a plurality of second source regions 112. The plurality of second source regions 112 are formed at intervals along the second trench gate structure 70 in the surface layer portion of the body region 55. Specifically, the plurality of second source regions 112 are formed along the first sidewall 71 or the second sidewall 72, or the first sidewall 71 and the second sidewall 72, of the second trench gate structure 70. In this embodiment, the plurality of second source regions 112 are formed at intervals along the first sidewall 71 and the second sidewall 72 of the second trench gate structure 70.

[0206] In this embodiment, each second source region 112 faces each first source region 92 along the first direction X. Also, each second source region 112 is integral with each first source region 92. In FIG. 5, the first source region 92 and the second source region 112 are shown distinguished by a boundary line, but in reality there is no clear boundary line between the first source region 92 and the second source region 112.

[0207] Each second source region 112 may be formed offset from each first source region 92 in the second direction Y so as not to face a part or all of each first source region 92 along the first direction X. In other words, the multiple first source regions 92 and the multiple second source regions 112 may be arranged in a staggered manner in a plan view.

[0208] The bottoms of the multiple second source regions 112 are located in a region on the first main surface 3 side with respect to the bottom of the body region 55. As a result, the multiple second source regions 112 face the second electrode 103 (second opening side electrode 107) with the second insulating layer 102 (second opening side insulating layer 105) sandwiched therebetween. In this manner, the second channel region 111 of the second MISFET 57 is formed in a region in the body region 55 sandwiched between the multiple second source regions 112 and the drift region 54.

[0209] Each of the second FET structures 68 is a p +The p-type impurity concentration of the second contact region 113 is greater than the p-type impurity concentration of the body region 55. The p-type impurity concentration of the second contact region 113 is greater than 1×10 19 cm -3 More than 1×10 21 cm -3 The p-type impurity concentration of the second contact region 113 is preferably equal to the p-type impurity concentration of the first contact region 93.

[0210] In this embodiment, each second FET structure 68 includes a plurality of second contact regions 113. The plurality of second contact regions 113 are formed at intervals along the second trench gate structure 70 in a surface layer portion of the body region 55. More specifically, the plurality of second contact regions 113 are formed along the first sidewall 71 or the second sidewall 72, or the first sidewall 71 and the second sidewall 72, of the second trench gate structure 70. The bottoms of the plurality of second contact regions 113 are located in a region on the first main surface 3 side with respect to the bottom of the body region 55.

[0211] In this embodiment, the second contact regions 113 are formed at intervals along the first sidewall 71 and the second sidewall 72 of the second trench gate structure 70. More specifically, the second contact regions 113 are formed in the surface layer portion of the body region 55 in an alternating arrangement with the second source regions 112.

[0212] 5, in this embodiment, each second contact region 113 faces each first contact region 93 along the first direction X. Each second contact region 113 is integral with each first contact region 93.

[0213] In FIG. 5, the first contact region 93 and the second contact region 113 are collectively referred to as “p + " symbol.

[0214] Each second contact region 113 may be formed offset from each first contact region 93 in the second direction Y so as not to face a part or all of each first contact region 93 along the first direction X. In other words, the multiple first contact regions 93 and the multiple second contact regions 113 may be arranged in a staggered manner in a plan view.

[0215] 5, in this embodiment, the body region 55 is exposed from a region between one end of the first trench gate structure 60 and one end of the second trench gate structure 70 on the first main surface 3 of the semiconductor layer 2. The first source region 92, the first contact region 93, the second source region 112, and the second contact region 113 are not formed in a region sandwiched between one end of the first trench gate structure 60 and one end of the second trench gate structure 70 on the first main surface 3.

[0216] Similarly, although not shown, in this embodiment, the body region 55 is exposed from a region between the other end of the first trench gate structure 60 and the other end of the second trench gate structure 70 on the first main surface 3 of the semiconductor layer 2. The first source region 92, the first contact region 93, the second source region 112, and the second contact region 113 are not formed in a region sandwiched between the other end of the first trench gate structure 60 and the other end of the second trench gate structure 70.

[0217] 5, a plurality (two in this example) of trench contact structures 120 are formed on the first main surface 3 of the semiconductor layer 2. The plurality of trench contact structures 120 include a trench contact structure 120 on one side and a trench contact structure 120 on the other side.

[0218] The trench contact structure 120 on one side is located in a region on one end side of the first trench gate structure 60 and one end side of the second trench gate structure 70. The trench contact structure 120 on the other side is located in a region on the other end side of the first trench gate structure 60 and the other end side of the second trench gate structure 70.

[0219] The other side trench contact structure 120 has a structure substantially similar to that of the one side trench contact structure 120. In the following, the structure of the one side trench contact structure 120 will be described as an example, and a detailed description of the structure of the other side trench contact structure 120 will be omitted.

[0220] The trench contact structure 120 is connected to one end of the first trench gate structure 60 and one end of the second trench gate structure 70. In this embodiment, the trench contact structure 120 extends in a strip shape along the first direction X in a plan view.

[0221] The width WTC of the trench contact structure 120 may be 0.5 μm or more and 5 μm or less. The width WTC is the width in a direction (second direction Y) perpendicular to the direction in which the trench contact structure 120 extends (first direction X).

[0222] The width WTC may be 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, or 4.5 μm to 5 μm. The width WTC is preferably 0.8 μm to 1.2 μm.

[0223] The width WTC is preferably equal to the first width WT1 of the first trench gate structure 60 (WTC=WT1). The width WTC is preferably equal to the second width WT2 of the second trench gate structure 70 (WTC=WT2).

[0224] The trench contact structure 120 penetrates the body region 55 and reaches the drift region 54. The depth DTC of the trench contact structure 120 may be 1 μm or more and 10 μm or less. The depth DTC may be 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less. The depth DTC is preferably 2 μm or more and 6 μm or less.

[0225] The depth DTC is preferably equal to the first depth DT1 of the first trench gate structure 60 (DTC=DT1). The depth DTC is preferably equal to the second depth DT2 of the second trench gate structure 70 (DTC=DT2).

[0226] The trench contact structure 120 includes a first sidewall 121 on one side, a second sidewall 122 on the other side, and a bottom wall 123 connecting the first sidewall 121 and the second sidewall 122. Hereinafter, the first sidewall 121, the second sidewall 122, and the bottom wall 123 may be collectively referred to as "inner walls." The first sidewall 121 is a connection surface connected to the first trench gate structure 60 and the second trench gate structure 70.

[0227] The first sidewall 121, the second sidewall 122, and the bottom wall 123 are located in the drift region 54. The first sidewall 121 and the second sidewall 122 extend along the normal direction Z. The first sidewall 121 and the second sidewall 122 may be formed perpendicular to the first main surface 3.

[0228] The absolute value of the angle (taper angle) formed by the first sidewall 121 and the first main surface 3 in the semiconductor layer 2 may be more than 90° and not more than 95° (for example, about 91°). The absolute value of the angle (taper angle) formed by the second sidewall 122 and the first main surface 3 in the semiconductor layer 2 may be more than 90° and not more than 95° (for example, about 91°). The trench contact structure 120 may be formed in a tapered shape (tapered shape) in which the width WTC narrows from the first main surface 3 side of the semiconductor layer 2 toward the bottom wall 123 side in a cross-sectional view.

[0229] The bottom wall 123 is located in a region on the first main surface 3 side with respect to the bottom of the drift region 54. The bottom wall 123 is formed in a convex curved shape toward the bottom of the drift region 54. The bottom wall 123 is located in a region on the first main surface 3 side with a gap ITC of 1 μm or more and 10 μm or less from the bottom of the drift region 54. The gap ITC may be 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less. The gap ITC is preferably 1 μm or more and 5 μm or less.

[0230] The interval ITC is preferably equal to the first interval IT1 of the first trench gate structure 60 (ITC=IT1). The interval ITC is preferably equal to the second interval IT2 of the second trench gate structure 70 (ITC=IT2).

[0231] The trench contact structure 120 includes a contact trench 131, a contact insulating layer 132, and a contact electrode 133. The contact trench 131 is formed by digging down the first main surface 3 of the semiconductor layer 2 toward the second main surface 4 side.

[0232] The contact trench 131 defines a first sidewall 121, a second sidewall 122, and a bottom wall 123 of the trench contact structure 120. Hereinafter, the first sidewall 121, the second sidewall 122, and the bottom wall 123 of the trench contact structure 120 are also referred to as the first sidewall 121, the second sidewall 122, and the bottom wall 123 of the contact trench 131.

[0233] The first sidewall 121 of the contact trench 131 communicates with the first sidewall 61 and the second sidewall 62 of the first gate trench 81. The first sidewall 121 of the contact trench 131 communicates with the first sidewall 71 and the second sidewall 72 of the second gate trench 101. The contact trench 131 forms one trench with the first gate trench 81 and the second gate trench 101.

[0234] The contact insulating layer 132 is formed in a film shape along the inner wall of the contact trench 131. The contact insulating layer 132 defines a concave space within the contact trench 131. The portion of the contact insulating layer 132 that covers the bottom wall 123 of the contact trench 131 is formed following the shape of the bottom wall 123 of the contact trench 131.

[0235] The contact insulating layer 132 defines a U-shaped space recessed into a U shape in the contact trench 131 in a similar manner to the first bottom side insulating layer 84 (second bottom side insulating layer 104). That is, the contact insulating layer 132 defines a U-shaped space in which the area on the bottom wall 123 side of the contact trench 131 is expanded and tapering is suppressed. Such a U-shaped space is formed, for example, by etching the inner wall of the contact insulating layer 132 (for example, wet etching).

[0236] The contact insulating layer 132 has a seventh thickness T7. The seventh thickness T7 may be 1500 Å or more and 4000 Å or less. The seventh thickness T7 may be 1500 Å or more and 2000 Å or less, 2000 Å or more and 2500 Å or less, 2500 Å or more and 3000 Å or less, 3000 Å or more and 3500 Å or less, or 3500 Å or more and 4000 Å or less. The seventh thickness T7 is preferably 1800 Å or more and 3500 Å or less.

[0237] The seventh thickness T7 may be 4000 Å or more and 12000 Å or less depending on the width WTC of the trench contact structure 120. The seventh thickness T7 may be 4000 Å or more and 5000 Å or less, 5000 Å or more and 6000 Å or less, 6000 Å or more and 7000 Å or less, 7000 Å or more and 8000 Å or less, 8000 Å or more and 9000 Å or less, 9000 Å or more and 10000 Å or more and 10000 Å or more and 11000 Å or less, or 12000 Å or more. In this case, the breakdown voltage of the semiconductor device 1 can be increased by thickening the contact insulating layer 132.

[0238] The seventh thickness T7 is preferably equal to the first thickness T1 of the first bottomside insulating layer 84 (T7=T1). The seventh thickness T7 is preferably equal to the fourth thickness T4 of the second bottomside insulating layer 104 (T7=T4).

[0239] The contact insulating layer 132 includes at least one of silicon oxide (SiO2), silicon nitride (SiN), aluminum oxide (Al2O3), zirconium oxide (ZrO2), and tantalum oxide (Ta2O3).

[0240] The contact insulating layer 132 may have a laminated structure including a SiN layer and a SiO2 layer laminated in this order from the semiconductor layer 2 side. The contact insulating layer 132 may have a laminated structure including a SiO2 layer and a SiN layer laminated in this order from the semiconductor layer 2 side. The contact insulating layer 132 may have a single layer structure made of a SiO2 layer or a SiN layer. In this embodiment, the contact insulating layer 132 has a single layer structure made of a SiO2 layer. The contact insulating layer 132 is preferably made of the same insulating material as the first insulating layer 82 (second insulating layer 102).

[0241] The contact insulating layer 132 is integrated with the first insulating layer 82 at the communicating portion between the first gate trench 81 and the contact trench 131. The contact insulating layer 132 is integrated with the second insulating layer 102 at the communicating portion between the second gate trench 101 and the contact trench 131.

[0242] In this embodiment, the contact insulating layer 132 has an extension insulating layer 132A that is extended to one end of the first gate trench 81 and one end of the second gate trench 101. The extension insulating layer 132A crosses the communicating portion and covers the inner wall of one end of the first gate trench 81. The extension insulating layer 132A crosses the communicating portion and covers the inner wall of one end of the second gate trench 101.

[0243] The extension insulating layer 132A is integral with the first bottom side insulating layer 84 and the first opening side insulating layer 85 in the first gate trench 81. The extension insulating layer 132A defines a U-shaped space together with the first bottom side insulating layer 84 on the inner wall of one end of the first gate trench 81.

[0244] The extension insulating layer 132A is integral with the second bottom side insulating layer 104 and the second opening side insulating layer 105 in the second gate trench 101. The extension insulating layer 132A defines a U-shaped space together with the second bottom side insulating layer 104 on the inner wall of one end of the second gate trench 101.

[0245] The contact electrode 133 is embedded in the contact trench 131 with the contact insulating layer 132 sandwiched therebetween. Unlike the first electrode 83 and the second electrode 103, the contact electrode 133 is embedded as a single unit in the contact trench 131. The contact electrode 133 has an upper end exposed from the contact trench 131 and a lower end in contact with the contact insulating layer 132.

[0246] The lower end of contact electrode 133 is formed in a convex curve toward bottom wall 123 of contact trench 131 in a similar manner to that of first bottom side electrode 86 (second bottom side electrode 106). More specifically, the lower end of contact electrode 133 is formed following the bottom wall of the U-shaped space partitioned by contact insulating layer 132, and is formed in a smooth convex curve toward bottom wall 123.

[0247] According to such a structure, local electric field concentration on the contact electrode 133 can be suppressed, and therefore a decrease in the breakdown voltage can be suppressed. In particular, by embedding the contact electrode 133 in the expanded U-shaped space of the contact insulating layer 132, it is possible to appropriately suppress the contact electrode 133 from becoming tapered from the upper end toward the lower end. This makes it possible to appropriately suppress local electric field concentration on the lower end of the contact insulating layer 132.

[0248] The contact electrode 133 is electrically connected to the first bottom side electrode 86 at a connection between the first gate trench 81 and the contact trench 131. The contact electrode 133 is electrically connected to the second bottom side electrode 106 at a connection between the second gate trench 101 and the contact trench 131. As a result, the second bottom side electrode 106 is electrically connected to the first bottom side electrode 86.

[0249] More specifically, the contact electrode 133 has an extraction electrode 133A extracted to one end of the first gate trench 81 and one end of the second gate trench 101. The extraction electrode 133A is located in the first gate trench 81 across the communication portion between the first gate trench 81 and the contact trench 131. The extraction electrode 133A is further located in the second gate trench 101 across the communication portion between the second gate trench 101 and the contact trench 131.

[0250] The extraction electrode 133A is embedded in a U-shaped space defined by the contact insulating layer 132 in the first gate trench 81. The extraction electrode 133A is integrated with the first bottom side electrode 86 in the first gate trench 81. As a result, the contact electrode 133 is electrically connected to the first bottom side electrode 86.

[0251] A first intermediate insulating layer 88 is interposed between the contact electrode 133 and the first opening side electrode 87 in the first gate trench 81. As a result, the contact electrode 133 is electrically insulated from the first opening side electrode 87 in the first gate trench 81.

[0252] The extraction electrode 133A is embedded in a U-shaped space defined by the contact insulating layer 132 in the second gate trench 101. The extraction electrode 133A is integrated with the second bottom side electrode 106 in the second gate trench 101. As a result, the contact electrode 133 is electrically connected to the second bottom side electrode 106.

[0253] In the second gate trench 101, a second intermediate insulating layer 108 is interposed between the contact electrode 133 and the second opening side electrode 107. As a result, the contact electrode 133 is electrically insulated from the second opening side electrode 107 in the second gate trench 101.

[0254] The contact electrode 133 may include at least one of conductive polysilicon, tungsten, aluminum, copper, an aluminum alloy, and a copper alloy. In this embodiment, the contact electrode 133 includes conductive polysilicon. The conductive polysilicon may include n-type impurities or p-type impurities. The conductive polysilicon preferably includes n-type impurities. The contact electrode 133 preferably includes the same conductive material as the first bottom side electrode 86 and the second bottom side electrode 106.

[0255] In this embodiment, the exposed portion of the contact electrode 133 that is exposed from the contact trench 131 is located on the bottom wall 123 side of the contact trench 131 with respect to the first main surface 3. The exposed portion of the contact electrode 133 is formed in a curved shape toward the bottom wall 123 of the contact trench 131.

[0256] The exposed portion of the contact electrode 133 is covered with a third cap insulating layer 139 formed in a film shape. The third cap insulating layer 139 is continuous with the contact insulating layer 132 in the contact trench 131. The third cap insulating layer 139 may contain silicon oxide (SiO2).

[0257] A gate control signal input from the control IC 10 to the first gate control wiring 17A (not shown) is transmitted to the first opening side electrode 87. A gate control signal input from the control IC 10 to the second gate control wiring 17B (not shown) is transmitted to the second opening side electrode 107. A gate control signal input from the control IC 10 to the third gate control wiring 17C (not shown) is transmitted to the first bottom side electrode 86 and the second bottom side electrode 106 via the contact electrode 133.

[0258] When the first MISFET 56 (first trench gate structure 60) and the second MISFET 57 (second trench gate structure 70) are both controlled to the off state, the first channel region 91 and the second channel region 111 are both controlled to the off state.

[0259] When the first MISFET 56 and the second MISFET 57 are both controlled to the on state, the first channel region 91 and the second channel region 111 are both controlled to the on state (Full-ON control).

[0260] When the first MISFET 56 is controlled to an on state while the second MISFET 57 is controlled to an off state, the first channel region 91 is controlled to an on state and the second channel region 111 is controlled to an off state (first half-on control).

[0261] When the first MISFET 56 is controlled to the OFF state while the second MISFET 57 is controlled to the ON state, the first channel region 91 is controlled to the OFF state and the second channel region 111 is controlled to the ON state (second half-ON control).

[0262] In this manner, in the power MISFET 9, a plurality of types of control including full-on control, first half-on control and second half-on control are realized by utilizing the first MISFET 56 and the second MISFET 57 formed in one output region 6.

[0263] When the first MISFET 56 is driven (i.e., when the gate is controlled to be on), an on signal Von may be applied to the first bottom side electrode 86, and an on signal Von may be applied to the first opening side electrode 87. In this case, the first bottom side electrode 86 and the first opening side electrode 87 function as gate electrodes.

[0264] This makes it possible to suppress a voltage drop between the first bottom side electrode 86 and the first opening side electrode 87, thereby suppressing electric field concentration between the first bottom side electrode 86 and the first opening side electrode 87. In addition, the on-resistance of the semiconductor layer 2 can be reduced, thereby reducing power consumption.

[0265] When the first MISFET 56 is driven (i.e., when the gate is controlled to be on), an off signal Voff (e.g., a reference voltage) may be applied to the first bottom side electrode 86, and an on signal Von may be applied to the first aperture side electrode 87. In this case, the first bottom side electrode 86 functions as a field electrode, while the first aperture side electrode 87 functions as a gate electrode. This can reduce parasitic capacitance, thereby improving switching speed.

[0266] When the second MISFET 57 is driven (i.e., when the gate is controlled to be on), an on signal Von may be applied to the second bottom side electrode 106, and an on signal Von may be applied to the second opening side electrode 107. In this case, the second bottom side electrode 106 and the second opening side electrode 107 function as gate electrodes.

[0267] This makes it possible to suppress a voltage drop between the second bottom side electrode 106 and the second opening side electrode 107, thereby suppressing electric field concentration between the second bottom side electrode 106 and the second opening side electrode 107. In addition, the on-resistance of the semiconductor layer 2 can be reduced, thereby reducing power consumption.

[0268] When the second MISFET 57 is driven (i.e., when the gate is controlled to be on), an off signal Voff (reference voltage) may be applied to the second bottom side electrode 106, and an on signal Von may be applied to the second aperture side electrode 107. In this case, the second bottom side electrode 106 functions as a field electrode, while the second aperture side electrode 107 functions as a gate electrode. This can reduce parasitic capacitance, thereby improving switching speed.

[0269] 5, the first channel region 91 is formed with a first channel area S1 in each cell region 75. The first channel area S1 is defined by the total planar area of ​​a plurality of first source regions 92 formed in each cell region 75.

[0270] The first channel region 91 is formed at a first channel ratio R1 (first ratio) in each cell region 75. The first channel ratio R1 is the ratio of the first channel area S1 in each cell region 75 when the planar area of ​​each cell region 75 is 100%.

[0271] The first channel ratio R1 is adjusted in the range of 0% to 50%. The first channel ratio R1 may be 0% to 5%, 5% to 10%, 10% to 15%, 15% to 20%, 20% to 25%, 25% to 30%, 30% to 35%, 35% to 40%, 40% to 45%, or 45% to 50%. The first channel ratio R1 is preferably 10% to 35%.

[0272] When the first channel ratio R1 is 50%, the first source region 92 is formed on almost the entire area of ​​the first sidewall 61 and the second sidewall 62 of the first trench gate structure 60. In this case, the first contact region 93 is not formed on the first sidewall 61 and the second sidewall 62 of the first trench gate structure 60. The first channel ratio R1 is preferably less than 50%.

[0273] When the first channel ratio R1 is 0%, the first source region 92 is not formed on the first sidewall 61 and the second sidewall 62 of the first trench gate structure 60. In this case, only the body region 55 and / or the first contact region 93 are formed on the first sidewall 61 and the second sidewall 62 of the first trench gate structure 60. It is preferable that the first channel ratio R1 is greater than 0%. In this embodiment, an example in which the first channel ratio R1 is 25% is shown.

[0274] The second channel region 111 is formed with a second channel area S2 in each cell region 75. The second channel area S2 is defined by the total planar area of ​​the multiple second source regions 112 formed in each cell region 75.

[0275] The second channel region 111 is formed at a second channel ratio R2 (second ratio) in each cell region 75. The second channel ratio R2 is the ratio of the second channel area S2 in each cell region 75 when the planar area of ​​each cell region 75 is 100%.

[0276] The second channel ratio R2 is adjusted in the range of 0% to 50%. The second channel ratio R2 may be 0% to 5%, 5% to 10%, 10% to 15%, 15% to 20%, 20% to 25%, 25% to 30%, 30% to 35%, 35% to 40%, 40% to 45%, or 45% to 50%. The second channel ratio R2 is preferably 10% to 35%.

[0277] When the second channel ratio R2 is 50%, the second source region 112 is formed on almost the entire area of ​​the first sidewall 71 and the second sidewall 72 of the second trench gate structure 70. In this case, the second contact region 113 is not formed on the first sidewall 71 and the second sidewall 72 of the second trench gate structure 70. The second channel ratio R2 is preferably less than 50%.

[0278] When the second channel ratio R2 is 0%, the second source region 112 is not formed on the first sidewall 71 and the second sidewall 72 of the second trench gate structure 70. In this case, only the body region 55 and / or the second contact region 113 are formed on the first sidewall 71 and the second sidewall 72 of the second trench gate structure 70. The second channel ratio R2 is preferably greater than 0%. In this embodiment, an example in which the second channel ratio R2 is 25% is shown.

[0279] In this manner, the first channel region 91 and the second channel region 111 are formed in each cell region 75 with a total channel ratio RT (RT=R1+R2) of 0% to 100% (preferably greater than 0% and less than 100%).

[0280] In this embodiment, the total channel ratio RT in each cell region 75 is 50%. In this embodiment, all the total channel ratios RT are set to the same value. Therefore, the average channel ratio RAV in the output region 6 (unit area) is 50%. The average channel ratio RAV is the sum of all the total channel ratios RT divided by the total number of the total channel ratios RT.

[0281] The total channel ratio RT may be adjusted for each cell region 75. That is, multiple total channel ratios RT each having a different value may be applied to each cell region 75. The total channel ratio RT is related to the temperature rise of the semiconductor layer 2. For example, when the total channel ratio RT is increased, the temperature of the semiconductor layer 2 is more likely to rise. On the other hand, when the total channel ratio RT is decreased, the temperature of the semiconductor layer 2 is less likely to rise.

[0282] Using this, the total channel ratio RT may be adjusted in accordance with the temperature distribution in the semiconductor layer 2. For example, the total channel ratio RT of a region in the semiconductor layer 2 where the temperature is likely to increase may be made relatively small, and the total channel ratio RT of a region in the semiconductor layer 2 where the temperature is unlikely to increase may be made relatively large.

[0283] An example of a region in the semiconductor layer 2 where the temperature is likely to increase is the central portion of the output region 6. An example of a region in the semiconductor layer 2 where the temperature is unlikely to increase is the peripheral portion of the output region 6. Of course, the average channel ratio RAV may be adjusted while adjusting the total channel ratio RT in accordance with the temperature distribution of the semiconductor layer 2.

[0284] A plurality of cell regions 75 having a total channel ratio RT of 20% or more and 40% or less (e.g., 25%) may be concentrated in a region where the temperature is likely to increase (e.g., the center). A plurality of cell regions 75 having a total channel ratio RT of 60% or more and 80% or less (e.g., 75%) may be concentrated in a region where the temperature is unlikely to increase (e.g., the periphery). A plurality of cell regions 75 having a total channel ratio RT of more than 40% and less than 60% (e.g., 50%) may be concentrated in a region between the region where the temperature is likely to increase and the region where the temperature is unlikely to increase.

[0285] Furthermore, the total channel ratios RT of 20% to 40%, the total channel ratios RT of 40% to 60%, and the total channel ratios RT of 60% to 80% may be applied to multiple cell regions 75 in a regular arrangement.

[0286] As an example, three types of total channel ratios RT, which are repeated in the order of 25% (low), 50% (middle), and 75% (high), may be applied to the multiple cell regions 75. In this case, the average channel ratio RAV may be adjusted to 50%. With such a structure, it is possible to suppress the formation of bias in the temperature distribution of the semiconductor layer 2 with a relatively simple design.

[0287] Fig. 6 is a graph showing the relationship between the active clamp withstand voltage Eac and the sheet resistivity Ron·A, which is investigated by actual measurements. The graph in Fig. 6 shows the characteristics when the first MISFET 56 and the second MISFET 57 are simultaneously controlled to the on state and the off state.

[0288] In Figure 6, the vertical axis represents the active clamp capacity Eac [mJ / mm 2 ], and the horizontal axis shows the sheet resistivity Ron·A [mΩ·mm 2 3, the active clamp withstand voltage Eac is the withstand voltage against the counter electromotive force. The sheet resistivity Ron·A represents the on-resistance in the semiconductor layer 2 during normal operation.

[0289] 6 shows a first plot point P1, a second plot point P2, a third plot point P3, and a fourth plot point P4. The first plot point P1, the second plot point P2, the third plot point P3, and the fourth plot point P4 show characteristics when the average channel ratio RAV (i.e., the total channel ratio RT in each cell area 75) is adjusted to 66%, 50%, 33%, and 25%, respectively.

[0290] When the average channel ratio RAV was increased, the sheet resistivity Ron·A decreased during normal operation, and the active clamp capacity Eac decreased during active clamp operation. Conversely, when the average channel ratio RAV was decreased, the sheet resistivity Ron·A increased during normal operation, and the active clamp capacity Eac improved during active clamp operation.

[0291] In consideration of the area resistivity Ron·A, it is preferable that the average channel ratio RAV is 33% or more (more specifically, 33% or more and less than 100%). In consideration of the active clamping capacity Eac, it is preferable that the average channel ratio RAV is less than 33% (more specifically, more than 0% and less than 33%).

[0292] The area resistivity Ron·A decreased due to an increase in the average channel ratio RAV because the number of current paths increased, and the active clamping capacity Eac decreased due to an increase in the average channel ratio RAV because a rapid temperature rise was caused by the back electromotive force.

[0293] In particular, when the average channel ratio RAV (total channel ratio RT) is relatively large, there is a high possibility that a local and rapid temperature rise occurs in the region between the adjacent first trench gate structure 60 and second trench gate structure 70. It is considered that the active clamp withstand voltage Eac decreases due to this type of temperature rise.

[0294] On the other hand, the reason why the area resistivity Ron·A increased due to the decrease in the average channel ratio RAV is because the current path became smaller. The reason why the active clamping capability Eac improved due to the decrease in the average channel ratio RAV is thought to be because the average channel ratio RAV (total channel ratio RT) became relatively small, suppressing local and rapid temperature increases.

[0295] The results of the graph in Figure 6 show that there is a trade-off relationship in the adjustment method based on the average channel ratio RAV (total channel ratio RT), and it is therefore difficult to achieve both an excellent sheet resistivity Ron·A and an excellent active clamp capability Eac independently of the trade-off relationship.

[0296] 6, it can be seen that by operating the power MISFET 9 so as to approach the first plot point P1 (RAV=66%) during normal operation and so as to approach the fourth plot point P4 (RAV=25%) during active clamp operation, it is possible to achieve both an excellent sheet resistivity Ron·A and an excellent active clamp withstand capability Eac. Therefore, the following control is performed in the semiconductor device 1.

[0297] Fig. 7 is a cross-sectional perspective view for explaining a normal operation of the semiconductor device 1 shown in Fig. 1. Fig. 8 is a cross-sectional perspective view for explaining an active clamp operation of the semiconductor device 1 shown in Fig. 1. For convenience of explanation, the structure on the first main surface 3 is omitted and the gate control wiring 17 is simplified in Figs. 7 and 8.

[0298] Referring to FIG. 7, during normal operation of the power MISFET 9, a first on signal Von1 is input to the first gate control wiring 17A, a second on signal Von2 is input to the second gate control wiring 17B, and a third on signal Von3 is input to the third gate control wiring 17C.

[0299] The first on signal Von1, the second on signal Von2, and the third on signal Von3 are input from the control IC 10. The first on signal Von1, the second on signal Von2, and the third on signal Von3 each have a voltage equal to or higher than the gate threshold voltage Vth. The first on signal Von1, the second on signal Von2, and the third on signal Von3 may each have the same voltage.

[0300] In this case, the first opening side electrode 87, the second opening side electrode 107, the first bottom side electrode 86, and the second bottom side electrode 106 are each in an ON state. That is, the first opening side electrode 87, the second opening side electrode 107, the first bottom side electrode 86, and the second bottom side electrode 106 each function as a gate electrode.

[0301] As a result, both the first channel region 91 and the second channel region 111 are controlled to be in the on state. In Fig. 7, the first channel region 91 and the second channel region 111 in the on state are indicated by dotted hatching.

[0302] As a result, both the first MISFET 56 and the second MISFET 57 are driven (Full-ON control). The channel utilization rate RU during normal operation is 100%. The characteristic channel ratio RC during normal operation is 50%. The channel utilization rate RU is the ratio of the first channel region 91 and the second channel region 111 that are controlled to be in the on state among the first channel region 91 and the second channel region 111.

[0303] The characteristic channel ratio RC is the average channel ratio RAV multiplied by the channel utilization ratio RU (RC = RAV x RU). The characteristics of the power MISFET 9 (area resistivity Ron·A and active clamp capability Eac) are determined based on the characteristic channel ratio RC. As a result, the area resistivity Ron·A approaches the area resistivity Ron·A indicated by the second plot point P2 in the graph of FIG. 6.

[0304] On the other hand, referring to FIG. 8, during active clamp operation of the power MISFET 9, an off signal Voff is input to the first gate control wiring 17A, a first clamp-on signal VCon1 is input to the second gate control wiring 17B, and a second clamp-on signal VCon2 is input to the third gate control wiring 17C.

[0305] The off signal Voff, the first clamp-on signal VCon1, and the second clamp-on signal VCon2 are each input from the control IC 10. The off signal Voff has a voltage (e.g., a reference voltage) less than the gate threshold voltage Vth. The first clamp-on signal VCon1 and the second clamp-on signal VCon2 each have a voltage equal to or greater than the gate threshold voltage Vth. The first clamp-on signal VCon1 and the second clamp-on signal VCon2 may each have the same voltage. The first clamp-on signal VCon1 and the second clamp-on signal VCon2 may each have a voltage equal to or less than the voltage during normal operation.

[0306] In this case, first opening side electrode 87 is in an OFF state, and first bottom side electrode 86, second bottom side electrode 106, and second opening side electrode 107 are in an ON state. As a result, first channel region 91 is controlled to an OFF state, and second channel region 111 is controlled to an ON state. In Fig. 8, first channel region 91 in an OFF state is shown by solid hatching, and second channel region 111 in an ON state is shown by dotted hatching.

[0307] As a result, the first MISFET 56 is controlled to an OFF state, while the second MISFET 57 is controlled to an ON state (second half-ON control), whereby the channel utilization rate RU during active clamp operation exceeds zero and becomes less than the channel utilization rate RU during normal operation.

[0308] The channel utilization rate RU during active clamp operation is 50%. Also, the characteristic channel ratio RC during active clamp operation is 25%. As a result, the active clamp withstand voltage Eac approaches the active clamp withstand voltage Eac indicated by the fourth plot point P4 in the graph of FIG.

[0309] In this case, the control IC 10 controls the first MISFET 56 and the second MISFET 57 so that different characteristic channel ratios RC (channel areas) are applied between normal operation and active clamp operation. More specifically, the control IC 10 controls the first MISFET 56 and the second MISFET 57 so that the channel utilization rate RU during active clamp operation exceeds zero and is less than the channel utilization rate RU during normal operation.

[0310] More specifically, the control IC 10 controls the first MISFET 56 and the second MISFET 57 to the ON state during normal operation, and controls the first MISFET 56 to the OFF state and the second MISFET 57 to the ON state during active clamp operation.

[0311] Therefore, during normal operation, the characteristic channel ratio RC increases relatively. That is, during normal operation, a current can be passed by using the first MISFET 56 and the second MISFET 57. This relatively increases the current path, making it possible to reduce the area resistivity Ron·A (on-resistance).

[0312] On the other hand, during active clamp operation, the characteristic channel ratio RC is relatively decreased. That is, since a current can be passed using the second MISFET 57 while the first MISFET 56 is stopped, the second MISFET 57 can consume (absorb) the back electromotive force. This makes it possible to suppress a sudden temperature rise caused by the back electromotive force, and therefore improve the active clamp withstand voltage Eac.

[0313] As a result, it is possible to provide a semiconductor device 1 that can achieve both an excellent sheet resistivity Ron·A and an excellent active clamping current capability Eac, independent of the trade-off relationship shown in FIG.

[0314] In the above control example, the second half-on control is applied during the active clamp operation. However, the first half-on control may be applied during the active clamp operation.

[0315] <Overcurrent protection circuit> 9 is a diagram showing a first configuration example of an overcurrent protection circuit incorporated in a semiconductor device. Similar to the semiconductor device 1 described above, the semiconductor device 200 in this diagram functions as a high-side switch IC in which an output electrode OUT (the above-mentioned source electrode 12) formed on a first main surface side (front side) of a semiconductor substrate is connected to a load (not shown), and a power supply electrode VBB (the above-mentioned drain electrode 11) formed on a second main surface side (back side) of the semiconductor substrate is connected to a power supply terminal (not shown).

[0316] The semiconductor device 200 includes a power MISFET 210 , a gate control circuit 220 , and an overcurrent protection circuit 230 .

[0317] The power MISFET 210, like the previously described power MISFET 9, is a split-gate power transistor configured so that a first channel region and a second channel region are individually controlled in response to a first gate control signal G11 input via a first gate control wiring 211 and a second gate control signal G12 input via a second gate control wiring 212.

[0318] For example, the on-resistance Ron of the power MISFET 210 is an on-resistance Ron1 when both channel regions are on, and is an on-resistance Ron2 (e.g., Ron2=20×Ron1) higher than the on-resistance Ron1 when only one of the channel regions is on. Specifically, for example, Ron1=0.05Ω and Ron2=1Ω may be used.

[0319] The gate control circuit 220 is a circuit part corresponding to the aforementioned gate control circuit 25, and is configured to generate a first gate control signal G11 and a second gate control signal G12, and supply each signal to the power MISFET 210 via a first gate control wiring 211 and a second gate control wiring 212.

[0320] The overcurrent protection circuit 230 is a circuit part corresponding to the aforementioned overcurrent protection circuit 34, and is configured to turn off the second channel region when the output current IOUT flowing through the power MISFET 210 exceeds a predetermined threshold current ITH.

[0321] Referring to this figure, the overcurrent protection circuit 230 includes a comparator 231, N-channel type MISFETs 232 and 233, and a current source 234.

[0322] The comparator 231 is configured to compare a predetermined threshold voltage VTH1 input to the non-inverting input terminal (+) with an output voltage VOUT (= terminal voltage of the output electrode OUT, VBB - IOUT × Ron) input to the inverting input terminal (-) and generate an overcurrent protection signal OCP1. The overcurrent protection signal OCP1 becomes a low level ( = logical level when overcurrent is not detected), for example, when VOUT > VTH1, and becomes a high level ( = logical level when overcurrent is detected) when VOUT < VTH1.

[0323] The MISFET 232 corresponds to a first transistor configured to conduct / block between the second gate control wiring 212 and the output electrode OUT according to the overcurrent protection signal OCP1. The MISFET 232 turns off when the overcurrent protection signal OCP1 is at a low level, and turns on when the overcurrent protection signal OCP1 is at a high level. That is, when the overcurrent protection signal OCP1 is at a high level ( = logical level when overcurrent is detected), the second gate control wiring 212 and the output electrode OUT (and thus the source of the power MISFET 210) are short-circuited, so that the second channel region is turned off.

[0324] The MISFET 233 corresponds to a second transistor that is connected between the power supply electrode VBB and an application terminal of a threshold voltage VTH1 and is configured to generate a threshold voltage VTH1 (=VBB-IREF1×Ron3) according to a constant current IREF1 flowing through the MISFET 233 and an on-resistance value Ron3 of the MISFET 233. It is preferable to set the on-resistance value Ron3 of the MISFET 233 to a value sufficiently higher than the on-resistance value Ron of the power MISFET 210 (i.e., the on-resistance value Ron1 or Ron2). Specifically, for example, Ron3=5 kΩ may be used.

[0325] Further, the gate of the MISFET 233 is connected to one of the gate control wirings 211 and 212 to which the MISFET 232 is not connected (i.e., the gate control wiring 211). Therefore, the MISFET 233 is turned on / off in synchronization with the power MISFET 233. With this configuration, the constant current IREF1 does not flow during the off period of the MISFET 210, so that power is not wasted.

[0326] Furthermore, it is desirable to use a split-gate transistor formed to have a pair with the power MISFET 210 as the MISFET 233. With such a configuration, the threshold voltage VTH1 (and hence the threshold current ITH) can be set with high accuracy, thereby improving the accuracy of overcurrent detection.

[0327] The current source 234 generates a constant current IREF1 that flows through the MISFET 233. Specifically, for example, IREF1 may be set to 100 μA.

[0328] 10 is a diagram showing an example of the overcurrent protection operation during the on-period of the power MISFET 210. The horizontal axis indicates the output current IOUT flowing through the power MISFET 210, and the horizontal axis indicates the output voltage VOUT appearing at the output electrode OUT.

[0329] When IOUT < ITH (= IREF1 × Ron3 / Ron1), since the voltage drop across the power MISFET 210 is relatively small, VOUT (= VBB - IOUT × Ron1) > VTH1 (= VBB - IREF1 × Ron3). At this time, the overcurrent protection signal OCP1 becomes low level and MISFET 232 turns off, so the connection between the second gate control wiring 212 and the output electrode OUT is open. Therefore, both the first channel region and the second channel region of the power MISFET 210 are turned on, and the on-resistance Ron of the power MISFET 210 is set to the on-resistance Ron1 (for example, 0.05 Ω).

[0330] On the other hand, when the output current IOUT increases and IOUT > ITH, VOUT < VTH1. At this time, the overcurrent protection signal OCP1 becomes high level and MISFET 232 turns on, so the connection between the second gate control wiring 212 and the output electrode OUT is shorted. Therefore, the second channel region of the power MISFET 210 is turned off and only the first channel region is in the on state, so the on-resistance Ron of the power MISFET 210 is increased from the on-resistance Ron1 to the on-resistance Ron2 (for example, 1 Ω). As a result, the output current IOUT flowing through the power MISFET 210 is suppressed.

[0331] For example, when Ron1 = 0.05 Ω, Ron2 = 1 Ω, Ron3 = 5 kΩ, IREF1 = 100 μA, and VBB = 14 V, when the output current IOUT exceeds 10 A, the on-resistance Ron of the power MISFET 210 is increased from Ron1 to Ron2, and the output current IOUT is suppressed to a predetermined upper limit value (= VBB / Ron2 = 14 A).

[0332] In particular, the overcurrent protection circuit 230 of this configuration example has a simple circuit configuration that does not require large elements (such as a phase compensation capacitor and a current detection resistor) unlike the conventional configuration that performs gate feedback control of the power transistor. Therefore, it can be said that it is optimal for low-cost products that emphasize area efficiency, for example. Since the gate feedback control of the power MISFET 210 is not performed, it depends on the variation of the on-resistance value Ron and the temperature characteristics, but since the purpose is to prevent the destruction of the semiconductor device 200, this is not a particular problem.

[0333] 11 is a diagram showing a second configuration example of an overcurrent protection circuit incorporated in a semiconductor device. A semiconductor device 300 in this diagram differs from the semiconductor devices 1 and 200 described above in that the ground electrode GND is connected to a ground terminal (not shown) and the output electrode OUT functions as a low-side switch IC connected to a load (not shown).

[0334] The semiconductor device 300 includes a power MISFET 310 , a gate control circuit 320 , and an overcurrent protection circuit 330 .

[0335] The power MISFET 310, like the previously described power MISFETs 9 and 210, is a split-gate power transistor configured so that the first and second channel regions are individually controlled in response to a first gate control signal G21 input via a first gate control wiring 311 and a second gate control signal G22 input via a second gate control wiring 312.

[0336] For example, the on-resistance Ron of the power MISFET 310 is an on-resistance Ron1 when both channel regions are on, and is an on-resistance Ron2 (e.g., Ron2=20×Ron1) higher than the on-resistance Ron1 when only one of the channel regions is on. Specifically, for example, Ron1=0.05Ω and Ron2=1Ω may be used.

[0337] The gate control circuit 320 is a circuit section corresponding to the foregoing gate control circuits 25 and 220, generates a first gate control signal G21 and a second gate control signal G22, and is configured to supply each signal to the power MISFET 310 via a first gate control wiring 311 and a second gate control wiring 312.

[0338] The overcurrent protection circuit 330 is a circuit section corresponding to the foregoing overcurrent protection circuits 34 and 230, and is configured to turn off the second channel region when the output current IOUT flowing through the power MISFET 310 exceeds a predetermined threshold current ITH.

[0339] Referring to this figure, the overcurrent protection circuit 330 includes a comparator 331, N-channel type MISFETs 332 and 333, and a current source 334.

[0340] The comparator 331 is configured to compare an output voltage VOUT (= terminal voltage of the output electrode OUT, IOUT × Ron) input to the non-inverting input terminal (+) with a predetermined threshold voltage VTH2 input to the inverting input terminal (-) and generate an overcurrent protection signal OCP2. The overcurrent protection signal OCP2 becomes a low level ( = logical level when overcurrent is not detected), for example, when VOUT < VTH2, and becomes a high level ( = logical level when overcurrent is detected) when VOUT > VTH2.

[0341] The MISFET 332 corresponds to a first transistor configured to conduct / cut off between the second gate control wiring 312 and the output electrode OUT according to the overcurrent protection signal OCP2. The MISFET 332 turns off when the overcurrent protection signal OCP2 is at a low level and turns on when the overcurrent protection signal OCP2 is at a high level. That is, when the overcurrent protection signal OCP2 is at a high level ( = logical level when overcurrent is detected), the second gate control wiring 312 and the output electrode OUT (and thus the source of the power MISFET 310) are short-circuited, so that the second channel region is turned off.

[0342] The MISFET 333 corresponds to a second transistor that is connected between the ground electrode GND and an application terminal of a threshold voltage VTH2 and is configured to generate a threshold voltage VTH2 (=IREF2×Ron3) according to a constant current IREF2 flowing through the MISFET 333 and an on-resistance value Ron3 of the MISFET 333. The on-resistance value Ron3 of the MISFET 333 is desirably set to a value sufficiently higher than the on-resistance value Ron of the power MISFET 310 (i.e., the on-resistance value Ron1 or Ron2). Specifically, for example, Ron3=5 kΩ may be used.

[0343] Further, the gate of the MISFET 333 is connected to one of the gate control wirings 311 and 312 to which the MISFET 332 is not connected (i.e., the gate control wiring 311). Therefore, the MISFET 333 is turned on / off in synchronization with the power MISFET 333. With this configuration, the constant current IREF2 does not flow during the off period of the MISFET 310, so that power is not wasted.

[0344] Furthermore, it is desirable to use a split-gate transistor formed to have a pair with the power MISFET 310 as the MISFET 333. With such a configuration, the threshold voltage VTH2 (and hence the threshold current ITH) can be set with high accuracy, thereby improving the accuracy of overcurrent detection.

[0345] The current source 334 generates a constant current IREF2 that flows through the MISFET 333. Specifically, for example, IREF2 may be set to 100 μA.

[0346] 12 is a diagram showing an example of the overcurrent protection operation during the on-period of the power MISFET 310. The horizontal axis indicates the output current IOUT flowing through the power MISFET 310, and the horizontal axis indicates the output voltage VOUT appearing at the output electrode OUT.

[0347] When IOUT < ITH (= IREF2 × Ron3 / Ron1), since the voltage drop across the power MISFET 310 is relatively small, VOUT (= IOUT × Ron1) < VTH2 (= IREF2 × Ron3). At this time, the overcurrent protection signal OCP2 becomes a low level and MISFET 332 turns off, so the connection between the second gate control wiring 312 and the output electrode OUT becomes open. Therefore, both the first channel region and the second channel region of the power MISFET 310 are turned on, and the on-resistance value Ron of the power MISFET 310 is set to the on-resistance value Ron1 (for example, 0.05 Ω).

[0348] On the other hand, when the output current IOUT increases and IOUT > ITH, VOUT > VTH2. At this time, the overcurrent protection signal OCP2 becomes a high level and MISFET 332 turns on, so the connection between the second gate control wiring 312 and the output electrode OUT is shorted. Therefore, the second channel region of the power MISFET 310 is turned off and only the first channel region is in the on state, so the on-resistance value Ron of the power MISFET 310 is increased from the on-resistance value Ron1 to the on-resistance value Ron2 (for example, 1 Ω). As a result, the output current IOUT flowing through the power MISFET 310 is suppressed.

[0349] For example, when Ron1 = 0.05 Ω, Ron2 = 1 Ω, Ron3 = 5 kΩ, IREF1 = 100 μA, and VBB = 14 V, when the output current IOUT exceeds 10 A, the on-resistance value Ron of the power MISFET 210 is increased from Ron1 to Ron2, and the output current IOUT is suppressed to a predetermined upper limit value (= VBB / Ron2 = 14 A).

[0350] In particular, the overcurrent protection circuit 330 of this configuration example has a simple circuit configuration that does not require large elements (such as a phase compensation capacitor and a current detection resistor) unlike the conventional configuration that performs gate feedback control of the power transistor. Therefore, it can be said that it is optimal for low-cost products that emphasize area efficiency, for example. Since the gate feedback control of the power MISFET 310 is not performed, it depends on the variation of the on-resistance value Ron and the temperature characteristics, but since the purpose is to prevent the destruction of the semiconductor device 300, this is not a particular problem.

[0351] <Comparison between split gate type and parallel connection type> Incidentally, instead of the split-gate type power MISFETs 210 and 310 described so far, a similar overcurrent protection operation can be performed by connecting a plurality of power transistors having different on-resistance values ​​in parallel and individually controlling each of them.

[0352] However, in a configuration using parallel-connected power transistors, when an overcurrent is detected, the output current flows intensively only through the small-area power transistor with a high on-resistance value, which can easily cause a problem of heat generation in the power transistor.

[0353] On the other hand, in a configuration using split-gate power MISFETs 210 and 310, even if the on-resistance values ​​Ron of the power MISFETs 210 and 310 are raised when an overcurrent is detected, the output current IOUT flows in a dispersed manner over the entire surface of the formation region of each of the power MISFETs 210 and 310, so there is an advantage that element destruction due to heat generation is unlikely to occur.

[0354] <Application to vehicles> 13 is an external view showing one configuration example of a vehicle. The vehicle X of this configuration example is equipped with a battery (not shown in this figure) and various electronic devices X11 to X18 that operate by receiving a power supply voltage from the battery. Note that the mounting positions of the electronic devices X11 to X18 in this figure may differ from the actual positions for convenience of illustration.

[0355] The electronic device X11 is an engine control unit that performs engine-related controls (such as injection control, electronic throttle control, idling control, oxygen sensor heater control, and auto-cruise control).

[0356] The electronic device X12 is a lamp control unit that controls the turning on and off of HID [high intensity discharged lamp] and DRL [daytime running lamp].

[0357] The electronic device X13 is a transmission control unit that performs control related to the transmission.

[0358] The electronic device X14 is a body control unit that performs control related to the motion of the vehicle X (ABS [anti-lock brake system] control, EPS [electric power steering] control, electronic suspension control, etc.).

[0359] The electronic device X15 is a security control unit that controls the operation of door locks, burglar alarms, and the like.

[0360] The electronic device X16 is an electronic device that is installed in the vehicle X at the factory as a standard equipment or a manufacturer's option, such as a wiper, an electric door mirror, a power window, a damper (shock absorber), an electric sunroof, and an electric seat.

[0361] The electronic device X17 is an electronic device that is optionally installed in the vehicle X as a user option, such as an in-vehicle A / V (audio / visual) device, a car navigation system, and an ETC (electronic toll collection system).

[0362] The electronic device X18 is an electronic device equipped with a high-voltage resistant motor, such as an in-vehicle blower, oil pump, water pump, or battery cooling fan.

[0363] The semiconductor device 1, 200, and 300 described above can be incorporated into any of the electronic devices X11 to X18.

[0364] <Other Modifications> In the above embodiment, an automotive high-side switch IC has been described as an example, but the application of the invention disclosed in this specification is not limited to this, and the invention can be widely applied to semiconductor devices having power transistors in general, including automotive IPDs [intelligent power devices] (such as automotive low-side switch ICs and automotive power supply ICs) used for other purposes.

[0365] That is, in addition to the above-mentioned embodiment, the invention disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. That is, the above-mentioned embodiment should be considered to be illustrative in all respects and not restrictive, and the technical scope of the present invention is indicated by the claims, not by the description of the above-mentioned embodiment, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims. [Explanation of symbols]

[0366] 1 Semiconductor device 9. Power MISFET 25 Gate control circuit 26 Active clamp circuit 56 1st MISFET 57 2nd MISFET 91 First channel region 111 Second channel region 200, 300 Semiconductor device 210, 310 Power MISFET 211, 311 First gate control wiring 212, 312 Second gate control wiring 220, 320 Gate control circuit 230, 330 Overcurrent protection circuit 231, 331 Comparator 232, 332 MISFETs 233, 333 MISFETs 234, 334 current source

Claims

1. a split-gate power transistor configured so that a plurality of channel regions are individually controlled in response to a plurality of gate control signals; a gate control circuit configured to generate the plurality of gate control signals; an overcurrent protection circuit configured to turn off at least one of the plurality of channel regions when an output current flowing through the power transistor exceeds a threshold; having The power transistor is A first electrode formed on a first main surface side of a semiconductor substrate; A second electrode formed on a second main surface side of the semiconductor substrate; Including, The overcurrent protection circuit includes: a comparator configured to compare a terminal voltage of the first electrode with a predetermined threshold voltage to generate an overcurrent protection signal; a first transistor configured to establish / cut off conduction between at least one of a plurality of gate control wirings and the first electrode in response to the overcurrent protection signal; a second transistor connected between the second electrode or the first electrode and an application terminal of the threshold voltage, and configured to generate the threshold voltage by a constant current flowing through the second transistor; Including, an on-resistance value of the power transistor becomes a first on-resistance value when both the first channel region and the second channel region are on, and becomes a second on-resistance value higher than the first on-resistance value when only one of the first channel region and the second channel region is on; an on-resistance value of the second transistor is a third resistance value higher than the second on-resistance value.

2. 2. The semiconductor device according to claim 1, wherein said second transistor is turned on / off in synchronization with said power transistor.

3. 3. The semiconductor device according to claim 1, wherein the second transistor is a split-gate transistor formed to have a pair with the power transistor.

4. 4. The semiconductor device according to claim 1, wherein the power transistor functions as a high-side switch having the first electrode connected to a load and the second electrode connected to a power supply terminal.

5. 4. The semiconductor device according to claim 1, wherein the power transistor functions as a low-side switch having the first electrode connected to a ground terminal and the second electrode connected to a load.

6. A semiconductor device according to any one of claims 1 to 5, A load connected to the semiconductor device; An electronic device having the

7. A vehicle comprising the electronic device according to claim 6.

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