Adaptive Clock Duty Cycle Controller

Abstract

A method for measuring a clock signal includes launching an edge of a timing signal on a first edge of the clock signal, outputting an edge of a capture signal on a second edge of the clock signal, receiving the edge of the timing signal and the edge of the capture signal at a time-to-digital converter (TDC), and measuring a time delay using the TDC between the time the edge of the timing signal is received at the TDC and the time the edge of the capture signal is received at the TDC.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to and the benefit of nonprovisional patent application Ser. No. 17 / 485,355, filed in the United States Patent Office on Sept. 25, 2021, the entire contents of which are incorporated herein by reference as if fully set forth below and for all applicable purposes. [Background technology]

[0002] Field Aspects of the present disclosure relate generally to clock distribution and, more particularly, to duty cycle distortion in clock distribution networks.

[0003] background The system may include a clock generator (e.g., a phase-locked loop) configured to generate a clock signal for timing the operation of one or more circuits (e.g., flip-flops) in the system. The system may also include a clock distribution network (also called a clock tree) for distributing the clock signal from the clock generator to the one or more circuits. A challenge facing clock distribution is that asymmetric aging in one or more signal paths of the clock distribution network can cause duty cycle distortion in the clock signal, which can lead to timing problems (e.g., timing violations) in one or more circuits. Summary of the Invention

[0004] SUMMARY OF THE DISCLOSURE The following presents a simplified summary of one or more implementations in order to provide a basic understanding of such implementations. This Summary is not an extensive overview of all contemplated implementations, and is not intended to identify key or critical elements of all implementations or to delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the Detailed Description presented later.

[0005] A first aspect relates to a timing measurement circuit. The timing measurement circuit includes a launch circuit having an enable input, a clock input, and an output, the launch circuit configured to receive an enable signal at the enable input, a clock signal at the launch circuit's clock input, and in response to receiving the enable signal, launch an edge of a timing signal at an output of the launch circuit on a first edge of the clock signal. The timing measurement circuit also includes a capture circuit having a clock input and an output, the capture circuit configured to receive the clock signal at the capture circuit's clock input, and output an edge of the capture signal at an output of the capture circuit on a second edge of the clock signal. The timing measurement circuit also includes a time-to-digital converter (TDC) having a signal input, a capture input, and an output, the signal input of the TDC is coupled to the output of the launch circuit, and the capture input of the TDC is coupled to the output of the capture circuit.

[0006] A second aspect relates to a method of measuring a clock signal, the method including: launching an edge of a timing signal on a first edge of the clock signal, outputting an edge of a capture signal on a second edge of the clock signal, receiving the edge of the timing signal and the edge of the capture signal at a time-to-digital converter (TDC), and measuring a time delay using the TDC between the time the edge of the timing signal is received at the TDC and the time the edge of the capture signal is received at the TDC. [Brief description of the drawings]

[0007] [Figure 1] 1 illustrates an example of a system including a clock distribution network in accordance with some aspects of the present disclosure. [Figure 2A] 1 illustrates an example of a signal path including a delay buffer in accordance with some aspects of the present disclosure. [Figure 2B] 1 illustrates an example in which the input of a signal path is held low in idle mode, according to some aspects of the present disclosure. [Figure 2C] 1 illustrates an example of duty cycle distortion in a signal path due to asymmetric aging, in accordance with some aspects of the present disclosure. [Diagram 3] 1 illustrates an example of an adaptive clock duty cycle controller in accordance with some aspects of the present disclosure. [Figure 4] 1 illustrates an example of a timing measurement circuit including a ring oscillator in accordance with some aspects of the present disclosure. [Diagram 5] 1 illustrates an example of a timing measurement circuit including a time-to-digital converter in accordance with some aspects of the present disclosure. [Figure 6] FIG. 2 is a timing diagram illustrating an example of a clock signal in accordance with some aspects of the present disclosure. [Figure 7] FIG. 2 illustrates an example implementation of a launch circuit and a capture circuit in accordance with some aspects of the disclosure. [Figure 8A] FIG. 1 is a timing diagram illustrating an example of a high phase measurement in accordance with some aspects of the present disclosure. [Figure 8B] FIG. 1 is a timing diagram illustrating an example of a low phase measurement in accordance with some aspects of the present disclosure. [Figure 8C] FIG. 2 is a timing diagram illustrating an example of a clock period measurement according to some aspects of the present disclosure. [Figure 8D] FIG. 11 is a timing diagram illustrating another example of a clock period measurement in accordance with some aspects of the present disclosure. [Figure 9] 1 illustrates an example implementation of a time-to-digital converter in accordance with certain aspects of the present disclosure. [Figure 10] 1 illustrates another example implementation of a time-to-digital converter in accordance with certain aspects of the present disclosure. [Figure 11] 1 illustrates an example implementation of a delay circuit in accordance with some aspects of the present disclosure. [Figure 12] 1 illustrates an example implementation of a duty cycle regulator according to some aspects of the present disclosure. [Figure 13] 1 illustrates an example implementation of a high phase extender in accordance with certain aspects of the present disclosure. [Figure 14A] FIG. 1 is a timing diagram illustrating an example of high phase extension in accordance with some aspects of the present disclosure. [Figure 14B] FIG. 1 is a timing diagram illustrating an example of high phase extension resulting in glitches, in accordance with some aspects of the present disclosure. [Figure 15A] 1 illustrates another exemplary implementation of a high phase extender in accordance with some aspects of the present disclosure. [Figure 15B] FIG. 2 is a timing diagram illustrating an example of multiple delayed versions of a clock signal generated by a high phase extender in accordance with some aspects of the present disclosure. [Figure 16] 1 illustrates yet another exemplary implementation of a high phase extender in accordance with some aspects of the present disclosure. [Figure 17] 1 illustrates another example implementation of a duty cycle regulator, according to some aspects. [Figure 18] 1 illustrates an example implementation of a low phase extender in accordance with certain aspects of the present disclosure. [Figure 19] 1 is a flowchart illustrating a method for measuring a clock signal in accordance with some aspects of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] The detailed description of the present invention described below in conjunction with the accompanying drawings is intended as an illustration of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description of the present invention includes specific details intended to provide a thorough understanding of the various concepts. However, it will be apparent to one skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0009] FIG. 1 illustrates an example of a system 110 including a clock generator 115, a clock distribution network 120, and a number of circuits 150-1-150-3, according to some embodiments. The clock generator 115 is configured to generate a clock signal for timing the operation of the circuits 150-1-150-3. The clock generator 115 may be implemented using a phase-locked loop (PLL) or another type of clock generator 115. The clock distribution network 120 (also referred to as a clock tree) is configured to distribute the clock signal from the clock generator 115 to the circuits 150-1-150-3. As used herein, a "clock signal" may be a periodic signal that oscillates between high and low. The clock signal may be used, for example, to time the operation of a synchronous digital circuit or other type of circuit. A clock signal has a duty cycle, which may be expressed as the percentage or fraction of a clock period (i.e., clock cycle) that the clock signal is high (i.e., 1). The clock signal may be gated to conserve power (e.g., when circuits 150-1 through 150-3 are not active). Clock gating is a known technique for reducing dynamic power consumption when one or more circuits are not active.

[0010] 1, each of the circuits 150-1 through 150-3 may include a respective flip-flop 155-1 through 155-3 that is clocked by a clock signal. It should be understood that the circuits 150-1 through 150-3 are not limited to flip-flops and may include other devices in addition to or in place of the flip-flops 155-1 through 155-3.

[0011] In this example, clock generator 115 is coupled to input 122 of clock distribution network 120, and each of circuits 150-1 through 150-3 is coupled to a respective output 124-1 through 124-3 of clock distribution network 120. Clock distribution network 120 receives a clock signal from clock generator 115 via input 122 (also called a root node) and distributes the clock signal to circuits 150-1 through 150-3 via outputs 124-1 through 124-3 (also called leaf nodes).

[0012] In the example shown in FIG. 1, clock distribution network 120 includes signal path 125 and delay buffers 132, 134, and 136. Signal path 125 includes delay buffers 130-1 through 130-n coupled in series. It should be understood that clock distribution network 120 may include additional delay buffers and / or other components not shown in FIG. 1. For example, clock distribution network 120 may include adaptive clock distribution (not shown) to mitigate the effects of supply voltage droop. Clock distribution network 120 may also include one or more clock gating circuits (also referred to as clock gating cells) that gate the clock signal when circuits 150-1 through 150-3 are idle to reduce dynamic power consumption when circuits 150-1 through 150-3 are idle. As used herein, a "signal path" is a path along which a signal (e.g., a clock signal) propagates and may include one or more delay buffers and / or one or more other components (e.g., splitters, amplifiers, switches, voltage level shifters, clock gating circuits, etc.).

[0013] A challenge with clock distribution network 120 is that asymmetric aging in clock distribution network 120 can cause duty cycle distortion in the clock signals at the leaf nodes (i.e., outputs 124-1 through 124-3) that are coupled to circuits 150-1 through 150-3. If not corrected, the duty cycle distortion can lead to timing problems (e.g., timing violations) in circuits 150-1 through 150-3.

[0014] An example of duty cycle distortion due to asymmetric aging in signal path 125 of clock distribution network 120 will now be described with reference to Figures 2A-2C. Figure 2A illustrates an example of signal path 125 including delay buffers 130-1 through 130-8 coupled in series. It should be understood that signal path 125 is not limited to the number of delay buffers 130-1 through 130-8 shown in Figure 2A, and signal path 125 may include a different number of delay buffers.

[0015] In the example shown in FIG. 2A, each of the delay buffers 130-1 through 130-8 is implemented with a respective complementary inverter including a first respective transistor 225-1 through 225-8 (e.g., an n-type field effect transistor (NFET)) and a second respective transistor 230-1 through 230-8 (e.g., a p-type field effect transistor (PFET)). However, it should be understood that other types of circuits or logic gates may be used to implement each of the delay buffers 130-1 through 130-8. It should also be understood that a delay buffer may include two inverters coupled in series to implement a non-inverting delay buffer. In this case, the delay buffers 130-1 and 130-2 of FIG. 2A may be considered a first non-inverting delay buffer, the delay buffers 130-3 and 130-4 of FIG. 2A may be considered a second non-inverting delay buffer, and so on.

[0016] In some aspects, a clock gating circuit (not shown) may be coupled between clock generator 115 and the input of signal path 125. In this example, the clock gating circuit may be configured to pass the clock signal in an active mode and gate (i.e., block) the clock signal in an idle mode to conserve power in the idle mode.

[0017] 2B shows an example in which the clock signal is gated in idle mode, such that the input of signal path 125 is held low (i.e., logic 0) in idle mode. FIG 2B also shows the logic state at the output of each of delay buffers 130-1 through 130-8 in idle mode. As shown in FIG 2B, delay buffers 130-1 through 130-8 are implemented with inverters in this example, so that the logic states at the outputs of delay buffers 130-1 through 130-8 alternate between 1 and 0.

[0018] In this example, transistors 230-1, 225-2, 230-3, 225-4, 230-5, 225-6, 230-7, and 225-8 are turned on in the idle mode, while transistors 225-1, 230-2, 225-3, 230-4, 225-5, 230-6, 225-7, and 230-8 are turned off in the idle mode. The transistors that are turned on are shown in bold in FIG. 2B. Transistors 230-1, 225-2, 230-3, 225-4, 230-5, 225-6, 230-7, and 225-8, which are turned on in idle mode, are loaded in idle mode and a DC voltage approximately equal to the supply voltage Vdd is applied across the gate-source of each of transistors 230-1, 225-2, 230-3, 225-4, 230-5, 225-6, 230-7, and 225-8. The voltage stress in idle mode causes transistors 230-1, 225-2, 230-3, 225-4, 230-5, 225-6, 230-7, and 225-8 to age more than transistors 225-1, 230-2, 225-3, 230-4, 225-5, 230-6, 225-7, and 230-8, which are turned off in idle mode, resulting in asymmetric aging of the transistors in signal path 125.

[0019] In this example, asymmetric aging increases the threshold voltages of transistors 230-1, 225-2, 230-3, 225-4, 230-5, 225-6, 230-7, and 225-8, which causes transistors 230-1, 225-2, 230-3, 225-4, 230-5, 225-6, 230-7, and 225-8 to slow down relative to transistors 225-1, 230-2, 225-3, 230-4, 225-5, 230-6, 225-7, and 230-8. The slowing of transistors 230-1, 225-2, 230-3, 225-4, 230-5, 225-6, 230-7, and 225-8 increases the falling edge delay at the output of signal path 125 relative to the rising edge delay at the output of signal path 125. This is because the falling edge (i.e., falling transition) of the clock signal propagates to the output of signal path 125 by sequentially turning on transistors 230-1, 225-2, 230-3, 225-4, 230-5, 225-6, 230-7, and 225-8, which are loaded in idle mode, while the rising edge (i.e., rising transition) of the clock signal propagates to the output of signal path 125 by sequentially turning on transistors 225-1, 230-2, 225-3, 230-4, 225-5, 230-6, 225-7, and 230-8, which are not loaded in idle mode. The increase in falling edge delay relative to the rising edge delay causes duty cycle distortion in signal path 125.

[0020] An example of duty cycle distortion is illustrated in the timing diagram shown in Figure 2C. In the example shown in Figure 2C, clock signal 250 is the input to signal path 125 when signal path 125 is not in idle mode (i.e., signal path 125 is active). In this example, clock signal 250 at the input of signal path 125 has a 50% duty cycle. Figure 2C also shows clock signal 260 at the output of signal path 125 after the clock signal has propagated through signal path 125. Signal path 125 delays the rising edge of clock signal 260 by a delay T r, and the falling edge of the clock signal 260 is delayed by a delay T f As shown in Figure 2C, the falling edge delay T f is the delay T of the rising edge due to the asymmetric aging of the transistors in the signal path 125 described above. r A longer delay of the falling edge increases the duty cycle of clock signal 260 at the output of signal path 125 (i.e., results in a duty cycle greater than 50%). Thus, in this example, the duty cycle distortion due to asymmetric aging increases the duty cycle of the clock signal.

[0021] Asymmetric aging also occurs when the input of signal path 125 is held high in idle mode. In this case, asymmetric aging increases the rising edge delay of signal path 125 relative to the falling edge delay of signal path 125, resulting in duty cycle distortion that reduces the duty cycle of the clock signal. Thus, asymmetric aging of the transistors in signal path 125 causes duty cycle distortion over time. Duty cycle distortion may increase or decrease the duty cycle of the clock signal depending on, for example, whether the input of signal path 125 is held low or high in idle mode, the number of delay buffers in signal path 125, and / or other factors.

[0022] 3 illustrates an example of an adaptive duty cycle controller 305 configured to compensate for duty cycle distortion, according to some embodiments. The adaptive duty cycle controller 305 includes a timing measurement circuit 310, a duty cycle adjuster 320, and a duty cycle control circuit 330.

[0023] The timing measurement circuit 310 has an input 312 and an output 314. In the example of FIG. 3, the input 312 of the timing measurement circuit 310 is coupled to a leaf node (i.e., output 124-3) of the clock distribution network 120. However, it should be understood that the input 312 of the timing measurement circuit 310 may be coupled to another node in other examples, as further described below. The timing measurement circuit 310 is configured to receive a clock signal at the input 312, measure one or more timing parameters of the clock signal, and output a measurement signal based on the one or more measured timing parameters. The one or more timing parameters provide information related to a duty cycle of the clock signal received at the input 312 of the timing measurement circuit 310. For example, the one or more timing parameters may include a measurement of a high phase of the clock signal, where the high phase is the duration that the clock signal is high (i.e., 1) during one clock period (i.e., one period of the clock signal). In this example, for a given clock period, a larger high phase indicates a larger duty cycle, and a smaller high phase indicates a smaller duty cycle. The one or more timing parameters may also include a measurement of a low phase of the clock signal, which is the duration that the clock signal is low (i.e., 0) during one clock period. In this example, for a given clock period, a larger low phase indicates a smaller duty cycle and a smaller low phase indicates a larger duty cycle.

[0024] 3, the timing measurement circuit 310 is coupled to a leaf node (i.e., output 124-3). Thus, in this example, the timing measurement circuit 310 receives the clock signal after the clock signal has experienced duty cycle distortion in the clock distribution network 120. As a result, the measurement signal from the timing measurement circuit 310 provides information about the duty cycle distortion of the clock signal at the leaf node due to aging effects in the clock distribution network 120. The timing measurement circuit 310 may also be referred to as a duty cycle monitor, a duty cycle measurement circuit, a duty cycle detector, or another term.

[0025] Duty cycle adjuster 320 has a signal input 322, a control input 326, and an output 324. Signal input 322 is coupled to clock generator 115, and output 324 is coupled to clock distribution network 120. In the example of FIG. 3, output 324 of duty cycle adjuster 320 is coupled to the root node (i.e., input 122) of clock distribution network 120. Duty cycle adjuster 320 is configured to receive a clock signal at signal input 322, adjust a duty cycle of the clock signal (i.e., perform a duty cycle adjustment of the clock signal), and output a duty cycle-adjusted clock signal at output 324. Because duty cycle adjuster 320 adjusts the duty cycle of the clock signal received at input 322 to generate a duty cycle-adjusted clock signal at output 324, the clock signal at output 324 may also be referred to as a duty cycle-adjusted clock signal. Duty cycle adjuster 320 is configured to adjust the duty cycle of the clock signal based on a control signal received at a control input 326, as described further below. An output 324 of duty cycle adjuster 320 is coupled to a root node (i.e., input 122) of clock distribution network 120 in this example, such that duty cycle adjuster 320 provides duty cycle adjustment of the clock signal at the root node. However, it should be appreciated that the disclosure is not limited to this example.

[0026] Duty cycle control circuit 330 has an input 332 and an output 334. Input 332 is coupled to output 314 of timing measurement circuit 310, and output 334 is coupled to a control input 326 of duty cycle adjuster 320. Duty cycle control circuit 330 is configured to receive a measurement signal from timing measurement circuit 310 and set a duty cycle adjustment of the clock signal by duty cycle adjuster 320 via control input 326 based on the measurement signal.

[0027] In one example, the duty cycle control circuit 330 compensates for the duty cycle distortion in the clock distribution network 120 by determining a duty cycle adjustment based on a measurement signal from the timing measurement circuit 310 and setting a duty cycle adjustment of the duty cycle adjuster 320 based on the determined duty cycle adjustment. For example, the measurement signal from the timing measurement circuit 310 may indicate a high phase of the clock signal measured at the leaf node. In this example, the duty cycle control circuit 330 may compare the measured high phase to a target high phase corresponding to a target duty cycle to determine a duty cycle adjustment for the duty cycle adjuster 320. In an example where the target duty cycle is a 50% duty cycle, the target high phase is approximately equal to half the clock period. If the measured high phase is greater than the target high phase (which occurs when the duty cycle of the clock signal at the leaf node is greater than the target duty cycle), the duty cycle control circuit 330 may determine a duty cycle adjustment for the duty cycle adjuster 320 that reduces the duty cycle of the clock signal at the leaf node. In this case, the decrease in the duty cycle reduces the difference between the duty cycle of the clock signal at the leaf node and the target duty cycle. On the other hand, if the measured high phase is less than the target high phase (which occurs when the duty cycle of the clock signal at the leaf node is less than the target duty cycle), the duty cycle control circuit 330 may determine a duty cycle adjustment for the duty cycle adjuster 320 that increases the duty cycle of the clock signal at the leaf node. Other examples for determining the duty cycle adjustment for the duty cycle adjuster 320 are further described below.

[0028] Thus, in this example, adaptive duty cycle controller 305 monitors the duty cycle of the clock signal at the leaf nodes using timing measurement circuit 310 and adjusts the duty cycle of the clock signal at the root node based on the measurement signal from timing measurement circuit 310 to compensate for duty cycle distortion in clock distribution network 120. In some aspects, adaptive duty cycle controller 305 may perform the duty cycle adjustment each time system 110 is booted.

[0029] In the example of FIG. 3, the adaptive duty cycle controller 305 uses the timing measurement circuit 310 to monitor the duty cycle of the clock signal at one leaf node (i.e., output 124-3). In this example, there may be a high correlation between the duty cycle distortion at the leaf node coupled to the timing measurement circuit 310 and the duty cycle distortion at each of the other leaf nodes (i.e., outputs 124-1 and 124-2). However, it should be understood that the adaptive duty cycle controller 305 is not limited to this example. In another example, the adaptive duty cycle controller 305 may include multiple timing measurement circuits, each coupled to a respective leaf node for monitoring the duty cycle of the clock signal at the respective leaf node.

[0030] It should be understood that the timing measurement circuit 310 is not limited to being coupled to a leaf node. For example, in some applications, the timing measurement circuit 310 may be coupled to a node located before or within the clock distribution network 120. This may be done, for example, to provide duty cycle compensation for another effect that causes duty cycle distortion of the clock signal in addition to the aging effect in the clock distribution network 120 described above. In one example, the clock generator 115 may introduce a duty cycle distortion into the clock signal. In this example, to achieve compensation for the duty cycle distortion in the clock generator 115, the timing measurement circuit 310 may be coupled to an output 324 of the duty cycle adjuster 320 before the clock distribution network 120. In another example, the timing measurement circuit 310 may be coupled to a node within the clock distribution network 120 to achieve duty cycle compensation in the clock distribution network 120. It should therefore be understood that the timing measurement circuit 310 may be coupled to any one of a number of nodes in a system (e.g., system 110) to provide duty cycle compensation for various effects in the system that cause duty cycle distortion.

[0031] A challenge in implementing timing measurement circuit 310 is achieving high-resolution timing measurements. High resolution allows for more accurate compensation of duty cycle distortions (e.g., in clock distribution network 120 and / or clock generator 115). Achieving high-resolution timing measurements becomes more difficult as the frequency of clock signals increases to achieve faster processing speeds, as described further below.

[0032] 4 illustrates an example of a current implementation of a timing measurement circuit 410. The timing measurement circuit 410 includes a flip-flop 420, a ring oscillator 430, and a counter 440. The flip-flop 420 has a signal input (labeled "D") configured to receive a clock signal, a clock input (labeled "CK"), and an output (labeled "Q"). The ring oscillator 430 has an enable input 432 and an output 434. The counter 440 has a target input 446, a count input 442, an enable input 444, and an output 448.

[0033] In this example, the timing measurement circuit 410 measures the high phase of the clock signal (i.e., the duration that the clock signal is high during one clock period). To do this, the ring oscillator 430 is enabled by inputting an enable signal to an enable input 432 of the ring oscillator 430. This causes the ring oscillator 430 to generate a ring oscillator (RO) signal that oscillates at the frequency of the ring oscillator 430. The ring oscillator 430 outputs the RO signal at an output 434 of the ring oscillator 430 that is coupled to the clock input of the flip-flop 420 and to a count input 442 of the counter 440.

[0034] In this example, flip-flop 420 is clocked by the RO signal. Flip-flop 420 is configured to latch the logic state of the clock signal on the rising edge of the RO signal and output the latched logic state of the clock signal to the enable input 444 of counter 440. In this example, flip-flop 420 latches a 1 when the clock signal is high, and therefore outputs a 1 to the enable input 444 of counter 440 for a duration approximately equal to the high phase of the clock signal.

[0035] In this example, counter 440 counts a number of oscillations of the RO signal at count input 442, and flip-flop 420 outputs a 1 to enable input 444 of counter 440. Because flip-flop 420 outputs a 1 to enable input 444 of counter 440 for a duration approximately equal to the high phase of the clock signal, counter 440 counts the number of oscillations of the RO signal during the high phase of the clock signal. As a result, the count value of counter 440 provides a measure of the high phase of the clock signal (i.e., the duration that the clock signal is high during one clock period).

[0036] Counter 440 receives a target count value at a target input 446, which indicates a count value for a target high phase that corresponds to a target duty cycle (e.g., a 50% duty cycle). Counter 440 then compares the count value from the RO signal to the target count value to determine whether the duty cycle of the clock signal is above or below the target duty cycle, and outputs a signal at an output 448 based on the comparison indicating whether to increase or decrease the duty cycle of the clock signal to compensate for the duty cycle distortion.

[0037] A problem with the RO-based timing measurement circuit 410 shown in FIG. 4 is that in order to achieve high resolution, the frequency of the ring oscillator 430 needs to be much higher than the frequency of the clock signal. As the frequency of the clock signal increases, high resolution becomes more and more difficult to achieve with the RO-based timing measurement circuit 410. For example, for a clock frequency of 2 GHz with a corresponding clock period of 500 ps, ​​a ring oscillator frequency of 10 GHz with a corresponding clock period of 100 ps only achieves a resolution of 20% of one clock period, which is very low.

[0038] To address the above, aspects of the present disclosure provide a timing measurement circuit that can measure one or more timing parameters of a clock signal with high resolution using an adjustable delay circuit and / or a time-to-digital converter (TDC), as further described below.

[0039] 5 illustrates an example timing measurement circuit 510 according to some aspects. The timing measurement circuit 510 may be used to implement the timing measurement circuit 310 of FIG. 3 (i.e., the timing measurement circuit 310 may be an example of the timing measurement circuit 510).

[0040] The timing measurement circuit 510 has an input 512 and an output 514. The timing measurement circuit 510 is configured to receive a clock signal (labeled "clk") via the input 512. In one example, the input 512 may be coupled to a leaf node of a clock distribution network (e.g., clock distribution network 120). However, it should be understood that the disclosure is not limited to this example and the input 512 may be coupled to another node (e.g., a node prior to the clock distribution network 120, a node within the clock distribution network 120, etc.). The timing measurement circuit 510 is configured to output a measurement signal at an output 514, as described further below. In an example where the timing measurement circuit 510 is used to implement the timing measurement circuit 310 of FIG. 3, the input 512 corresponds to the input 312 of FIG. 3 and the output 514 corresponds to the output 314 of FIG. 3. In examples where input 512 of timing measurement circuit 510 is coupled to output 324 of duty cycle adjuster 320, the clock signal at input 512 of timing measurement circuit 510 may be referred to as a duty-cycle adjusted clock signal because duty cycle adjuster 320 adjusts the duty cycle of the clock signal received at input 322 of duty cycle adjuster 320. Input 512 of timing measurement circuit 510 may be coupled to output 324 of duty cycle adjuster 320 via signal path 125.

[0041] In this example, the timing measurement circuit 510 includes a measurement control circuit 520, a launch circuit 530, a delay circuit 550, a time-to-digital converter (TDC) 560, and a capture circuit 540. The measurement control circuit 520 controls the operation of the timing measurement circuit 510, as described further below.

[0042] The launch circuit 530 has an enable input 532, a clock input 534, a control input 536, and an output 538. The enable input 532 is coupled to a first output 523 of the measurement control circuit 520, the clock input 534 is coupled to an input 512 of the timing measurement circuit 510 for receiving a clock signal, and the control input 536 is coupled to a second output 524 of the measurement control circuit 520. The launch circuit 530 is configured to receive an enable signal from the measurement control circuit 520 via the enable input 532 to initiate a measurement. In response to the enable signal, the launch circuit 530 launches (i.e., outputs) an edge of the timing signal at the output 538 with an edge of the clock signal. The edge of the clock signal used to launch the edge of the timing signal can be a rising edge or a falling edge. In some aspects, the launch circuit 530 selects the edge of the clock signal used to launch the edge of the timing signal based on a first edge selection signal received from the measurement control circuit 520 via the control input 536. For example, the launch circuit 530 may launch an edge of the timing signal on a rising edge of the clock signal when the first edge select signal has a first logical value, and may launch an edge of the timing signal on a falling edge of the clock signal when the first edge select signal has a second logical value. The first logical value may be 1 and the second logical value may be 0, or vice versa. The edge of the timing signal may be a rising edge or a falling edge.

[0043] The delay circuit 550 has a signal input 552, a control input 554, and an output 556. The signal input 552 is coupled to the output 538 of the launch circuit 530. The control input 554 is coupled to the third output 525 of the measurement control circuit 520. The delay circuit 550 is configured to receive an edge of a timing signal from the launch circuit 530 via the signal input 552, delay the edge of the timing signal by a time delay, and output the delayed edge of the timing signal at the output 556. In some embodiments, the time delay of the delay circuit 550 is adjustable (i.e., programmable). In these embodiments, the delay circuit 550 is configured to set the time delay of the delay circuit 550 based on a delay control signal received from the measurement control circuit 520 via the control input 554.

[0044] The capture circuit 540 has a clock input 542, a control input 544, and an output 546. The clock input 542 is coupled to the input 512 of the timing measurement circuit 510 to receive a clock signal, and the control input 544 is coupled to a fourth output 526 of the measurement control circuit 520. The capture circuit 540 is configured to generate a capture signal and output the capture signal at the output 546. In some aspects, the capture circuit 540 is configured to output an edge of the capture signal at a rising edge or a falling edge of the clock signal based on a second edge selection signal received from the measurement control circuit 520 via the control input 544. For example, the capture circuit 540 may output an edge of the capture signal at a rising edge of the clock signal when the second edge selection signal has a first logical value, and output an edge of the capture signal at a falling edge of the clock signal when the second edge selection signal has a second logical value. The first logical value may be 1 and the second logical value may be 0, or vice versa. The edge of the capture signal may be a rising edge or a falling edge, hi some aspects the capture signal may be a capture clock signal, as described further below.

[0045] The TDC 560 has a signal input 562, a capture input 564, and an output 566. The signal input 562 of the TDC 560 is coupled to the output 556 of the delay circuit 550 to receive a delayed edge of the timing signal from the delay circuit 550. The capture input 564 is coupled to the output 546 of the capture circuit 540 to receive an edge of the capture signal from the capture circuit 540. The output 566 of the TDC 560 is coupled to the time measurement input 522 of the measurement control circuit 520. The TDC 560 is configured to measure the time delay (i.e., the elapsed time) between the time the TDC 560 receives an edge of the timing signal at the signal input 562 and the time the TDC 560 receives an edge of the capture signal at the capture input 564, and output a digital time measurement signal at the output 566 indicative of the measured time delay. In this example, the time delay measurement may start with an edge of the timing signal and stop with an edge of the capture signal.

[0046] In some aspects, the measurement control circuit 520 can measure various timing parameters of the clock signal by using a first edge select signal to select an edge of the clock signal that is used to launch an edge of the timing signal and a second edge select signal to select an edge of the clock signal that is used to output an edge of the capture signal. An example of this is shown in FIG. 6, which shows an example timing diagram of a clock signal. It should be understood that the clock signal may have a duty cycle different from that shown in FIG. 6.

[0047] For example, the measurement control circuit 520 may measure the high phase of the clock signal by selecting the rising edge 610 of the clock signal to launch an edge of the timing signal and the falling edge 620 of the clock signal to output an edge of the capture signal. As discussed above, the high phase is the duration that the clock signal is high (i.e., 1) during one clock period. In this example, as shown in FIG. 6, the high phase starts at the rising edge 610 of the clock signal and ends at the falling edge 620 of the clock signal. In this example, the high phase is approximately equal to the sum of the time delay of the delay circuit 550 and the time delay measured by the TDC 560. This is because the high phase is approximately equal to the time delay from when the edge of the timing signal is launched at the rising edge 610 of the clock signal to when the edge of the capture signal is output at the falling edge 620 of the clock signal, which is equal to the sum of the time delay of the delay circuit 550 and the time delay measured by the TDC 560. Assuming the time delay of delay circuit 550 is known, measurement control circuit 520 can determine the high phase using the measured time delay indicated by the digital time measurement signal from TDC 560 and the known time delay of delay circuit 550.

[0048] In another example, the measurement control circuit 520 may measure the low phase of the clock signal by selecting the falling edge 620 of the clock signal to launch an edge of the timing signal and the rising edge 630 of the clock signal to output an edge of the capture signal. The low phase is the duration that the clock signal is low during one clock period. In this example, the low phase starts at the falling edge 620 of the clock signal and ends at the rising edge 630 of the clock signal, as shown in FIG. 6. In this example, the low phase is equal to the sum of the time delay of the delay circuit 550 and the time delay measured by the TDC 560. This is because the low phase is approximately equal to the time delay from when the edge of the timing signal is launched at the falling edge 620 of the clock signal to when the edge of the capture signal is output at the rising edge 630 of the clock signal, which is equal to the sum of the time delay of the delay circuit 550 and the time delay measured by the TDC 560. Assuming the time delay of delay circuit 550 is known, measurement control circuit 520 can determine the low phase using the measured time delay indicated by the digital time measurement signal from TDC 560 and the known time delay of delay circuit 550.

[0049] In another example, the measurement control circuit 520 may measure the period of the clock signal by selecting a first rising edge 610 of the clock signal to launch an edge of the timing signal and a second rising edge 630 of the clock signal to output an edge of the capture signal. In this example, the period of the clock signal is approximately equal to the sum of the time delay of the delay circuit 550 and the time delay measured by the TDC 560. This is because the clock period is approximately equal to the time delay from when an edge of the timing signal is launched at the first rising edge 610 of the clock signal to when an edge of the capture signal is output at the second rising edge 630 of the clock signal, which is approximately equal to the sum of the time delay of the delay circuit 550 and the time delay measured by the TDC 560. Assuming the time delay of the delay circuit 550 is known, the measurement control circuit 520 can use the measured time delay indicated by the digital time measurement signal from the TDC 560 and the known time delay of the delay circuit 550 to determine the period of the clock signal.

[0050] The measurement control circuit 520 may also measure the period of the clock signal by selecting a first falling edge 620 of the clock signal that launches an edge of the timing signal and a second falling edge 640 of the clock signal that outputs an edge of the capture signal. In this example, the period of the clock signal is approximately equal to the sum of the time delay of the delay circuit 550 and the time delay measured by the TDC 560. Thus, in this example, the timing measurement circuit 510 supports two techniques for measuring the clock period (i.e., measuring the period between two successive rising edges of the clock signal or measuring the period between two successive falling edges of the clock signal). Either technique may be used to measure the clock period, or both techniques may be used to measure the clock period.

[0051] Thus, the measurement control circuit 520 can measure any one of one or more timing parameters of the clock signal, including a high phase of the clock signal, a low phase of the clock signal, and a period of the clock signal. The measurement control circuit 520 selects the timing parameter to be measured by selecting a launch clock edge (i.e., an edge of the clock signal used to launch an edge of the timing signal) and correspondingly selecting a capture clock edge (i.e., an edge of the clock signal used to output an edge of the capture signal). For example, to measure the high phase, the measurement control circuit 520 selects a rising edge of the clock signal for the launch clock edge and a falling edge of the clock signal for the capture clock edge. In some aspects, the launch clock edge may be referred to as a first edge of the clock signal, and the capture clock edge may be referred to as a second edge of the clock signal.

[0052] In some aspects, the measurement control circuit 520 is configured to generate a measurement signal based on the one or more measured timing parameters of the clock signal and output the measurement signal at a fifth output 527 that is coupled to the output 514 of the timing measurement circuit 510. In one example, the measurement signal may be indicative of one or more of a measured high phase of the clock signal, a measured low phase of the clock signal, and a measured period of the clock signal.

[0053] In another example, the measurement control circuit 520 may determine the duty cycle of the clock signal based on two or more of the measured high phase of the clock signal, the measured low phase of the clock signal, and the measured period of the clock signal. For example, the measurement control circuit 520 may determine the duty cycle of the clock signal based on a ratio of the measured high phase of the clock signal to the measured period of the clock signal. In this example, a ratio of 0.5 corresponds to a 50% duty cycle. The measurement control circuit 520 may then output a measurement signal indicative of the determined duty cycle.

[0054] In another example, the measurement control circuit 520 can determine a duty cycle adjustment of the clock signal based on one or more of a measured high phase of the clock signal, a measured low phase of the clock signal, and a measured period of the clock signal. For example, the clock signal may have a target duty cycle of 50%. In this example, the measurement control circuit 520 can compare the measured high phase of the clock signal to the measured low phase of the clock signal to determine the duty cycle adjustment. For example, if the measured high phase is greater than the measured low phase (which occurs when the duty cycle of the clock signal is greater than the target duty cycle of 50%), the measurement control circuit 520 can determine a duty cycle adjustment that decreases the duty cycle of the clock signal to bring the duty cycle of the clock signal closer to the target duty cycle of 50%. On the other hand, if the measured high phase is less than the measured low phase (which occurs when the duty cycle of the clock signal is less than the target duty cycle), the measurement control circuit 520 can determine a duty cycle adjustment that increases the duty cycle of the clock signal to bring the duty cycle of the clock signal closer to the target duty cycle of 50%. The measurement control circuit 520 may then output a measurement signal indicative of the determined duty cycle adjustment. It should be understood that the disclosure is not limited to this example and that the measurement control circuit 520 may determine the duty cycle adjustment in different manners based on one or more of the measured timing parameters of the clock signal.

[0055] It should be understood that in some implementations, the measurement signal may include two or more signals. For example, the measurement signal may include a first signal indicating the sign of the duty cycle adjustment (i.e., whether the duty cycle of the clock signal should be increased or decreased) and a second signal indicating the amount by which the duty cycle should be adjusted. In this example, the first signal and the second signal may be output in series on one line or on two parallel lines.

[0056] Duty cycle control circuit 330 may receive a measurement signal from timing measurement circuit 510, determine a duty cycle adjustment for duty cycle adjuster 320 based on the measurement signal, and set the duty cycle adjustment of duty cycle adjuster 320 based on the determined duty cycle adjustment (i.e., generate a control signal that controls the duty cycle adjustment of duty cycle adjuster 320 based on the determined duty cycle adjustment and input the control signal to a control input 326 of duty cycle adjuster 320). As described further below, duty cycle adjuster 320 may increase the duty cycle of the clock signal by increasing a high phase of the clock signal or decreasing a low phase of the clock signal, and duty cycle adjuster 320 may decrease the duty cycle of the clock signal by decreasing a high phase of the clock signal or increasing a low phase of the clock signal.

[0057] In an example where the measurement signal indicates a measured high phase of the clock signal, the duty cycle control circuit 330 may compare the measured high phase to a target high phase corresponding to a target duty cycle (e.g., a 50% duty cycle). If the measured high phase is greater than the target high phase (which occurs when the duty cycle of the clock signal is greater than the target duty cycle), the duty cycle control circuit 330 may determine a duty cycle adjustment for the duty cycle adjuster 320 that decreases the duty cycle of the clock signal at the node coupled to the input 512 of the timing measurement circuit 510. On the other hand, if the measured high phase is less than the target high phase (which occurs when the duty cycle of the clock signal is less than the target duty cycle), the duty cycle control circuit 330 may determine a duty cycle adjustment for the duty cycle adjuster 320 that increases the duty cycle of the clock signal at the node coupled to the input 512 of the timing measurement circuit 510.

[0058] In an example where the measurement signal indicates a measured low phase of the clock signal, the duty cycle control circuit 330 may compare the measured low phase to a target low phase corresponding to a target duty cycle (e.g., a 50% duty cycle). If the measured low phase is greater than the target low phase (which occurs when the duty cycle of the clock signal is less than the target duty cycle), the duty cycle control circuit 330 may determine a duty cycle adjustment for the duty cycle adjuster 320 that increases the duty cycle of the clock signal at the node coupled to the input 512 of the timing measurement circuit 510. On the other hand, if the measured low phase is less than the target low phase (which occurs when the duty cycle of the clock signal is greater than the target duty cycle), the duty cycle control circuit 330 may determine a duty cycle adjustment for the duty cycle adjuster 320 that decreases the duty cycle of the clock signal at the node coupled to the input 512 of the timing measurement circuit 510.

[0059] In examples where the measurement signal indicates a duty cycle adjustment based on one or more of the measured timing parameters of the clock signal, duty cycle control circuit 330 sets the duty cycle adjustment of duty cycle adjuster 320 based on the indicated duty cycle adjustment.

[0060] In an example where the measurement signal indicates both a measured high phase of the clock signal and a measured low phase of the clock signal, and the target duty cycle is 50%, the duty cycle control circuit 330 may compare the measured high phase to the measured low phase of the clock signal to determine a duty cycle adjustment. For example, if the measured high phase is greater than the measured low phase (which occurs when the duty cycle of the clock signal is greater than the target duty cycle of 50%), the duty cycle control circuit 330 may determine a duty cycle adjustment that decreases the duty cycle of the clock signal at the node coupled to the input 512 of the timing measurement circuit 510. On the other hand, if the measured high phase is less than the measured low phase (which occurs when the duty cycle of the clock signal is less than the target duty cycle), the duty cycle control circuit 330 may determine a duty cycle adjustment that increases the duty cycle of the clock signal at the node coupled to the input 512 of the timing measurement circuit 510.

[0061] In examples where the measurement signal indicates the duty cycle of a clock signal, the duty cycle control circuit 330 may compare the indicated duty cycle to a target duty cycle to determine a duty cycle adjustment. For example, if the indicated duty cycle is greater than the target duty cycle, the duty cycle control circuit 330 may determine a duty cycle adjustment that decreases the duty cycle of the clock signal at the node coupled to the input 512 of the timing measurement circuit 510. If the indicated duty cycle is less than the target duty cycle, the duty cycle control circuit 330 may determine a duty cycle adjustment that increases the duty cycle of the clock signal at the node coupled to the input 512 of the timing measurement circuit 510.

[0062] FIG. 7 illustrates an example implementation of a launch circuit 530 and a capture circuit 540 according to some aspects.

[0063] In this example, the launch circuit 530 includes an inverter 710, a multiplexer 720, a first flip-flop 730, a second flip-flop 740, and a launch flip-flop 750. The multiplexer 720 has a first input 722, a second input 724, a selection input 726, and an output 728. The first input 722 is coupled to a clock input 534 of the launch circuit 530, and the selection input 726 is coupled to a control input 536 of the launch circuit 530. The inverter 710 is coupled between the clock input 534 of the launch circuit 530 and the second input 724 of the multiplexer 720. Thus, the first input 722 of the multiplexer 720 receives a clock signal, and the second input 724 of the multiplexer 720 receives an inverted clock signal. The multiplexer 720 is configured to select either the clock signal at the first input 722 or the inverted clock signal at the second input 724 based on a control signal at a selection input 726, and output the selected one of the clock signal and the inverted clock signal at an output 728. The selected one of the clock signal and the inverted clock signal at the output 728 is referred to as the launch clock signal (labeled "clk_1") in the following description. As described further below, the multiplexer 720 enables the measurement control circuit 520 to select either a rising clock edge or a falling clock edge that launches an edge of the timing signal.

[0064] The first flip-flop 730 has a signal input 732 coupled to the enable input 532 of the launch circuit 530, a clock input 734 coupled to the clock input 534 of the launch circuit 530, and an output 736. The second flip-flop 740 has a signal input 742 coupled to the output 736 of the first flip-flop 730, a clock input 744 coupled to the output 728 of the multiplexer 720, and an output 746. The launch flip-flop 750 has a signal input 752 coupled to the output 746 of the second flip-flop 740, a clock input 754 coupled to the output 728 of the multiplexer 720, and an output 756 coupled to the output 538 of the launch circuit 530.

[0065] In this example, the launch circuit 530 uses an enable signal from the measurement control circuit 520 to provide a timing signal and launches an edge of the timing signal on either a rising edge or a falling edge of the clock signal depending on whether the multiplexer 720 selects the clock signal or the inverted clock signal. In one example, the enable signal from the measurement control circuit 520 is set high to initiate the duty cycle measurement. In this example, the rising edge of the enable signal propagates through the first flip-flop 730 and the second flip-flop 740 to the signal input 752 of the launch flip-flop 750, with the first flip-flop 730 being clocked by the clock signal and the second flip-flop 740 being clocked by the launch clock signal (i.e., the selected one of the clock signal and the inverted clock signal).

[0066] Launch flip-flop 750 is configured to launch the rising edge of the enable signal on the rising edge of a launch clock signal (labeled "clk_1"). In this example, the rising edge of the enable signal provides the rising edge of the timing signal (labeled "din"). If a clock signal is selected by multiplexer 720, launch flip-flop 750 launches an edge of the timing signal (i.e., the rising edge of the enable signal in this example) on the rising edge of the clock signal. If an inverted clock signal is selected by multiplexer 720, launch flip-flop 750 launches an edge of the timing signal (i.e., the rising edge of the enable signal in this example) on the falling edge of the clock signal.

[0067] Thus, in this example, launch circuit 530 launches an edge of the timing signal in response to receiving an enable signal from measurement control circuit 520, and launches an edge of the timing signal on either the rising edge or the falling edge of the clock signal, depending on whether multiplexer 720 selects the clock signal or the inverted clock signal.

[0068] 7, the enable signal propagates through a first flip-flop 730 and a second flip-flop 740 to a signal input 752 of a launch flip-flop 750. In this example, the first flip-flop 730 and the second flip-flop 740 can be used to adjust the timing of the rising edge of the enable signal to help ensure that the rising edge of the enable signal is timed (e.g., setup time and / or hold time) at the launch flip-flop 750. It should be understood that the disclosure is not limited to this example and that in some implementations (e.g., implementations in which the timing of the enable signal does not matter), one or both of the first flip-flop 730 and the second flip-flop 740 may be omitted.

[0069] In the example of FIG. 7, the capture circuit 540 includes a first inverter 755, a multiplexer 760, a flip-flop 770, a second inverter 780, and a clock gating circuit 790 (also referred to as a clock gating cell). The multiplexer 760 has a first input 762, a second input 764, a selection input 766, and an output 768. The first input 762 is coupled to the clock input 542 of the capture circuit 540, and the selection input 766 is coupled to the control input 544 of the capture circuit 540. The first inverter 755 is coupled between the clock input 542 of the capture circuit 540 and the second input 764 of the multiplexer 760. Thus, the first input 762 of the multiplexer 760 receives a clock signal, and the second input 764 of the multiplexer 760 receives an inverted clock signal. The multiplexer 760 is configured to select either the clock signal at the first input 762 or the inverted clock signal at the second input 764 based on a second edge selection signal at a selection input 766, and output the selected one of the clock signal and the inverted clock signal at an output 768. The selected one of the clock signal and the inverted clock signal at the output 768 is referred to as the capture clock signal in the following description. As described further below, the multiplexer 760 enables the measurement control circuit 520 to select either the rising edge or the falling clock edge to output an edge of the capture clock signal.

[0070] Flip-flop 770 has a signal input 772 coupled to output 538 of launch circuit 530, a clock input 774 coupled to output 768 of multiplexer 760, and an output 776. An input of a second inverter 780 is coupled to the output 776 of flip-flop 770.

[0071] The clock gating circuit 790 has an enable input 792 coupled to the output of the second inverter 780, a signal input 794 coupled to the output 768 of the multiplexer 760, and an output 796 coupled to the capture input 564 of the TDC 560. The clock gating circuit 790 is configured to pass or gate the capture clock signal (i.e., a selected one of the clock signal and the inverted clock signal) from the multiplexer 760 based on the logic value at the enable input 792. For example, the clock gating circuit 790 may pass the capture clock signal when the enable input 792 is high and gate (i.e., block) the capture signal when the enable input 792 is low, or vice versa in alternative implementations. The capture clock signal after the clock gating circuit 790 is labeled "clk_c" in FIG. 7.

[0072] In this example, capture circuit 540 uses the capture clock signal output at output 546 to provide the capture signal described above. The edge of the clock signal used to output the edge of the capture clock signal depends on whether multiplexer 760 selects the clock signal or the inverted clock signal. For example, the edge of the capture clock signal may be output on a rising edge of the clock signal if multiplexer 760 selects the clock signal, and the edge of the capture clock signal may be output on a falling edge of the clock signal if multiplexer 760 selects the inverted clock signal.

[0073] A flip-flop 770 and a second inverter 780 are used to gate the capture clock signal after the edge of the capture clock signal such that after the edge of the capture clock signal, the TDC 560 holds the time delay measurement at the output 566 of the TDC 560.

[0074] The exemplary launch circuit 530 and capture circuit 540 shown in FIG. 7 may be used to measure any one of a high phase of a clock signal, a low phase of a clock signal, and a period of a clock signal. In this regard, FIG. 8A is a timing diagram illustrating an example of a high phase measurement of a clock signal, according to some embodiments. FIG. 8A illustrates an example of a clock signal (labeled "clk"), a launch clock signal (labeled "clk_l"), a timing signal (labeled "din"), a signal at an enable input 792 of a clock gating circuit 790 (labeled "clk_c_en"), a capture clock signal at an output of the clock gating circuit 790 (labeled "clk_c"), and an output of the TDC 560 (labeled "tdc_q").

[0075] In the example of FIG. 8A, multiplexer 720 in launch circuit 530 selects the clock signal, and multiplexer 760 in capture circuit 540 selects the inverted clock signal. Thus, in this example, the launch clock signal is provided by the clock signal, and the capture clock signal is provided by the inverted clock signal. In this example, launch flip-flop 750 launches a rising edge 814 of a timing signal (labeled "din") on a rising edge 812 of the launch clock signal (labeled "clk_1") corresponding to a rising edge 810 of the clock signal. In this example, launch flip-flop 750 is a rising edge triggered flip-flop (also called a positive edge triggered flip-flop). The rising edge 814 of the timing signal propagates through delay circuit 550 to TDC 560.

[0076] The capture circuit 540 outputs a rising edge 816 of the capture clock signal on a falling edge 818 of the clock signal. Note that the capture circuit 540 generates the capture clock signal (labeled "clk_c") in this example. The rising edge 816 of the capture clock signal causes the TDC 560 to capture a time delay measurement of the timing signal at the TDC 560 and output a corresponding digital time measurement signal (labeled "tdc_q") to the measurement control circuit 520. In this example, the TDC 560 is rising edge triggered (i.e., it captures the time delay measurement on the rising edge of the capture clock signal).

[0077] After the rising edge 816 of the capture clock signal, the signal at the enable input 792 of the clock gating circuit 790 (labeled "clk_c_en") goes low. This causes the clock gating circuit 790 to gate the capture clock signal and causes the TDC 560 to hold the time delay measurement. The TDC 560 can hold the time delay measurement until the measurement control circuit 520 resets the launch circuit 530 and the capture circuit 540 (e.g., by outputting a 0 to the enable input 532 of the launch circuit 530).

[0078] FIG. 8B is a timing diagram illustrating an example of a low-phase measurement of a clock signal, according to some embodiments. In the example of FIG. 8B, multiplexer 720 in launch circuit 530 selects the inverted clock signal, and multiplexer 760 in capture circuit 540 selects the clock signal. Thus, in this example, the launch clock signal is provided by the inverted clock signal, and the capture clock signal is provided by the clock signal. In this example, launch flip-flop 750 launches a rising edge 824 of a timing signal (labeled "din") on a rising edge 822 of the launch clock signal (labeled "clk_1") that corresponds to a falling edge 820 of the clock signal. The rising edge 824 of the timing signal propagates through delay circuit 550 to TDC 560.

[0079] The capture circuit 540 outputs a rising edge 826 of the capture clock signal at a rising edge 828 of the clock signal. Note that the capture circuit 540 generates the capture clock signal (labeled “clk_c”) in this example. The rising edge 826 of the capture clock signal causes the TDC 560 to capture a time delay measurement of the timing signal at the TDC 560 and output a corresponding digital time measurement signal (labeled “tdc_q”) to the measurement control circuit 520.

[0080] After the rising edge 826 of the capture clock signal, the signal at the enable input 792 of the clock gating circuit 790 (labeled "clk_c_en") goes low. This causes the clock gating circuit 790 to gate the capture clock signal and causes the TDC 560 to hold the time delay measurement. The TDC 560 can hold the time delay measurement until the measurement control circuit 520 resets the launch circuit 530 and the capture circuit 540 (e.g., by outputting a 0 to the enable input 532 of the launch circuit 530).

[0081] 8C is a timing diagram illustrating an example of a clock period measurement, according to some embodiments. In the example of FIG. 8C, multiplexer 720 in launch circuit 530 selects the clock signal, and multiplexer 760 in capture circuit 540 selects the clock signal. Thus, in this example, the launch clock signal is provided by the clock signal, and the capture clock signal is provided by the clock signal. In this example, launch flip-flop 750 launches a rising edge 834 of a timing signal (labeled "din") at a rising edge 832 of the launch clock signal (labeled "clk_1") corresponding to a rising edge 830 of the clock signal. The rising edge 834 of the timing signal propagates through delay circuit 550 to TDC 560.

[0082] The capture circuit 540 outputs a rising edge 836 of the capture clock signal at a rising edge 838 of the clock signal. Note that the capture circuit 540 generates the capture clock signal (labeled “clk_c”) in this example. The rising edge 836 of the capture clock signal causes the TDC 560 to capture a time delay measurement of the timing signal at the TDC 560 and output a corresponding digital time measurement signal (labeled “tdc_q”) to the measurement control circuit 520.

[0083] After the rising edge 836 of the capture clock signal, the signal at the enable input 792 of the clock gating circuit 790 (labeled "clk_c_en") goes low. This causes the clock gating circuit 790 to gate the capture clock signal and causes the TDC 560 to hold the time delay measurement. The TDC 560 can hold the time delay measurement until the measurement control circuit 520 resets the launch circuit 530 and the capture circuit 540 (e.g., by outputting a 0 to the enable input 532 of the launch circuit 530).

[0084] 8D is a timing diagram illustrating another example of clock period measurement, according to some embodiments. In the example of FIG. 8D, multiplexer 720 in launch circuit 530 selects the inverted clock signal, and multiplexer 760 in capture circuit 540 selects the inverted clock signal. Thus, in this example, the launch clock signal is provided by the inverted clock signal, and the capture clock signal is provided by the inverted clock signal. In this example, launch flip-flop 750 launches a rising edge 844 of a timing signal (labeled "din") on a rising edge 842 of the launch clock signal (labeled "clk_1") corresponding to a falling edge 840 of the clock signal. The rising edge 844 of the timing signal propagates through delay circuit 550 to TDC 560.

[0085] The capture circuit 540 outputs a rising edge 846 of the capture clock signal at a falling edge 848 of the clock signal. Note that the capture circuit 540 generates the capture clock signal (labeled “clk_c”) in this example. The rising edge 846 of the capture clock signal causes the TDC 560 to capture a time delay measurement of the timing signal at the TDC 560 and output a corresponding digital time measurement signal (labeled “tdc_q”) to the measurement control circuit 520.

[0086] After the rising edge 846 of the capture clock signal, the signal at the enable input 792 of the clock gating circuit 790 (labeled "clk_c_en") goes low. This causes the clock gating circuit 790 to gate the capture clock signal and causes the TDC 560 to hold the time delay measurement. The TDC 560 can hold the time delay measurement until the measurement control circuit 520 resets the launch circuit 530 and the capture circuit 540 (e.g., by outputting a 0 to the enable input 532 of the launch circuit 530).

[0087] 9 illustrates an example implementation of a TDC 560, according to some aspects. In this example, the TDC 560 is configured to receive a timing signal at a signal input 562 and measure a time delay between the time an edge of the timing signal is received at the signal input 562 of the TDC 560 and the time an edge of a capture clock signal is received at the capture input 564 of the TDC 560. In this example, a digital time measurement signal (labeled "tdc_q") includes a number of bits (labeled "tdc_q[0]" through "tdc_q[k]") that indicate the measured time delay.

[0088] In the example of FIG. 9, the TDC 560 includes a delay line 915 and a plurality of flip-flops 930-1 through 930-n coupled to the delay line 915. The flip-flops 930-1 through 930-n are clocked by a capture clock signal received at a capture input 564. The delay line 915 has an input 918 coupled to a signal input 562 of the TDC 560 and a plurality of nodes 922-1 through 922-n, each node corresponding to a different delay along the delay line 915. In the example of FIG. 9, the delay line 915 includes a plurality of delay buffers 920-1 through 920-n coupled in series, with the output of each of the delay buffers 920-1 through 920-n corresponding to a respective one of the nodes 922-1 through 922-n. In operation, a timing signal received by the TDC 560 propagates through the delay line 915. The output of each delay buffer 920-1 through 920-n provides a different delayed version of the timing signal at a respective node 922-1 through 922-n.

[0089] Each of the flip-flops 930-1 to 930-n has a signal input 932-1 to 932-n, an output 934-1 to 934-n, and a clock input 936-1 to 936-n. The clock input 936-1 to 936-n of each flip-flop 930-1 to 930-n is coupled to the capture input 564 and configured to receive a capture clock signal. Each flip-flop 930-1 to 930-n is configured to latch the bit value at its respective signal input 932-1 to 932-n on an edge of the capture clock signal and output the latched bit value at its respective output 934-1 to 934-n. The edge of the capture clock signal may be a rising edge in an example where the flip-flops 930-1 to 930-n are implemented using rising edge triggered flip-flops. Note that in the example shown in Figures 8A to 8D, the edge of the capture clock signal is a rising edge. However, it should be appreciated that the present disclosure is not limited to this example.

[0090] The signal inputs 932-1 to 932-n of each flip-flop 930-1 to 930-n are coupled to a respective one of the nodes 922-1 to 922-n on the delay line 915. Thus, the signal inputs 932-1 to 932-n of each flip-flop 930-1 to 930-n receive a different delayed version of the timing signal. In the example of FIG. 9, the signal inputs 932-1 to 932-n of each flip-flop 930-1 to 930-n are coupled to the output of a respective one of the delay buffers 920-1 to 920-n. The outputs 934-1 to 934-n of each flip-flop 930-1 to 930-n provide a respective one of the bits (labeled "tdc_q[0]" to "tdc_q[k]") of the digital time measurement signal (labeled "tdc_q"). In this example, each flip-flop 930-1 to 930-n latches the bit value of its respective node 922-1 to 922-n on an edge of the capture clock signal (e.g., a rising edge of the capture clock signal) and outputs the latched bit value as the bit value of the respective bit of a digital time measurement signal (labeled “tdc_q”).

[0091] In this example, the time delay of the timing signal is indicated by the number of bits of the digital time measurement signal (labeled "tdc_q[0]" through "tdc_q[k]") that are 1. The more bits that are 1, the longer the time delay. This is because the further the timing signal propagates through the delay line 915, the more bits that are 1, which occurs when the time delay is longer.

[0092] In this example, the TDC 560 measures the time delay of the timing signal in time increments equal to the delay of one delay buffer, which provides a much higher resolution than that provided by the RO-based timing measurement circuit 410. This is because the ring oscillator 430 includes multiple delay buffers coupled in a loop, and the RO signal must propagate through the multiple delay buffers twice to generate each oscillation of the RO signal. As a result, the time increment in the RO-based timing measurement circuit 410 is equal to twice the sum of the delays of the multiple delay buffers in the ring oscillator 430. Thus, the time increments at which the RO-based timing measurement circuit 410 measures the time delay are much larger than the TDC 560, which results in a much lower resolution of the RO-based timing measurement circuit 410.

[0093] It should be understood that the timing measurement circuit 510 is not limited to the examples shown in Figures 5 and 7. For example, in some implementations, the delay circuit 550 may have a fixed time delay, or the delay circuit 550 may be omitted (e.g., when the TDC 560 has a time measurement range spanning a clock period). In implementations in which the delay circuit 550 is omitted, the signal input 562 of the TDC 560 may be directly coupled to the output 538 of the launch circuit 530.

[0094] 10 illustrates another exemplary implementation of a TDC 560, according to some aspects. In this example, the TDC 560 includes a flip-flop 1010 having a signal input 1012, a clock input 1014, and an output 1016. The signal input 1012 is coupled to a signal input 562 of the TDC 560, the clock input 1014 is coupled to a capture input 564 of the TDC 560, and the output 1016 is coupled to an output 566 of the TDC 560.

[0095] In this example, flip-flop 1010 is clocked by a capture clock signal received at a capture input 564 of TDC 560. Flip-flop 1010 is configured to latch the logic value at its signal input 1012 on an edge (e.g., a rising edge) of the capture clock signal and output the latched logic value to measurement control circuit 520. Thus, in this example, the latched logic value provides the digital time measurement signal that is output by TDC 560.

[0096] In this example, the latched logic value output by flip-flop 1010 indicates whether an edge of the timing signal will arrive at TDC 560 by the time an edge of the capture clock signal is received at clock input 1014. For example, if the edge of the timing signal is a rising edge (as shown in the examples of FIGS. 8A-8D), the latched logic value is 1 if the edge of the timing signal arrives before the edge of the capture clock signal and 0 if the edge of the timing signal arrives after the edge of the capture clock signal. Because the edge of the timing signal arrives at TDC 560 after the time delay of delay circuit 550, the latched value output by flip-flop 1010 indicates whether the time delay of delay circuit 550 is less than or greater than the time delay between the launch clock edge and the capture clock edge. This information can be used to measure the high phase, low phase, or period of the clock signal by sequentially adjusting the time delay of delay circuit 550 to different delay settings and observing the latched logic value for each delay setting, as described further below.

[0097] To measure the high phase of the clock signal in this example, the measurement control circuit 520 may use a first edge select signal to select a rising edge for the launch clock edge and a second edge select signal to select a falling edge for the capture clock edge. The measurement control circuit 520 may then use the delay control signal to sequentially adjust the time delay of the delay circuit 550 to different delay settings. For each delay setting, the measurement control circuit 520 initiates a measurement and receives a latched logic value from the TDC 560 indicating whether the time delay of the delay circuit 550 is less than or greater than the high phase of the clock signal. For example, in an example where the edge of the timing signal is a rising edge, the latched value is 0 if the time delay of the delay circuit 550 is greater than the high phase and 1 if the time delay of the delay circuit 550 is less than the high phase. In this example, the measurement control circuit 520 may determine the high phase by determining the highest delay setting with a latched value of 1 and the lowest delay setting with a latched value of 0. In this case, the high phase of the clock signal may be between the time delay corresponding to the highest delay setting, where the latched value is 1, and the time delay corresponding to the lowest delay setting, where the latched value is 0. Measurement control circuit 520 may then estimate that the high phase is equal to one of the two time delays. Alternatively, measurement control circuit 520 may estimate that the high phase is equal to the time delay between the two time delays. Thus, in this example, measurement control circuit 520 measures the high phase by sequentially adjusting the time delay of delay circuit 550 to different delay settings and observing the latched logic value for each delay setting to determine the time delay approximately equal to the high phase.

[0098] In this example, the low phase and clock period may each be measured in a manner similar to the high phase described above. For a low phase measurement, the measurement control circuit 520 may use a first edge select signal to select a falling edge for the launch clock edge and a rising edge for the capture clock edge using a second edge select signal. For a clock period measurement, the measurement control circuit 520 may select a rising edge for the launch clock edge and a rising edge for the capture clock edge, or may select a falling edge for the launch clock edge and a falling edge of the capture clock edge.

[0099] FIG. 11 illustrates an example implementation of a delay circuit 550 according to some aspects of the disclosure. In this example, the delay circuit 550 includes multiple delay devices 1110-1 to 1110-N coupled in series to form a delay line (e.g., a delay chain). Each of the delay devices 1110-1 to 1110-N has a respective input (labeled "in") and a respective output (labeled "out"). Each of the delay devices 1110-1 to 1110-N may have approximately the same delay τ. An input of the delay device 1110-1 is coupled to a signal input 552 of the delay circuit 550. An output of each of the delay devices 1110-1 to 1110-(N-1) is coupled to an input of the next delay device 1110-2 to 1110-N in the delay line. Each of the delay devices 1110-1 to 1110-N may also be referred to as a delay stage, a delay element, a delay unit, a delay buffer, or another terminology.

[0100] The delay circuit 550 also includes a multiplexer 1130 having a plurality of inputs 1132-1 through 1132-N, an output 1134, and a select input 1136. Each of the inputs 1132-1 through 1132-N of the multiplexer 1130 is coupled to the output of a respective one of the delay devices 1110-1 through 1110-N in the delay line. As a result, each of the inputs 1132-1 through 1132-N is coupled to a different point on the delay line corresponding to a different time delay. The output 1134 of the multiplexer 1130 is coupled to an output 556 of the delay circuit 550, and the select input 1136 of the multiplexer 1130 is coupled to a control input 554 of the delay circuit 550.

[0101] Multiplexer 1130 is configured to receive a delay control signal at a selection input 1136 from measurement control circuit 520 and to select one of inputs 1132-1 through 1132-N of multiplexer 1130 based on the received delay control signal, with the selected one of inputs 1132-1 through 1132-N being coupled to an output 1134 of multiplexer 1130. Because each of inputs 1132-1 through 1132-N is coupled to a different point on the delay line corresponding to a different time delay, the delay control signal controls which of inputs 1132-1 through 1132-N is selected by multiplexer 1130, thereby controlling the time delay of delay circuit 550.

[0102] It should be understood that the delay circuit 550 is not limited to the exemplary implementation shown in Figure 11. In general, the delay circuit 550 may include multiple delay devices and circuitry for selectively switching the delay devices in and out of a delay path between a signal input 552 and an output 556 of the delay circuit 550 based on a delay control signal. The circuitry may include switches, one or more multiplexers, logic gates, or any combination thereof.

[0103] 12 illustrates another exemplary implementation of a duty cycle adjuster 1220 according to some aspects. The duty cycle adjuster 1220 may be used to implement the duty cycle adjuster 320 of FIG. 3 (i.e., the duty cycle adjuster 320 may be one example of the duty cycle adjuster 320). The duty cycle adjuster 1220 has a signal input 1222, a first control input 1226, a second control input 1228, and an output 1224. In an example in which the duty cycle adjuster 1220 implements the duty cycle adjuster 320 of FIG. 3, the signal input 1222 corresponds to the signal input 322, the output 1224 corresponds to the output 324, and the first control input 1226 and the second control input 1228 correspond to the control input 326 (i.e., the control input 326 includes two inputs in this example).

[0104] In this example, the duty cycle adjuster 1220 includes a first inverter 1235, a first multiplexer 1240, a high phase extender 1250, a second inverter 1265, and a second multiplexer 1270. The first multiplexer 1240 has a first input 1242, a second input 1244, a selection input 1246, and an output 1248. The first input 1242 of the first multiplexer 1240 is coupled to the signal input 1222 of the duty cycle adjuster 1220, and the selection input 1246 of the first multiplexer 1240 is coupled to the first control input 1226. The first inverter 1235 is coupled between the signal input 1222 of the duty cycle adjuster 1220 and the second input 1244 of the first multiplexer 1240. As used herein, an "inverter" encompasses any circuit implementation capable of performing an inversion function, such as using a NAND gate, a complementary metal-oxide semiconductor (CMOS) inverter, or any logic gate or combination of logic gates capable of performing an inversion function.

[0105] High phase extender 1250 has a signal input 1252, a control input 1254, and an output 1256. The signal input 1252 of high phase extender 1250 is coupled to the output 1248 of the first multiplexer 1240, and the control input 1254 of high phase extender 1250 is coupled to the second control input 1228 of the duty cycle adjuster 1220. As described further below, high phase extender 1250 is configured to extend the high phase of the clock signal by an adjustable amount based on a phase control signal received at the control input 1254.

[0106] The second multiplexer 1270 has a first input 1272, a second input 1274, a selection input 1276, and an output 1278. The first input 1272 of the second multiplexer 1270 is coupled to the output 1256 of the high phase extender 1250, and the selection input 1276 of the second multiplexer 1270 is coupled to the first control input 1226. The second inverter 1265 is coupled between the output 1256 of the high phase extender 1250 and the second input 1274 of the second multiplexer 1270. The output 1278 of the second multiplexer 1270 is coupled to the output 1224.

[0107] Duty cycle adjuster 1220 is configured to receive a clock signal at signal input 1222 (e.g., from clock generator 115), adjust the duty cycle of the clock signal, and output the duty-cycle-adjusted clock signal at output 1224. Duty cycle adjuster 1220 can increase or decrease the duty cycle of the clock signal. Thus, duty cycle adjuster 1220 supports duty cycle adjustment in either direction.

[0108] To increase the duty cycle of the clock signal input to the duty cycle adjuster 1220, the duty cycle control circuit 330 (shown in FIG. 3) causes each of the first multiplexer 1240 and the second multiplexer 1270 to select their respective first inputs 1242 and 1272 via the first control input 1226. In this case, the first multiplexer 1240 passes the clock signal to the signal input 1252 of the high phase extender 1250. The high phase extender 1250 then extends the high phase of the clock signal by an adjustable amount based on a phase control signal received from the duty cycle control circuit 330 via the second control input 1228. By extending the high phase of the clock signal, the high phase extender 1250 increases the duty cycle of the clock signal. The greater the amount of high phase extension by the high phase extender 1250, the greater the increase in the duty cycle of the clock signal. In this example, the second multiplexer 1270 passes the high phase expanded clock signal to the output 1224 of the duty cycle adjuster 1220 .

[0109] To reduce the duty cycle of the clock signal input to the duty cycle adjuster 1220, the duty cycle control circuit 330 (shown in FIG. 3) causes each of the first multiplexer 1240 and the second multiplexer 1270 to select their respective second inputs 1244 and 1274 via the first control input 1226. In this case, the first inverter 1235 inverts the clock signal, and the first multiplexer 1240 passes the inverted clock signal to the signal input 1252 of the high phase extender 1250. The high phase extender 1250 then extends the high phase of the inverted clock signal by an adjustable amount based on a phase control signal received from the duty cycle control circuit 330 via the second control input 1228. In this case, extending the high phase of the inverted clock signal is equivalent to extending the low phase of the clock signal, which reduces the duty cycle of the clock signal. The greater the amount that the high phase extender 1250 extends the high phase of the inverted clock signal, the greater the reduction in the duty cycle of the clock signal. In this example, the second inverter 1265 inverts the inverted clock signal after the high phase extension to obtain the clock signal, and the second multiplexer 1270 passes the clock signal from the second inverter 1265 to the output 1224 of the duty cycle adjuster 1220.

[0110] Thus, the duty cycle adjuster 1220 can increase or decrease the duty cycle of the clock signal. To increase the duty cycle of the clock signal, the high phase extender 1250 extends the high phase of the clock signal. To decrease the duty cycle of the clock signal, the first inverter 1235 inverts the clock signal, the high phase extender 1250 extends the high phase of the inverted clock signal (which is equivalent to extending the low phase of the clock signal), and the second inverter 1265 inverts the inverted clock signal back to the clock signal. In applications where only the high phase extension is used, the multiplexers 1240 and 1270 and the inverters 1235 and 1265 may be omitted.

[0111] 13 illustrates an exemplary implementation of the high phase extender 1250 according to some embodiments. In this example, the high phase extender 1250 includes an OR gate 1330 and a delay circuit 1320. It should be understood that the OR gate 1330 may be implemented with a combination of two or more gates to generate an equivalent logical function. For example, in some implementations, the OR gate 1330 may include a NOR gate and an inverter.

[0112] The OR gate 1330 has a first input 1332, a second input 1334, and an output 1336. The first input 1332 is coupled to the signal input 1252 of the high phase extender 1250, and the output 1336 is coupled to the output 1256 of the high phase extender 1250. The delay circuit 1320 has a signal input 1322, a control input 1324, and an output 1326. The signal input 1322 of the delay circuit 1320 is coupled to the signal input 1252 of the high phase extender 1250, the control input 1324 of the delay circuit 1320 is coupled to the control input 1254 of the high phase extender 1250, and the output 1326 of the delay circuit 1320 is coupled to the second input 1334 of the OR gate 1330.

[0113] The delay circuit 1320 is configured to delay the clock signal by an adjustable time delay based on a delay control signal received via the control input 1254. The resulting delayed clock signal is input to a second input 1334 of the OR gate 1330. The OR gate 1330 performs an OR function on the clock signal at the first input 1332 and the delayed clock signal at the second input 1334 to generate a clock signal at an output 1336. The clock signal at the output 1336 has an extended high phase compared to the clock signal at the signal input 1252, the high phase extension being controlled by the time delay of the delay circuit 1320. The greater the time delay of the delay circuit 1320, the greater the high phase extension of the clock signal at the output 1336. Thus, in this example, the duty cycle control circuit 330 (shown in FIG. 3) controls the high phase extension of the clock signal at the output 1256 of the high phase extender 1250 by controlling the time delay of the delay circuit 1320. In this example, the phase control signal described above corresponds to a delay control signal input to the control input 1324 of the delay circuit 1320 .

[0114] In this example, the time delay of the delay circuit 1320 may be limited by the high phase of the clock signal at the signal input 1252 (i.e., the time delay of the delay circuit 1320≦the input high phase). This is because increasing the time delay beyond the input high phase may result in clock glitches. In this regard, FIG. 14A shows an example of a clock signal at the signal input 1252 (labeled “hpe_in”) and at the output 1256 (labeled “hpe_out”) when the time delay is less than the high phase of the clock signal at the signal input 1252, and FIG. 14B shows an example of a clock signal at the signal input 1252 (labeled “hpe_in”) and at the output 1256 (labeled “hpe_out”) when the time delay is greater than the high phase of the clock signal at the signal input 1252. 14B, making the time delay of the delay circuit 1320 larger than the high phase of the clock signal at the signal input 1252 may result in a clock glitch 1410. Thus, an example implementation of the high phase extender 1250 may be limited to extending the high phase of the output clock signal by an amount equal to or less than the high phase of the input clock signal (i.e., the time delay of the delay circuit 1320≦the input high phase) for a maximum output high phase equal to twice the input high phase, and therefore may not be suitable for use cases requiring a larger high phase extension.

[0115] To address this, FIG. 15A illustrates an exemplary implementation of a delay circuit 1320 that provides a larger high-phase extension range, according to some embodiments. In this example, the delay circuit 1320 includes a plurality of delay devices 1510-1 to 1510-m coupled in series to form a delay line. The delay devices 1510-1 to 1510-m may also be referred to as delay segments, or by other terms. Each of the delay devices 1510-1 to 1510-m has a respective first signal input 1512-1 to 1512-m, a respective second signal input 1514-1 to 1514-m, a respective control input 1516-1 to 1516-m, and a respective delay output 1518-1 to 1518-m. The first signal input 1512-1 of the delay device 1510-1 is coupled to the signal input 1252 of the high-phase extender 1250. In the example of Figure 15A, the second signal input 1514-1 of the delay device 1510-1 is coupled to ground. The delay output 1518-1 to 1518-(m-1) of each of the delay devices 1510-1 to 1510-(m-1) is coupled to the second signal input 1514-2 to 1514-m of the next delay device 1510-2 to 1510-m in the delay line, and the delay output 1518-m of the delay device 1510-m is coupled to the second input 1334 of the OR gate 1330 as shown in Figure 15A. The first signal input 1512-2 to 1512-m of each of the delay devices 1510-2 to 1510-m is coupled to the signal input 1252 of the high phase extender 1250.

[0116] Each of the delay devices 1510-1 to 1510-m is configured to receive a respective control signal (e.g., a control bit) via a respective control input 1516-1 to 1516-m. In this example, the control input 1254 of the high phase extender 1250 includes a plurality of control inputs 1254-1 to 1254-m, each of the plurality of control inputs 1254-1 to 1254-m coupled to a respective one of the control inputs 1516-1 to 1516-m of the delay devices 1510-1 to 1510-m.

[0117] In this example, each of the delay devices 1510-1-1510-m is configured to enable or disable a respective delay output 1518-1-1518-m based on a respective control signal. For example, each of the delay devices 1510-1-1510-m may be configured to enable a respective delay output 1518-1-1518-m when the respective control signal has a first logical value and to disable a respective delay output 1518-1-1518-m when the respective control signal has a second logical value. The first logical value may be 1 and the second logical value may be 0, or vice versa.

[0118] Each of the delay devices 1510-1 to 1510-m is configured to pass a high phase (i.e., logic 1) at the respective first signal input 1512-1 to 1512-m to the respective delay output 1518-1 to 1518-m and pass a high phase (i.e., logic 1) at the respective second signal input 1514-1 to 1514-m to the respective delay output 1518-1 to 1518-m when the respective delay output 1518-1 to 1518-m is enabled. In the example of FIG. 15A, the second signal input 1514-1 of the delay device 1510-1 is coupled to ground. Each of the delay devices 1510-1 to 1510-m is configured to block the signal (i.e., clock signal) at the respective first signal input 1512-1 to 1512-m and to block (i.e., gate) the signal (i.e., clock signal) at the respective second signal input 1514-2 to 1514-m when the respective delay output 1518-1 to 1518-m is disabled. In this example, each of the delay devices 1510-1 to 1510-m may output a static logic value at the respective delay output 1518-1 to 1518-m when the respective delay output 1518-1 to 1518-m is disabled. The static logic value may be 0 or 1.

[0119] In this example, duty cycle control circuit 330 (shown in FIG. 3) controls the high phase extension of high phase extender 1250 by controlling the number of delay devices 1510-1-1510-m that have their delay outputs 1518-1-1518-m enabled via control inputs 1254-1-1254-m. The more delay devices 1510-1-1510-m that have their delay outputs 1518-1-1518-m enabled, the greater the high phase extension of the clock signal at output 1256. In this example, duty cycle control circuit 330 enables delay outputs 1518-1-1518-m of delay devices 1510-1-1510-m (also referred to as delay segments) starting with delay output 1518-m of delay device 1510-m and proceeding from right to left in FIG. 15A. Thus, to enable one delayed output of delay devices 1510-1 through 1510-m, duty cycle control circuit 330 enables delayed output 1518-m of delay device 1510-m. To enable two delayed outputs of delay devices 1510-1 through 1510-m, duty cycle control circuit 330 enables delayed outputs 1518-m and 1518-(m-1) of delay devices 1510-m and 1510-(m-1). To enable three delayed outputs of delay devices 1510-1 through 1510-m, duty cycle control circuit 330 enables delayed outputs 1518-m, 1518-(m-1), and 1518-(m-2) of delay devices 1510-m, 1510-(m-1), and 1510-(m-2), and so on. Note that delay devices 1510-(m-1) and 1510-(m-2) are not explicitly shown in FIG. 15A for ease of illustration.

[0120] In this example, delay devices 1510-1 through 1510-m increase the high phase extension range of high phase extender 1250 because delay devices with enabled delay outputs generate multiple delayed versions of the clock signal that are delayed by different time delays. The high phases of the multiple delayed versions of the clock signal are combined at output 1326 of delay circuit 1320 and ORed with the clock signal at OR gate 1330. This allows high phase extender 1250 to achieve a large high phase extension range for the output clock signal, as described further below.

[0121] An example of multiple delayed versions of the clock signal is shown in FIG. 15B for an example in which three delayed outputs 1518-m, 1518-(m-1), and 1518-(m-2) of delay devices 1510-m, 1510-(m-1), and 1510-(m-2) are enabled. FIG. 15B shows the clock signal at the signal input 1252 of the high phase extender 1250 (labeled "hpe_in") and the clock signal at the output 1256 of the high phase extender 1250 (labeled "hpe_out"). FIG. 15B also conceptually illustrates, in this example, a first delayed version of the clock signal (labeled "clk1"), a second delayed version of the clock signal (labeled "clk2"), and a third delayed version of the clock signal (labeled "clk3"). The delayed versions of clock signals clk1, clk2, and clk3 are shown separately at the output 1326 of delay circuit 1320 in Figure 15B for ease of explanation. In practice, the high phases of the delayed versions of clock signals clk1, clk2, and clk3 are combined (i.e., merged) at the output 1326 of delay circuit 1320 to form the delayed output signal (labeled "D_out") shown in Figure 15B.

[0122] In this example, a first delayed version of the clock signal, clk1, is generated from the clock signal entering a first signal input 1512-m of the delay device 1510-m and is delayed by the time delay of the delay device 1510-m to reach the output 1326. A second delayed version of the clock signal, clk2, is generated from the clock signal entering a first signal input 1512-(m-1) of the delay device 1510-(m-1) and is delayed by the time delays of the delay devices 1510-(m-1) and 1510-m to reach the output 1326. A third delayed version of the clock signal, clk3, is generated from the clock signal entering a first signal input 1512-(m-2) of the delay device 1510-(m-2) and is delayed by the time delays of the delay devices 1510-(m-2), 1510-(m-1) and 1510-m to reach the output 1326. Note that the high phases of the multiple delayed versions of the clock signal, clk1, clk2, and clk3, overlap in time.

[0123] In this example, the delayed output signal D_out at the output 1326 of the delay circuit 1320 is ORed with the clock signal at the signal input 1252 (labeled "hpe_in") by OR gate 1330 to generate a clock signal at the output 1256 (labeled "hpe_out") that has a large high phase extension. In this example, clock glitches are prevented by making the individual time delays of each of the delay devices 1510-1 to 1510-m smaller than the high phase of the input clock signal such that the delayed versions of the clock signals overlap in time. However, because the delay circuit 1320 includes multiple delay devices 1510-1 to 1510-m, the high phase extender 1250 can achieve a high phase extension that is greater than the high phase of the input clock signal without a glitch.

[0124] 16 illustrates an exemplary implementation of each of the delay devices 1510-1 to 1510-m according to some embodiments. In this example, each of the delay devices 1510-1 to 1510-m includes a respective OR gate 1610-1 to 1610-m, a respective AND gate 1620-1 to 1620-m, and a respective delay buffer 1630-1 to 1630-m and 1640-1 to 1640-m. In each of the delay devices 1510-1 to 1510-m, the respective OR gate 1610-1 to 1610-m has a first input coupled to a respective first signal input 1512-1 to 1512-m and a second input coupled to a respective second signal input 1514-1 to 1514-m. In each of the delay devices 1510-1 to 1510-m, a respective AND gate 1620-1 to 1620-m has a first input coupled to an output of the respective OR gate 1610-1 to 1610-m and a second input coupled to a respective control input 1516-1 to 1516-m. In each of the delay devices 1510-1 to 1510-m, a respective delay buffer 1630-1 to 1630-m and 1640-1 to 1640-m is coupled in series between the output of the respective AND gate 1620-1 to 1620-m and the respective delay output 1518-1 to 1518-m.

[0125] In this example, in each of the delay devices 1510-1 to 1510-m, a respective OR gate 1610-1 to 1610-m passes the high phase at the respective first signal input 1512-1 to 1512-m and the high phase at the respective second signal input 1514-1 to 1514-m to the output of the respective OR gate 1610-1 to 1610-m. In each of the delay devices 1510-1 to 1510-m, a respective AND gate 1620-1 to 1620-m enables the respective delayed output when the respective control signal is 1 (i.e., the AND gate passes the high phase to the respective delayed output) and disables the respective delayed output when the respective control signal is 0 (i.e., the AND gate blocks the high phase and outputs a 0).

[0126] It should be understood that each of the delay devices 1510-1 through 1510-m may include a different number of delay buffers than the number of delay buffers shown in the example of Figure 16, depending on, for example, the desired delay for each of the delay devices 1510-1 through 1510-m. In some implementations, the delay buffers 1630-1 through 1630-m and 1640-1 through 1640-m may be omitted altogether, for example, when the delays of the OR gates 1610-1 through 1610-m and the delays of the AND gates 1620-1 through 1620-m already provide the desired delay for each of the delay devices 1510-1 through 1510-m.

[0127] In the exemplary implementation of the high phase extender 1250 shown in Figures 15A and 16, to avoid clock glitches, only the time delay of the individual delay devices (i.e., 1510-m, 1510-(m-1), ..., 1510-1) needs to be less than or equal to the high phase of the input clock signal; the high phase of the output clock can be extended by the accumulation of time delays from the enabled delay devices. The exemplary implementation of the high phase extender 1250 of Figures 15A and 16 allows for an extension of the high phase of the output clock signal that is greater than the high phase of the input clock signal, thus allowing a larger range of high phase extension while avoiding clock glitches.

[0128] It should be understood that the duty cycle adjuster 1220 is not limited to the high phase extender 1250. In this regard, FIG. 17 illustrates an example in which the duty cycle adjuster 1220 includes a low phase extender 1750 instead of the high phase extender 1250. In this example, the low phase extender has a signal input 1752 coupled to the output 1248 of the first multiplexer 1240, a control input 1754 coupled to the second control input 1228, and an output 1756 and a first input 1272 of the second multiplexer 1270. In this example, the low phase extender 1750 is configured to extend the low phase of the clock signal by an adjustable amount based on a phase control signal received via the control input 1754.

[0129] To reduce the duty cycle of the clock signal input to the duty cycle adjuster 1220, the duty cycle control circuit 330 (shown in FIG. 3) causes each of the first multiplexer 1240 and the second multiplexer 1270 to select their respective first inputs 1242 and 1272 via the first control input 1226. In this case, the first multiplexer 1240 passes the clock signal to a signal input 1752 of the low phase extender 1750. The low phase extender 1750 then extends the low phase of the clock signal by an adjustable amount based on a phase control signal received from the duty cycle control circuit 330 via the second control input 1228. By extending the low phase of the clock signal, the low phase extender 1750 reduces the duty cycle of the clock signal.

[0130] To increase the duty cycle of the clock signal input to the duty cycle adjuster 1220, the duty cycle control circuit 330 (shown in FIG. 3) causes each of the first multiplexer 1240 and the second multiplexer 1270 to select their respective second inputs 1244 and 1274 via the first control input 1226. In this case, the first inverter 1235 inverts the clock signal, and the first multiplexer 1240 passes the inverted clock signal to the low phase extender 1750. The low phase extender 1750 then extends the low phase of the inverted clock signal by an adjustable amount based on a phase control signal received from the duty cycle control circuit 330 via the second control input 1228. In this case, extending the low phase of the inverted clock signal is equivalent to extending the high phase of the clock signal, which increases the duty cycle of the clock signal. In this example, the second inverter 1265 inverts the inverted clock signal after low phase extension to obtain a clock signal, and the second multiplexer 1270 passes the clock signal from the second inverter 1265 to the output 1224 of the duty cycle adjuster 1220.

[0131] Generally, the duty cycle adjuster 1220 includes a high phase extender (e.g., high phase extender 1250) or a low phase extender (e.g., low phase extender 1750) between the output 1248 of the first multiplexer 1240 and the first input 1272 of the second multiplexer 1270, where the high phase extender extends the high phase of the clock signal or the low phase extender extends the low phase of the clock signal by an adjustable amount based on a phase control signal received via the second control input 1228.

[0132] 18 illustrates an exemplary implementation of a low phase extender 1750 according to some embodiments. In this example, the low phase extender 1750 includes an AND gate 1830 and a delay circuit 1820. The AND gate 1830 has a first input 1832, a second input 1834, and an output 1836. The first input 1832 of the AND gate 1830 is coupled to a signal input 1752 of the low phase extender 1750, the delay circuit 1820 is coupled between the signal input 1752 of the low phase extender 1750 and a second input 1834 of the AND gate 1830, and the output 1836 of the AND gate 1830 is coupled to an output 1756 of the low phase extender 1750. It should be understood that the AND gate may be implemented with a combination of a NAND gate and an inverter, or any other combination of logic gates capable of performing an AND operation.

[0133] In this example, the delay circuit 1820 includes a plurality of delay devices 1810-1 to 1810-m coupled in series to form a delay line. Each of the delay devices 1810-1 to 1810-m has a respective first signal input 1812-1 to 1812-m, a respective second signal input 1814-1 to 1814-m, a respective control input 1816-1 to 1816-m, and a respective delay output 1818-1 to 1818-m. The first signal input 1812-1 of the delay device 1810-1 is coupled to the signal input 1752 of the low phase extender 1750, and the second signal input 1814-1 of the delay device 1810-1 is coupled to a (i.e., one) power supply rail. The delay output 1818-1 to 1818-(m-1) of each of the delay devices 1810-1 to 1810-(m-1) is coupled to a second signal input 1814-2 to 1814-m of the next delay device 1810-2 to 1810-m in the delay line, and the delay output 1818-m of the delay device 1810-m is coupled to an output 1826 of the delay circuit 1820, which output 1826 is coupled to a second input 1834 of the AND gate 1830. The first signal input 1812-2 to 1812-m of each of the delay devices 1810-2 to 1810-m is coupled to a signal input 1752 of the low phase extender 1750.

[0134] Each of the delay devices 1810-1 through 1810-m is configured to receive a respective control signal (e.g., a control bit) via a respective control input 1816-1 through 1816-m. In this example, the control input 1754 of the low phase extender 1750 includes a plurality of control inputs 1754-1 through 1754-m, each of the plurality of control inputs 1754-1 through 1754-m coupled to a respective one of the control inputs 1816-1 through 1816-m of the delay devices 1810-1 through 1810-m.

[0135] In this example, each of the delay devices 1810-1-1810-m is configured to enable or disable a respective delayed output 1818-1-1818-m based on a respective control signal. For example, each of the delay devices 1810-1-1810-m may be configured to enable a respective delayed output 1818-1-1818-m when the respective control signal has a first logical value and to disable a respective delayed output 1818-1-1818-m when the respective control signal has a second logical value. The first logical value may be 0 and the second logical value may be 1, or vice versa.

[0136] Each of the delay devices 1810-1 to 1810-m is configured to pass a low phase (i.e., logic 0) at the respective first signal input 1812-1 to 1812-m to the respective delay output 1818-1 to 1818-m and pass a low phase (i.e., logic 0) at the respective second signal input 1814-1 to 1814-m to the respective delay output 1818-1 to 1818-m when the respective delay output 1818-1 to 1818-m is enabled. In the example of FIG. 18, the second signal input 1814-1 of the delay device 1810-1 is coupled to a power supply rail. Each of the delay devices 1810-1 to 1810-m is configured to block the signal (i.e., clock signal) at the respective first signal input 1812-1 to 1812-m and block (i.e., gate) the signal (i.e., clock signal) at the respective second signal input 1814-2 to 1814-m when the respective delay output 1818-1 to 1818-m is disabled. In this example, each of the delay devices 1810-1 to 1810-m may output a static logic value at the respective delay output 1818-1 to 1818-m when the respective delay output 1818-1 to 1818-m is disabled. The static logic value may be 1 or 0.

[0137] In this example, duty cycle control circuit 330 (shown in FIG. 3) controls the low phase extension of low phase extender 1750 by controlling the number of delay devices 1810-1-1810-m that have their delay outputs 1818-1-1818-m enabled via control inputs 1754-1-1754-m. The more delay devices 1810-1-1810-m that have their delay outputs 1818-1-1818-m enabled, the greater the low phase extension of the clock signal at output 1756. In this example, duty cycle control circuit 330 enables delay outputs 1818-1-1818-m of delay devices 1810-1-1810-m (also referred to as delay segments) from right to left in FIG. 18, starting with delay output 1818-m of delay device 1810-m. Delay devices 1810-1 to 1810-m with enabled delay outputs 1818-1 to 1818-m generate multiple versions of the clock signal with the low phases of the multiple versions of the clock signal coupled to output 1826 of delay circuit 1820 to provide a delayed output signal with an extended low phase. The more delay devices 1810-1 to 1810-m with enabled delay outputs 1818-1 to 1818-m, the greater the low phase extension. The delayed output signal is ANDed with the clock signal at signal input 1752 by AND gate 1830 to provide the clock signal at output 1756.

[0138] 18 illustrates an exemplary implementation of each of the delay devices 1810-1-1810-m according to some embodiments. In this example, each of the delay devices 1810-1-1810-m includes a respective AND gate 1840-1-1840-m, a respective OR gate 1850-1-1850-m, and a respective delay buffer 1860-1-1860-m and 1870-1-1870-m. In each of the delay devices 1810-1-1810-m, the respective AND gate 1840-1-1840-m has a first input coupled to a respective first signal input 1812-1-1812-m and a second input coupled to a respective second signal input 1814-1-1814-m. In each of the delay devices 1810-1 to 1810-m, a respective OR gate 1850-1 to 1850-m has a first input coupled to an output of a respective AND gate 1840-1 to 1840-m and a second input coupled to a respective control input 1816-1 to 1816-m. In each of the delay devices 1810-1 to 1810-m, a respective delay buffer 1860-1 to 1860-m and 1870-1 to 1870-m are coupled in series between the output of the respective OR gate 1850-1 to 1850-m and the respective delay output 1818-1 to 1818-m.

[0139] In this example, in each of delay devices 1810-1-1810-m, a respective AND gate 1840-1-1840-m passes a low phase at a respective first signal input 1812-1-1812-m and a low phase at a respective second signal input 1814-1-1814-m to an output of the respective AND gate 1840-1-1840-m. In each of delay devices 1810-1-1810-m, a respective OR gate 1850-1-1850-m enables a respective delayed output when a respective control signal is 0 (i.e., the OR gate passes the low phase to the respective delayed output) and disables a respective delayed output when a respective control signal is 1 (i.e., the OR gate blocks the low phase and outputs a 1).

[0140] It should be understood that each of the delay devices 1810-1 to 1810-m may include a different number of delay buffers than the number of delay buffers shown in the example of FIG. 18, depending, for example, on the desired delay for each of the delay devices 1810-1 to 1810-m.

[0141] 19 illustrates a method 1900 for measuring a clock signal. The method 1900 may be performed by the timing measurement circuit 510, according to some aspects.

[0142] In block 1910, an edge of the timing signal is launched at a first edge of the clock signal. For example, the edge of the timing signal may be launched by launch circuit 530. The first edge of the clock signal may be a rising edge or a falling edge of the clock signal.

[0143] In block 1920, an edge of the capture signal is output at a second edge of the clock signal. For example, the edge of the capture signal may be output by the capture circuit 540. The second edge of the clock signal may be a rising edge or a falling edge of the clock signal.

[0144] In block 1930, the edges of the timing signal and the edges of the capture signal are received at a time-to-digital converter (TDC). The TDC may correspond to the TDC 560.

[0145] In block 1940, the time delay between the time an edge of the timing signal is received at the TDC and the time an edge of the capture signal is received at the TDC is measured using the TDC.

[0146] The following numbered clauses describe example implementations. 1. a launch circuit having an enable input, a clock input, and an output, the launch circuit being configured to receive an enable signal at the enable input and a clock signal at the clock input of the launch circuit, and in response to receiving the enable signal, to launch an edge of the timing signal at an output of the launch circuit with a first edge of the clock signal; a capture circuit having a clock input and an output, the capture circuit being configured to receive a clock signal at the clock input of the capture circuit and to output an edge of the capture signal at an output of the capture circuit on a second edge of the clock signal; a time-to-digital converter (TDC) having a signal input, a capture input, and an output, the signal input of the TDC being coupled to the output of the launch circuit and the capture input of the TDC being coupled to the output of the capture circuit; A timing measurement circuit comprising:

[0147] 2.TDC is receiving an edge of a timing signal at the signal input of the TDC; Receive an edge of a capture signal at the capture input of the TDC; measuring a time delay between a time that an edge of the timing signal is received and a time that an edge of the capture signal is received; At the output of the TDC, a signal is generated that indicates the measured time delay. 2. The timing measurement circuit of claim 1, configured as follows:

[0148] 3. The timing measurement circuit of clause 1 or 2, further comprising a delay circuit having a signal input and an output, the signal input of the delay circuit being coupled to the output of the launch circuit and the output of the delay circuit being coupled to the signal input of the TDC.

[0149] 4. The delay circuit has an adjustable time delay, and the delay circuit receiving a delay control signal at a control input of the delay circuit; setting a time delay of the delay circuit based on the received delay control signal; 4. The timing measurement circuit of claim 3, configured to:

[0150] 5. TDC a flip-flop having a signal input, a clock input, and an output, the signal input of the flip-flop being coupled to the signal input of the TDC, the clock input of the flip-flop being coupled to the capture input of the TDC, and the output of the flip-flop being coupled to the output of the TDC. 5. The timing measurement circuit of claim 4, comprising:

[0151] 6. TDC a delay line coupled to a signal input of the TDC, the delay line including a serially coupled delay buffer; flip-flops, each of the flip-flops having a respective signal input, a respective clock input, and a respective output, each of the signal inputs of the flip-flops being coupled to an output of a respective one of the delay buffers, and each of the clock inputs of the flip-flops being coupled to a capture input of the TDC; 5. The timing measurement circuit according to any one of claims 1 to 4, comprising:

[0152] 7. A launch circuit having a control input configured to receive an edge select signal, the launch circuit comprising: selecting a rising edge of the clock signal for a first edge of the clock signal when the edge selection signal has a first logic value; selecting a falling edge of the clock signal for the first edge of the clock signal when the edge selection signal has a second logic value; The timing measurement circuit according to any one of claims 1 to 6, configured as follows:

[0153] 8. The launch circuit a multiplexer having a first input, a second input, a select input, and an output, the first input being coupled to a clock input of the launch circuit and the select input being coupled to a control input of the launch circuit; an inverter coupled between the clock input of the launch circuit and a second input of the multiplexer; a launch flip-flop having a signal input, a clock input, and an output, the signal input of the launch flip-flop being coupled to the enable input of the launch circuit, the clock input of the launch flip-flop being coupled to the output of the multiplexer, and the output of the launch flip-flop being coupled to the output of the launch circuit; 8. The timing measurement circuit of claim 7, comprising:

[0154] 9. The launch circuit a first flip-flop having a signal input, a clock input, and an output, the signal input of the first flip-flop being coupled to the enable input of the launch circuit and the clock input of the first flip-flop being coupled to the clock input of the launch circuit; a second flip-flop having a signal input, a clock input, and an output, the signal input of the second flip-flop being coupled to the output of the first flip-flop, the clock input of the second flip-flop being coupled to the output of the multiplexer, and the output of the second flip-flop being coupled to the signal input of the launch flip-flop; 9. The timing measurement circuit of claim 8, further comprising:

[0155] 10. A capture circuit having a control input configured to receive an edge select signal, the capture circuit comprising: selecting a rising edge of the clock signal for a second edge of the clock signal when the edge selection signal has a first logic value; selecting a falling edge of the clock signal for a second edge of the clock signal when the edge selection signal has a second logic value; 10. The timing measurement circuit according to any one of claims 1 to 9, configured as follows:

[0156] 11. The capture circuit is a multiplexer having a first input, a second input, a selection input, and an output, the first input being coupled to a clock input of the capture circuit and the selection input being coupled to a control input of the capture circuit; an inverter coupled between the clock input of the capture circuit and a second input of the multiplexer; a clock gating circuit coupled between the output of the multiplexer and the output of the capture circuit; 11. The timing measurement circuit of claim 10, comprising:

[0157] 12. A timing measurement circuit as claimed in any one of clauses 1 to 11, wherein the first edge of the clock signal is a rising edge and the second edge of the clock signal is a falling edge.

[0158] 13. A timing measurement circuit as claimed in any one of clauses 1 to 11, wherein the first edge of the clock signal is a falling edge and the second edge of the clock signal is a rising edge.

[0159] 14. A method for measuring a clock signal, comprising: launching an edge of the timing signal on a first edge of the clock signal; outputting an edge of the capture signal on a second edge of the clock signal; receiving an edge of a timing signal and an edge of a capture signal at a time-to-digital converter (TDC); measuring a time delay using the TDC between a time when an edge of a timing signal is received at the TDC and a time when an edge of a capture signal is received at the TDC; A method comprising:

[0160] 15. A method comprising: a first edge of a clock signal is a rising edge; a second edge of the clock signal is a falling edge; and Determining a phase of a clock signal based on the measured time delay 15. The method of claim 14, further comprising:

[0161] 16. Propagating the edges of a timing signal through a delay circuit before the edges are received at the TDC 16. The method of claim 15, further comprising: 16. The method of claim 15, wherein determining the high phase of the clock signal includes determining the high phase of the clock signal based also on a time delay of the delay circuit.

[0162] 17. A method comprising: a first edge of a clock signal is a falling edge; a second edge of the clock signal is a rising edge; and Determining a phase of a clock signal based on the measured time delay 15. The method of claim 14, further comprising:

[0163] 18. Propagating the edges of a timing signal through a delay circuit before the edges are received at the TDC 18. The method of claim 17, further comprising: determining a low phase of the clock signal includes determining a low phase of the clock signal based also on a time delay of the delay circuit; The method described in clause 17.

[0164] It should be understood that the present disclosure is not limited to the exemplary terminology used above to describe aspects of the present disclosure. For example, a clock generator may be referred to as a clock source, a clock synthesizer, or other terminology. In another example, a delay buffer may be referred to as a delay element, a delay unit, or other terminology. In another example, a timing measurement circuit may be referred to as a duty cycle measurement circuit, a duty cycle detector, or other terminology. A signal input of a flip-flop may be referred to as a data input (e.g., a D input) or other terminology. A signal path used for a clock signal may be referred to as a clock path. Also, launching an edge of a signal may be referred to as outputting an edge of a signal.

[0165] The duty cycle control circuit 330 and the measurement control circuit 520 can each be implemented using a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete hardware components (e.g., logic gates), a state machine, or any combination thereof, designed to perform the functions described herein. The functions described herein can be performed by a processor executing software that contains code for performing those functions. The software can be stored on a computer-readable storage medium, such as a RAM, a ROM, an EEPROM, an optical disk, and / or a magnetic disk.

[0166] Within the scope of this disclosure, the word "exemplary" is used to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" should not necessarily be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the described feature, advantage, or mode of operation. The term "coupled" is used herein to refer to a direct or indirect electrical coupling between two structures.

[0167] The above description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. 1. A timing measurement circuit, comprising: a launch circuit having an enable input, a clock input, and an output, the launch circuit being configured to receive an enable signal at the enable input and a clock signal at the clock input of the launch circuit, and in response to receiving the enable signal, to launch an edge of a timing signal at the output of the launch circuit on a first edge of the clock signal; a delay circuit having a signal input, a control input and an output, the signal input of the delay circuit being coupled to the output of the launch circuit, the delay circuit having an adjustable time delay, the delay circuit comprising: receiving a delay control signal at the control input of the delay circuit; Setting the time delay of the delay circuit based on the received delay control signal. A delay circuit configured as follows: a capture circuit having a clock input and an output, the capture circuit being configured to receive the clock signal at the clock input of the capture circuit and to output an edge of a capture signal at the output of the capture circuit on a second edge of the clock signal; a time-to-digital converter (TDC) having a signal input, a capture input, and an output, wherein the signal input of the TDC is coupled to the output of the launch circuit, the capture input of the TDC is coupled to the output of the capture circuit, and the output of the delay circuit is coupled to the signal input of the TDC.

2. The TDC is receiving the edge of the timing signal at the signal input of the TDC; receiving the edge of the capture signal at the capture input of the TDC; measuring a time delay between a time that the edge of the timing signal is received and a time that the edge of the capture signal is received; At the output of the TDC, a signal indicative of the measured time delay is output.

2. The timing measurement circuit of claim 1, configured as follows:

3. The TDC is a flip-flop having a signal input, a clock input, and an output, the signal input of the flip-flop coupled to the signal input of the TDC, the clock input of the flip-flop coupled to the capture input of the TDC, and the output of the flip-flop coupled to the output of the TDC.

2. The timing measurement circuit of claim 1, comprising:

4. The TDC is a delay line coupled to the signal input of the TDC, the delay line including serially coupled delay buffers; flip-flops, each of the flip-flops having a respective signal input, a respective clock input, and a respective output, the signal input of each of the flip-flops being coupled to an output of a respective one of the delay buffers, and the clock input of each of the flip-flops being coupled to the capture input of the TDC; 2. The timing measurement circuit of claim 1, comprising:

5. The launch circuit has a control input configured to receive an edge select signal, the launch circuit comprising: selecting a rising edge of the clock signal for the first edge of the clock signal when the edge selection signal has a first logic value; When the edge selection signal has a second logic value, a falling edge of the clock signal is selected for the first edge of the clock signal.

2. The timing measurement circuit of claim 1, configured as follows:

6. The launch circuit, a multiplexer having a first input, a second input, a select input, and an output, the first input being coupled to the clock input of the launch circuit and the select input being coupled to the control input of the launch circuit; an inverter coupled between the clock input of the launch circuit and the second input of the multiplexer; a launch flip-flop having a signal input, a clock input, and an output, the signal input of the launch flip-flop being coupled to the enable input of the launch circuit, the clock input of the launch flip-flop being coupled to the output of the multiplexer, and the output of the launch flip-flop being coupled to the output of the launch circuit; 6. The timing measurement circuit of claim 5, comprising:

7. The launch circuit, a first flip-flop having a signal input, a clock input, and an output, the signal input of the first flip-flop being coupled to the enable input of the launch circuit and the clock input of the first flip-flop being coupled to the clock input of the launch circuit; a second flip-flop having a signal input, a clock input, and an output, the signal input of the second flip-flop being coupled to the output of the first flip-flop, the clock input of the second flip-flop being coupled to the output of the multiplexer, and the output of the second flip-flop being coupled to the signal input of the launch flip-flop; 7. The timing measurement circuit of claim 6, further comprising:

8. The capture circuit has a control input configured to receive an edge select signal, the capture circuit comprising: selecting a rising edge of the clock signal for the second edge of the clock signal when the edge selection signal has a first logic value; When the edge selection signal has a second logic value, a falling edge of the clock signal is selected for the second edge of the clock signal.

2. The timing measurement circuit of claim 1, configured as follows:

9. The capture circuit, a multiplexer having a first input, a second input, a select input, and an output, the first input being coupled to the clock input of the capture circuit and the select input being coupled to the control input of the capture circuit; an inverter coupled between the clock input of the capture circuit and the second input of the multiplexer; a clock gating circuit coupled between the output of the multiplexer and the output of the capture circuit; 9. The timing measurement circuit of claim 8, comprising:

10. 2. The timing measurement circuit of claim 1, wherein the first edge of the clock signal is a rising edge and the second edge of the clock signal is a falling edge.

11. 2. The timing measurement circuit of claim 1, wherein the first edge of the clock signal is a falling edge and the second edge of the clock signal is a rising edge.

12. 1. A method for measuring a clock signal, comprising the steps of: launching an edge of a timing signal on a first edge of the clock signal; outputting an edge of a capture signal at a second edge of the clock signal; receiving the edges of the timing signal and the edges of the capture signal at a time-to-digital converter (TDC); measuring a time delay using the TDC, the time delay being between a time when the edge of the timing signal is received at the TDC and a time when the edge of the capture signal is received at the TDC, the time delay being adjustable using a control signal; A method comprising:

13. the first edge of the clock signal is a rising edge and the second edge of the clock signal is a falling edge, and the method further comprises: determining a high phase of the clock signal based on the measured time delay; The method of claim 12 further comprising:

14. propagating the edge of the timing signal through a delay circuit before the edge is received at the TDC. Further comprising: determining the high phase of the clock signal further comprises determining the high phase of the clock signal based on a time delay of the delay circuit. The method of claim 13.

15. the first edge of the clock signal is a falling edge and the second edge of the clock signal is a rising edge, and the method further comprises: determining a phase of the clock signal based on the measured time delay; The method of claim 12 further comprising:

16. propagating the edge of the timing signal through a delay circuit before the edge is received at the TDC. Further comprising: determining the low phase of the clock signal further comprises determining the low phase of the clock signal based on a time delay of the delay circuit. The method of claim 15.

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