Storage device and control method for storage device

Abstract

To enable error correction corresponding to a plurality of types of ECCs with a relatively small number of check codes.SOLUTION: A memory control unit 12 is configured to: at the time of writing data into a memory 11, generate a first check code (PCB) common to a plurality of types of error correction codes from the data on the basis of a correlation relationship between the plurality of types of error correction codes; add the first check code to the data and write the data into the memory 11; convert the PCB into a second check code based on any one of the plurality of types of error correction codes at the time of reading the data from the memory 11; and perform error correction by using the second check code.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a storage device and a control method for the storage device. [Background technology]

[0002] In recent years, in order to improve the performance of computers, the integration and scale of computers have progressed, while at the same time, high reliability of components has become important. In memory, a phenomenon may occur in which data stored in the memory becomes invalid due to external neutron or alpha rays, deterioration of internal elements, etc. Therefore, an error-correcting code (hereinafter referred to as ECC) is used to correct error information when data is read from the memory (for example, see Patent Documents 1 to 3). Error correction is performed in the following steps: error detection information called a check code (sometimes called a check bit or check byte) is generated, the check code is added to the data, the data is stored in the memory, and when the data is read, information indicating the correction location is generated using the check code, and the correction is performed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2016-530655 [Patent Document 2] JP 2014-140111 A [Patent Document 3] JP 2013-143118 A Summary of the Invention [Problem to be solved by the invention]

[0004] ECC has a limited correction capability, and if the failure tendency and the ECC protection range do not match, it may not be effective. However, because the failure tendency of memory cannot be known in advance, it is not possible to design an optimal ECC. Therefore, it is possible to add multiple types of ECC check codes to the data and switch the check code to be used according to the failure tendency during operation, but the number of check codes increases, and the ratio of the check code length to the data length increases, which reduces the data encoding efficiency.

[0005] In one aspect, the present invention aims to provide a storage device and a control method for the storage device that are capable of performing error correction compatible with a plurality of types of ECC with a relatively small number of check codes. [Means for solving the problem]

[0006] In one embodiment, a storage device is provided that has a memory and a memory control unit that, when writing data to the memory, generates a first check code common to each of the multiple types of error correcting codes from the data based on a correlation between the multiple types of error correcting codes, adds the first check code to the data and writes it to the memory, and, when reading the data from the memory, converts the first check code into a second check code based on one of the multiple types of error correcting codes, and performs error correction using the second check code.

[0007] Also, in one embodiment, a method for controlling a storage device is provided. Effect of the Invention

[0008] In one aspect, the present invention is capable of performing error correction compatible with a plurality of types of ECC using a relatively small number of check codes. [Brief description of the drawings]

[0009] [Figure 1] 1 illustrates an example of a storage device and a method of controlling the storage device according to a first embodiment; [Diagram 2]FIG. 13 illustrates an example of a storage device according to a second embodiment. [Diagram 3] 11 is a flowchart showing the flow of a write process according to a control method of a storage device of a comparative example. [Figure 4] 11 is a flowchart showing the flow of a read process according to a control method of a storage device of a comparative example. [Diagram 5] 11A and 11B are diagrams illustrating a number of cases of error correction by ECC in the control method of the storage device of the comparative example. [Figure 6] 13 is a flowchart showing the flow of a write process according to a control method for a storage device according to a second embodiment. [Figure 7] 13 is a flowchart showing the flow of a read process according to a control method of a storage device according to a second embodiment. [Figure 8] FIG. 13 is a diagram showing an example in which a common PCB is used among three correction logics (part 1). [Figure 9] FIG. 13 is a diagram showing an example of using a common PCB among three correction logics (part 2). [Figure 10] FIG. 13 is a diagram illustrating an example of switching of correction logic. [Figure 11] 13 is a flowchart showing the flow of an example of a PCB generation process. [Figure 12] FIG. 2 is a diagram illustrating an example of a check matrix for two types of block correcting codes. [Figure 13] 1A to 1C are diagrams illustrating examples of calculation of check codes in two types of block correcting codes. [Figure 14] FIG. 13 is a diagram illustrating an example of correlation between check codes in two types of block correcting codes. [Figure 15] 1A to 1C are diagrams illustrating examples of calculation of check codes in two types of block correcting codes. [Figure 16] FIG. 13 is a diagram illustrating an example of correlation between check codes in two types of block correcting codes. [Figure 17] 13A and 13B are diagrams illustrating an example of a check matrix and an example of calculating check bytes when a Reed-Solomon code and a 1-bit correcting code are combined. [Figure 18]1A and 1B are diagrams illustrating an example of a check matrix of a Reed-Solomon code and an example of calculating check bytes. [Figure 19] 1 is a diagram illustrating an example of correlation between check codes in two types of correcting codes including a Reed-Solomon code. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, an embodiment of the invention will be described with reference to the drawings. (First embodiment) FIG. 1 illustrates an example of a storage device and a method of controlling the storage device according to the first embodiment.

[0011] The storage device 10 of the first embodiment includes a memory 11 and a memory control unit 12 . Various types of nonvolatile memories or various types of volatile memories are used as the memory 11. Examples of nonvolatile memories include flash memories, MRAMs (Magneto-resistive Random Access Memory), and FeRAMs (Ferroelectric Random Access Memory), while examples of volatile memories include DRAMs (Dynamic Random Access Memory).

[0012] The memory control unit 12 is a controller that controls writing of data to the memory 11 and reading of data from the memory 11. The memory control unit 12 may be a memory access controller included in a processor such as a CPU (Central Processing Unit) or a DSP (Digital Signal Processor). The memory control unit 12 performs the following processes at the time of writing and reading.

[0013] The memory control unit 12 generates a check code common to each of the multiple types of ECCs from the data based on the correlation between the multiple types of ECCs when writing data to the memory 11. As the multiple types of ECCs, for example, multiple types of block correction codes with different block sizes, Reed-Solomon codes, BCH codes, etc. can be used.

[0014] For example, when there is a correlation in which all the check codes of the second type of ECC can be converted from the check codes of the first type of ECC, the check codes of the first type of ECC can be used as a common check code. Also, when there is a correlation in which a part of the check codes of the second type of ECC can be converted from the check codes of the first type of ECC, a common check code that combines the check codes of the first type of ECC and the check codes of the second type of ECC that cannot be converted can be used. Hereinafter, the common check code may be called a PCB (Pseudo Check Bit). A more specific example of generating a PCB will be described in the second embodiment described later.

[0015] The memory control unit 12 adds the PCB to the data and writes it into the memory 11 . On the other hand, when reading data from the memory 11, the memory control unit 12 converts the PCB into a check code based on one of a plurality of types of error correction codes, and performs error correction using the check code.

[0016] The memory control unit 12 converts the PCB into a check code based on a conversion formula used when the PCB was generated, etc. For example, when the PCB is a first type of ECC check code, and a conversion formula for converting the first type of ECC check code into a second type of ECC check code is obtained, the PCB is converted into the second type of ECC check code using the conversion formula.

[0017] The location of the error is found from information called a syndrome, which is calculated by the matrix product of a check matrix (to be described later) and a column vector based on the read data and the check code obtained by conversion.

[0018] FIG. 1 shows an example of a process performed by the memory control unit 12 (a method of controlling the storage device 10). In a write process, the memory control unit 12 selects multiple types of ECC, generates a PCB from the received data, adds it to the data, and writes it to the memory 11. In a read process, if abnormal data (data containing an error) and a PCB are read, the memory control unit 12 converts the PCB into, for example, a check code of a first type of ECC. Then, the memory control unit 12 detects errors using the check code and corrects the detected errors.

[0019] However, if the error cannot be corrected by the first type of ECC check code, the memory control unit 12 converts the PCB to a second type of ECC check code. The memory control unit 12 then uses the check code to detect errors and correct the detected errors. In the example of FIG. 1, when the second type of ECC check code is used, the errors are corrected and normal data is obtained.

[0020] According to the storage device 10 described above, a common check code (PCB) based on the correlation between multiple types of ECCs is added to data and written, and when reading, the PCB is converted to one of the check codes of the multiple types of ECCs. This makes it possible to correct errors corresponding to multiple types of ECCs without adding the check codes of the multiple types of ECCs to the data in a format in which they are directly linked. In other words, it is possible to correct errors corresponding to multiple types of ECCs with a relatively small number of check codes.

[0021] (Second embodiment) Next, a storage device and a control method thereof according to a second embodiment will be described. FIG. 2 illustrates an example of a storage device according to the second embodiment.

[0022] The storage device 20 of the second embodiment includes a memory 21 and a CPU 22 . As the memory 21, for example, various non-volatile memories or various volatile memories as described above are used.

[0023] The CPU 22 includes a secondary cache 22a and a memory access controller 22b. Other components of the CPU 22 are not shown in the figure. In the secondary cache 22a, data to be written to the memory 21 and data read from the memory 21 are temporarily stored.

[0024] The memory access controller 22b controls writing of data to the memory 21 and reading of data from the memory 21, and also has a function of generating a PCB and a function of performing error detection and error correction.

[0025] The memory access controller 22b includes a check code generating unit 22b1 and an error correcting unit 22b2. When writing data to the memory 21, the check code generating unit 22b1 generates the aforementioned PCB, which is a check code common to each of the multiple types of ECCs, from the data based on the correlation between the multiple types of ECCs. The PCB is added to the data and written to the memory 21.

[0026] When data is read from the memory 21, the error correction unit 22b2 converts the PCB added to the data into a check code based on one of a plurality of types of ECC, and performs error correction using the check code.

[0027] In the example of FIG. 2, the error correction unit 22b2 includes correction units 22b2a, 22b2b, and 22b2c. The correction unit 22b2a converts the PCB into a check code based on a first type of ECC and performs error correction using the check code. If the correction unit 22b2a cannot perform error correction, the correction unit 22b2b converts the PCB into a check code based on a second type of ECC and performs error correction using the check code. If the correction units 22b2a and 22b2b cannot perform error correction, the correction unit 22b2c converts the PCB into a check code based on a third type of ECC and performs error correction using the check code.

[0028] The number of applicable ECC types is not limited to three, but may be two, or four or more. Next, before describing the control method and effects of the storage device 20 of the second embodiment, a control method of a storage device of a comparative example will be described.

[0029] (Comparative Example) The control method of the storage device of the comparative example shown below is a method in which, in order to reduce the number of check codes added to data, check codes based on one type of ECC are added to the data, and if error correction is not possible, the data is rewritten after switching to a check code based on a different type of ECC. In other words, if error correction is not possible, a check code generated by a different type of error correction logic is added to the data and the data is rewritten.

[0030] FIG. 3 is a flowchart showing the flow of a write process according to the control method of the storage device of the comparative example. FIG. 4 is a flowchart showing the flow of a read process according to the control method of the storage device of the comparative example.

[0031] FIG. 5 is a diagram for explaining a number of cases of error correction by ECC in the control method of the storage device of the comparative example. As shown in FIG. 3, in the memory write process, the storage device of the comparative example determines whether or not memory write has started, for example, by receiving a memory write command (step S10), and repeats the process of step S10 until it is determined that memory write has started.

[0032] When it is determined that memory writing has started, the storage device of the comparative example receives data (step S11), generates a check code based on one type of ECC (step S12), and writes the data to the memory by adding the check code (step S13), thereby completing the memory writing process.

[0033] As shown in FIG. 4, in the memory read process, the storage device of the comparative example determines whether or not memory read has started, for example, by receiving a memory read command (step S20), and repeats the process of step S20 until it is determined that memory read has started.

[0034] When it is determined that memory reading has started, the storage device of the comparative example reads data and a check code added to the data from the memory (step S21).Then, the storage device of the comparative example generates information indicating a correction location of the data, called a syndrome, from the check code (step S22), and performs error correction based on the generated syndrome (step S23).

[0035] C1 in Fig. 5 shows a case where data is successfully corrected by error correction. "CB generation logic 1" in Fig. 5 shows generating a check code "CB1" based on a first type of ECC. If an abnormality occurs in the data while it is stored in memory as in Fig. 5 (if an error occurs), a syndrome "Syn1" is generated based on "CB1" by "syndrome generation 1", which is a syndrome generation process. Then, "correction logic" is applied based on "Syn1" to perform error correction.

[0036] If error correction only supports one type of ECC, the system will shut down if an error cannot be corrected, as in the case of C2. Therefore, when an error cannot be corrected by error correction based on the first type of ECC, as in the case of C3, the storage device of the comparative example issues a rewrite request.

[0037] In the example of FIG. 5, a check code "CB2" is generated from the data received again based on the second type of ECC by "CB generation logic 2", and when reading, "Syn2" is generated based on "CB2" by "syndrome generation 2". Then, "correction logic" is applied based on "Syn2" to perform error correction. In the example of FIG. 5, the error cannot be corrected even by error correction based on the second type of ECC, and the storage device of the comparative example requests a rewrite. A check code "CB3" is generated from the data received again based on the third type of ECC by "CB generation logic 3", and when reading, "Syn3" is generated based on "CB3" by "syndrome generation 3". Then, "correction logic" is applied based on "Syn3" to perform error correction. In the example of FIG. 5, the error is corrected by error correction based on the third type of ECC, and normal data is obtained.

[0038] In order to perform processing such as C3 in FIG. 5, the memory device of the comparative example, as shown in FIG. 4, determines whether the error is not resolved after the processing of step S23 and whether there is another applicable correction logic (meaning correction using another type of ECC) (step S24).

[0039] The storage device of the comparative example ends the read process when it determines that the error has been eliminated, or when it determines that the error has not been eliminated and there is no other applicable correction logic. When it determines that the error has not been eliminated and there is no other applicable correction logic, the storage device of the comparative example issues a rewrite request and repeats the process from step S10 in Fig. 3. In this case, in the process of step S12, a check code based on another correction logic is generated.

[0040] In the control method of the memory device of the comparative example described above, when selecting correction logic with sufficient correction capability and switching between them, it becomes necessary to rewrite data to the memory, as shown in Figure 5, which may have a negative impact on system performance.

[0041] (Method of controlling a storage device according to a second embodiment) FIG. 6 is a flowchart showing the flow of a write process according to the control method of the storage device according to the second embodiment.

[0042] In the memory write process, the memory access controller 22b of the storage device 20 determines whether or not memory write has started, for example, by receiving a memory write command (step S30). The memory access controller 22b repeats the process of step S30 until it is determined that memory write has started.

[0043] When it is determined that memory writing has started, the check code generating unit 22b1 of the memory access controller 22b receives data to be written from the secondary cache 22a (step S31) and generates a PCB from the received data (step S32). An example of the PCB generation process will be described later.

[0044] The memory access controller 22b adds the PCB to the data and writes it to the memory 21 (step S33), and ends the memory write process. FIG. 7 is a flowchart showing the flow of a read process according to the control method of the storage device according to the second embodiment.

[0045] In the memory read process, the memory access controller 22b determines whether or not memory read has started, for example, by receiving a memory read command (step S40), and repeats the process of step S40 until it is determined that memory read has started.

[0046] When it is determined that memory reading has started, the memory access controller 22b reads data and a PCB added to the data from the memory 21 (step S41). Then, the error correction unit 22b2 of the memory access controller 22b converts the PCB into a check code based on one of multiple types of ECC (multiple error correction logics) (step S42). Then, the error correction unit 22b2 generates a syndrome using the check code (step S43) and performs error correction based on the generated syndrome (step S44).

[0047] The error correction unit 22b2 determines whether the error is not eliminated and there is another applicable correction logic (step S45). When the error correction unit 22b2 determines that the error has been eliminated, or when the error has not been eliminated and there is no other applicable correction logic, the read process ends. When the error correction unit 22b2 determines that the error has not been eliminated and there is no other applicable correction logic, the process from step S42 is repeated. In this case, in the process of step S42, the PCB is converted into a check code based on another correction logic.

[0048] 8 and 9 are diagrams showing an example in which a common PCB is used among three correction logics. 8, the check code generation unit 22b1 converts the check codes "CB1" to "CB3" generated by three types of "CB generation logic 1" to "CB generation logic 3" into a common PCB by conversion using "conversion logic 1" to "conversion logic 3." The PCB is added to the data and stored in the memory 21.

[0049] Then, at the time of reading, the error correction unit 22b2 converts the common PCB into one of "CB1" to "CB3" using one of "inverse conversion logic 1" to "inverse conversion logic 3", and generates "Syn1" to "Syn3" using "syndrome generation 1" to "syndrome generation 3".

[0050] Incidentally, "CB generation logic 1" to "CB generation logic 3" and "conversion logic 1" to "conversion logic 3" can be regarded as a single entity and expressed as "PCB generation logic" as shown in Fig. 9. Also, "inverse conversion logic 1" to "inverse conversion logic 3" and "syndrome generation 1" to "syndrome generation 3" can be regarded as a single entity and expressed as "conversion syndrome generation 1" to "conversion syndrome generation 3" as shown in Fig. 9.

[0051] FIG. 10 is a diagram showing an example of switching of correction logic. In the write process, the check code generating unit 22b1 generates, for example, a PCB common to three correction logics from the data by the “PCB generation logic.” The PCB is added to the data and stored in the memory 21.

[0052] 10, if an abnormality occurs in the data (if an error occurs) while the data is stored in the memory, the correction unit 22b2a of the error correction unit 22b2 converts PCB to "CB1" by "conversion syndrome generation 1". Furthermore, the correction unit 22b2a generates "Syn1" by performing a matrix product of a check matrix (to be described later) and the read data and a column vector by "CB1" by "conversion syndrome generation 1". Then, the correction unit 22b2a performs error correction by "correction logic" based on "Syn1" (error correction by the first type of ECC).

[0053] As in the example of Fig. 10, when an error cannot be corrected by error correction using the first type of ECC, the error correction unit 22b2 switches syndrome generation logic, and the correction unit 22b2b converts PCB to "CB2" using "conversion syndrome generation 2". Furthermore, the correction unit 22b2b generates "Syn2" using "conversion syndrome generation 2" by a matrix product of a check matrix (to be described later) and the read data and a column vector using "CB2". Then, the correction unit 22b2b performs error correction (error correction using the second type of ECC) using "correction logic" based on "Syn2".

[0054] As in the example of FIG. 10, if the error cannot be corrected even by the error correction using the second type of ECC, the error correction unit 22b2 switches the syndrome generation logic, and the correction unit 22b2c converts PCB to "CB3" using "conversion syndrome generation 3". Furthermore, the correction unit 22b2c generates "Syn3" using "conversion syndrome generation 3" by performing a matrix product of a check matrix (to be described later) and the read data and a column vector using "CB3". Then, the correction unit 22b2c performs error correction (error correction using the third type of ECC) using "correction logic" based on "Syn3". In the example of FIG. 10, the error is corrected by error correction based on the third type of ECC, and normal data is obtained.

[0055] According to the storage device 20 of the second embodiment described above, a common check code (PCB) based on the correlation between multiple types of ECC is added to data and written, and when reading, the PCB is converted to one of the check codes of the multiple types of ECC. This makes it possible to perform error correction corresponding to multiple types of ECC without adding the check codes of the multiple types of ECC to the data in a format in which they are directly linked. In other words, it is possible to perform error correction corresponding to multiple types of ECC with a relatively small number of check codes.

[0056] Furthermore, when switching the type of ECC (correction logic) to be used as in the above comparative example, rewriting is not required as shown in FIG. (Example of PCB generation) An example of PCB generation will be described below.

[0057] FIG. 11 is a flowchart showing the flow of an example of a PCB generation process. The check code generating unit 22b1 selects a plurality of types of ECC (step S50). The plurality of types of ECC may include, for example, a plurality of types of block correcting codes with different block sizes, a Reed-Solomon code, a BCH code, and the like.

[0058] Then, the check code generating unit 22b1 creates a generator matrix so that the check codes based on the multiple types of ECCs are correlated with each other (step S51). An example of the generator matrix will be described later. The check code generating unit 22b1 converts the correlated portion between different check codes into a common code A (step S52), and connects the non-correlated portion B between different check codes to A to generate a PCB (step S53).

[0059] (Example of application to two types of block correcting codes (part 1)) First, for simplicity, an example will be shown in which two types of block correcting codes are applied to 12-bit data (data0 to data11).

[0060] Of the two types of block correcting codes, the correction logic of one block correcting code (first correction logic) divides 12-bit data into 3 blocks of 4 bits each and corrects 1-bit errors in each block. The correction logic of the other block correcting code (second correction logic) divides 12-bit data into 2 blocks of 6 bits each and corrects 1-bit errors in each block.

[0061] FIG. 12 is a diagram showing an example of a check matrix for two types of block correcting codes. H1 is an example of a check matrix when the first correction logic is used, and H2 is an example of a check matrix when the second correction logic is used. H1 and H2 are matrices in which a 12-row x 12-column unit matrix (I) from the 13th to the 24th columns is concatenated with a matrix (A1, A2) from the 1st to the 12th columns.

[0062] The generator matrix for generating the check code has the transposed matrix of A1 and A2 as columns 13 to 24, and columns 1 to 12 as I. However, the check code can also be expressed using A1 and A2 as shown in Figure 13. For this reason, A1 and A2 can also be called generator matrices (or parts thereof).

[0063] FIG. 13 is a diagram showing an example of calculation of check codes in two types of block correcting codes. cb a0 ~cb a11 is the check code obtained using A1, and cb b0 ~cb b11 is the check code obtained using A2.

[0064] FIG. 14 is a diagram showing an example of correlation between check codes in two types of block correcting codes. cb a0 ~cb a11 Let cb be a column vector of a If we write the column vector data0 to data11 as data, then cb a , cb a It can be calculated using the formula: =A1·data.

[0065] Since A1 is a square matrix, the inverse matrix A1 -1 is required. b0 ~cb b11 Let cb be a column vector of b If we write it as cb b , cb a In contrast, cb b =A2 A1 -1 A1 data=A2 A1 -1 ·cb a , and cb a From cb b can be converted to

[0066] For this reason, the check code generating unit 22b1 a By adding only the PCB to the data and writing it to the memory 21, when reading, the error correction unit 22b2 calculates cb a From cb b can be converted to .

[0067] For example, if data5 and data6 are erroneous, then in H1 of FIG. 12, there will be two errors in the same block, and correction will be impossible. In that case, the error correction unit 22b2 aFrom cb b and performing error correction based on H2 in FIG. 12, it becomes a state in which there is one error in one block, which can be corrected.

[0068] In this way, the data is a By adding the above and writing it to the memory 21, it becomes possible to protect the data with two types of correction logic. Also, cb a (cb a0 ~cb a11 ) needs to be added to the data, so cb a0 ~cb a11 and cb b0 ~cb b11 This makes it possible to reduce the number of check codes (the number of check bits) compared to concatenating the above and adding them to the data, thereby preventing a decrease in data coding efficiency.

[0069] (Example of application to two types of block correcting codes (part 2)) Next, an example will be shown in which two types of block correcting codes are applied to 24-bit data (data0 to data23).

[0070] Of the two types of block correcting codes, the correction logic using one block correcting code (third correction logic) divides 24-bit data into three 8-bit blocks and corrects one-bit errors in each block. The correction logic using the other block correcting code (fourth correction logic) divides 24-bit data into two 12-bit blocks and corrects one-bit errors in each block.

[0071] FIG. 15 is a diagram showing an example of calculation of check codes in two types of block correcting codes. A3 is a matrix obtained by removing the unit matrix portion from the parity check matrix when the third correction logic is used, and A4 is a matrix obtained by removing the unit matrix portion from the parity check matrix when the fourth correction logic is used.

[0072] The check code can be expressed as shown in FIG. 15 using A3 and A4. cb A0 ~cb A11 is the check code obtained using A3, and cb B0 ~cb B11 is the check code obtained using A4.

[0073] Unlike the first application example, A3 and A4 are not square matrices, so they cannot be transformed using an inverse matrix. A (cb A0 ~cb A11 ) and cb B (cb B0 ~cb B11 A PCB is generated by concatenating the correlated and non-correlated parts between the vectors (column vectors of

[0074] In Figure 15, from the similar parts of A3 and A4, cb A and cb B has the following relationship: As shown in Figure 15, cb B0 is cb A0 and cb A4 cb B1 is cb A1 and cb A5 cb B2 is cb A2 and cb A4 cb B3 is cb A3 and cb A5 It is expressed as the exclusive OR of cb B6 is cb A6 and cb A8 cb B7 is cb A7 and cb A9 cb B8 is cb A6 and cb A10 cb B9 is cb A7 and cb A11 It is expressed as the exclusive OR of

[0075] FIG. 16 is a diagram showing an example of correlation between check codes in two types of block correcting codes. As above cb B0 ~cb B11 Of these, the above 8 bits are cb A Therefore, cb A The correlation part, cb B0 ~cb B11 Of the 8 bits other than the above (cb B4 , cb B5 , cb B10 , cb B11 ) is treated as the non-correlated part, and a PCB is generated by connecting these.

[0076] The uncorrelated part is only 4 bits, so cb A0 ~cb A11 and cb B0 ~cb B11 This makes it possible to reduce the number of check codes (the number of check bits) compared to concatenating the above and adding them to the data, thereby preventing a decrease in data coding efficiency.

[0077] The check code generating unit 22b1 adds a PCB as shown in FIG. 16 to the data and writes it to the memory 21. When reading, the error correcting unit 22b2 b Of these, cb B4 , cb B5 , cb B10 , cb B11 Other than the above formula, cb A It can be found from.

[0078] In this way, by adding a PCB as shown in FIG. 16 to the data and writing it to the memory 21, it becomes possible to protect the data using two types of correction logic. (Example of application to Reed-Solomon codes) Next, a case where a Reed-Solomon code and a one-bit correcting code are applied as two types of ECC to be combined will be described.

[0079] FIG. 17 is a diagram showing an example of a check matrix and an example of calculation of check bytes when a Reed-Solomon code and a 1-bit correcting code are combined. FIG. 17 shows an example of a check matrix with 3 rows and 8 columns. α is F 256 (a set with 256 elements). That is, we divide the 256 elements into α x The check matrix is ​​multiplied by the 8-byte data (data0 to data7) to generate a 3-byte check byte (CB A0 ~CB A2 ) is obtained.

[0080] CB A1 is a check code for 1-bit correcting code for even-numbered bytes, and CB A2 is a check code for 1-bit correcting code for odd-numbered bytes. FIG. 18 is a diagram showing an example of a check matrix of a Reed-Solomon code and an example of calculating check bytes.

[0081] FIG. 18 shows an example of a check matrix of a Reed-Solomon code with 2 rows and 8 columns. The matrix product of this check matrix and 8 bytes of data (data0 to data7) produces a 2-byte check byte (CB B0 ~CB B1 ) is obtained.

[0082] Here, C.B. B0 ~CB B1 CB A0 ~CB A2 That is, as shown in Figure 18, CB B0 =CB A0 And C.B. B1 CB A1 and C.B. A2 This can be expressed as the exclusive OR of

[0083] FIG. 19 is a diagram showing an example of correlation between check codes in two types of correcting codes including a Reed-Solomon code. As mentioned above, CB B0 ~CB B1 CB A0 ~CB A2 Therefore, the check code generating unit 22b1 can obtain the check code from the CB A0 ~CB A2The PCB consisting of the above is added to the data and written into the memory 21.

[0084] In addition, in FIG. 19, the check code (cb x ) is CB A1 and the check code for the 1-bit correcting code for odd-numbered bytes (cb y ) is CB A2 It has been shown that.

[0085] In this way, by adding a PCB as shown in FIG. 19 to the data and writing it to the memory 21, the data can be protected by two types of ECC, 1-bit correcting code and Reed-Solomon code. Also, C.B. A0 ~CB A2 Since only the data needs to be added, CB A0 ~CB A2 and C.B. B0 ~CB B1 This makes it possible to reduce the number of check codes (the number of check bits) compared to concatenating the above and adding them to the data, thereby preventing a decrease in data coding efficiency.

[0086] While one aspect of the storage device and the control method for the storage device of the present invention has been described above based on the embodiment, these are merely examples and the present invention is not limited to the above description. For example, as a combination of multiple types of ECC, a combination of a BCH code and a Reed-Solomon code may be used. [Explanation of symbols]

[0087] 10 Storage device 11. Memory 12 Memory control section

Claims

1. Memory, a memory control unit which, when writing data to the memory, generates a first check code common to each of the plurality of types of error correction codes from the data based on a correlation between the plurality of types of error correction codes, adds the first check code to the data, and writes the data to the memory; and, when reading the data from the memory, converts the first check code into a second check code based on any one of the plurality of types of error correction codes, and performs error correction using the second check code; A storage device having:

2. When an error is not eliminated by correcting the first check code using the second check code based on the first error correcting code of the plurality of types of error correcting codes, the memory control unit converts the first check code into a third check code based on the second error correcting code of the plurality of types of error correcting codes, and performs error correction using the third check code. The storage device according to claim 1 .

3. 3. The storage device according to claim 2, wherein, when the entirety of the third check code can be converted from the second check code, the first check code is the second check code.

4. 3. The storage device according to claim 2, wherein, when a portion of the third check code can be converted from the second check code, the first check code is generated by concatenating the third check code other than the portion to the second check code.

5. The storage device according to claim 2 , wherein the first error correcting code or the second error correcting code is a block correcting code, a Reed-Solomon code, or a BCH code.

6. The memory control unit generating a first check code common to each of the plurality of types of error correcting codes from the data based on a correlation between the plurality of types of error correcting codes when writing the data to the memory; adding the first check code to the data and writing the data to the memory; When reading the data from the memory, the first check code is converted into a second check code based on any one of the plurality of types of error correcting codes, and error correction is performed using the second check code. A method for controlling a storage device.

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