Radar Signal Processing

Abstract

To provide a method of processing radar signals.SOLUTION: According to an embodiment, a method of processing a radar signal comprises adjusting a processing clock signal, where the processing clock signal determines an operation period of a signal processing circuit. The processing clock signal is determined based on a time window, where the size of the time window is determined based on the maximum time available for processing a portion of the radar signal, and the end of the time window is determined such that it does not occur during an active transmission period of a radar system.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] Embodiments of the present invention relate to radar applications, and in particular to an efficient method for processing radar signals acquired by at least one radar sensor (e.g., via at least one antenna), where the processed radar signals in this case specifically refer to radar signals received at the sensor or antenna. [Background technology]

[0002] Several types of radar are used in automobiles for different applications. For example, radar can be used for blind spot detection (parking assistance, pedestrian protection, oncoming traffic), collision mitigation, lane change assistance, and adaptive cruise control. Different use case scenarios for radar equipment can involve different directions (e.g., rear, side, forward), varying angles (e.g., azimuth), and / or different distances (short, medium, or long). For example, adaptive cruise control may utilize azimuth angles as high as ±18 degrees, and the radar signal is emitted from the front of the automobile, allowing a detection range of hundreds of meters.

[0003] A radar source emits a signal and a sensor detects the reflected signal. A frequency shift between the emitted signal and the detected signal (e.g., based on a moving car emitting a radar signal) can be used to obtain information based on the reflection of the emitted signal. Front-end processing of the signal acquired by the sensor may include a Fast Fourier Transform (FFT), resulting in a signal spectrum, i.e., the frequency distribution of the signal. The amplitude of this signal can indicate the amount of echo, and its peaks can represent targets that need to be detected and used for further processing (e.g., adjusting the vehicle speed based on another car traveling ahead).

[0004] Various types of output are available from the radar processor, such as commands to the controller, objects or object lists to be post-processed by at least one controller, and at least one FFT peak to be post-processed by at least one controller. The use of the FFT peaks allows for high performance post-processing. Summary of the Invention [Problem to be solved by the invention]

[0005] A particular problem is that the high speed processing performed by the signal processing unit (SPU) can cause jumps in the power supply current that can disrupt the radar unit, especially during transmission via the radar antenna.

[0006] The problem to be solved is to overcome the above mentioned disadvantages and in particular to provide a solution for efficient processing of signals in a radar system. [Means for solving the problem]

[0007] This problem is solved according to the features of the independent claims. Further embodiments result from the dependent claims.

[0008] Each of the examples proposed herein may be specifically based on at least one of the following solutions: Specifically, a combination of the following features may be utilized to reach the desired result: Features of this method may be combined with any features of this device, apparatus or system, or any features of this device, apparatus or system may be combined with features of this method.

[0009] 1. A method for processing a radar signal, the method comprising: - adjusting a processing clock signal, the processing clock signal determining an operation period of the signal processing unit, the processing clock signal being determined based on a time window; - the size of the time window is determined based on the maximum time available to process a portion of the radar signal; A method is proposed in which the end of the time window is determined such that it does not occur during the active transmission part of the radar system.

[0010] This allows the signal processing to be carried out at a variable speed thanks to the adjusted processing clock signal. It is therefore possible to provide time windows for subsequent processing with no or very little gap between them. Without gaps, there is no disturbance of on / off switching during the time windows, and therefore no disturbances transmitted through the power lines.

[0011] In other words, the signal processing duration is continuously spread out, consuming a single DC power supply current, ensuring seamless operation of the radar system (instead of the current jumps that would otherwise occur by switching the SPU on and off).

[0012] In addition to only mitigating the detrimental effects of load jumps, the solutions presented herein can be used to efficiently distribute the power consumed during an acquisition period. For example, instead of using an SPU that runs at 100% capacity 50% of the time, the SPU can run at 50% capacity for the entire duration of the acquisition period. This would also avoid reaching high current consumption loads.

[0013] According to one embodiment, the start of the time window is determined such that it does not occur during the active transmission portion of the radar system.

[0014] According to one embodiment, the processing clock signal is adjusted based on the clock signal via a divided clock divider.

[0015] A divide-by clock divider is also known as a frequency divider, clock divider, scaler, or prescaler. It has the formula: out =f in / n, the input frequency f in Based on the output frequency f out where n is an integer.

[0016] One option for this is to be implemented by a programmable divide-by clock divider configured to meet the requirements as defined above. Such configuration can be done once or several times.

[0017] The configuration of the divided clock divider can even be done on the fly, ie at run time.

[0018] According to one embodiment, the portion of the radar signal includes a transmit portion of the radar signal and / or a receive portion of the radar signal, each of which specifically includes a frequency ramp.

[0019] The part of the radar signal that undergoes said processing may in particular be the transmission part as described herein. The transmission part may be associated with a radar chip (or any radar unit) that emits and receives radar signals, in particular radar signals of various frequencies. During the time that the radar signals are emitted and / or received by the radar unit, a power supply transfers electrical energy to the radar unit and the signal processing unit. If the signal processing unit is switched on (enabled) or switched off (disabled) during the transmission part of the radar signal, this will result in a load jump and therefore disrupt the transmission / reception of the radar signal by the radar unit and therefore degrade the overall perception of the radar system.

[0020] As proposed, if no such load jumps are present during the transmit or receive portions of the radar signal, such disturbances can be reduced or avoided.

[0021] According to one embodiment, adjusting the processing clock signal comprises reducing or increasing the cycle rate at which the signal processing unit executes.

[0022] Therefore, the speed at which the SPU runs can be adjusted by the divided clock divider.

[0023] According to one embodiment, adjusting the processing clock signal comprises: - gradually increasing the frequency at the beginning of the time window until it reaches the frequency of the processing clock signal; and / or - gradually decreasing the frequency until, at the end of the time window, it reaches the frequency of the processing clock signal; Includes at least one of the following:

[0024] Therefore, the solution is directed to, for example, ramping up and / or down the frequency at which the SPU is driven. This is particularly useful for the start of the first time window (of many adjacent time windows) and at the end of a time window (that does not have an adjacent time window of operation for the SPU). Such a measure effectively reduces any voltage overshoot or undershoot at the power supply, thus mitigating any potential load jumps.

[0025] The gradual increase may be done by ramping up the frequency towards a processing frequency, which may be a maximum frequency for driving the SPU. It could also be a frequency less than the maximum frequency. This ramp up may be achieved in discrete steps, which may have the same or different length / height. The same is true for the ramp down, where the ramp up and ramp down may utilize the same or different ramp patterns.

[0026] There is also provided a radar system, a receiver configured to receive a radar signal via an antenna; a processing unit, - configured to adjust a processing clock signal, the processing clock signal determining an operation period of the processing unit, the processing clock signal being determined based on a time window; - the size of the time window is determined based on the maximum time available to process a portion of the radar signal; a processing unit for determining the end of the time window such that it does not occur during an active transmission portion of the radar system; A radar system is provided, comprising:

[0027] According to one embodiment, the processing unit is or comprises a signal processing unit.

[0028] Also proposed is a vehicle comprising at least one radar system as described herein.

[0029] Furthermore, a computer program product is provided, which is directly loadable into the memory of a digital processing device and which comprises software code portions for performing each of the steps of the methods described herein.

[0030] The embodiments are shown and illustrated with reference to the drawings. The drawings serve to illustrate basic principles. Therefore, only those aspects necessary for understanding the basic principles are shown. The drawings are not to scale. In the drawings, the same reference numbers represent similar features. [Brief description of the drawings]

[0031] [Figure 1] 1 shows an exemplary diagram including curves of high frequency (HF) transmissions of a radar system. [Diagram 2] 1 shows a schematic radar system comprising (among other things) a microcontroller (MCU: Microcontroller Unit), a signal processing unit (SPU), a memory, a central processing unit (CPU), and a scalable clock control unit. [Diagram 3] 1 shows an exemplary diagram including curves of HF transmission of a radar system with improved signal processing by an SPU. [Figure 4] 1 shows a schematic diagram visualizing positive and negative voltage load jumps when an SDU is switched on and off. [Diagram 5] 1 shows an exemplary diagram in which the frequency for operating a module or SPU is gradually ramped up and down. [Figure 6] 5 shows a schematic diagram with reduced positive voltage load jumps and reduced negative voltage load jumps compared to the scenario shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0032] Due to the high performance of on-the-fly signal processing radar applications, high current load jumps can occur.

[0033] FIG. 1 shows an exemplary diagram including a curve of a high frequency (HF) transmission 101 of a radar system. The HF transmission 101 indicates a ramp including an active transmission portion 102 and an idle transmission portion 103. Thus, a radar signal may be transmitted during the active transmission portion 102 and a reflected radar signal may be processed during the idle transmission portion 103. Thus, after the active transmission portion 102 ends, signal processing 104 may start. The signal processing 104 may be performed by a signal processing unit of the radar system, which may include an active state 105 and an inactive state 106. At time t1, the signal processing unit changes from the inactive state 106 to the active state 105. The signal processing continues until time t2, at which time the signal processing unit returns to the inactive state 106 until time t3.

[0034] In this example, time t1 corresponds to the moment when the HF transmission 101 changes from an active transmission portion 102 to an idle transmission portion 103. The signal processing unit 104 is switched to an active state 105 and processes data. Such processing ends at time t2, and the signal processing unit 104 enters its inactive state 106. However, the change of the signal processing unit 104 from its active state 105 to its inactive state 106 results in a current jump 107 (also referred to herein as a "load jump") occurring during the portion of the active transmission 102 of the radar system, creating noise disturbances that violate the low noise requirements of the radar system.

[0035] Therefore, controlling the size and / or occurrence of load jumps becomes an important aspect to ensure low noise for high performance radar operation.

[0036] The general demand for high performance radar computing increases the total power consumption of the modules of the radar system, which results in higher currents and therefore a larger impact on load jumps when the modules are switched on and off.

[0037] Therefore, the examples described herein propose, inter alia, fine-grained control over the performance of signal processing duration and / or its speed.

[0038] FIG. 2 shows a schematic radar system comprising (among other things) a microcontroller 200 (MCU: Microcontroller Unit), a signal processing unit (SPU) 201, a memory 202, a central processing unit (CPU) 203, and a scalable clock control unit 204.

[0039] Scalable clock control unit 204 may be part of SPU 201 or it may be configured as a separate unit. SPU 201 may obtain a clock signal 206 (also referred to as a "module clock" or "clock"), or - alternatively - SPU 201 may generate such clock signal 206 by itself.

[0040] The scalable clock control unit 204 calculates a clock signal 206 into a processing clock signal 205 (also referred to as the "processing clock"), which allows the clock signal 206 to be adjusted in a flexible manner so that the detrimental effects of load jumps are reduced or even prevented.

[0041] The scalable clock control unit 204 can be realized as or it may include a divided clock divider, which generates a processing clock signal 205 based on a clock signal 206. The processing clock signal 205 can then be used for signal processing purposes.

[0042] The scalable clock control unit 204 allows fine-grained configuration of the processing clock signal 205 and thus the signal processing duration.

[0043] Thanks to the adjusted processing clock signal 205, the processing duration interval of the SPU 201 can be exactly within the time window, so that the transmission portion 102 is not interrupted, i.e., the processing interval does not end during such transmission portion 102.

[0044] Therefore, load jumps cannot adversely affect HF performance as shown in FIG.

[0045] Fig. 3 shows an exemplary diagram including a curve of a radar system's HF transmission 301. The HF transmission 301 indicates a ramp including an active transmission portion 302 and an idle transmission portion 303. Fig. 3 also shows a curve 304 of the radar system's SPU, said curve 304 including an active state 305 and an inactive state 306.

[0046] At time t 1 , the SPU changes from the inactive state 306 to the active state 305 , and at a subsequent time t 2 , it returns to the inactive state 306 .

[0047] However, at or about the same time t2 (without a significant gap), the signal processing unit goes back from the inactive state 306 to the active state 305. The same is repeated at time t3. This results in an optimized scenario with no load jumps (compared to the scenario shown in FIG. 1).

[0048] Therefore, the active transmission portion 302 falls exactly within the time window during which the SPU is in the active state 305 (in the example shown in FIG. 3, the time window is between t1 and t2 and between t2 and t3). This avoids load jumps during the transmission portion 302.

[0049] As an option, the time window may in particular be as long as the active transmission portion 302 and the inactive transmission portion 303. The time window in such an example ends / starts only at the time when the active transmission portion 302 ends and the inactive transmission portion 303 begins.

[0050] By utilizing the divided clock divider of the scalable control unit 204, any gap between two adjacent active states 305 can be minimized, thereby further reducing any load jumps.

[0051] Assuming that the signal processor runs at a maximum frequency that reaches 300 MHz, the duration of the processing task of the signal processor may reach 0.4T. Reducing the frequency to, for example, 180 MHz may increase the duration of the processing task to T. In this regard, T may be the time that allows two consecutive active states 305 to occur without having a (substantial) time gap. The division clock divider that sets the frequency of the signal processor may be configured to minimize such a gap. The duration T of the processing task may correspond to the time interval t2-t1 in FIG. 1.

[0052] 4 shows a schematic diagram visualizing yet another detrimental effect in existing radar solutions: the higher the overall computing performance, the higher the impact of positive voltage load jumps 401 and negative voltage load jumps 402 when such computing is enabled or disabled.

[0053] This can become significant if such voltage overshoots and / or voltage undershoots exceed the range or limits of the power supply concept, which can trigger functional safety alarms, resets, or the like, disrupting seamless operation of the radar system.

[0054] Therefore, the divided clock divider described above can be configured to provide an up-ramp and / or down-ramp sequence of the processing clock, allowing the module or SPU 201 to gradually ramp up to its full processing speed (or any higher speed short of the full speed) and gradually ramp down to a lower speed or a quiescent state.

[0055] This further reduces the deleterious effects of load jumps at the beginning and / or end of a processing cycle.

[0056] FIG. 5 shows that the frequency for operating the module or SPU 201 from time t1 to time t3 is a predetermined maximum frequency f max The module or SPU 201 gradually ramps up to this frequency fmax from time t3 to time t4. After time t4 the frequency is gradually ramped down to 0 until time t6. This allows, among other things, a gentle start and a gentle end to the processing cycle.

[0057] The ramps shown in FIG. 5 are primarily for illustrative purposes. The ramps may include more or fewer stages, and the ramps may be asymmetric, i.e., include a different number of stages that increase frequency compared to the number of stages used to decrease frequency. The ramps may have different sizes or shapes. The timing for each of the ramps may be the same or it may be different. Also, the ramps may be applied between two operating frequencies, and at least one operating frequency need not be zero.

[0058] Figure 6 shows a schematic diagram with reduced positive voltage load jumps 601 and reduced negative voltage load jumps 602 compared to the scenario shown in Figure 4. Thanks to the ramp concept shown in Figure 6, voltage overshoots and voltage undershoots are significantly reduced, thus avoiding compromising the power supply concept and thus the seamless operation of the radar system.

[0059] In one or more examples, each function described herein may be implemented at least in part in hardware, e.g., in a particular hardware component or processor. More generally, these techniques may be implemented in hardware, processors, software, firmware, or any combination thereof. When implemented in software, these functions may be stored or transmitted as one or more instructions or codes on a computer-readable medium and executed by a hardware-based processing unit. A computer-readable medium may be a computer-readable storage medium or a communication medium, etc., where a computer-readable storage medium corresponds to a tangible medium, such as a data storage medium, and a communication medium includes any medium that facilitates the transfer of a computer program from one place to another (e.g., according to a communication protocol). Thus, a computer-readable medium may generally correspond to (1) a non-transitory, tangible computer-readable storage medium, or (2) a communication medium, such as a signal or carrier wave. A data storage medium may be any available medium accessible by one or more computers or one or more processors to retrieve instructions, codes, and / or data structures for implementing the techniques described in this disclosure. The computer program product may include a computer-readable medium.

[0060] By way of example, and not limitation, such computer-readable storage media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage, flash memory, or any other medium operable to store desired program code in the form of instructions or data structures and accessible by a computer. Also, strictly speaking, any connection is referred to as a computer-readable medium, i.e., a computer-readable transmission medium. For example, when instructions are transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio waves, microwaves, etc., the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio waves, microwaves, etc., are included in the definition of media. However, it should be understood that computer-readable storage media and data storage media do not encompass connections, carrier waves, signals, or other transient media, but instead cover persistent, tangible storage media. As used herein, disk and disc encompass compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while discs reproduce data optically with a laser. Combinations of the above should also be included within the scope of computer readable media.

[0061] The instructions may be executed in one or more processors, such as one or more central processing units (CPUs), digital signal processors (DSPs), general-purpose microprocessors, application specific integrated circuits (ASICs), field programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuitry. Thus, as used herein, the term "processor" may refer to any of the above structures, or any other structure suitable for implementing the techniques described herein. Furthermore, in some aspects, the functionality described herein may be provided in dedicated hardware and / or software modules configured to perform encoding and decoding, or may be incorporated in the form of a complex codec. Additionally, the techniques may be fully embodied in one or more circuit or logic elements.

[0062] The techniques of the present disclosure may be implemented in a variety of devices or apparatuses, including a wireless handset, an integrated circuit (IC), or a set of ICs (e.g., a chipset). The present disclosure illustrates various components, modules, or units to highlight functional aspects of an apparatus configured to implement the techniques of the present disclosure, which do not necessarily require realization in separate hardware units. Rather, as described above, the various units may be combined in a single hardware unit or may be provided by a collection of interoperable hardware units including one or more processors as described above in combination with appropriate software and / or firmware.

[0063] Although various exemplary embodiments of the present invention have been disclosed, it will be apparent to one skilled in the art that various changes and modifications may be made to achieve some of the advantages of the present invention without departing from the spirit and scope of the present invention. Other components performing the same functions may be appropriately substituted, as will be apparent to one skilled in the art. It will be appreciated that features described with respect to a particular drawing may be combined with features of other drawings, even if this is not explicitly mentioned. Furthermore, the methods of the present invention may be achieved in an all-software implementation using appropriate processor instructions, or in a hybrid implementation that utilizes a combination of hardware and software logic to achieve the same results. Such modifications to the inventive concept are intended to be covered by the appended claims. [Explanation of symbols]

[0064] 101 High Frequency Transmission 102 Active Transmission Part 103 Idle transmission part 104 Signal Processing 105 Active 106 Inactivity 107 Current Jump 200 Microcontrollers 201 Signal Processing Unit 202 Memory 203 Central Processing Unit 204 Scalable Clock Control Unit 205 Processing Clock Signal 206 Clock Signal 301 HF transmission 302 Active Sending Part 303 Idle Send Part 305 Active 306 Inactive

Claims

1. 1. A method for processing a radar signal, comprising: - adjusting a processing clock signal, said processing clock signal determining an operating period of the signal processing unit, said processing clock signal being determined based on a time window; the size of the time window is determined based on a maximum time available to process a portion of the radar signal; A method in which the start and end of said time window are determined so as not to occur during an active transmission portion of the radar system.

2. 2. The method of claim 1, wherein the processing clock signal is adjusted based on a clock signal via a divided clock divider.

3. 3. The method of claim 1 or 2, wherein the portions of the radar signal include a transmit portion of the radar signal and / or a receive portion of the radar signal, each of which specifically includes a frequency ramp.

4. 4. A method according to claim 1, wherein adjusting the processing clock signal comprises reducing or increasing the cycle rate at which the signal processing unit is executed.

5. adjusting the processing clock signal comprises: - gradually increasing the frequency of the processing clock signal at the beginning of said time window until it reaches the frequency of the processing clock signal at which the signal processing unit is driven, and / or - gradually decreasing the frequency of the processing clock signal until, at the end of said time window, it reaches the frequency of the processing clock signal at which said signal processing unit is driven; The method according to claim 1 , comprising at least one of the following:

6. 1. A radar system comprising: a receiver arranged to receive radar signals via an antenna; a processing unit, - adapted to adjust a processing clock signal, said processing clock signal determining an operating period of said processing unit, said processing clock signal being determined on the basis of a time window; the size of the time window is determined based on a maximum time available to process a portion of the radar signal; a processing unit, the start and end of said time window being determined so as not to occur during an active transmission portion of said radar system; A radar system comprising:

7. The radar system of claim 6 , wherein the processing unit is or includes a signal processing unit.

8. A vehicle equipped with at least one radar system according to claim 6 or 7.

9. A computer program directly loadable into the memory of a digital processing device and comprising software code portions which, when executed by the digital processing device, cause the digital processing device to perform the method according to any one of claims 1 to 5.

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