Phase interpolator circuit, clock recovery circuit and chip

Abstract

The utility model relates to a phase interpolator circuit, a clock recovery circuit and a chip, and the phase interpolator circuit mainly comprises a first clock filter which is used for filtering a high-frequency harmonic wave of a first clock signal to generate a first filtering signal; the second clock filter is used for filtering the high-frequency harmonic wave of the second clock signal to generate a second filtering signal; the phase mixer is coupled to the first clock filter and the second clock filter and is used for generating a phase mixed signal according to the first filtering signal and the second filtering signal; and the alternating current coupling output circuit is used for receiving the phase mixed signal and generating an interpolation clock signal according to the phase mixed signal. The phase interpolator circuit can support phase interpolation operation in a wide frequency range, the output linearity performance is optimized, the sensitivity of INL and DNL to power supply amplitude changes is weakened, the duty ratio of the output interpolation clock signal can be optimized, and the interpolation clock signal can support a high-speed interface half-rate transmission mode.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuits, and in particular to a phase interpolator circuit, a clock recovery circuit and a chip. Background Art

[0002] Phase Interpolator (PI) is a circuit that performs weighted interpolation on input clock signals of different phases to generate an output clock signal with the required phase offset. Phase interpolators play an important role in digital communication systems, radar systems, image processing, audio processing and other fields.

[0003] In digital communications, phase interpolators can be used for clock data recovery (CDR) to help the receiver synchronize its clock with the transmitter's clock to accurately recover data.

[0004] With the development of communication technology, high-performance and high-speed physical layer interface (Physical Layer Interface, PHY) plays a very important role in high-speed communication systems. As an important component in the high-speed physical layer interface circuit, the phase interpolator has the performance requirements of high linearity, high speed and wide frequency working range. In addition, in order to transmit data more efficiently, high-speed interfaces usually need to support half-rate transmission mode. Therefore, there is also a need to use both edges of the clock signal for data transmission at the same time. Utility Model Content

[0005] In view of this, the present disclosure provides a phase interpolator circuit, a clock recovery circuit and a chip to help expand the applicable frequency range of the phase interpolator, help improve the output phase linearity performance of the phase interpolator, help reduce the integral nonlinearity error and differential nonlinearity error of the phase interpolator, and enable it to support the high-speed interface half-rate transmission mode.

[0006] According to one aspect of an embodiment of the present disclosure, a phase interpolator circuit is provided, comprising:

[0007] A first clock filter, configured to receive a first clock signal and filter the first clock signal to generate a first filtered signal;

[0008] a second clock filter, configured to receive a second clock signal and filter the second clock signal to generate a second filtered signal, wherein the second clock signal is different in phase from the first clock signal;

[0009] a phase mixer, coupled to the first clock filter and the second clock filter, configured to receive the first filtered signal and the second filtered signal, and generate a phase mixed signal according to the first filtered signal and the second filtered signal, wherein a phase of the phase mixed signal is between a phase of the first filtered signal and a phase of the second filtered signal;

[0010] The AC coupling output circuit is coupled to the phase mixer and is used for receiving the phase mixing signal and generating an interpolation clock signal according to the phase mixing signal.

[0011] In a possible implementation manner, the first clock filter includes a first variable resistor and a first capacitor; one end of the first variable resistor receives the first clock signal, and the other end of the first variable resistor is coupled to the phase mixer; the first capacitor is coupled between the other end of the first variable resistor and ground;

[0012] The second clock filter includes a second variable resistor and a second capacitor; one end of the second variable resistor receives the second clock signal, and the other end of the second variable resistor is coupled to the phase mixer; the second capacitor is coupled between the other end of the second variable resistor and ground.

[0013] In one possible implementation, the phase mixer includes:

[0014] N phase mixing units are each coupled between the first clock filter, the second clock filter and the AC coupling output circuit, wherein N≥1.

[0015] In a possible implementation manner, each of the phase mixing units includes:

[0016] A first tri-state inverter, wherein an input terminal of the first tri-state inverter is coupled to the first clock filter, and a control terminal of the first tri-state inverter is used to receive a first switch control signal;

[0017] A second tri-state inverter, wherein an input terminal of the second tri-state inverter is coupled to the second clock filter, and a control terminal of the second tri-state inverter is used to receive a second switch control signal;

[0018] A first resistor, one end of the first resistor is coupled to the output end of the first tri-state inverter and the output end of the second tri-state inverter, and the other end of the first resistor is coupled to the AC coupling output circuit.

[0019] In one possible implementation, the AC coupling output circuit includes:

[0020] a third capacitor, one end of which is coupled to the phase mixer;

[0021] an inverter, wherein an input end of the inverter is coupled to the other end of the third capacitor, and an output end of the inverter generates the interpolation clock signal;

[0022] A second resistor, one end of the second resistor is coupled to the other end of the third capacitor, and the other end of the second resistor is coupled to the output end of the inverter.

[0023] In one possible implementation, the phase interpolator circuit further includes:

[0024] A first multiplexer, wherein the first multiplexer has at least two input terminals, one output terminal and a selection control terminal, wherein the at least two input terminals of the first multiplexer respectively receive at least two first clock signals with different phases, the output terminal of the first multiplexer is coupled to the first clock filter, and the first multiplexer connects a clock signal transmission link between one of its input terminals and the output terminal based on a first selection control signal received by its selection control terminal.

[0025] In one possible implementation, the phase interpolator circuit further includes:

[0026] A second multiplexer, the second multiplexer has at least two input terminals, one output terminal and a selection control terminal, the at least two input terminals of the second multiplexer respectively receive at least two second clock signals with different phases, the output terminal of the second multiplexer is coupled to the second clock filter, and the second multiplexer connects the clock signal transmission link between one of its input terminals and the output terminal based on the second selection control signal received by its selection control terminal.

[0027] In a possible implementation manner, the first multiplexer includes:

[0028] At least two active switches, wherein the signal input terminal of each active switch is respectively coupled to each input terminal of the first multiplexer, the signal output terminal of each active switch is coupled to the output terminal of the first multiplexer, and the control terminal of each active switch is used to receive the first selection control signal.

[0029] In a possible implementation manner, the second multiplexer includes:

[0030] At least two active switches, wherein the signal input terminal of each active switch is respectively coupled to each input terminal of the second multiplexer, the signal output terminal of each active switch is coupled to the output terminal of the second multiplexer, and the control terminal of each active switch is used to receive the second selection control signal.

[0031] According to another aspect of an embodiment of the present disclosure, a clock recovery circuit is provided, which adopts the phase interpolator circuit as described in any one of the above items.

[0032] According to another aspect of an embodiment of the present disclosure, a chip is provided, which adopts the phase interpolator circuit as described in any one of the above items.

[0033] It can be seen from the above scheme that the phase interpolator circuit, clock recovery circuit and chip disclosed in the present invention can support phase interpolation operations in a wide frequency range. Compared with the phase interpolator of the CMOS structure in the traditional related technology, the phase interpolator circuit disclosed in the present invention further optimizes the output phase linearity performance and reduces the sensitivity of INL and DNL to changes in power supply amplitude. At the same time, the phase interpolator circuit disclosed in the present invention also helps to optimize the duty cycle of the output interpolation clock signal, so that the output interpolation clock signal can support the half-rate transmission mode of the high-speed interface. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1A It is a schematic diagram of the circuit principle of a phase interpolator of a CMOS structure in the related art;

[0035] Figure 1B It is a schematic diagram of the circuit principle of a controllable three-state switch inverter in the related art;

[0036] Figure 2 yes Figure 1A A schematic diagram of the phase relationship between the input signal and the output signal of the phase interpolator shown;

[0037] Figure 3 yes Figure 1A A schematic diagram showing the relationship between the weight ratio of the phase interpolator and the output phase;

[0038] Figure 4 is a structural schematic diagram of a phase interpolator circuit according to an exemplary embodiment;

[0039] Figure 5A It is a schematic diagram of the phase relationship between the input signal and the output signal when the output signal is distorted;

[0040] Figure 5B It is a schematic diagram of the phase relationship between the input signal and the output signal when the output signal distortion is eliminated by extending the transition time of the clock edge;

[0041] Figure 6 is a schematic structural diagram of a phase mixing unit according to an exemplary embodiment;

[0042] Figure 7 is a structural schematic diagram of an AC coupling output circuit according to an exemplary embodiment;

[0043] Figure 8 is a schematic diagram of the relationship between the threshold voltage and the phase before and after the second resistor is added to the AC coupling output circuit;

[0044] Fig. 9 is a structural schematic diagram of another phase interpolator circuit according to an exemplary embodiment;

[0045] Fig.10 yes Fig. 9 A schematic diagram of the phase relationship of clock signals within a clock cycle corresponding to the phase interpolator circuit shown;

[0046] Fig.11 is a schematic structural diagram of a multiplexer according to an exemplary embodiment;

[0047] Fig.12 It is a schematic diagram of a circuit structure of an active switch according to an exemplary embodiment. DETAILED DESCRIPTION

[0048] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below with reference to the accompanying drawings and examples.

[0049] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0050] A phase interpolator is a circuit used to generate an output clock signal phase between two input clock signal phases. It is usually used in high-speed, low-power transceivers, clock and data recovery systems. In practical applications, a phase interpolator can be used in conjunction with a phase-locked loop (PLL) or delay-locked loop circuit to achieve accurate clock signal generation and adjustment. Compared with traditional CML (Current Mode Logic) phase interpolators, CMOS (Complementary Metal-Oxide-Semiconductor) phase interpolators are simple and easy to implement. Therefore, modern high-speed communications mostly use CMOS phase interpolation circuits.

[0051] Figure 1A FIG. 1 is a schematic diagram of the circuit principle of a phase interpolator of a CMOS structure in the related art. Figure 1A As shown, the phase interpolator of the CMOS structure is mainly composed of two input inverter groups with adjustable driving capabilities and an output inverter, specifically including a first input inverter group inv1, a second input inverter group inv2 and an output inverter inv3, wherein the first input inverter group inv1 includes n parallel inverters with phases of The controllable three-state switch inverter between the input terminal of the clock input signal and the input terminal of the output inverter inv3, the second input inverter group inv2 includes n parallel inverters with a phase of A controllable three-state switch inverter is provided between the input end of the clock input signal and the input end of the output inverter inv3, and the output phase of the output inverter inv3 is The phase interpolated clock output signal is: lie in and between.

[0052] Figure 1B Schematic diagram of the circuit principle of a controllable three-state switch inverter in the related art. Figure 1B As shown, the controllable three-state switch inverter mainly includes a first PMOS P01, a second PMOS P02, a first NMOS N01 and a second NMOS N02, wherein the gate of the first PMOS P01 and the gate of the first NMOS N01 serve as the input terminal in of the controllable three-state switch inverter to receive the clock input signal, the gate of the second PMOS P02 receives the inverted control signal selb, the gate of the second NMOS N02 receives the positive control signal sel, the source of the first PMOS P01 is coupled to the power supply, the source of the second PMOS P02 is coupled to the drain of the first PMOS P01, the source of the first NMOS N01 is grounded, the source of the second NMOS N02 is coupled to the drain of the first NMOS N01, the drain of the second PMOS P02 is coupled to the drain of the second NMOS N02 and serves as the output terminal out of the controllable three-state switch inverter to output the inverted clock signal.

[0053] In the first input inverter group inv1 and the second input inverter group inv2, the control signals (positive phase control signal sel and negative phase control signal selb) of each controllable three-state switch inverter are used to control the opening and closing of each controllable three-state switch inverter, thereby controlling the driving capability of the first input inverter group inv1 and the second input inverter group inv2 as a whole. In an ideal case, Figure 1A The output phase of the phase interpolator shown can be expressed as

[0054]

[0055] Wherein, n is the sum of the number of controllable three-state switch inverters turned on simultaneously in the first input inverter group inv1 and the second input inverter group inv2, and k is the number of controllable three-state switch inverters turned on in the second input inverter group inv2. Figure 2 yes Figure 1A The phase relationship diagram between the input signal and the output signal of the phase interpolator shown in FIG. Figure 2 As shown, when k=1, the number of controllable three-state switch inverters turned on in the second input inverter group inv2 is 1, and the number of controllable three-state switch inverters turned on in the first input inverter group inv1 is n-1, so the output phase Closer to the input phase of the first input inverter group inv1 As k increases, the output phase From the input phase of the first input inverter group inv1 One side gradually approaches the input phase of the second input inverter group inv2 Move sideways.

[0056] Figure 3 yes Figure 1A The relationship between the weight ratio and the output phase of the phase interpolator shown in FIG. 1 is a schematic diagram showing the relationship between the weight ratio and the output phase of the phase interpolator, wherein the horizontal axis is the weight ratio and the vertical axis is the output phase. Figure 1A The weight ratio of the phase interpolator shown can be expressed as

[0057]

[0058] Wherein, B is a weight ratio, which indicates the turn-on weight ratio of the second input inverter group inv2. Figure 3 As shown, when all the controllable three-state switch inverters in the first input inverter group inv1 are turned on and all the controllable three-state switch inverters in the second input inverter group inv2 are turned off, that is, when B=0, = On the contrary, when all the controllable three-state switch inverters in the first input inverter group inv1 are turned off and all the controllable three-state switch inverters in the second input inverter group inv2 are turned on, that is, when B=1, = ;from Figure 3 It can be seen that as the weight ratio B increases, the output phase By input phase Gradually towards the input phase transition, thereby achieving an increase in the linearity of the output phase line.

[0059] Although the traditional CMOS phase interpolator has a simple structure and is easy to implement, it also has some problems.

[0060] Traditional CMOS phase interpolators only perform phase interpolation on a single edge (rising or falling edge) of the clock, and can only guarantee the linear performance of the single-edge output phase. However, in half-rate transmission mode, both the rising and falling edge phase outputs of the clock need to have good linear performance. The general solution is to use two phase interpolators to operate on the rising and falling edges of the clock respectively. However, the use of dual-phase interpolators increases the complexity of the circuit structure and the area occupied by the circuit.

[0061] Traditional CMOS phase interpolators generally do not support phase interpolation operations over a wide frequency range. One feature of CMOS phase interpolators is that the higher the clock frequency, the better the linearity, and the lower the clock frequency, the worse the linearity, because too low a clock frequency will cause the phase time difference between the two clock input signals to be greater than the transition time of the clock edge (for example, the transition time of the rising edge is the time it takes to jump from a low level to a high level). In this case, the waveform of the clock output signal after phase mixing by the CMOS phase interpolator will be "distorted", which directly leads to the deterioration of the output phase linearity. As the clock frequency increases, especially at high clock frequencies, the phase time difference between the clock input signals will become no greater than the transition time of the clock edge, thereby eliminating the "distortion" of the clock output signal waveform, thereby ensuring better linearity. Among them, the linearity of the phase interpolator refers to its ability to generate an intermediate phase with a constant and well-defined phase difference. The linearity determines how accurately the circuit can provide precise clock phase steps between 0° and 360° phases. A high-linearity phase interpolator enables the clock and data recovery (CDR) system to correctly align the clock within the valid data window. If the linearity of the phase interpolator is low, additional phase errors may be introduced during the phase compensation process, affecting the quality of data signal recovery.

[0062] Although compared with CML phase interpolators, CMOS phase interpolators are simple and easy to implement due to their simple structure, but compared with CML phase interpolators, due to the high process sensitivity of CMOS, the small signal swing of CMOS circuits, and the weak driving ability of CMOS circuits, the INL (Integral Non-Linearity) and DNL (Differential Nonlinearity) performance of CMOS phase interpolators are poor. Among them, INL refers to the deviation between the output phase of the phase interpolator and the ideal phase. INL describes the maximum deviation between the actual output phase and the ideal phase obtained by linear fitting. INL is the cumulative effect of DNL error and can be regarded as the linearity indicator of the phase interpolator in the entire phase range. A low INL value indicates that the phase interpolator provides a good linear phase output in the entire working range. DNL refers to the deviation between the actual phase difference and the ideal phase difference between two adjacent phase steps. DNL reflects the linearity of the phase interpolator between adjacent phase steps and is an indicator to measure the linearity of the phase interpolator in a single step. The smaller the DNL value, the more linear the change of the phase interpolator between adjacent phase steps.

[0063] The INL and DNL output performance of CMOS phase interpolators are very sensitive to power supply fluctuations. Because power supply fluctuations will cause changes in the working conditions of CMOS devices and will also cause clock jitter. At the same time, the CMOS threshold voltage is also very sensitive to the power supply voltage. The combined influence of many situations makes power supply fluctuations directly affect the working state and signal stability of the CMOS phase interpolator, thereby affecting the performance of the phase interpolator. In most cases, when circuit fluctuation noise occurs, the performance of the CMOS phase interpolator may deteriorate.

[0064] In view of this, an embodiment of the present disclosure provides a phase interpolator circuit to help expand the applicable frequency range of the phase interpolator, so that the phase interpolator circuit can support phase interpolation operations in a wide frequency range. At the same time, it helps to optimize the output linearity performance of the phase interpolator, helps to improve the INL and DNL output performance, helps to reduce the sensitivity of the phase interpolator to changes in power supply amplitude, and helps to improve the duty cycle performance of the clock output signal, so that the phase interpolator can support the high-speed interface half-rate transmission mode.

[0065] Figure 4 is a schematic diagram of a phase interpolator circuit according to an exemplary embodiment. Figure 4As shown, the phase interpolator circuit mainly includes a first clock filter 1, a second clock filter 2, a phase mixer 3 and an AC coupling output circuit 4. The first clock filter 1 is used to receive a first clock signal and filter the first clock signal to generate a first filtered signal. The second clock filter 2 is used to receive a second clock signal and filter the second clock signal to generate a second filtered signal, wherein the second clock signal has a different phase from the first clock signal. The phase mixer 3 is coupled to the first clock filter 1 and the second clock filter 2, and the phase mixer 3 is used to receive the first filtered signal and the second filtered signal, and generate a phase mixed signal according to the first filtered signal and the second filtered signal, wherein the phase of the phase mixed signal is between the phase of the first filtered signal and the phase of the second filtered signal. The AC coupling output circuit 4 is coupled to the phase mixer 3, and the AC coupling output circuit 4 is used to receive the phase mixed signal and generate an interpolated clock signal according to the phase mixed signal.

[0066] In the phase interpolator circuit of the disclosed embodiment, the clock signal is first filtered by the first clock filter 1 and the second clock filter 2 arranged before the phase mixer 3 to filter out unnecessary components, such as high-frequency harmonic components, so that the edge of the input clock signal becomes slower, which helps to improve the output linearity performance of the phase interpolator circuit (i.e., the interpolated clock signal).

[0067] In order to achieve a better filtering effect and make the phase interpolator circuit of the embodiment of the present disclosure have applicability in a wider frequency range, in the schematic embodiment, variable resistors are set in the first clock filter 1 and the second clock filter 2, and the corresponding filtering is achieved by adjusting the resistance of the variable resistors. Based on this, in the schematic embodiment, the first clock filter 1 includes a first variable resistor VR1 and a first capacitor C1, and the second clock filter 2 includes a second variable resistor VR2 and a second capacitor C2. Among them, one end of the first variable resistor VR1 receives the first clock signal, and the other end of the first variable resistor VR1 is coupled to the phase mixer 3; the first capacitor C1 is coupled between the other end of the first variable resistor VR1 and the ground. The second clock filter 2 includes a second variable resistor VR2 and a second capacitor C2; one end of the second variable resistor VR2 receives the second clock signal, and the other end of the second variable resistor VR2 is coupled to the phase mixer 3; the second capacitor C2 is coupled between the other end of the second variable resistor VR2 and the ground.

[0068] In this way, when the clock signal is at a higher frequency, the first variable resistor VR1 and the second variable resistor VR2 use smaller resistance values, so that the higher input frequency fundamental wave in the input clock signal can pass through the first clock filter 1 and the second clock filter 2, and the high-frequency harmonic components in the input clock signal can be filtered out; when the clock signal is at a lower frequency, the first variable resistor VR1 and the second variable resistor VR2 use larger resistance values, so that the input frequency fundamental wave in the input clock signal can pass through the first clock filter 1 and the second clock filter 2, and the remaining harmonic components in the input clock signal can be filtered out and the rising and falling edges of the clock signal become smoother, so that the conversion time of the clock edge becomes longer, which helps to eliminate the "distortion" phenomenon of the phase mixing signal.

[0069] Figure 5A It is a schematic diagram of the phase relationship between the input signal and the output signal when the output signal is distorted, such as Figure 5A As shown, the phase The clock input signal and phase are Taking the rising edge of the clock input signal as an example, the phase is The time it takes for the clock input signal to change from a low level to a high level is t 2 , that is, the phase is The transition time of the rising edge of the clock input signal is t 2 (Phase is The transition time of the rising edge of the clock input signal is also t 2 ), the phase is The clock input signal and phase are The phase time difference between the clock input signals is t 1 The phase is The rising edge start time and phase of the clock input signal are The time difference between the rising edge and ending time of the clock input signal. Figure 5A It can be seen that when the clock signal is at a lower frequency, the clock signal is at a high level or a low level for a longer period of time, which will cause the phase to be The rising edge of the clock input signal ends before the phase time difference is The rising edge of the clock input signal starts at the time (the time difference is greater than 0), which means that the phase is The phase of the clock input signal during the high level period is The clock input signal is in a low level state, and the phase during this period is The clock output signal will have a platform between the high level and the low level, causing a kink on the rising edge of the clock output signal. This kink makes it impossible to accurately grasp the transition moment of the clock output signal. Usually, the transition confirmation position of the clock signal is the middle level between the high level and the low level (the average value of the high level and the low level), and this platform kink causes a deviation in the transition confirmation position of the clock output signal, making the transition moment of the clock output signal uncertain and causing the degradation of the phase linearity of the clock output signal.

[0070] Figure 5B This is a schematic diagram of the phase relationship between the input signal and the output signal when the output signal distortion is eliminated by extending the transition time of the clock edge, such as Figure 5B Combined with Figure 4 As shown, when the clock signal is at a lower frequency, the phase is made to be The clock input signal and phase are The rising edge of the clock input signal becomes smoother and the phase is The time it takes for the clock input signal to change from a low level to a high level is determined by Figure 5A The t shown 2 Stretched to Figure 5B The t shown 2 ′, which makes the transition time of the clock edge longer, making the phase The rising edge end time of the clock input signal is close to or even lags behind the phase time difference of The rising edge of the clock input signal starts at the time (the time difference is close to 0 and is set to be less than 0), which means that the phase is The phase of the clock input signal during the high level period is The clock input signal changes continuously from a low level state to a high level state, so that the phase during this period is The clock output signal will be The clock input signal continuously changes from a low level state to a high level state, thereby eliminating the distortion of the rising edge of the clock output signal, so that the jump moment of the clock output signal can be accurately determined. Therefore, based on the phase interpolator circuit of the embodiment of the present disclosure, when the clock signal is at a lower frequency, by increasing the resistance of the first variable resistor VR1 and the second variable resistor VR2, it is helpful to improve the phase linearity of the clock output signal.

[0071] The first capacitor C1 and the second capacitor C2 set in the first clock filter 1 and the second clock filter 2 have the function of filtering out high-frequency harmonic components in the clock signal and retaining the fundamental wave of the clock signal, so that the fundamental wave components of the clock signal in the first filtered signal and the second filtered signal are higher, so as to help improve the fundamental wave purity of the clock input signal.

[0072] like Figure 4 As shown, in the exemplary embodiment, the phase mixer 3 includes N phase mixing units 31, and the N phase mixing units 31 are all coupled between the first clock filter 1, the second clock filter 2 and the AC coupling output circuit 4, wherein N≥1, N is an integer, preferably, N≥2.

[0073] Figure 6 is a schematic diagram of the structure of a phase mixing unit according to an exemplary embodiment, such as Figure 4 , Figure 6 As shown, in the exemplary embodiment, each phase mixing unit 31 includes a first three-state inverter tinv1, a second three-state inverter tinv2 and a first resistor R1. The input end of the first three-state inverter tinv1 is coupled to the first clock filter 1, and the control end (not shown) of the first three-state inverter tinv1 is used to receive the first switch control signal. The input end of the second three-state inverter tinv2 is coupled to the second clock filter 2, and the control end (not shown) of the second three-state inverter tinv2 is used to receive the second switch control signal. One end of the first resistor R1 is coupled to the output end of the first three-state inverter tinv1 and the output end of the second three-state inverter tinv2, and the other end of the first resistor R1 is coupled to the AC coupling output circuit 4.

[0074] In the exemplary embodiment, the first tri-state inverter tinv1 and the second tri-state inverter tinv2 may be tri-state inverters of related art, for example Figure 1B Compared with the related art, the phase interpolator circuit of the embodiment of the present disclosure can effectively suppress the inherent linear error of the phase interpolator by setting the first resistor R1 at the output end of the first three-state inverter tinv1 and the second three-state inverter tinv2, which helps to improve the INL and DNL of the phase interpolator circuit.

[0075] like Figure 4 As shown, in the exemplary embodiment, the AC coupling output circuit 4 includes a third capacitor C3, an inverter inv and a second resistor R2. Among them, one end of the third capacitor C3 is coupled to the phase mixer 3. The input end of the inverter inv is coupled to the other end of the third capacitor C3, and the output end of the inverter inv generates an interpolation clock signal. One end of the second resistor R2 is coupled to the other end of the third capacitor C3, and the other end of the second resistor R2 is coupled to the output end of the inverter inv.

[0076] Figure 7 is a schematic diagram of the structure of an AC coupling output circuit according to an exemplary embodiment. Figure 7 Combined with Figure 4 As shown, the inverter inv in the AC coupling output circuit 4 is composed of a third PMOS P03 and a third NMOS N03, the gate of the third PMOS P03 is coupled to the gate of the third NMOS N03 and serves as the input terminal of the inverter inv, the source of the third PMOS P03 is coupled to the power supply, the source of the third NMOS N03 is grounded, and the drain of the third PMOS P03 and the drain of the third NMOS N03 are coupled and serve as the output terminal of the inverter inv. Figure 7 It can be seen that the second resistor R2 is connected between the gate of the third PMOS P03 (the gate of the third NMOS N03) and the drain of the third PMOS P03 (the drain of the third NMOS N03). This structure helps to increase the threshold voltage of the inverter inv clock edge (such as the rising edge) flipping.

[0077] Figure 8 This is a schematic diagram of the relationship between the threshold voltage and phase before and after adding the second resistor in the AC coupled output circuit. Figure 8 Combined with Figure 7 As shown, by adding the second resistor R2 in the AC coupling output circuit 4, the static operating point of the node in_a (i.e., the input end of the inverter inv) and the node z (i.e., the output end of the inverter inv) can be fixed at 1 / 2 of the amplitude of the power supply voltage. If the second resistor R2 is not added, the flip threshold voltage of the inverter inv is relatively small. Figure 8 As shown, the threshold voltage of the inverter inv when the normal rising edge flips is V th1 Without adding the second resistor R2, because V th1 As the k value (the number of the second three-state inverters tinv2 turned on in the phase mixer 3) increases, the interpolated clock signal (output phase The time interval t of the clock output signal 1 ,t 2 ,t 3 Extremely uneven, and V th1 The lower the value, the more serious the uneven time intervals. Figure 8 As shown, when the second resistor R2 is added, the threshold voltage of the inverter inv when the rising edge is flipped will be increased to 1 / 2 of the power supply voltage amplitude, that is, V th2 At this time, as the k value increases, the time interval t of the interpolation clock signal output by the phase interpolator circuit 1 ′、t 2′、t 3 ' becomes more uniform, it can be seen that by adding the second resistor R2, the interpolation clock signal output by the phase interpolation circuit can be changed with the change of k value. and The more evenly spaced changes between them help to improve the linearity of the interpolation clock signal output by the phase interpolation circuit.

[0078] in, Figure 8 The t shown 1 ,t 2 ,t 3 Indicates that the threshold voltage when the rising edge of the inverter inv is flipped is V th1 The time intervals corresponding to different k values ​​in the case of ; Figure 8 The t shown 1 ′、t 2 ′、t 3 ' indicates that the threshold voltage when the rising edge of the inverter inv is flipped is V th2 The time intervals corresponding to different k values ​​in the case of th2 >V th1 ; Figure 5A t in 1 The phase is The clock input signal and phase are The phase time difference between the clock input signals; Figure 5A t in 2 The phase is The transition time of the rising edge of the clock input signal; Figure 5B t in 1 ' represents the phase when the resistance values ​​of the first variable resistor VR1 and the second variable resistor VR2 are increased. The clock input signal and phase are The phase time difference between the clock input signals; Figure 5B t in 2 ' represents the phase when the resistance values ​​of the first variable resistor VR1 and the second variable resistor VR2 are increased. The transition time of the rising edge of the clock input signal.

[0079] In addition, in the embodiment of the present disclosure, the AC coupling output circuit 4 also has the advantage of correcting the duty cycle of the interpolation clock signal output by the phase interpolation circuit, so that the interpolation clock signal output by the phase interpolator has good duty cycle performance, and can control the duty cycle of the interpolation clock signal output by the phase interpolator to about 50%, thereby helping to support the high-speed interface half-rate transmission mode. In addition, due to the presence of the second resistor R2, the threshold voltage when the rising edge of the inverter inv is flipped is fixed at 1 / 2 of the source voltage amplitude, which helps to suppress the sensitivity of the power supply voltage amplitude change to the output linearity of the AC coupling output circuit 4 of the embodiment of the present disclosure.

[0080] Fig. 9 is a schematic diagram of another phase interpolator circuit according to an exemplary embodiment. Figure 4 Compared to the phase interpolator circuit shown, Fig. 9 The phase interpolator circuit shown further includes a first multiplexer 51. The first multiplexer 51 has at least two input terminals, an output terminal and a gating control terminal (not shown), at least two input terminals of the first multiplexer 51 respectively receive at least two first clock signals with different phases, the output terminal of the first multiplexer 51 is coupled to the first clock filter 1, and the first multiplexer 51 connects the clock signal transmission link between one of its input terminals and the output terminal based on the first gating control signal received by its gating control terminal.

[0081] like Fig. 9 As shown, in the exemplary embodiment, Figure 4 Compared to the phase interpolator circuit shown, Fig. 9 The phase interpolator circuit shown further includes a second multiplexer 52. The second multiplexer 52 has at least two input terminals, one output terminal and a gating control terminal (not shown). The at least two input terminals of the second multiplexer 52 respectively receive at least two second clock signals with different phases. The output terminal of the second multiplexer 52 is coupled to the second clock filter 2. The second multiplexer 52 connects the clock signal transmission link between one of its input terminals and the output terminal based on the second gating control signal received by its gating control terminal.

[0082] like Fig. 9 As shown, in the exemplary embodiment, the first multiplexer 51 has four input terminals, and the second multiplexer 52 also has four input terminals. In the exemplary embodiment, the phases of the four first clock signals may be 0°, 90°, 180° and 270°, respectively, and the phases of the four second clock signals may be 45°, 135°, 225° and 315°, respectively.

[0083] Fig.10 yes Fig. 9 The phase relationship diagram of the clock signal within a clock cycle corresponding to the phase interpolator circuit shown in FIG. Fig.10 As shown, in the exemplary embodiment, the phase of one clock cycle is 360° ( ) is divided into 8 intervals, each interval is 45° ( ) phase range, the phase selection is realized by the first multiplexer 51 and the second multiplexer 52, further, each interval is divided into N equal parts, wherein N is the number of phase mixing units 31, that is, the number of first three-state inverters tinv1 is N, the number of second three-state inverters tinv2 is N, and the corresponding number of first three-state inverters tinv1 and the corresponding number of second three-state inverters tinv2 are turned on by the control signal, and the total number of the turned-on first three-state inverters tinv1 and the second three-state inverters tinv2 is N, thereby realizing the 45° ( ) is divided into N equal parts of the phase range interval. In an illustrative embodiment, the number of the first three-state inverter tinv1 and the second three-state inverter tinv2 that are turned on can be controlled by a 16-bit control signal. Based on this, the number of phase mixing units 31 is 16, that is, N=16, which means that the number of the first three-state inverter tinv1 is 16, and the number of the second three-state inverter tinv2 is 16. In an illustrative embodiment, a corresponding number of phase mixing units 31 can be used according to design requirements. The larger N is, the smaller the phase change amplitude of the interpolated clock signal that can be generated by the phase interpolator circuit of the embodiment of the present disclosure, and the higher the resolution of the phase change of the interpolated clock signal.

[0084] In the exemplary embodiment, the first multiplexer 51 and the second multiplexer 52 select the clock signals of two adjacent phases each time under the control of the first selection control signal and the second selection control signal to ensure that the phase difference between the first clock signal and the second clock signal is 45°. For example, the first multiplexer 51 selects the first clock signal with a phase of 0° and the second multiplexer 52 selects the second clock signal with a phase of 45°, or the second multiplexer 52 selects the second clock signal with a phase of 45° and the first multiplexer 51 selects the first clock signal with a phase of 90°, and so on. The first clock signal and the second clock signal are respectively passed through the first clock filter 1 and the second clock filter 2 to filter out the high-frequency components in the square wave clock signal to improve its output linear performance. The filtered clock signal is sent to the phase mixer 3. The phase mixer 3 turns on the corresponding number of first three-state inverters tinv1 and second three-state inverters tinv2 under the control signal, and then the phase mixer 3 outputs a phase mixed signal between the phase of the first clock signal and the phase of the second clock signal. The phase mixed signal is then passed through the AC coupling output circuit 4 to improve the linearity of the clock output signal and correct and optimize the duty cycle of the clock output signal, and finally an interpolated clock signal with better linearity and better duty cycle is output, and the interpolated clock signal can support the half-rate transmission mode of the high-speed interface.

[0085] In the exemplary embodiment, the first multiplexer 51 includes at least two active switches, wherein the signal input terminal of each active switch is respectively coupled to each input terminal of the first multiplexer 51, the signal output terminal of each active switch is coupled to the output terminal of the first multiplexer 51, and the control terminal of each active switch is used to receive a first selection control signal.

[0086] In the exemplary embodiment, the second multiplexer 52 includes at least two active switches, wherein the signal input terminal of each active switch is respectively coupled to each input terminal of the second multiplexer 52, the signal output terminal of each active switch is coupled to the output terminal of the second multiplexer 52, and the control terminal of each active switch is used to receive the second selection control signal.

[0087] In the phase interpolator circuit of the disclosed embodiment, active switches are used in the first multiplexer 51 and the second multiplexer 52, thereby enhancing the driving capabilities of the first multiplexer 51 and the second multiplexer 52 for the first clock signal and the second clock signal, helping to ensure the strength of the filtered signal entering the phase mixer 3 after filtering by the first clock filter 1 and the second clock filter 2, and helping the first filtered signal and the second filtered signal to be adopted by the phase mixer 3 in the high-frequency working mode and ultimately output a usable interpolation clock signal.

[0088] Fig.11is a schematic diagram of the structure of a multiplexer according to an exemplary embodiment. Fig.11 As shown, in the exemplary embodiment, the first multiplexer 51 and the second multiplexer 52 can both adopt Fig.11 The structure shown in the figure mainly includes four active switches, namely the first active switch s1, the second active switch s2, the third active switch s3 and the fourth active switch s4. The first active switch s1 receives the clock signal ck1, the second active switch s2 receives the clock signal ck2, the third active switch s3 receives the clock signal ck3, and the fourth active switch s4 receives the clock signal ck4. The output signal ckout is one of the clock signal ck1, the clock signal ck2, the clock signal ck3 and the clock signal ck4. In the exemplary embodiment, corresponding to the first multiplexer 51, the clock signal ck1 can be a first clock signal with a phase of 0°, the clock signal ck2 can be a first clock signal with a phase of 90°, the clock signal ck3 can be a first clock signal with a phase of 180°, and the clock signal ck4 can be a first clock signal with a phase of 270°. In an exemplary embodiment, corresponding to the second multiplexer 52, the clock signal ck1 may be a second clock signal with a phase of 45°, the clock signal ck2 may be a second clock signal with a phase of 135°, the clock signal ck3 may be a second clock signal with a phase of 225°, and the clock signal ck4 may be a second clock signal with a phase of 315°.

[0089] Active switches can be designed in a variety of implementation forms according to needs. Fig.12 is a schematic diagram of a circuit structure of an active switch according to an exemplary embodiment, such as Fig.12As shown, in an exemplary embodiment, the active switch may include a first switch circuit PMOS P11, a second switch circuit PMOS P12, a first switch circuit NMOS N11, a second switch circuit NMOS N12, a third switch circuit NMOS N21, a fourth switch circuit NMOS N22, a third switch circuit PMOS P21, a fourth switch circuit PMOS P22, a fifth switch circuit PMOS P31 and a fifth switch circuit NMOS N31. Wherein, the gate of the first switch circuit PMOS P11 is connected to the input signal a (for example, a clock signal), the gate of the second switch circuit PMOS P12 is connected to the positive phase control signal s, the gate of the first switch circuit NMOS N11 is connected to the positive phase control signal s, the gate of the second switch circuit NMOS N12 is connected to the input signal a, the gate of the third switch circuit NMOS N21 is connected to the input signal a, the gate of the fourth switch circuit NMOS N22 is connected to the negative phase control signal s_n, the gate of the third switch circuit PMOS P21 is connected to the negative phase control signal s_n, the gate of the fourth switch circuit PMOS P22 is connected to the input signal a, the source of the first switch circuit PMOS P11 and the second switch circuit PMOS P12 are connected to the power supply voltage, the source of the first switch circuit NMOS N11 is grounded, the source of the second switch circuit NMOS N12 is coupled to the drain of the first switch circuit NMOS N11, the drain of the first switch circuit PMOS P11, the drain of the second switch circuit PMOS P12, and the drain of the second switch circuit NMOS N12 are coupled to the fifth switch circuit PMOS The gate of the fifth switch circuit NMOS N31 is connected to the power supply voltage, the source of the third switch circuit PMOS P21 is connected to the power supply voltage, the source of the fourth switch circuit PMOS P22 is coupled to the drain of the third switch circuit PMOS P21, the drain of the third switch circuit NMOS N21, the drain of the fourth switch circuit NMOS N22 and the drain of the fourth switch circuit PMOS P22 are coupled to the gate of the fifth switch circuit NMOS N31, the source of the fifth switch circuit PMOS P31 is connected to the power supply voltage, the source of the fifth switch circuit NMOS N31 is connected to the ground, and the drain of the fifth switch circuit PMOS P31 is coupled to the drain of the fifth switch circuit NMOS N31 and generates an output signal out. Under the control of the positive phase control signal s and the negative phase control signal s_n, the opening and closing of the active switch can be realized. When the active switch is turned on, the output signal out is equal to the input signal a and the driving ability of the input signal a is enhanced under the action of the power supply voltage, thereby ensuring the strength of the output signal out. In an exemplary embodiment, the positive phase control signal s and the negative phase control signal s_n may be a pair of differential signals. In an exemplary embodiment, the negative phase control signal s_n may also be obtained by the positive phase control signal s through an inverter. Fig.12 The switching circuit shown is a combinational logic switch, which can be equivalent to a buffer. Compared with a transmission gate switch, the combinational logic switch has a strong driving capability and is more suitable for high-frequency working mode.

[0090] To sum up, the phase interpolator circuit of the embodiment of the present disclosure can support phase interpolation operations in a wide frequency range. Compared with the phase interpolator of the CMOS structure in the related technology, the phase interpolator circuit of the embodiment of the present disclosure further optimizes the output phase linearity performance and reduces the sensitivity of INL and DNL to changes in power supply amplitude. At the same time, the phase interpolator circuit of the embodiment of the present disclosure also helps to optimize the duty cycle of the output interpolation clock signal, so that the output interpolation clock signal can support the half-rate transmission mode of the high-speed interface.

[0091] In an illustrative embodiment, a clock recovery circuit is further provided. The clock recovery circuit adopts the phase interpolator circuit of any of the above embodiments.

[0092] In an exemplary embodiment, a chip is also provided, which adopts the phase interpolator circuit of any of the above embodiments.

[0093] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A phase interpolator circuit, characterized in that: include: A first clock filter, configured to receive a first clock signal and filter the first clock signal to generate a first filtered signal; a second clock filter, configured to receive a second clock signal and filter the second clock signal to generate a second filtered signal, wherein the second clock signal is different in phase from the first clock signal; a phase mixer, coupled to the first clock filter and the second clock filter, configured to receive the first filtered signal and the second filtered signal, and generate a phase mixed signal according to the first filtered signal and the second filtered signal, wherein a phase of the phase mixed signal is between a phase of the first filtered signal and a phase of the second filtered signal; The AC coupling output circuit is coupled to the phase mixer and is used for receiving the phase mixing signal and generating an interpolation clock signal according to the phase mixing signal.

2. The phase interpolator circuit according to claim 1, characterized in that: The first clock filter includes a first variable resistor and a first capacitor; one end of the first variable resistor receives the first clock signal, and the other end of the first variable resistor is coupled to the phase mixer; The first capacitor is coupled between the other end of the first variable resistor and the ground; The second clock filter comprises a second variable resistor and a second capacitor; one end of the second variable resistor receives the second clock signal, and the other end of the second variable resistor is coupled to the phase mixer; The second capacitor is coupled between the other end of the second variable resistor and ground.

3. The phase interpolator circuit according to claim 1, characterized in that: The phase mixer comprises: N phase mixing units are each coupled between the first clock filter, the second clock filter and the AC coupling output circuit, wherein N≥1.

4. The phase interpolator circuit according to claim 3, characterized in that: Each of the phase mixing units comprises: A first tri-state inverter, wherein an input terminal of the first tri-state inverter is coupled to the first clock filter, and a control terminal of the first tri-state inverter is used to receive a first switch control signal; A second tri-state inverter, wherein an input terminal of the second tri-state inverter is coupled to the second clock filter, and a control terminal of the second tri-state inverter is used to receive a second switch control signal; A first resistor, one end of the first resistor is coupled to the output end of the first tri-state inverter and the output end of the second tri-state inverter, and the other end of the first resistor is coupled to the AC coupling output circuit.

5. The phase interpolator circuit according to claim 1, characterized in that: The AC coupling output circuit comprises: a third capacitor, one end of which is coupled to the phase mixer; an inverter, wherein an input end of the inverter is coupled to the other end of the third capacitor, and an output end of the inverter generates the interpolation clock signal; A second resistor, one end of the second resistor is coupled to the other end of the third capacitor, and the other end of the second resistor is coupled to the output end of the inverter.

6. The phase interpolator circuit according to claim 1, characterized in that: The phase interpolator circuit further includes: A first multiplexer, wherein the first multiplexer has at least two input terminals, one output terminal and a selection control terminal, wherein the at least two input terminals of the first multiplexer respectively receive at least two first clock signals with different phases, the output terminal of the first multiplexer is coupled to the first clock filter, and the first multiplexer connects a clock signal transmission link between one of its input terminals and the output terminal based on a first selection control signal received by its selection control terminal.

7. The phase interpolator circuit according to claim 1, characterized in that: The phase interpolator circuit further includes: A second multiplexer, the second multiplexer has at least two input terminals, one output terminal and a selection control terminal, the at least two input terminals of the second multiplexer respectively receive at least two second clock signals with different phases, the output terminal of the second multiplexer is coupled to the second clock filter, and the second multiplexer connects the clock signal transmission link between one of its input terminals and the output terminal based on the second selection control signal received by its selection control terminal.

8. The phase interpolator circuit according to claim 6, characterized in that: The first multiplexer comprises: At least two active switches, wherein the signal input terminal of each active switch is respectively coupled to each input terminal of the first multiplexer, the signal output terminal of each active switch is coupled to the output terminal of the first multiplexer, and the control terminal of each active switch is used to receive the first selection control signal.

9. The phase interpolator circuit according to claim 7, characterized in that: The second multiplexer comprises: At least two active switches, wherein the signal input terminal of each active switch is respectively coupled to each input terminal of the second multiplexer, the signal output terminal of each active switch is coupled to the output terminal of the second multiplexer, and the control terminal of each active switch is used to receive the second selection control signal.

10. A clock recovery circuit, characterized in that: A phase interpolator circuit as claimed in any one of claims 1 to 9 is used.

11. A chip, characterized in that: A phase interpolator circuit as claimed in any one of claims 1 to 9 is used.

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