Memory System

Abstract

To materialize a memory system that can reduce the time required to search for an encryption key.SOLUTION: A key search circuit comprises: a hit determination circuit that determines whether or not a received key search request hits retained contents of a search result buffer; and an update determination circuit that determines whether or not to update the retained contents of the search result buffer. If the hit determination circuit determines that the received key search request hits the retained contents of the search result buffer, the key search circuit outputs a search result retained in the search result buffer to an encrypting / decoding circuit. If the update determination circuit determines to update the retained contents of the search result buffer, the key search circuit updates the retained contents of the search result buffer, with the received key search request and the search result acquired from a range table.SELECTED DRAWING: Figure 9

Description

[Technical field]

[0001] SUMMARY OF THE DISCLOSURE The present invention relates to a technique for encrypting data to be written to a storage device. [Background technology]

[0002] In recent years, memory systems equipped with non-volatile memories have become widespread. One such memory system is a solid-state drive (SSD) that includes a NAND flash memory.

[0003] Recently, SSDs with a data encryption function have been developed, and the SSDs with the data encryption function can be used as self-encrypting drives.

[0004] In a memory system such as an SSD equipped with a data encryption function, data is encrypted and decrypted by selectively using a plurality of encryption keys corresponding to a plurality of ranges.

[0005] Therefore, in order to improve the I / O throughput or reduce the I / O latency of a memory system, it is necessary to realize a new technique for reducing the time required to search for an encryption key. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] U.S. Pat. No. 9,904,807 [Patent Document 2] U.S. Patent No. 10,164,770 [Patent Document 3] US Patent Application Publication No. 2020 / 0125770 [Non-patent literature]

[0007] [Non-Patent Document 1] J. Henessy and D. Patterson, "Computer Architecture, Sixth Edition: A Quantitative Approach" Morgan Kaufmann Publishers, 2017. [Non-Patent Document 2] “Trusted Computing Group and NVMe Work Group Joint White Paper: TCG Storage, Opal, and NVMe”, 2015. Summary of the Invention [Problem to be solved by the invention]

[0008] An object of the present invention is to provide a memory system capable of reducing the time required to search for an encryption key. [Means for solving the problem]

[0009] According to an embodiment, a memory system connectable to a host includes a storage device, an encryption / decryption circuit, and a key search circuit. The encryption / decryption circuit is configured to generate ciphertext data to be written to the storage device by encrypting plaintext data received from the host using an encryption key obtained by the key search circuit, and to generate the plaintext data by decrypting the ciphertext data read from the storage device using the encryption key obtained by the key search circuit. The key search circuit is configured to output, to the encryption / decryption circuit, access permission information indicating permission or prohibition of access to the logical block address specified by the received key search request and an encryption key to be used by the encryption / decryption circuit in response to receiving from the encryption / decryption circuit a key search request specifying a logical block address specified by an access request received from the host and an access type indicating whether the access request is a read or write request. The key search circuit manages a range table for each of a plurality of ranges set in a logical block address space of the memory system, which holds information indicating a range of consecutive logical block addresses included in the range, access permission information indicating permission or prohibition of access to the range, and an encryption key to be applied to data corresponding to the range, and a search result buffer for holding a search result including the access permission information and the encryption key obtained by referring to the range table based on a key search request together with the key search request. The key search circuit further includes a hit determination circuit for determining whether the received key search request hits the contents held in the search result buffer, and an update determination circuit for determining whether the contents held in the search result buffer are updated. When the hit determination circuit determines that the received key search request hits the contents held in the search result buffer, the key search circuit outputs the search result held in the search result buffer to the encryption / decryption circuit.When the hit determination circuit determines that the received key search request does not hit the stored contents of the search result buffer, the key search circuit refers to the range table based on the received key search request to obtain a search result including access permission information indicating permission or prohibition of access to the logical block address specified by the received key search request and an encryption key to be applied to data corresponding to the logical block address from the range table, and outputs the obtained search result to the encryption / decryption circuit.When the update determination circuit determines that the stored contents of the search result buffer should be updated, the key search circuit updates the stored contents of the search result buffer with the received key search request and the search result obtained from the range table. [Brief description of the drawings]

[0010] [Figure 1] 1 is a block diagram showing an example of the configuration of an information processing system including a memory system according to an embodiment. [Diagram 2] FIG. 2 is a block diagram showing an example of the configuration of a controller and a storage device included in the memory system according to the embodiment. [Diagram 3] 11 is a diagram showing a data encryption process executed using a range table managed in the memory system according to the embodiment. FIG. [Figure 4] 1 is a sequence diagram showing the procedure of data encryption processing and data decryption processing executed in a memory system according to an embodiment. [Diagram 5] 11 is a diagram showing a process of converting a virtual address into a physical address used in a processor according to a comparative example. [Figure 6] FIG. 13 is a diagram showing an example of the configuration of a TLB (Translation Look-aside Buffer) used in a processor according to a comparative example. [Figure 7] 11 is a diagram showing an example of a range setting process executed in the memory system according to the embodiment; [Figure 8] 1 is a diagram showing an example of the contents of a range table managed in the memory system according to the embodiment; [Figure 9] FIG. 2 is a block diagram showing an example of the configuration of a key search circuit included in a controller of the memory system according to the embodiment. [Figure 10] FIG. 13 is a diagram showing the operation of the key search circuit when a search result buffer hit occurs. [Figure 11] 13 is a diagram showing the operation of the key search circuit when a search result buffer miss occurs and it is determined that the contents held in the search result buffer should be updated. [Figure 12] 13 is a diagram showing the operation of the key search circuit when a search result buffer miss occurs and it is determined not to update the contents held in the search result buffer. [Figure 13] 11 is a flowchart showing the procedure of a search result buffer hit determination process executed in the memory system according to the embodiment. [Figure 14] 11 is a flowchart showing the procedure of a search result buffer update determination process executed in the memory system according to the embodiment. [Figure 15] 11A and 11B are diagrams showing a specific example of a key search operation executed for each logical block address included in an access range specified by an access request from a host. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, an embodiment will be described with reference to the drawings. 1 is a block diagram showing an example of the configuration of an information processing system including a memory system according to an embodiment. The information processing system 1 includes a host (host device) 2 and a memory system 3.

[0012] The host 2 is an information processing device. The host 2 is, for example, a personal computer or a server computer. The host 2 accesses the memory system 3. Specifically, the host 2 transmits a write command, which is a command for writing data, to the memory system 3. In addition, the host 2 transmits a read command, which is a command for reading data, to the memory system 3.

[0013] The memory system 3 is a storage device and can be connected to the host 2 via a bus 100.

[0014] The bus 100 is mainly used for transmitting I / O commands from the host 2 to the memory system 3, and transmitting responses from the memory system 3 to the host 2. An I / O command is a command for writing or reading data to a non-volatile memory. Examples of I / O commands include a write command and a read command.

[0015] Communication between the host 2 and the memory system 3 via the bus 100 may be performed using, for example, NVM Express TM (NVMe TM The bus 100 is implemented in compliance with the PCI Express standard. TM Bus (PCIe TM bus).

[0016] When the bus 100 is a PCIe bus, the bus 100 includes a plurality of lanes. Each of the plurality of lanes is a full-duplex data transmission path including a differential signal line pair for data transmission and a differential signal line pair for data reception.

[0017] Next, a description will be given of the internal configuration of the host 2. The host 2 includes a processor 21, a memory 22, and a connector .

[0018] The processor 21 is a CPU (Central Processing Unit). The processor 21 communicates with the memory system 3 via a bus 100. The processor 21 executes software (host software) loaded into the memory 22. The host software is loaded into the memory 22 from the memory system 3 or another storage device connected to the host 2. The host software includes an operating system, a file system, a device driver, an application program, and the like.

[0019] The memory 22 is a volatile memory, for example, a random access memory such as a dynamic random access memory (DRAM).

[0020] The connector 23 is a connector for connecting a peripheral device, and is, for example, a PCIe connector.

[0021] Next, a description will be given of the internal configuration of the memory system 3. The memory system 3 includes a controller 4, a storage device 5, a DRAM 6, and a connector .

[0022] The controller 4 is a memory controller that controls the storage device 5. The controller 4 is, for example, a System-on-a-Chip (SoC). The controller 4 is connected to the storage device 5 so as to be able to communicate with it. The controller 4 writes and reads data to and from the storage device 5. The controller 4 also communicates with the host 2 via a bus 100.

[0023] The storage device 5 is a non-volatile memory such as a NAND flash memory. In this embodiment, the memory system 3 is realized as a solid state drive (SSD) having a NAND flash memory as the storage device 5, but the storage device 5 may be provided with a non-volatile semiconductor memory other than the NAND flash memory, such as a NOR flash memory, MRAM (Magnetoresistive Random access memory), PRAM (Phase change Random access memory), ReRAM (Resistive Random access memory), or FeRAM (Ferroelectric Random Access Memory). The memory system 3 according to this embodiment may be realized as an SD card or USB memory having a non-volatile memory, or may be realized as a hard disk drive (HDD) having a magnetic disk medium instead of a non-volatile semiconductor memory as the storage device 5.

[0024] The DRAM 6 is a volatile memory. A part of the storage area of ​​the DRAM 6 is used, for example, as a data buffer for temporarily storing data. Another part of the storage area of ​​the DRAM 6 is used to store management data used by the controller 4.

[0025] Next, an internal configuration of the controller 4 will be described. Fig. 2 is a block diagram showing a configuration example of the controller 4 and the storage device 5 included in the memory system 3 according to the embodiment. Fig. 2 illustrates a case where the memory system 3 is realized as a solid state drive (SSD) equipped with a NAND flash memory as the storage device 5.

[0026] The memory system 3 is a self-encrypting drive having a data encryption function. The memory system 3 is, for example, an NVM Express compliant with the TCG Opal standard. TM (NVMe TM ) SSD.

[0027] The controller 4 includes a host interface circuit (I / F) 11, a CPU 12, a NAND interface circuit (I / F) 13, a DRAM interface circuit (I / F) 14, a static random access memory (SRAM) 15, a key search circuit 16, an access permission determination circuit 17, and an encryption / decryption circuit 18. The host interface circuit 11, the CPU 12, the NAND interface circuit 13, the DRAM interface circuit 14, the SRAM 15, the key search circuit 16, the access permission determination circuit 17, and the encryption / decryption circuit 18 are connected to an internal bus 10.

[0028] The host interface circuit 11 is a hardware interface. The host interface circuit 11 executes communication with the host 2 via a bus 100. The communication between the host interface circuit 11 and the host 2 is executed in compliance with, for example, the NVMe standard. The host interface circuit 11 receives various commands from the host 2. The various commands include a write command, a read command, and the like.

[0029] The CPU 12 is a processor. The CPU 12 loads a control program (firmware) from a ROM (not shown) or the storage device 5 to the DRAM 6 or SRAM 15 in response to the supply of power to the memory system 3. The CPU 12 executes various processes by executing the loaded control program (firmware). For example, the CPU 12, as a flash translation layer (FTL), executes management of data stored in the NAND flash memories 151, 152, ... used as the storage device 5, and management of blocks included in the NAND flash memories 151, 152, .... The management of data is, for example, management of mapping information indicating the correspondence between each logical address and each physical address. The logical address is an address used by the host 2 to access the memory system 3. The logical address is, for example, a logical block address LBA. The physical address is an address indicating a physical storage location included in the NAND flash memories 151, 152, .... The management of blocks contained in the NAND type flash memories 151, 152, . . . includes, for example, management of defective blocks (bad blocks) contained in the NAND type flash memories 151, 152, .

[0030] The NAND interface circuit 13 is an example of a storage device interface circuit that controls the storage device 5. The NAND interface circuit 13 is a circuit that controls the NAND type flash memories 151, 152, .... The NAND interface circuit 13 is connected to each of the NAND type flash memories 151, 152, ... via, for example, a plurality of channels.

[0031] The DRAM interface circuit 14 is a circuit that controls the DRAM 6 .

[0032] The SRAM 15 is a volatile memory that can be accessed faster than the DRAM 6. Instead of the DRAM 6, a part of the storage area of ​​the SRAM 15 may be used as a data buffer, and another part of the storage area of ​​the SRAM 15 may be used to store management data used by the controller 4.

[0033] The key search circuit 16, the access permission decision circuit 17, and the encryption / decryption circuit 18 are hardware used to realize the data encryption function.

[0034] The key search circuit 16 is a circuit that executes a key search process. The key search process is a process that outputs to the encryption / decryption circuit 18 access permission information indicating whether access to an LBA specified by a key search request received from the encryption / decryption circuit 18 is permitted or prohibited, and an encryption key to be used by the encryption / decryption circuit 18. The encryption key to be used by the encryption / decryption circuit 18 means an encryption key to be used for encrypting or decrypting data corresponding to the LBA specified by the key search request.

[0035] The key search circuit 16 manages the range table. The range table is a table for storing information about each of a plurality of ranges set in the logical block address space of the memory system 3. The range table includes a plurality of entries corresponding to a plurality of ranges (LBA ranges). Each of the plurality of entries in the range table holds information indicating an LBA range belonging to a certain range, access permission information indicating whether access to this range is permitted or prohibited, and an encryption key to be applied to data corresponding to this range.

[0036] The key search request output from the encryption / decryption circuit 18 specifies the LBA specified by the access request (write command or read command) received from the host 2, and the access type indicating whether this access request is a read or write.

[0037] When a key search request is received from the encryption / decryption circuit 18, the key search circuit 16 basically refers to the range table to obtain a search result including the access permission information and the encryption key from the range table.

[0038] The range table is a table for storing information regarding each of a plurality of ranges (LBA ranges) set in the logical block address space of the memory system 3. The range table includes a plurality of entries corresponding to the plurality of ranges. Each of the plurality of entries holds information indicating a range of consecutive LBAs included in the corresponding range, access permission information indicating whether access to this range is permitted or prohibited, and an encryption key to be applied to data corresponding to this range.

[0039] In the memory system 3 according to this embodiment, the key search circuit 16 further manages a search result buffer. The search result buffer is used to hold a search result obtained by referring to the range table based on the key search request together with the key search request. The search result includes access permission information and an encryption key. The search result buffer may be stored in a memory having a faster read speed than the range table. For example, when the range table is stored in the DRAM 6, the search result buffer may be stored in the SRAM 15. Also, when the range table is stored in the SRAM 15, the search result buffer may be stored in a flip-flop circuit (not shown) of the key search circuit 16. The search result buffer may be stored in the memory in which the range table is stored. The number of entries included in the search result buffer is smaller than the number of entries included in the range table. Therefore, even when the search result buffer and the range table are stored in the same memory, the search result can be obtained at high speed from the search result buffer.

[0040] The key search circuit 16 further includes a search result buffer hit determination circuit and a search result buffer update determination circuit.

[0041] The search result buffer hit determination circuit is a hit determination circuit that determines whether a received key search request hits the contents stored in the search result buffer. The search result buffer hit determination circuit can determine whether the received key search request hits the contents stored in the search result buffer by comparing the received key search request with the key search requests stored in the search result buffer.

[0042] If the search result buffer hit determination circuit determines that the received key search request hits the contents stored in the search result buffer, the key search circuit 16 outputs the search result stored in the search result buffer to the encryption / decryption circuit 18.

[0043] On the other hand, if the search result buffer hit determination circuit determines that the received key search request does not hit the contents held in the search result buffer, the key search circuit 16 acquires the search result from the range table by referring to the range table based on the received key search request, and outputs the acquired search result to the encryption / decryption circuit 18. The search result acquired from the range table includes access permission information indicating whether access to the LBA specified by the received key search request is permitted or prohibited, and an encryption key to be applied to the data corresponding to this LBA.

[0044] The search result buffer update decision circuit is a decision circuit that decides whether to update the contents stored in the search result buffer. If the search result buffer update decision circuit decides to update the contents stored in the search result buffer, the key search circuit 16 updates the contents stored in the search result buffer with the received key search request and the search result obtained from the range table. In other words, the received key search request and the search result obtained from the range table are stored in the search result buffer.

[0045] Thus, in the memory system 3 according to the present embodiment, the key search circuit 16 executes a key search process using a search result buffer and a range table. The search result buffer holds both a certain key search request and a search result obtained by referring to the range table based on the key search request. Therefore, it is possible to determine whether a search result that matches a new key search request received from the encryption / decryption circuit 18 is held in the search result buffer. Therefore, when the received key search request hits the contents held in the search result buffer, the desired search result can be obtained immediately without referring to the range table. Therefore, even if the memory system 3 is configured to support a large number of ranges (LBA ranges), it is possible to reduce the latency of the key search. As a result, it is possible to improve the IO throughput of the memory system 3 or reduce the IO latency.

[0046] If the access range specified by the access request includes multiple LBAs, the key search circuit 16 sequentially receives multiple key search requests from the encryption / decryption circuit 18, the number of which is equal to the number of LBAs included in the access range. Each of the multiple key search requests specifies one LBA included in the access range and an access type indicating whether the access request is a read or write request. Each time a key search request is received from the encryption / decryption circuit 18, the key search circuit 16 executes a key search process. Therefore, if the access range specified by the access request includes multiple LBAs, the key search process is executed the same number of times as the number of LBAs. Then, the key search circuit 16 outputs search results equal to the number of LBAs.

[0047] The key search circuit 16 can also perform access permission determination processing. The access permission determination processing is processing for determining whether access is permitted or prohibited for the entire access range specified by an access request (write command or read command) received from the host 2.

[0048] The access permission determination circuit 17 is a circuit that executes a process of terminating the command as an error or a process of transferring control to the encryption / decryption circuit 18 based on the result of the access permission determination process.

[0049] The encryption / decryption circuit 18 is a circuit that executes encryption and decryption processes. The encryption and decryption processes are executed using the encryption key acquired by the key search circuit 16. When the key search circuit 16 outputs access permission information indicating that access is prohibited, the encryption and decryption processes are not executed. The encryption / decryption circuit 18 includes an encryption circuit 181 and a decryption circuit 182.

[0050] The encryption circuit 181 executes encryption processing. The encryption processing is processing for generating ciphertext data to be written to the storage device 5 by encrypting plaintext data received from the host 2 using an encryption key acquired by the key search circuit 16. The generated ciphertext data (i.e., encrypted data) is written to the storage device 5 (i.e., NAND type flash memory) by the NAND interface circuit 13. In addition, the CPU 12 may execute a predetermined process such as error correction coding on the generated ciphertext data, and then write the data on which the predetermined process has been executed to the storage device 5 via the NAND interface circuit 13. In other words, data based on the generated ciphertext data is written to the storage device 5 via the NAND interface circuit 13.

[0051] The decryption circuit 182 executes a decryption process. The decryption process is a process of generating plaintext data by decrypting ciphertext data read from the storage device 5 (i.e., the NAND flash memory) using the encryption key acquired by the key search circuit 16. The generated plaintext data is transmitted to the host 2 by the host interface circuit 11. Alternatively, the CPU 12 may execute a predetermined process such as an error correction process on the data read from the storage device 5 via the NAND interface circuit 13 to generate ciphertext data, and the decryption circuit 182 may execute a decryption process to generate plaintext data by decrypting the ciphertext data based on the data read from the storage device 5 using the encryption key acquired by the key search circuit 16. In other words, the decryption process is a process of generating plaintext data by decrypting ciphertext data based on the data read from the storage device 5 using the encryption key acquired by the key search circuit 16.

[0052] Next, the internal configuration of the NAND type flash memory provided as the storage device 5 will be described. Each of the NAND type flash memories 151, 152, ... is a NAND type flash memory die. Each of the NAND type flash memories 151, 152, ... includes a plurality of blocks BLK0 to BLKx-1. Each of the blocks BLK0 to BLKx-1 is a unit of a data erase operation. A data erase operation is an operation for erasing data. Each of the blocks BLK0 to BLKx-1 is also referred to as a physical block, an erase block, a flash block, or a memory block. Each of the blocks BLK0 to BLKx-1 includes a plurality of pages P0 to Py-1. Each of the pages P0 to Py-1 is a unit of a data write operation and a data read operation. A data write operation is an operation for writing data. A data read operation is an operation for reading data. Each of the pages P0 to Py-1 includes a plurality of memory cells connected to the same word line.

[0053] Next, the data encryption process will be described. Fig. 3 is a diagram showing the data encryption process executed using the range table 31 managed in the memory system 3 according to the embodiment. Here, the case where the key search process is executed without using the search result buffer will be described.

[0054] When an access request (write command or read command) is received from the host 2, the memory system 3 operates as follows. Here, it is assumed that the memory system 3 receives a write command from the host 2.

[0055] (1) The host 2 issues a write command (e.g., NS3, SLBA=90, NLB=20) to the memory system 3. This write command specifies the namespace identifier (NSID), the starting LBA of the access range (SLBA), and the number of logical blocks included in the access range (NLB). Each logical block corresponds to a sector specified by one LBA. Therefore, the number of logical blocks (NLB) is the number of sectors included in the access range, that is, the number of LBAs included in the access range. NS3 is a namespace identifier that identifies the namespace NS3. This write command requests that data be written to 20 logical blocks (20 sectors) from LBA90 to LBA109 in the namespace NS3.

[0056] (2) Upon receiving this write command from the host 2, the host interface circuit 11 transmits an access permission judgment request to the key search circuit 16 to inquire of the key search circuit 16 whether access to the entire access range specified by this write command is permitted or not. The access permission judgment request includes information specifying the access range and access type information indicating whether to read or write to this access range.

[0057] (3) Upon receiving an access permission judgment request, the key search circuit 16 refers to the range table 31 and checks whether the entire access range is locked or unlocked. If the entire access range is unlocked, the key search circuit 16 transmits a judgment result indicating "access permitted" to the access permission judgment circuit 17. On the other hand, if at least a part of the access range is locked, the key search circuit 16 transmits a judgment result indicating "access prohibited" to the access permission judgment circuit 17. In the example of FIG. 3, in the namespace NS3, LBA90 to LBA99 and LBA100 to LBA109 are set to different ranges, but both are in an unlocked state (a state shown by an illustration of an unlocked lock). Therefore, the key search circuit 16 transmits a judgment result indicating "access permitted" to the access permission judgment circuit 17. In this way, the access permission judgment process is performed for each access request (command). The permission or prohibition of access to each range can be set for each access type indicating read or write. In this case, if the entire access range is in an unlocked state for writing, the key search circuit 16 transmits a determination result indicating “access prohibited” to the access permission determination circuit 17 .

[0058] (4) If the key search circuit 16 determines that access is permitted, the access permission judgment circuit 17 transfers control to the encryption / decryption circuit 18. On the other hand, if the key search circuit 16 determines that access is prohibited, the access permission judgment circuit 17 terminates the processing of the received write command as an error and transmits a response indicating the error in the received write command to the host 2 via the host interface circuit 11.

[0059] (5) If the key search circuit 16 judges that the access is permitted, the encryption / decryption circuit 18 sequentially outputs 20 key search requests corresponding to the 20 LBAs (LBA90 to LBA109) to the key search circuit 16. Each time the key search circuit 16 receives one key search request, the key search circuit 16 obtains the search result from the range table 31 by referring to the range table 31. Then, the key search circuit 16 outputs the search result to the encryption / decryption circuit 18. As a result, the encryption / decryption circuit 18 sequentially receives 20 search results corresponding to the 20 LBAs (LBA90 to LBA109) from the key search circuit 16. Each of the 20 search results includes access permission information indicating permission or prohibition of access to the LBA specified by the corresponding key search request, and an encryption key to be applied to the data corresponding to this LBA. Here, since access to the entire LBA range (LBA99 to LBA109) has already been permitted, the access permission information included in each key search request basically indicates permission of access to the corresponding LBA. Furthermore, LBA90-LBA99 and LBA100-LBA109 belong to different ranges. Therefore, each of the 10 search results corresponding to LBA90-LBA99 includes an encryption key corresponding to the range to which LBA90-LBA99 belong. On the other hand, each of the 10 search results corresponding to LBA100-LBA109 includes another encryption key corresponding to another range to which LBA100-LBA109 belong. Then, when one search result corresponding to a certain key search request is received, the encryption / decryption circuit 18 encrypts one sector of write data corresponding to the LBA specified by the key search request using the encryption key included in the search result, thereby generating ciphertext data to be written to the storage device 5.

[0060] In this way, the key search process is executed for each key search request, and is therefore executed in units of LBA (sector). This makes it possible to correctly obtain the encryption key corresponding to the range to which each LBA included in the access range belongs, even if the access range spans different ranges.

[0061] 3, the encryption / decryption circuit 18 transmits a key search request to the key search circuit 16 after executing the access permission judgment process for the entire access range specified by the write command. However, since each search result includes the access permission information and the encryption key to be applied to the data corresponding to this LBA, it is possible to omit the execution of the access permission judgment process. Even in this case, it is possible to prohibit access to each LBA included in the range set to the locked state.

[0062] In addition, the access range specified by the write command may include only one LBA. In this case, the encryption / decryption circuit 18 only needs to output one key search request specifying this LBA and the access type indicating write to the key search circuit 16, and only needs to obtain one search result from the key search circuit 16.

[0063] Next, the procedure of the data encryption process and the data decryption process will be described with reference to Fig. 4. Fig. 4 is a sequence diagram showing the procedure of the data encryption process and the data decryption process executed in the memory system 3 according to the embodiment.

[0064] The upper part of FIG. 4 shows the steps of a data encryption process executed by the controller 4 in response to receiving a write command from the host 2.

[0065] When the host interface circuit 11 receives a write command from the host 2, an access permission judgment request is sent from the host interface circuit 11 to the key search circuit 16. The key search circuit 16 executes access permission judgment processing for each command. Then, the access permission judgment result for each command is sent from the key search circuit 16 to the host interface circuit 11.

[0066] If the access permission determination result for each command indicates that access is permitted, control is passed from the host interface circuit 11 to the encryption / decryption circuit 18. In this case, the host interface circuit 11 executes a process of storing the write data to be encrypted in a data buffer (not shown) and a process of requesting the encryption / decryption circuit 18 to prepare the encrypted write data in the data buffer (buffer write issue).

[0067] The encryption / decryption circuit 18 transmits a key search request to the key search circuit 16 for each LBA included in the access range specified by the write command. Then, the key search circuit 16 executes a key search process for each sector. When the search result corresponding to a certain LBA is acquired from the key search circuit 16, the encryption / decryption circuit 18 executes a process of generating ciphertext data by encrypting the write data corresponding to this LBA using the encryption key included in the acquired search result, and a process of writing the generated ciphertext data to the data buffer. When the ciphertext data corresponding to all LBAs included in the access range specified by the write command is prepared in the data buffer, the encryption / decryption circuit 18 notifies the NAND interface circuit 13 of the completion of the buffer write. The NAND interface circuit 13 writes the ciphertext data stored in the data buffer to the NAND flash memory 151 (or 152). When the writing to the NAND type flash memory 151 (or 152) is completed, a response (NAND write response) indicating that the writing to the NAND type flash memory 151 (or 152) is completed is notified from the NAND interface circuit 13 to the host interface circuit 11. In response to receiving this notification, the host interface circuit 11 transmits a command completion response indicating the completion of the write command to the host 2.

[0068] The lower part of FIG. 4 shows the procedure of the data decryption process executed by the controller 4 in response to receiving a read command from the host 2.

[0069] When the host interface circuit 11 receives a read command from the host 2, an access permission judgment request is sent from the host interface circuit 11 to the key search circuit 16. The key search circuit 16 executes access permission judgment processing for each command. Then, the access permission judgment result for each command is sent from the key search circuit 16 to the host interface circuit 11.

[0070] If the access permission determination result for each command indicates access permission, the host interface circuit 11 requests the NAND interface circuit 13 to read data (ciphertext data) corresponding to the LBA range specified by the read command (NAND read issue).Then, the host interface circuit 11 requests the encryption / decryption circuit 18 to prepare plaintext data obtained by decrypting the ciphertext data in the data buffer.

[0071] The host interface circuit 11 reads the ciphertext data from the NAND flash memory 151 (or 152) in units of pages, for example. The read ciphertext data is stored in a data buffer. The encryption / decryption circuit 18 transmits a key search request to the key search circuit 16 for each LBA included in the access range specified by the read command. Then, the key search circuit 16 executes a key search process in units of sectors. When the key search circuit 16 acquires a search result corresponding to a certain LBA, the encryption / decryption circuit 18 executes a process of generating plaintext data by decrypting the ciphertext data corresponding to this LBA using an encryption key included in the acquired search result, and a process of writing the generated plaintext data to the data buffer. When the plaintext data corresponding to all LBAs included in the access range specified by the read command is prepared in the data buffer, the host interface circuit 11 reads the plaintext data from the data buffer and transmits the read plaintext data to the host 2.

[0072] In this way, the type of encryption key required for one access request (I / O command) is not limited to one, and multiple types of encryption keys corresponding to multiple ranges may be used. Therefore, it becomes necessary to associate one encryption key with one LBA. The maximum number of ranges that can be set in the memory system 3 is determined as a product specification of the memory system 3, but the TCG Opal standard states that it is at least eight or more, and in reality, there may be several hundred.

[0073] Next, an example of processing performance required for encryption / decryption will be described, assuming that a PCIe interface having a PCI Express Gen6×4 lane configuration is used as the bus 100.

[0074] The throughput that saturates a PCIe interface having a configuration of PCI Express Gen6 x 4 lanes is 31.5 GB / s. When accessing a memory system 3 that uses a format that stores 512 bytes of data per LBA, the average time required per LBA (512 bytes) is 16 ns (512 / (31.5 x 10 9 ) sec). In the case where the controller 4 is configured to operate on a clock having a frequency of, for example, 500 MHz, 16 ns corresponds to eight cycles of this clock. In other words, the key search circuit 16 needs to obtain the encryption key within an average of eight cycles.

[0075] In this way, when there is a need to quickly match one piece of information with another, a cache is a common solution to speed things up. For example, in the case of a processor, code or data stored in one place on external DRAM is often used repeatedly for a while. For this reason, it is common to have an instruction cache and a data cache built into the same chip as the processor.

[0076] An example of speeding up using a cache is the TLB (Translation Look-aside Buffer) of an MMU (Memory Management Unit) included in a processor with a virtual memory function, although the purpose, configuration, and effect are different from those of the memory system 3 according to this embodiment. The virtual memory function of the processor has a function of converting a virtual address specified by a program into an actual physical address. This makes it possible to place programs at various physical addresses and run them simultaneously without modifying them, and also makes it possible to run many programs even with a small amount of physical memory by delaying the allocation of the actual physical addresses until they are actually used.

[0077] Here, the configuration and operation of converting a virtual address into a physical address will be described. Fig. 5 is a diagram showing a process of converting a virtual address into a physical address used in a processor according to a comparative example.

[0078] A 64-bit virtual address is shown at the top of Figure 5. Of these, bits [63:48] are assumed to be all 0 or all 1, the same value as bit

[47] , and the remaining 48 bits [47:0] are essentially the virtual address space.

[0079] The upper 9 bits [47:39] of the 48 bits [47:0] are used as an index to reference the page map L4 table. The next 9 bits [38:30] of the 48 bits [47:0] are used as an index to reference the page directory pointer table. The next 9 bits [29:21] of the 48 bits [47:0] are used as an index to reference the page directory table. The next 9 bits [20:12] of the 48 bits [47:0] are used to reference the page table.

[0080] The physical address stored in the Page Map L4 Base Address Register (CR3 Register) indicates the top address of the Page Map L4 table. The physical address obtained by adding 9 bits [47:39] as an offset to the physical address stored in the CR3 Register is used to reference the external DRAM. This obtains the physical address stored in one of the 512 entries in the Page Map L4 table.

[0081] The physical address obtained from the page map L4 table points to the top address of the page directory pointer table. The external DRAM is referenced again using the physical address obtained by adding 9 bits [38:30] as an offset to the physical address obtained from the page map L4 table. This obtains the physical address stored in one of the 512 entries in the page directory pointer table.

[0082] The physical address obtained from the page directory pointer table points to the top address of the page directory table. The external DRAM is referenced again using the physical address obtained by adding 9 bits [29:21] as an offset to the physical address obtained from the page directory pointer table. This obtains the physical address stored in one of the 512 entries in the page directory table.

[0083] The physical address obtained from the page directory table points to the start address of the page table. The external DRAM is again referenced using the physical address obtained by adding 9 bits [20:12] as an offset to the physical address obtained from the page directory table. This obtains the 28-bit physical address stored in one of the 512 entries in the page table.

[0084] This 28-bit physical address indicates one of the physical page frame numbers, each of which has a size of 4 KB.

[0085] The lowest 12 bits [11:0] of the virtual address are added to the physical page frame number as the page offset address, resulting in a 40-bit physical address that contains the physical page frame number and the page offset address.

[0086] Thus, because the page directory table / page table is located in external DRAM, four external DRAM references are required to convert a virtual address to a physical address.

[0087] FIG. 6 is a diagram illustrating an example of the configuration of a TLB (Translation Look-aside Buffer) used in a processor according to a comparative example.

[0088] Here, an example of the configuration of a fully associative TLB having 40 entries is shown. The TLB is not an external DRAM, but is a storage area built into the same chip as the processor. This allows high-speed access to the TLB. The TLB acts as a cache for the page table described in FIG. 5. That is, each entry of the TLB stores tag information (36 bits [47:12]) and a 28-bit physical address (physical page frame number) corresponding to this tag information.

[0089] When translating a virtual address into a physical address, 36 bits [47:12] of the virtual address are compared to the tag information stored in each of the 40 entries of the TLB to determine whether there is an entry in the TLB that stores tag information that matches 36 bits [47:12] of the virtual address.

[0090] If an entry exists in the TLB that stores tag information that matches the 36 bits [47:12] of the virtual address, the 28-bit physical address stored in this entry becomes the desired physical page frame number. The lower 12 bits [11:0] of the virtual address are added to the physical page frame number as an offset address within the page. This results in a 40-bit physical address that contains the physical page frame number and the offset address within the page.

[0091] Although the page table configuration in Figure 5 has a hierarchical structure, the page directory table / page table reference itself can simply use part of the virtual address as an index. Also, because the TLB configuration in Figure 6 is fully associative, it is necessary to compare part of the virtual address [47:12] with the tag information of all 40 entries. However, the comparison operation only needs to determine whether part of the virtual address [47:12] completely matches the tag information.

[0092] Next, an example of range setting in compliance with the TCG Opal standard will be described. Fig. 7 is a diagram showing an example of range setting processing executed in the memory system 3 according to the embodiment.

[0093] The storage area of ​​the storage device 5 of the memory system 3 is roughly divided into a system area and a user area. The system area is allocated to store system information of the memory system 3, and cannot be referenced from the outside. The user area is a storage area that can be referenced from the outside. In the user area, LBAs are allocated in order starting from 0. In the initial state after the shipment of the memory system 3, the entire user area is allocated to an area called the global range. By the administrator allocating consecutive LBA ranges such as range 1 and range 2 to the global range, different users can encrypt and store data with different encryption keys. Here, the administrator specifies the LBA range by specifying the start LBA and end LBA (or the LBA size of the range) of each range. Note that the areas such as range 1 and range 2 are overlaid on the global range. As a result, the global range that was initially allocated to each of the LBA ranges of range 1 and range 2 is hidden by each of range 1 and range 2. In addition, the LBA range corresponding to each range can be set in units of 1 LBA at the finest unit.

[0094] FIG. 8 is a diagram showing an example of the contents of the range table 31 managed in the memory system 3 according to the embodiment.

[0095] Range table 31 has a data structure in which a set of a start LBA and an end LBA is used as a setting unit. The TCG Opal standard specifies that the size of the range is set instead of the end LBA, but since the range size is information for identifying the end of the range, it is similar to the example in Figure 8 in that the range is defined by the start and end information. Specifically, in the example of range table 31 in Figure 8, each entry has the following information:

[0096] NSID: NSID is a namespace identifier. NSID is defined by NVMe.

[0097] IsGlobal flag: The IsGlobal flag is a flag (value of "0" or "1") that indicates whether the corresponding range setting is for the global range. An IsGlobal flag of "1" indicates that the corresponding range is a global range. An IsGlobal flag of "0" indicates that the corresponding range is not a global range.

[0098] Permission information: Permission information is accessibility information that indicates whether access to the corresponding range setting is permitted or prohibited. Permission information includes information indicating whether read access is permitted or prohibited, and information indicating whether write access is permitted or prohibited. "r" indicates that reading is permitted, "w" indicates that writing is permitted, and "-" indicates that reading and writing are not permitted. For example, "--" indicates that reading is not permitted, and writing is not permitted. "r--" indicates that reading is permitted, and writing is not permitted. "--w" indicates that reading is not permitted, and writing is permitted. "rw" indicates that reading is permitted, and writing is permitted.

[0099] Start LBA, End LBA: The start LBA and end LBA indicate the start LBA and end LBA that are the targets of the corresponding Range setting. In the case of a global range, the start LBA and end LBA are not set because the entire global range is the target of the setting.

[0100] Encryption Key: The encryption key indicates the encryption key used for the corresponding range.

[0101] Thus, unlike the page table in the virtual memory of the processor, the range table 31 conforming to the TCG Opal standard does not have a data structure that allows a desired encryption key or permission information to be searched for by referring to the range table using the LBA as an index. If range settings were to be managed with a data structure similar to that of the page table in the virtual memory of the processor, the required additional storage capacity would be enormous. For example, since the data encryption key of the commonly used XTS-AES-256 method is 64 bytes, if a data structure that allows a desired encryption key to be simply searched for from the LBA is used, it is necessary to hold a 64-byte data encryption key in association with each individual LBA. Therefore, if the data capacity per LBA is 512 bytes, an additional 64 bytes per LBA is required to hold the data encryption key. This consumes 10% or more of the additional data capacity. Furthermore, if the range table 31 has a data structure that allows a desired encryption key to be simply searched for from the LBA, the size of the range table 31 becomes huge, and it is necessary to store the range table 31 in the DRAM 6. In this case, since there is a latency involved in referencing the range table 31, it is practically impossible to search such a huge data structure to satisfy, for example, the aforementioned design constraint of obtaining an encryption key within an average of eight cycles.

[0102] Therefore, in a configuration in which a range table 31 conforming to the TCG Opal standard is used to manage the LBA range, encryption key, and accessibility information corresponding to each range, a new technology is needed that can reduce the time required to search for the encryption key and accessibility information.

[0103] Next, the key search circuit 16 will be described in detail. Fig. 9 is a block diagram showing a configuration example of the key search circuit 16 included in the controller 4 of the memory system 3 according to the embodiment. The key search circuit 16 includes a key search request input circuit 1601, a register 1602, a selector 1603, a register 1604, a normal determination circuit 1605, a selector 1606, a register 1607, an encryption key output circuit 1608, an RLB Hit determination circuit 1609, an RLB update determination circuit 1610, a selector 1611, and a Range-check Look-aside Buffer (RLB) 1612.

[0104] The key search request input circuit 1601 is a circuit that receives a key search request from the encryption / decryption circuit 18. Upon receiving a key search request, the key search request input circuit 1601 inputs the received key search request to a register 1602.

[0105] The register 1602 is a storage circuit that temporarily holds a key search request.

[0106] The selector 1603 is a selection circuit. The selector 1603 selects whether or not to input the key search request obtained from the register 1602 to the register 1604 based on a control signal received from the RLB Hit determination circuit 1609.

[0107] The register 1604 is a storage circuit that temporarily holds a key search request.

[0108] The normal judgment circuit 1605 is a circuit that executes normal judgment processing. The normal judgment circuit 1605 acquires a key search request from the register 1604. Then, as the normal judgment processing, the normal judgment circuit 1605 executes a process of acquiring a search result including access permission information and an encryption key from the range table 31 by referring to the range table 31 based on the acquired key search request. Specifically, the normal judgment circuit 1605 identifies an entry in the range table 31 that includes information about a range corresponding to an NSID and a logical block address (LBA) specified by the received key search request. Then, the normal judgment circuit 1605 acquires the access permission information and the encryption key as a search result from the identified entry in the range table 31. The normal judgment circuit 1605 inputs the acquired search result to the selector 1606 and the selector 1611.

[0109] The selector 1606 is a selection circuit that selects the search result input from either the normal determination circuit 1605 or the RLB 1612, and inputs the selected search result to the register 1607.

[0110] The register 1607 is a storage circuit that temporarily stores the search result.

[0111] The encryption key output circuit 1608 is a circuit that outputs a search result. The encryption key output circuit 1608 acquires the search result stored in the register 1607. Then, the encryption key output circuit 1608 outputs the search result to the encryption / decryption circuit 18 as a response to the key search request. The search result output by the encryption key output circuit 1608 includes access permission information and an encryption key.

[0112] The RLB Hit determination circuit 1609 is a search result buffer hit determination circuit. The RLB Hit determination circuit 1609 acquires the key search request input by the key search request input circuit 1601 from the register 1602. The RLB Hit determination circuit 1609 judges whether the acquired key search request hits the search result held by the RLB 1612. The RLB 1612 holds the key search request and the search result corresponding to this key search request. Therefore, the RLB Hit determination circuit 1609 judges whether the acquired key search request hits the search result held by the RLB 1612 based on whether the acquired key search request matches the key search request held by the RLB 1612. For example, the RLB Hit determination circuit 1609 can judge whether the received key search request hits the contents held by the RLB 1612 based on whether the LBA specified by the acquired key search request and the LBA specified by the key search request held by the RLB 1612 are included in the same batch search unit. Here, the batch search unit is one of a plurality of batch search units obtained by dividing the LBA space for accessing the memory system 3 into units each including a predetermined number of consecutive LBAs. The batch search unit is, for example, a cluster including eight consecutive LBAs.

[0113] If the acquired key search request hits the search result held by the RLB 1612, the RLB Hit judging circuit 1609 transmits a hit notification to the selector 1603. The hit notification is transmitted to the selector 1603 as a control signal instructing the selector 1603 not to input the key search request acquired from the register 1602 to the register 1604. If the acquired key search request does not hit the search result held by the RLB 1612 (miss), the RLB Hit judging circuit 1609 transmits a miss notification to the selector 1603. The miss notification is transmitted to the selector 1603 as a control signal instructing the selector 1603 to input the key search request acquired from the register 1602 to the register 1604.

[0114] The RLB update determination circuit 1610 is a search result buffer update determination circuit. The RLB update determination circuit 1610 acquires a key search request from the register 1604. The RLB update determination circuit 1610 determines whether to update the contents held in the RLB 1612 based on the acquired key search request. For example, the RLB update determination circuit 1610 may determine whether to update the contents held in the RLB 1612 based on whether the range boundaries of multiple ranges managed in the range table 31 are included within the batch search unit including the LBA specified by the acquired key search request. If no range boundaries are included within the batch search unit (e.g., cluster) including the LBA specified by the acquired key search request, the RLB update determination circuit 1610 determines to update the contents held in the RLB 1612. On the other hand, if a range boundary is included within the batch search unit including the LBA specified by the acquired key search request, the RLB update determination circuit 1610 determines not to update the contents held in the RLB 1612. When it is determined that the contents held in the RLB 1612 should be updated, the RLB update determination circuit 1610 transmits to the selector 1611 a control signal instructing the selector 1611 to update the contents held in the RLB 1612 using the search result input from the normal determination circuit 1605. When it is determined that the contents held in the RLB 1612 should not be updated, the RLB update determination circuit 1610 transmits to the selector 1611 a control signal instructing the selector 1611 not to update the RLB 1612 with the search result input from the normal determination circuit 1605.

[0115] The selector 1611 is a selection circuit. The selector 1611 uses the search result input from the normal determination circuit 1605 to select whether or not to update the contents held in the RLB 1612 based on a control signal transmitted from the RLB update determination circuit 1610.

[0116] The RLB 1612 is a search result buffer. The RLB 1612 is a buffer that holds a key search request and a search result obtained by the normal determination circuit 1605 corresponding to the key search request. The key search request and the search result held in the RLB 1612 are called RLB Info. Specifically, the RLB Info includes a Valid flag, Range Check request information, and Range Check result information. Valid is a flag indicating whether the search result stored in the RLB 1612 is valid or not. The Range Check request information is information indicating a key search request. The Range Check request information includes NSID, which is information for identifying a namespace included in the key search request, LBA, which is information indicating a logical block address included in the key search request, and DIR, which is a flag indicating whether the command associated with the key search request is a read command or a write command. The Range Check result information includes PROTECTION_ERR, which is a flag indicating access permission information, and RETURN_ALLZERO, which is a flag indicating whether a condition for returning all zeros as read data of a read command is satisfied or not. The IV Key is one of the encryption keys in the XTS-AES mode. The Data Key is also one of the encryption keys in the XTS-AES mode.

[0117] Next, the operation of the key search circuit 16 will be described when the RLB Hit judging circuit 1609 judges that the key search request hits the contents stored in the RLB 1612. Fig. 10 is a diagram showing the operation of the key search circuit when a search result buffer hit occurs. First, in response to the key search request input circuit 1601 of the key search circuit 16 receiving a key search request from the encryption / decryption circuit 18, the key search request input circuit 1601 starts operation.

[0118] (1) A key search request input circuit 1601 inputs a received key search request to a register 1602 .

[0119] (2) The RLB Hit determination circuit 1609 obtains a key search request from the register 1602. Similarly, the selector 1603 obtains a key search request from the register 1602.

[0120] (3) The RLB Hit determination circuit 1609 determines whether or not the acquired key search request hits the search results stored in the RLB 1612. Here, a case where the acquired key search request hits the search results stored in the RLB 1612 will be described.

[0121] (4) The RLB Hit judging circuit 1609 transmits a Hit notification to the selector 1603. The selector 1603 that has received the Hit notification is controlled so as not to input the input key search request to the register 1604.

[0122] (5) After making a hit determination, the RLB hit determination circuit 1609 outputs the search result held in the RLB 1612 to the selector 1606 .

[0123] (6) The selector 1606 receives the search result from the RLB 1612 , selects this search result, and outputs it to the register 1607 .

[0124] (7) The encryption key output circuit 1608 obtains the search result from the register 1607 and outputs the obtained search result to the encryption / decryption circuit 18 .

[0125] This allows the key search circuit 16 to output a search result including the access permission information and the encryption key in response to a key search request, without executing the normal judgment process by the normal judgment circuit 1605.

[0126] Next, the operation of the key search circuit 16 will be described when the RLB Hit judgment circuit 1609 judges that the acquired key search request does not hit (miss) the search result stored in the RLB 1612, and the RLB update judgment circuit 1610 judges that the stored contents of the RLB 1612 should be updated. Fig. 11 is a diagram showing the operation of the key search circuit when a search result buffer miss occurs and it is judged that the stored contents of the search result buffer should be updated. First, as in Fig. 10, in response to the key search request input circuit 1601 of the key search circuit 16 receiving a key search request from the encryption / decryption circuit 18, the key search request input circuit 1601 starts operation.

[0127] (1) A key search request input circuit 1601 inputs a received key search request to a register 1602 .

[0128] (2) The RLB Hit determination circuit 1609 obtains a key search request from the register 1602. Similarly, the selector 1603 obtains a key search request from the register 1602.

[0129] (3) The RLB Hit determination circuit 1609 determines whether or not the acquired key search request hits the search results stored in the RLB 1612. Here, a case where the acquired key search request does not hit the search results stored in the RLB 1612 (miss) will be described.

[0130] (4) The RLB Hit judging circuit 1609 transmits a miss notification to the selector 1603. The selector 1603 that has received the miss notification is controlled so as to input the input key search request to the register 1604.

[0131] (5) The selector 1603 inputs the key search request obtained from the register 1602 to the register 1604 based on the miss notification sent from the RLB Hit determination circuit 1609 .

[0132] (6) The normal determination circuit 1605 and the RLB update determination circuit 1610 obtain a key search request from the register 1604 .

[0133] (7) The normal determination circuit 1605 executes normal determination processing, and the RLB update determination circuit 1610 determines whether or not to update the contents held in the RLB 1612. The normal determination circuit 1605 inputs the search result acquired by the normal determination processing to the selector 106 and the selector 1611. Then, the RLB update determination circuit 1610 transmits a notification to the selector 1611 indicating whether or not to update the RLB 1612. Here, a case will be described where the RLB update determination circuit 1610 notifies an update determination.

[0134] (8) The selector 1611 updates the RLB 1612 using the search result input from the normal determination circuit 1605 based on the update determination sent from the RLB update determination circuit 1610. As a result, the contents held in the RLB 1612 are updated.

[0135] (9) The selector 1606 receives the search result from the normal decision circuit 1605 , selects this search result, and outputs it to the register 1607 .

[0136] (10) The encryption key output circuit 1608 obtains the search result from the register 1607 and outputs the obtained search result to the encryption / decryption circuit 18 .

[0137] This allows the key search circuit 16 to newly store the search result acquired by executing the normal judgment process by the normal judgment circuit 1605 in the RLB 1612. Therefore, when a key search request specifying the same cluster is subsequently received, the operation in the case where the RLB Hit judgment circuit 1609 judges a hit, as described in Fig. 10, is executed, so that the search result including the access permission information and the encryption key can be output without executing the normal judgment process by the normal judgment circuit 1605.

[0138] Next, the operation of the key search circuit 16 will be described when the RLB Hit determination circuit 1609 determines that the acquired key search request does not hit (miss) the search result stored in the RLB 1612, and the RLB update determination circuit 1610 determines not to update the contents stored in the RLB 1612. Fig. 12 is a diagram showing the operation of the key search circuit when a search result buffer miss occurs and it is determined not to update the contents stored in the search result buffer. First, as in Fig. 10, in response to the key search request input circuit 1601 of the key search circuit 16 receiving a key search request from the encryption / decryption circuit 18, the key search request input circuit 1601 starts operation.

[0139] (1) A key search request input circuit 1601 inputs a received key search request to a register 1602 .

[0140] (2) The RLB Hit determination circuit 1609 obtains a key search request from the register 1602. Similarly, the selector 1603 obtains a key search request from the register 1602.

[0141] (3) The RLB Hit determination circuit 1609 determines whether or not the acquired key search request hits the search results stored in the RLB 1612. Here, a case where the acquired key search request does not hit the search results stored in the RLB 1612 (miss) will be described.

[0142] (4) The RLB Hit judging circuit 1609 transmits a miss notification to the selector 1603. The selector 1603 that has received the miss notification is controlled so as to store the input key search request in the register 1604.

[0143] (5) The selector 1603 stores the key search request obtained from the register 1602 in the register 1604 based on the miss notification sent from the RLB Hit determination circuit 1609 .

[0144] (6) The normal determination circuit 1605 and the RLB update determination circuit 1610 obtain a key search request from the register 1604 .

[0145] (7) The normal determination circuit 1605 executes normal determination processing, and the RLB update determination circuit 1610 determines whether or not to update the contents held in the RLB 1612. The normal determination circuit 1605 inputs the search result acquired by the normal determination processing to the selector 106 and the selector 1611. Then, the RLB update determination circuit 1610 transmits a notification indicating whether or not to update the RLB 1612 to the selector 1611. Here, a case will be described in which the RLB update determination circuit 1610 determines not to update the contents held in the RLB 1612. The selector 1611 does not store the search result input from the normal determination circuit 1605 in the RLB 1612 based on the determination not to update transmitted from the RLB update determination circuit 1610. As a result, the contents held in the RLB 1612 are not updated.

[0146] (8) The selector 1606 receives the search result from the normal decision circuit 1605 , selects this search result, and outputs it to the register 1607 .

[0147] (9) The encryption key output circuit 1608 obtains the search result from the register 1607 and outputs the obtained search result to the encryption / decryption circuit 18 .

[0148] As a result, when the RLB update determination circuit determines not to update, the key search circuit 16 does not newly store the search result acquired by executing the normal determination process by the normal determination circuit 1605 in the RLB 1612. Next, the RLB hit determination process executed by the RLB Hit determination circuit 1609 will be described. FIG. 13 is a flowchart showing the procedure of the search result buffer hit determination process executed in the memory system 3 according to the embodiment. First, the RLB Hit determination circuit 1609 starts the RLB hit determination process in response to acquiring a key search request.

[0149] First, the RLB Hit determination circuit 1609 determines whether or not the information held in the RLB 1612 is valid (step S11). The RLB Hit determination circuit 1609 refers to the RLB Info and determines whether or not the Valid flag indicates validity.

[0150] If the information held in the RLB 1612 is not valid (No in step S11), the RLB Hit judging circuit 1609 outputs a miss as the RLB Hit judging result (step S15). As a result, a key search request is sent to the normal judging circuit 1605.

[0151] On the other hand, if the information held in the RLB 1612 is valid (Yes in step S11), the RLB Hit determination circuit 1609 executes the following determinations (1), (2), and (3) (step S12).

[0152] (1) The NSID specified in the key search request matches the NSID stored in RLB 1612.

[0153] (2) The logical product of the LBA and the LBA mask specified by the key search request matches the logical product of the LBA and the LBA mask stored in the RLB 1612.

[0154] (3) The DIR specified in the key search request matches the DIR stored in the RLB 1612.

[0155] Here, the LBA mask is a value defined such that the logical product of the LBA and the LBA mask is a value ignoring the lower bits of this LBA. By comparing the logical product of the LBA and the LBA mask specified by the key search request with the logical product of the LBA and the LBA mask stored in the RLB1612, it is possible to perform a comparison ignoring the value of a predetermined number of lower bits determined by the LBA mask. For example, if the LBA mask is "ffff_ffff_fff8" in hexadecimal notation, the lower 3 bits of the 48-bit LBA can be ignored, and only the upper 45 bits of the 48-bit LBA specified by the key search request can be compared with only the upper 45 bits of the 48-bit LBA stored in the RLB1612. In this way, if the LBA mask is defined to a value that masks the lower 3 bits, it is possible to determine whether or not the cluster including the LBA specified by the key search request matches the cluster including the LBA stored in the RLB1612.

[0156] Then, the RLB Hit determination circuit 1609 determines whether or not the determinations in (1), (2), and (3) in step S12 are all Yes (step S13).

[0157] If any of the judgments in step S12 is No (No in step S13), the RLB Hit judgment circuit 1609 outputs Miss as the RLB Hit judgment result (step S15). As a result, a key search request is transmitted to the normal judgment circuit 1605.

[0158] If all the judgments in step S13 are Yes (Yes in step S13), the RLB Hit judgment circuit 1609 outputs a hit as the RLB Hit judgment result (step S14). As a result, a key search request is not sent to the normal judgment circuit 1605, and the search result held in the RLB 1612 is sent to the encryption key output circuit 1608.

[0159] Next, a description will be given of the RLB update determination process executed by the RLB update determination circuit 1610. Fig. 14 is a flowchart showing the procedure of the search result buffer update determination process executed in the memory system 3 according to the embodiment. First, the RLB update determination circuit 1610 starts the RLB update determination process in response to acquiring a key search request.

[0160] The LBA mask used in the RLB update determination process of Fig. 14 may have the same mask pattern as the LBA mask used in the RLB hit determination process of Fig. 13. For example, in a case where the LBA mask (="hffff_ffff_fff8) is used in the RLB hit determination process of Fig. 13, the LBA mask (="hffff_ffff_fff8) is also used in the RLB update determination process of Fig. 14.

[0161] In the RLB update judgment process, it is judged whether or not the batch search range including the LBA specified by the key search request includes range boundaries of multiple ranges set in the range table 31. If it is confirmed that the batch search range including the LBA specified by the key search request does not include any range boundaries of multiple ranges set in the range table 31, the RLB update judgment circuit 1610 outputs "update" as the RLB update judgment result, otherwise the RLB update judgment circuit 1610 outputs "do not update" as the RLB update judgment result. The specific procedure is as follows.

[0162] First, the RLB update determination circuit 1610 initializes the value of a variable (i) used as an index for referring to the range table 31 (step S21). The RLB update determination circuit 1610 refers to an entry in the range table 31 that corresponds to the value of the index.

[0163] The RLB update determination circuit 1610 executes the following determinations (1), (2), and (3) (step S22).

[0164] (1) The RLB update determination circuit 1610 determines whether the information in the i-th entry of the range table 31 is valid or not.

[0165] (2) The RLB update determination circuit 1610 determines whether the IsGlobal flag of the i-th entry in the range table 31 is 0 (indicating a Non-Global Range entry).

[0166] (3) The RLB update determination circuit 1610 determines whether the NSID of the i-th entry in the range table 31 matches the NSID specified by the key search request.

[0167] The RLB update determination circuit 1610 determines whether or not all the determinations executed in step S22 are Yes (step S23).

[0168] If all the determinations in step S22 are Yes (Yes in step S23), the RLB update determination circuit 1610 executes the following determinations (1) and (2) (step S24).

[0169] (1) The RLB update judgment circuit 1610 judges whether the following condition is satisfied: the end LBA of the i-th entry in the range table 31 and the LBA specified by the key search request belong to the same cluster, and the end LBA indicated by the entry does not match the end LBA of the cluster. In this case, the RLB update judgment circuit 1610 first compares the logical product of the end LBA and LBA mask of the i-th entry in the range table 31 with the logical product of the LBA and LBA mask specified by the key search request. This makes it possible to judge whether the end LBA of the i-th entry in the range table 31 and the LBA specified by the key search request belong to the same cluster. If the ending LBA of the i-th entry in the range table 31 and the LBA specified by the key search request belong to the same cluster, the RLB update determination circuit 1610 compares the ending LBA indicated by the i-th entry with the ending LBA of the cluster, and determines whether the condition that the ending LBA indicated by the i-th entry does not match the ending LBA of the cluster is satisfied.

[0170] (2) The RLB update judgment circuit 1610 judges whether the condition that the start LBA of the i-th entry in the range table 31 and the LBA specified by the key search request belong to the same cluster and the start LBA indicated by the entry does not match the start LBA of the cluster is satisfied. In this case, the RLB update judgment circuit 1610 first compares the logical product of the start LBA and LBA mask of the i-th entry in the range table 31 with the logical product of the LBA and LBA mask specified by the key search request. This makes it possible to judge whether the start LBA of the i-th entry in the range table 31 and the LBA specified by the key search request belong to the same cluster. If the start LBA of the i-th entry in the range table 31 and the LBA specified by the key search request belong to the same cluster, the RLB update judgment circuit 1610 compares the start LBA indicated by the i-th entry with the start LBA of the cluster and judges whether the condition that the start LBA indicated by the i-th entry does not match the start LBA of the cluster is satisfied.

[0171] The RLB update determination circuit 1610 determines whether or not at least one of the conditions in step S24 is satisfied (step S25).

[0172] If at least one of the conditions in step S24 is satisfied (Yes in step S25), the RLB update decision circuit 1610 outputs no update as the RLB update decision (step S26).

[0173] Then, the RLB update determination circuit 1610 ends the RLB update determination process (END).

[0174] If any of the determinations in step S22 is No (No in step S23) or none of the determinations in step S24 is satisfied (No in step S25), the RLB update determination circuit 1610 determines whether the value of the variable (i) is equal to the number of entries in the range table 31 minus 1 (step S27). In other words, it determines whether the entry indicated by the variable (i) corresponds to the last entry in the range table 31.

[0175] If the value of the variable (i) is equal to the number of entries in the range table 31 minus 1 (Yes in step S27), the RLB update decision circuit 1610 outputs an RLB update decision indicating that the update should be performed (step S28).

[0176] Then, the RLB update determination circuit 1610 ends the RLB update determination process (END).

[0177] If the value of the variable (i) is different from the number of entries in the range table 31 minus 1 (No in step S27), the RLB update determination circuit 1610 increments the value of the index (i) by 1 (step S29).

[0178] After that, the RLB update determination circuit 1610 executes the process from step S22 onwards again, thereby making it possible to determine whether the range boundaries of multiple ranges set in the range table 31 are included within the batch search range that includes the LBA specified by the key search request.

[0179] Such an operation of the RLB update determination circuit 1610 detects whether the key search results are the same across a batch search unit (for example, a cluster including 8 LBAs), and is controlled so that the RLB 1612 is updated only if they are the same. The RLB update determination circuit 1610 also determines whether the received key search request hits the contents held in the RLB 1612 based on whether the LBA specified by the key search request and the LBA held in the RLB 1612 are included in the same batch search unit.

[0180] If it is not detected whether the key search results are the same across the batch search units, the RLB 1612 can be treated as a hit only when the LBA specified by the received key search request exactly matches the LBA stored in the RLB 1612. However, by detecting whether the key search results are the same across the batch search units, the hit rate of the RLB 1612 can be increased.

[0181] Next, a description will be given of the key search process when the memory system 3 receives a write command. Fig. 15 is a diagram showing a specific example of a key search operation executed for each LBA included in the access range specified by an access request from the host.

[0182] 15, range 1 and range 2 are set in namespace NS3. The start LBA of range 1 is LBA0, and the end LBA of range 1 is LBA99. The start LBA of range 2 is LBA100, and the end LBA of range 2 is LBA199.

[0183] Furthermore, the LBA space of namespace NS3 includes multiple clusters, each including eight consecutive LBAs. Here, cluster 10 includes LBA88, LBA89, ..., LBA95, cluster 11 includes LBA96, LBA97, ..., LBA103, and cluster 12 includes LBA104, LBA105, ..., LBA111.

[0184] Here, it is assumed that the memory system 3 receives a write command. This write command specifies NS3 as the NSID, LBA90 as the starting LBA, and 20 as the number of LBAs (NLBA).

[0185] At this time, the key search circuit 16 executes a key search process for each LBA specified by the write command. Here, a case will be described in which the key search circuit 16 executes the key search process in order from the start LBA 90. At this time, it is assumed that the RLB 1612 of the key search circuit 16 does not hold the search result.

[0186] First, the key search circuit 16 executes a key search process for a key search request that specifies LBA90. Here, the RLB Hit determination circuit 1609 determines that the RLB 1612 does not hold the search result, so that it is a miss. Then, the RLB update determination circuit 1610 executes an update determination process. The cluster 10 that includes LBA90 belongs only to range 1, and the cluster 10 does not include the start LBA and end LBA of range 1, and the start LBA and end LBA of range 2. The RLB update determination circuit 1610 determines that the RLB 1612 is to be updated. As a result, the RLB 1612 holds the key search request that specifies LBA90 and the search result corresponding to LBA90. Since the cluster 10 does not include a range boundary, the search result corresponding to LBA90 is a search result common to all eight LBAs included in the cluster 10.

[0187] Next, the key search circuit 16 executes a key search process for a key search request that specifies LBA 91. Since the RLB hit determination circuit 1609 holds the search result corresponding to LBA 90, it determines a hit for the key search request that specifies LBA 91, which is included in the same cluster as LBA 90. Therefore, the key search circuit 16 uses the search result stored in the RLB 1612 to respond to the key search request that specifies LBA 91.

[0188] The key search circuit 16 performs the same processing for key search requests specifying LBAs 92, 93, 94, and 95 as for a key search request specifying LBA 91.

[0189] Next, the key search circuit 16 executes a key search process for a key search request that specifies LBA96. Since the RLB1612 holds the search result corresponding to LBA90, the RLB Hit judgment circuit 1609 judges a miss for the key search request that specifies LBA96 included in a different cluster. Then, the RLB update judgment circuit 1610 executes an update judgment process. Since the cluster 11 that includes LBA96 includes the start LBA and the end LBA of range 1 and range 2, the RLB update judgment circuit 1610 outputs a judgment that no update is performed. Therefore, the key search circuit 16 does not update the search result stored in the RLB1612, but responds to the key search request that specifies LBA96 using the search result obtained by the normal judgment circuit 1605.

[0190] The key search circuit 16 performs the same processing for key search requests specifying LBA 97, 98, . . . and 103 as for a key search request specifying LBA 96.

[0191] Next, the key search circuit 16 executes a key search process for a key search request that specifies LBA 104. Here, the RLB Hit determination circuit 1609 determines a miss because the RLB 1612 holds the search result corresponding to LBA 90. Then, the RLB update determination circuit 1610 executes an update determination process. Because the cluster 12 that includes LBA 104 does not include the start LBA and end LBA of range 1 and range 2, the RLB update determination circuit 1610 outputs a determination to perform an update. As a result, the RLB 1612 holds the search result corresponding to LBA 104.

[0192] Next, the key search circuit 16 executes a key search process for the key search request that specifies LBA 105. Since the RLB hit determination circuit 1609 holds the search result corresponding to LBA 104, it determines a hit for the key search request that specifies LBA 105 included in the same cluster. Therefore, the key search circuit 16 uses the search result stored in the RLB 1612 to respond to the key search request that specifies LBA 105.

[0193] The key search circuit 16 performs the same processing for key search requests specifying LBAs 106, 107, 108, and 109 as for key search requests specifying LBA 105.

[0194] As described above, according to the embodiment, the key search circuit 16 can refer to the range table 31 based on the LBA specified by the received key search request, and store the acquired access permission information and encryption key in the RLB 1612. When the received key search request hits the contents held in the RLB 1612, the key search circuit 16 can output the search result including the access permission information and the encryption key held in the RLB 1612.

[0195] This allows the key search circuit 16 to skip the normal judgment process by the normal judgment circuit 1605 and output a search result including the accessibility information and the encryption key. This makes it possible to reduce the time required to search for the accessibility information and the encryption key.

[0196] Also, according to the embodiment, the RLB update determination circuit 1610 determines whether to update the contents held in the RLB 1612 based on whether the range boundaries of multiple ranges are included in the batch search unit that includes the LBA specified by the received key search request. Also, the RLB Hit determination circuit 1609 determines whether the received key search request hits the contents held in the RLB 1612 based on whether the LBA specified by the received key search request and the LBA held in the RLB 1612 are included in the same batch search unit. This makes it possible to use the contents held in the RLB 1612 as the search result not only when the LBA specified by the received key search request matches the LBA held in the RLB 1612, but also when, for example, the cluster including the LBA specified by the received key search request matches the cluster including the LBA held in the RLB 1612. Therefore, it is possible to increase the hit rate of the RLB 1612.

[0197] In this embodiment, the RLB update determination circuit 1610 sequentially searches all the entries of the range table 31 independently of the normal determination process by the normal determination circuit 1605. However, the conditions under which the RLB update determination circuit 1610 operates are the same as the conditions under which the normal determination circuit 1605 operates, and since the normal determination circuit 1605 also needs to search all the entries of the range table 31, the normal determination process and the RLB update determination process may be performed simultaneously by arranging both in the same design module. In addition, when an error is detected in the normal determination process by the normal determination circuit 1605 such that range information corresponding to the key search request is not found and a corresponding encryption key does not exist, the RLB 1612 may be controlled not to be updated. Furthermore, in this embodiment, the case where the number of entries included in the RLB 1612 is 1 is exemplified, but the RLB 1612 may be configured to include multiple entries and may be configured as a full associative or set associative.

[0198] The embodiments are illustrative and the scope of the invention is not limited thereto. [Explanation of symbols]

[0199] 1...information processing system, 2...host, 3...memory system, 4...controller, 5...storage device, 11...host interface circuit, 12...CPU, 13...NAND interface circuit, 16...key search circuit 16, 18...encryption / decryption circuit 18, 1601...key search request input circuit 1601, 1602, 1604...register, 1603, 1606, 1611...selector, 1605...normal judgment circuit, 1608...encryption key output circuit, 1609...RLB Hit judgment circuit, 1610...RLB update judgment circuit.

Claims

1. 1. A memory system connectable to a host, comprising: The apparatus includes a storage device, an encryption / decryption circuit, and a key search circuit, The encryption / decryption circuit includes: configured to generate ciphertext data to be written to the storage device by encrypting plaintext data received from the host using the encryption key obtained by the key search circuit, and to generate the plaintext data by decrypting the ciphertext data read from the storage device using the encryption key obtained by the key search circuit; The key search circuit includes: in response to receiving from the encryption / decryption circuit a key search request specifying a logical block address specified by an access request received from the host and an access type indicating whether the access request is a read or write, outputting to the encryption / decryption circuit access permission information indicating permission or prohibition of access to the logical block address specified by the received key search request and an encryption key to be used by the encryption / decryption circuit, The key search circuit includes: a range table for holding, for each of a plurality of ranges set in a logical block address space of the memory system, information indicating a range of consecutive logical block addresses included in the range, access permission information indicating permission or prohibition of access to the range, and an encryption key to be applied to data corresponding to the range; a search result buffer for storing a search result including access permission information and an encryption key, the search result being obtained by referring to the range table based on a key search request, together with the key search request; and managing the search result buffer. The key search circuit further comprises: a hit determination circuit that determines whether the received key search request hits the contents held in the search result buffer; an update determination circuit for determining whether to update the contents held in the search result buffer; When the hit determination circuit determines that the received key search request hits the contents stored in the search result buffer, the hit determination circuit outputs the search result stored in the search result buffer to the encryption / decryption circuit; when the hit determination circuit determines that the received key search request does not hit the contents stored in the search result buffer, by referring to the range table based on the received key search request, obtain a search result from the range table, the search result including access permission information indicating permission or prohibition of access to the logical block address specified by the received key search request and an encryption key to be applied to data corresponding to the logical block address, and output the obtained search result to the encryption / decryption circuit; If the update determination circuit determines that the contents held in the search result buffer should be updated, the contents held in the search result buffer are updated with the received key search request and the search result acquired from the range table. It is configured as follows: Memory system.

2. The update determination circuit includes: and determining whether to update the contents held in the search result buffer based on whether a range boundary of the plurality of ranges is included within a batch search unit including the logical block address specified by the received key search request, the batch search unit being one of a plurality of batch search units obtained by dividing a logical block address space for accessing the memory system into units including a predetermined number of consecutive logical block addresses; The hit determination circuit includes: and determining whether the received key search request hits the contents held in the search result buffer based on whether the logical block address specified by the received key search request and the logical block address specified by the key search request held in the search result buffer are included in the same batch search unit.

2. The memory system of claim 1.

3. The hit determination circuit includes: If the logical block address specified by the received key search request and the logical block address specified by the key search request stored in the search result buffer are included in the same batch search unit, it is determined that the received key search request has hit the contents stored in the search result buffer; When the logical block address specified by the received key search request and the logical block address specified by the key search request stored in the search result buffer are not included in the same batch search unit, it is determined that the received key search request has not hit the contents stored in the search result buffer.

3. The memory system of claim 2.

4. Each of the plurality of batch search units is a cluster including eight consecutive logical block addresses.

3. The memory system of claim 2.

5. The key search circuit includes: receiving from the encryption / decryption circuit a number of key search requests equal to the number of logical block addresses included in an access range specified by the access request received from the host, each key search request specifying one logical block address included in the access range and an access type indicating whether the access request is a read or write; Each time a key search request is received from the encryption / decryption circuit, access permission information indicating permission or prohibition of access to the logical block address specified by the received key search request and an encryption key to be used by the encryption / decryption circuit are output to the encryption / decryption circuit.

2. The memory system of claim 1.

6. The access request from the host specifies an identifier of a namespace to be accessed, a start logical block address indicating a first sector included in an access range, and a number of logical block addresses included in the access range; Each of the multiple key search requests includes an identifier of the namespace, one logical block address included in the access range, and an access type indicating whether the access request is a read or write request.

6. The memory system of claim 5.

7. The storage device is a non-volatile semiconductor memory.

2. The memory system of claim 1.

8. The storage device is a magnetic disk medium.

2. The memory system of claim 1.

9. 1. A memory system connectable to a host, comprising: The apparatus includes a storage device, an encryption / decryption circuit, and a key search circuit, The encryption / decryption circuit includes: configured to generate ciphertext data to be written to the storage device by encrypting plaintext data received from the host using the encryption key obtained by the key search circuit, and to generate the plaintext data by decrypting the ciphertext data read from the storage device using the encryption key obtained by the key search circuit; The key search circuit includes: receiving from the encryption / decryption circuit a number of key search requests equal to the number of logical block addresses included in an access range specified by an access request received from the host, each key search request specifying one logical block address included in the access range and an access type indicating whether the access request is a read or write; each time a key search request of the plurality of key search requests is received, access permission information indicating permission or prohibition of access to the logical block address specified by the received key search request and an encryption key to be applied to data corresponding to the logical block address are output to the encryption / decryption circuit; The key search circuit includes: a range table for holding, for each of a plurality of ranges set in a logical block address space of the memory system, information indicating a range of consecutive logical block addresses included in the range, access permission information indicating permission or prohibition of access to the range, and an encryption key to be applied to data corresponding to the range; a search result buffer for storing a search result including access permission information and an encryption key, the search result being obtained by referring to the range table based on a key search request, together with the key search request; and managing the search result buffer. The key search circuit further comprises: a hit determination circuit for determining whether the received key search request hits the contents stored in the search result buffer based on whether the logical block address designated by the received key search request and the logical block address designated by the key search request stored in the search result buffer are included in the same batch search unit; an update determination circuit that determines whether to update the contents held in the search result buffer based on whether a range boundary of the plurality of ranges is included within a batch search unit that includes the logical block address specified by the received key search request, the batch search unit being one of a plurality of batch search units obtained by dividing a logical block address space for accessing the memory system into units including a predetermined number of consecutive logical block addresses; When the hit determination circuit determines that the received key search request hits the contents stored in the search result buffer, the hit determination circuit outputs the search result stored in the search result buffer to the encryption / decryption circuit; when the hit determination circuit determines that the received key search request does not hit the contents stored in the search result buffer, by referring to the range table based on the received key search request, obtain a search result from the range table, the search result including access permission information indicating permission or prohibition of access to the logical block address specified by the received key search request and an encryption key to be applied to data corresponding to the logical block address, and output the obtained search result to the encryption / decryption circuit; When the update determination circuit determines that the contents held in the search result buffer should be updated, the contents held in the search result buffer are updated with the received key search request and the search result acquired from the range table. It is configured as follows: Memory system.

10. Each of the plurality of batch search units is a cluster including eight consecutive logical block addresses.

10. The memory system of claim 9.

11. The access request from the host specifies an identifier of a namespace to be accessed, a start logical block address indicating a first sector included in an access range, and a number of logical block addresses included in the access range; Each of the multiple key search requests includes an identifier of the namespace, one logical block address included in the access range, and an access type indicating whether the access request is a read or write request.

10. The memory system of claim 9.

12. The storage device is a non-volatile semiconductor memory.

10. The memory system of claim 9.

13. The storage device is a magnetic disk medium.

10. The memory system of claim 9.

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