Chemical Etching of Nonvolatile Materials for MRAM Patterning

Abstract

A method is provided in which a substrate disposed in a chamber is exposed to a halogen-containing gas containing an element selected from the group consisting of silicon, germanium, carbon, titanium, and tin, a plasma is ignited to modify the surface of the substrate to form a modified surface, and the substrate is exposed to an activated gas to etch at least a portion of the modified surface.

Description

[Background technology]

[0001] [CROSS REFERENCE TO RELATED APPLICATIONS] This application claims the benefit of priority to U.S. Patent Application No. 62 / 881,131, filed July 31, 2019. The above application is incorporated herein by reference for all purposes.

[0002] The background art provided herein is intended to provide a general background to the present disclosure. The contents of this background art, and possibly each aspect described in the specification, are not admitted, either explicitly or implicitly, to be prior art with respect to the present application.

[0003] Semiconductor manufacturing processes involve the etching of various materials, including metals and metal alloys. However, as devices become smaller and structures become more complex to manufacture, some of the etched by-products can redeposit on other exposed areas of the substrate, causing defects and ultimately device failure. As a result, other etching techniques have become popular.

[0004] In the etching of a memory stack, different metal-containing layers are etched. Dielectric layers may be placed between the different metal-containing layers. These different metal layers need to be etched in a way that minimizes redeposition. Summary of the Invention

[0005] To achieve the above and in accordance with the purpose of the present disclosure, a method is provided. A substrate disposed in a chamber is exposed to a halogen-containing gas containing an element selected from the group consisting of silicon, germanium, carbon, titanium, and tin. In this specification and claims, a halogen-containing gas containing an element selected from the group consisting of silicon, germanium, carbon, titanium, and tin means that the gas has molecules, the molecules having at least one atom of a halogen and at least one atom of at least one of the group consisting of silicon, germanium, carbon, titanium, and tin. A plasma is ignited to modify the surface of the substrate to form a modified surface. The substrate is exposed to an activated gas to etch at least a portion of the modified surface.

[0006] In another aspect, an apparatus for etching features of a stack is provided. A plasma chamber is provided. A substrate support is provided within the plasma chamber. A supply system supplies gas to the plasma chamber. A gas source supplies the gas to the supply system. The gas source includes a halogen-containing gas source and an activated gas source. An electrode supplies radio frequency (RF) power to the plasma chamber. At least one RF generator is connected to the electrode. A controller is controllably connected to the gas source and the at least one RF generator. The controller includes at least one processor and a computer readable medium including computer readable code for etching at least a portion of the stack. The computer readable code includes computer readable code for flowing a halogen-containing gas comprising an element selected from the group consisting of silicon, germanium, carbon, titanium, and tin from the halogen-containing gas source into the plasma chamber; computer readable code for igniting a plasma from the halogen-containing gas to modify a surface of the substrate to form a modified surface; a computer readable medium for flowing an activation gas from the activation gas source; and computer readable code for activating the activation gas to form an activated activated gas in the plasma chamber and etching at least a portion of the modified surface.

[0007] These and other features of the present disclosure are described in more detail below in the detailed description of the present disclosure in conjunction with the following drawings. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a schematic diagram of an exemplary substrate.

[0009] [Diagram 2] FIG. 2 is a process flow diagram illustrating method steps performed in accordance with an embodiment of the present disclosure.

[0010] [Figure 3A] FIG. 3A is a schematic diagram of an exemplary substrate during processing according to an embodiment of the present disclosure. [Figure 3B] FIG. 3B is a schematic diagram of an exemplary substrate during processing according to an embodiment of the present disclosure. [Figure 3C] FIG. 3C is a schematic diagram of an exemplary substrate during processing in accordance with an embodiment of the present disclosure. [Figure 3D] FIG. 3D is a schematic diagram of an exemplary substrate during processing according to an embodiment of the present disclosure. [Figure 3E] FIG. 3E is a schematic diagram of an exemplary substrate during processing according to an embodiment of the present disclosure. [Figure 3F] FIG. 3F is a schematic diagram of an exemplary substrate during processing in accordance with an embodiment of the present disclosure. [Figure 3G] FIG. 3G is a schematic diagram of an exemplary substrate during processing according to an embodiment of the present disclosure.

[0011] [Figure 4A] FIG. 4A is a schematic diagram of an exemplary mechanism for etching a substrate in accordance with certain embodiments of the present disclosure. [Figure 4B] FIG. 4B is a schematic diagram of an exemplary mechanism for etching a substrate in accordance with certain embodiments of the present disclosure. [Figure 4C]FIG. 4C is a schematic diagram of an exemplary mechanism for etching a substrate in accordance with certain embodiments of the present disclosure. [Figure 4D] FIG. 4D is a schematic diagram of an exemplary mechanism for etching a substrate in accordance with certain embodiments of the present disclosure. [Figure 4E] FIG. 4E is a schematic diagram of an exemplary mechanism for etching a substrate in accordance with certain embodiments of the present disclosure. [Figure 4F] FIG. 4F is a schematic diagram of an exemplary mechanism for etching a substrate in accordance with certain embodiments of the present disclosure. [Figure 4G] FIG. 4G is a schematic diagram of an exemplary mechanism for etching a substrate in accordance with certain embodiments of the present disclosure. [Figure 4H] FIG. 4H is a schematic diagram of an exemplary mechanism for etching a substrate in accordance with certain embodiments of the present disclosure. [Figure 4I] FIG. 4I is a schematic diagram of an exemplary mechanism for etching a substrate in accordance with certain embodiments of the present disclosure. [Figure 4J] FIG. 4J is a schematic diagram of an exemplary mechanism for etching a substrate in accordance with certain embodiments of the present disclosure. [Figure 4K] FIG. 4K is a schematic diagram of an exemplary mechanism for etching a substrate in accordance with certain embodiments of the present disclosure.

[0012] [Figure 4L] FIG. 4L is a schematic diagram of a metal silo composite.

[0013] [Diagram 5] FIG. 5 is a schematic diagram of an exemplary process chamber for practicing embodiments of the present disclosure.

[0014] [Figure 6] FIG. 6 is a schematic diagram of an exemplary process apparatus for practicing embodiments of the present disclosure.

[0015] [Figure 7] FIG. 7 is a graph illustrating the etch rate of a CoPt material exposed to SiCl 4 and He, versus He sputtering alone, from experiments performed in accordance with certain embodiments of the present disclosure.

[0016] [Figure 8] FIG. 8 is a schematic diagram of another plasma processing chamber used in another embodiment.

[0017] [Figure 9] FIG. 9 is a schematic diagram of a computer system that can be used to implement one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] In the following description, numerous specific details are provided to provide a detailed understanding of the embodiments presented. The embodiments of the present disclosure may be practiced without some or all of these specific details. In other instances, well-known process steps are not described in detail to avoid unnecessarily obscuring the embodiments of the present disclosure. It is to be understood that the embodiments of the present disclosure are described in connection with specific embodiments, but are not intended to limit the scope of the embodiments of the present disclosure.

[0019] In semiconductor wafer processing, features may be etched through metal-containing layers. In the formation of magnetic random access memories (MRAM), multiple thin metal layers or films may be etched in succession to form magnetic tunnel junction stacks.

[0020] A magnetic tunnel junction (MTJ) consists of a thin layer of a dielectric barrier between two magnetic materials. Electrons pass through the barrier by quantum tunneling. This can be used as the basis for magnetic-based memory.

[0021] Spin transfer torque is an effect by which the orientation of a magnetic layer in an MTJ can be changed using a spin-polarized current. Charge carriers (e.g. electrons) have a property known as spin, which is a small amount of angular momentum inherent to the carrier. The current is normally unpolarized (having 50% spin-up electrons and 50% spin-down electrons). By passing a current through a thick magnetic layer (commonly called the "pinned layer"), a spin-polarized current can be generated, with more electrons of one spin or the other. Directing this spin-polarized current through a second, thinner magnetic layer (the "free layer") transfers angular momentum to this layer, allowing it to change its orientation. This effect can be used to excite vibrations or even flip the orientation of a magnetic material.

[0022] Spin transfer torque can be used to flip the active element in a magnetic random access memory. Spin transfer torque magnetic random access memory (STT-RAM or STT-MRAM) has the advantages of lower power consumption and higher scalability compared to conventional magnetoresistive random access memory (MRAM), which flips the active element using a magnetic field. Spin transfer torque technology may enable MRAM devices that are both low current consumption and low cost. Ralph, DC, Stiles, MD, "Spin transfer torques," Journal of Magnetism and Magnetic Materials, Vol. 320, No. 7, pp. 1190-1216 (April 2008).

[0023] An example of an MTJ stack is shown in FIG. 1. FIG. 1 shows a stack 100 including a silicon oxide etch stop layer 101, a tantalum nitride barrier layer 103, a ruthenium metal layer 105, a pinned layer 107, a dielectric layer 109, a free layer 111, a tantalum layer 113, and another ruthenium metal layer 115. As shown, an MTJ stack 120 is comprised of a free layer 111, a dielectric layer 109, and a pinned layer 107. It is noted that although specific chemistries are shown in FIG. 1, other suitable chemistries may be present in such a stack. The free and pinned layers may include metals and / or metal alloys, such as cobalt iron or cobalt platinum. The dielectric layer 109 is adjacent to the pinned layer 107 and the free layer 111.

[0024] One of the key unsolved challenges in the high density scaling of Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) is the patterning of MRAM stacks. MRAM stacks contain non-volatile ferromagnetic materials such as cobalt (Co), iron (Fe), manganese (Mn), nickel (Ni), platinum (Pt), palladium (Pd), and ruthenium (Ru), which are extremely difficult to pattern without complex techniques using ion beam etching (IBE), reactive ion etching (RIE), and wet chemistry. Despite years of development, current patterning techniques still suffer from many shortcomings, including sidewall redeposition resulting in tapering and shorting to the pinned layer of the MTJ, and damage to the MTJ layer due to corrosion. Some conventional techniques use chlorine-containing chemistries to etch metals, but the etched by-products contain non-volatile compounds that can later redeposit on the sidewalls of the features.

[0025] As described herein, in MRAM applications, the materials used for the free and pinned layers of MRAM are primarily cobalt-iron-boron (CoFeB), cobalt-platinum alloy (CoPt), and other non-volatile metals. A magnesium oxide (MgO) layer is a critical layer between the free and pinned layers, which is highly sensitive in electrical and magnetic properties and is easily damaged by halogen plasma processes. Therefore, etching processes using physical sputtering with ion beam etching can have adverse effects on each layer of the MRAM stack. Sputtering processes have challenges. For example, in some cases, redeposition of metal materials can occur, which can affect yield. Also, in some cases, metal species can redeposit along the sidewalls during etching, creating short paths in the MTJ. Similarly, redeposition at the etch front can create shunt paths connecting pillars. In some cases, aspect ratios are limited, making the process inapplicable for smaller device sizes. For example, as the pitch gets smaller, pattern transfer using IBE can become difficult due to ion shading from neighboring pillars, since angled ions have a harder time reaching the etch front and the bottom of the pillars, which can affect the etch profile. In some cases, iso-dense loading can occur because sputtering is more efficient in iso-dense regions that are free of transport limitations for reactants and by-products. Iso-dense means that the region has a uniform density.

[0026] Etching non-volatile metals such as Co, CoFe, and CoPt is challenging because the common by-products of metal halides are not volatile. This paper addresses current issues with IBE technology by forming volatile by-products to chemically etch such materials used in devices.

[0027] The present disclosure provides a chemical etching approach to etch MRAM stacks using an atomic layer etching (ALE) process with a gas having molecules containing halogen and one or more of silicon, germanium, titanium, carbon, and tin. For example, the ALE chemical process used in certain embodiments of the present disclosure may include two steps: (i) modifying a surface with a silicon and chlorine-containing plasma (such as silicon tetrachloride (SiCl4)); and (ii) removing the modified surface by forming volatile by-products using directional ions. While an example of modification using a silicon and halogen-containing plasma is described herein, it is understood that in various embodiments, a germanium and halogen-containing plasma or a tin and halogen-containing plasma may be used. The use of an ALE process using SiCl4 fundamentally overcomes the various challenges described above in processing non-volatile metals for MRAM patterning.

[0028] ALE is a technique that uses a sequential self-limiting reaction to remove a thin layer of material. ALE may generally be performed by any suitable technique. The concept of an "ALE cycle" is relevant to the description of various embodiments herein. An ALE cycle generally refers to a set of a minimum number of steps used to perform an etching process once, such as etching a single layer. A cycle is performed to etch a film layer on a substrate surface by a predictable and fixed amount. An ALE cycle typically includes a modification step to form a modified layer, followed by a removal step to remove or etch only the modified layer. An ALE cycle may include certain auxiliary steps, such as cleaning either the reactants or by-products. A cycle generally includes one instance of a sequence of steps. As an example, an ALE cycle may include the steps of (i) supplying a reactive gas to a chamber, (ii) purging the reactive gas from the chamber, (iii) supplying a removal gas and optionally a plasma, and (iv) purging the chamber. In some embodiments, the etching may be performed non-conformally.

[0029] The disclosed methodology provides conformality and etch uniformity of MRAM features, as well as precise control of etch rate and prevention of MTJ damage. As described herein, volatile etch byproducts typically occur when materials such as Si react with halogens such as Cl and metal ions in a near stoichiometric manner to form M-SiCl. x where M can be Co, Fe, Mn, Ni, Pt, Pd, or Ru. In some embodiments, the attachment of a silyl group (-SiCl x ) adhesion, M-SiCl x The melting / boiling points of the species are greatly reduced and their partial pressures, especially in vacuum, are greatly increased.

[0030] Using near-stoichiometric amounts of reactants avoids adverse effects on the process, such as too much silicon (Si) flux in the plasma, which can lead to Si deposition and M-SiCl x Conversely, if there is too little Si, for example, M-SiCl x The formation of species is inhibited, thus suppressing the etch rate. Similarly, the addition of excess chloride (Cl) to a metal surface will result in the formation of metal chlorides such as cobalt(II) chloride (CoCl2) and ferric chloride (FeCl3), which are non-volatile (boiling points above 1200 °C).

[0031] According to one embodiment, a halide and / or halogen-containing gas and a near stoichiometric amount of a material that reacts with the metal to form a volatile species are deposited on the metal (e.g., CoFe) surface in a chamber by an atomic layer deposition (ALD) process. Examples of materials include silicon nitride (SiN), silicon oxide (SiO2), Si, and titanium dioxide (TiO2). In the ALE process, the deposited Si layer and the metal surface are activated with Cl as chlorine (Cl2) or boron trichloride (BCl3). The excess Cl2 is then pumped out of the chamber. In some embodiments, an argon (Ar) desorption may be performed to bombard and further activate the chlorinated surface to form volatile metal silyl species. The metal silyl species are then pumped out of the chamber. The etch rate is maximized when the Si and Cl reactants are stoichiometrically matched. In some embodiments, the ALE and ALD steps may be performed in the same chamber or in different chamber modules in the tool without breaking vacuum.

[0032] In certain embodiments of the present disclosure, non-volatile etch products (e.g., MClx) are not formed. Conventional plasma processes using halogens react with metals to form non-volatile MClx species, which react with magnesium oxide (MgO) layers and cause damage. In certain embodiments of the present disclosure using SiCl4 plasma, the etch reaction can form volatile species with the metal-silo composite. The metal-silo composite is M-SiCl x The metal silo compound is a volatile by-product that improves chemical etching. This breakthrough brings "non-volatile metals" that were previously dependent on physical sputtering processes into the realm of plasma etching.

[0033] The non-volatile etching products formed in the sputtering process are shown in Reaction 1 below. M+Cl→MClx(s) (non-volatile) (1)

[0034] The volatile etch profile formed in certain embodiments of the present disclosure is shown below in Equation 2. M+SiClx → M-SiClx (volatile) (2)

[0035] In various embodiments, the metal designated as M in the formulas described herein may be any one or more of Co, Pt, Pd, Fe, Cr, and Ir.

[0036] SiCl4-based etch chemistries can also be incorporated into the ALE process for MRAM patterning to minimize damage to the MTJ. The SiCl4-based ALE process includes two cycleable steps. These two steps are aspiration with SiCl4 plasma to modify the metal surface to form a modified metal surface. arrival and an ion bombardment step that forms volatile etch byproducts and removes the modified metal surface. In such an ALE process, the etch front and sidewall surfaces are reset after each ALE cycle by removing the modified surface. Damage to the MTJ layer can be reduced by etching the metal surface layer by layer, rather than by constant exposure to chemical reactants.

[0037] Other types of plasma chemistries using different precursors can also be used to deliver the Si and Cl species. Non-limiting examples of Si precursors include silane (SiH4), SixRy (where R is Cl, fluorine (F), bromine (Br), or iodine (I)), and Si i H j R k(i is an integer between 1 and 4, j is an integer between 1 and 10, and k is an integer between 1 and 10). Optionally, x is an integer between 1 and 10, and y=2x+2. In some embodiments, the substituents on the silicon atom of the silane include at least one halogen, and the remaining substituents are any one or more of hydrogen, chlorine, fluorine, bromine, and iodine. The silane may be a cyclosilane or a linear silane. Any suitable halosilane may be used. The halosilane includes at least one halogen group and may or may not include hydrogen and / or carbon groups. Examples of halosilanes include iodosilane, bromosilane, chlorosilane, hydrochlorosilane, and fluorosilane. Although halosilanes, particularly fluorosilanes, may form reactive halide species during plasma generation to etch silicon materials, in some embodiments, the halosilane may not be introduced into the chamber during plasma generation to reduce the formation of reactive halide species from the halosilane. Specific examples of chlorosilanes include tetrachlorosilane, trichlorosilane, dichlorosilane, monochlorosilane, chloroallylsilane, chloromethylsilane, dichloromethylsilane, chlorodimethylsilane, chloroethylsilane, t-butylchlorosilane, di-t-butylchlorosilane, chloroisopropylsilane, chloro-sec-butylsilane, t-butyldimethylchlorosilane, thexyldimethylchlorosilane, SiHCl-(N(CH3)2)2, and the like.

[0038] The process can also be used for etching and device processing of other non-volatile materials besides MRAM stacks.

[0039] In some embodiments, certain embodiments of the present disclosure provide various advantages. One advantage is that certain embodiments of the present disclosure minimize residual metal redeposition. The selected etching chemistry forms volatile by-products, which minimizes sputtering due to redeposition, compared to physical sputtering processes that cause sidewall redeposition. At the same time, chemical etching removes the metal layer, overcoming the problem of metal residues remaining or redeposition at the etch front.

[0040] Another advantage is that certain embodiments of the present disclosure can pattern MRAM stacks with minimal loading effects. The ALE chemical etching process with SiCl4 plasma can provide minimal loading in MRAM patterning. IBE processes typically provide more efficient and denser array etching with iso-density. ALE with SiCl4 can provide aspect ratio independent recesses between MRAM pillars.

[0041] Yet another advantage is that certain embodiments of the present disclosure allow for scaling to narrow pitches. For example, the pitch may be narrower than 200 nm, or 100 nm, or 50 nm, or 20 nm, or 10 nm, or 5 nm. A major challenge with IBE physical sputtering processes is the difficulty in scaling the process to produce narrow pitch devices. Ion beam patterning becomes significantly less efficient in pattern transfer when the pitch reaches a shape equivalent to the angle of the ion beam. In contrast, ALE chemical etching with SiCl4 opens up a larger patterning window without the limitations of ion shading from the mask.

[0042] Next, the embodiments of the present disclosure will be described in more detail with reference to some specific embodiments. FIG. 2 is a process flow chart for carrying out steps according to the embodiments of the present disclosure. FIGS. 3A-3G are schematic diagrams of an exemplary stack etched according to the embodiments of the present disclosure. FIGS. 4A-4K are schematic diagrams of an exemplary mechanism for performing etching according to the embodiments of the present disclosure. Although FIGS. 4A-4K are illustrated with an example of etching a metal layer, the embodiments of the present disclosure may be used to etch a variety of materials, such as semiconductive, conductive, and dielectric materials. Furthermore, it should be understood that FIGS. 4A-4K are merely exemplary mechanisms, and the present disclosure or claims are not limited by any particular theory of operation. These figures are described collectively.

[0043] Referring to FIG. 2, at step 202, a substrate is provided. The substrate may be a silicon wafer and a stack of various layers is provided on the silicon wafer. The silicon wafer may be a 200 mm wafer, a 300 mm wafer, or a 450 mm wafer. The stack may include one or more layers of materials, such as dielectric materials, conductive materials, semiconductive materials, etc. In various embodiments, the substrate is patterned. The patterned substrate may have "features" such as pillars, poles, trenches, vias, contact holes, etc. These features may be characterized by one or more of narrow and / or reentrant openings, constrictions within the features, and high aspect ratios. The features may be formed in one or more of the layers mentioned above. An example of a feature is a pillar or pole formed in a semiconductor wafer or a layer on the wafer. Another example is a trench formed in a substrate or layer. In various embodiments, the features may include an underlying layer, such as a barrier layer or an adhesion layer. Non-limiting examples of underlayers include dielectric layers and conductive layers, such as silicon oxides, silicon nitrides, silicon carbides, metal oxides, metal nitrides, metal carbides, and metal layers.

[0044] In some embodiments, features such as pillars may have an aspect ratio of at least about 1:1, at least about 2:1, at least about 4:1, at least about 6:1, at least about 10:1, or more. Features may also have dimensions near the opening, such as opening diameter or line width, between about 10 nm and 500 nm, such as between about 25 nm and about 300 nm. The methods of the present disclosure may be performed on substrates with features having openings of less than about 150 nm. Vias, trenches, or other recessed features may be referred to as unfilled features or features. According to various embodiments, the shape of the feature may narrow gradually and / or have an overhang at the feature opening. A reentrant shape is a shape that narrows from the bottom, closed end, or interior of the feature toward the feature opening. Reentrant shapes may be formed due to asymmetric etching operations during patterning and / or overhangs resulting from non-conformal film step coverage during a previous film deposition, such as deposition of a diffusion barrier. In various examples, a feature may have an opening that is narrower at the top than it is at the bottom.

[0045] In some embodiments, the patterned substrate may have various topographies across the substrate. In some embodiments, a partially fabricated gate may be present on the substrate. In various embodiments, the substrate may include layers of metal, dielectric, and semiconductor materials suitable for etching MRAM stacks in subsequent processing. For example, some substrates may have an MRAM design in which the memory element includes an MTJ. As described elsewhere herein, the MTJ memory element includes two electrodes separated by a thin tunnel barrier. The two electrodes may be thin ferromagnetic layers, which may be elliptical. In some embodiments, the MTJ memory element includes additional magnetic layers. For example, the MTJ memory element may further include a pair of ferromagnetic layers sandwiching a thin metal layer, which may be referred to as a synthetic antiferromagnet and an antiferromagnetic layer. Further description of the shapes and designs of exemplary MRAM memory elements that can be fabricated on a substrate by the methods described herein is provided in "Cell Shape and Patterning Considerations for Magnetic Random Access Memory (MRAM) Fabrication" (Ditizio, Robert et al.), published in Semiconductor Manufacturing Magazine, pages 90-96.

[0046] Returning to Figure 2, in step 202, the substrate may be prepared by wet etching. For example, in Figure 3B, a wet etch is performed to etch a first metal layer 315 on the substrate. In some embodiments, a wet etch is not performed.

[0047] FIG. 3A illustrates an example of an MRAM stack that may be present as part of a substrate described herein. Note that while exemplary chemistries for each stack are shown, any other suitable materials may be present in place of or in combination with these chemistries. For example, embodiments of the present disclosure may be used to etch materials for different patterns (e.g., non-MRAM patterns). Note that while exemplary layers are shown in FIGS. 3A-3G, embodiments of the present disclosure may be used to etch other materials on a surface while reducing redeposition of non-volatile by-products on components of the substrate.

[0048] The substrate 300 includes an etch stop layer 301 made of SiO2. The etch stop layer 301 may be disposed over other layers (not shown) of the substrate 300. A thin barrier layer 303 made of tantalum nitride (TaN) is disposed over the etch stop layer 301 in the stack. A metal layer 305 including ruthenium (Ru) is disposed over the TaN barrier layer 303. In some embodiments, the metal layer 305 may have a thickness of about 8 nm. A metal or metal alloy layer 307 is disposed over the Ru metal layer 305. The metal alloy layer 307 may include cobalt platinum (CoPt). In some embodiments, the metal alloy layer 307 may include PtMn. This layer 307 may be referred to herein as a "pinning layer" 307. In some embodiments, the pinning layer 307 may have a thickness of about 10-30 nm. Also shown in FIG. 3A is a dielectric barrier layer 309. The dielectric barrier layer 309 may include MgO. The dielectric barrier layer 309 may be referred to herein as the "dielectric layer" 309. In some embodiments, the dielectric layer 309 may be an extremely thin layer, for example having a thickness of about 1.5 nm or less.

[0049] A metal alloy layer 311 is provided on the dielectric layer 309. The metal alloy layer 311 may include cobalt iron (CoFe). The metal alloy layer 311 may include CoFeB. The metal alloy layer 311 may be referred to herein as the "free layer." A tantalum (Ta) barrier layer 313 is provided on the free layer 311. A Ru metal layer 315 is provided on the Ta barrier layer 313. In embodiments disclosed herein, the Ru metal layer 315 may be referred to as the "first metal layer" and the Ru metal layer 305 may be referred to as the "second metal layer." A Ta hard mask 317 may be deposited and etched into a pattern as shown in FIG. 3A. It is noted that the hard mask 317 need not necessarily be a tantalum hard mask. For example, other suitable hard masks include carbon-containing hard masks, nitrogen-containing hard masks, and oxygen-containing hard masks.

[0050] Returning to FIG. 2, in step 204, a material is optionally conformally deposited on the substrate. The material reacts with a halide and / or halogen-containing gas and a material of the layer of the substrate to form a volatile species. In some embodiments, the material reacts with one or more halide and / or halogen-containing gas and one or more materials of the layer of the substrate to form a volatile species. For example, the material may react with a cobalt-containing metal and a mixture of BCl3 and Cl2 to form a volatile species. The material serves as both a material source for forming a volatile species and a protective layer for the substrate. In the following description, the conformal material may be referred to as a "protective layer," but it is understood that the protective layer may be conformal, including a material that reacts with a halide and / or halogen-containing gas and a material on the substrate to form a volatile species.

[0051] The protective layer, optionally deposited in step 202, includes an element capable of forming a metal halide and a volatile species. The protective layer may include a Group IV transition metal-containing material. For example, the protective layer may be a silicon-containing layer, a titanium-containing layer, a germanium-containing layer, a tin-containing layer, a carbon-containing layer, or any combination thereof. Examples of silicon-containing layers include silicon oxide, silicon nitride, amorphous silicon, polysilicon, and mixtures thereof. Examples of titanium-containing layers include titanium oxide, titanium nitride, titanium, and mixtures thereof. In some embodiments, the protective layer is a dielectric material.

[0052] The protective layer may be deposited by any suitable method, including chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), plasma enhanced ALD (PEALD), spin-on deposition, and sputtering. In some embodiments, the protective layer is a material source for reacting with halides and / or halogens and metal-containing compounds to form volatile species. For example, a Si source may be introduced to the MRAM surface using gases such as SiH4, SiCl4, or liquids such as orthosilicate compounds (e.g., tetraethylorthosilicate (TEOS), spin-on glass (SOG), hexamethyldisilazane (HMDS)) to react by methods other than ALD, such as PVD, PECVD, spin-coating processes.

[0053] For example, the protective layer may be deposited by PECVD, such as by exposing the substrate to a silicon-containing precursor and a nitrogen-containing reactant simultaneously in a plasma. For example, the substrate may be exposed to silane and nitrogen plasma simultaneously. Any suitable precursor and reactant capable of depositing a protective layer including any of the above-mentioned chemicals may be used to deposit the protective layer.

[0054] 3C illustrates a protective layer 320 deposited on the substrate 300. Note that while protective layer 320 is illustrated, in some embodiments this layer may be optional. In some embodiments, protective layer 320 may be a first protective layer (e.g., in some processes, a separate protective layer 320 may be deposited). Note that protective layer 320 is shown as conformal. In some embodiments, protective layer 320 may not be conformal. In some embodiments, a portion of protective layer 320 may be a sacrificial layer.

[0055] FIG. 4A is another example of a schematic representation of a portion of a substrate 400. In this example, the substrate 400 includes a metal layer 411. The metal layer 411 may include, for example, Co, Fe, Mn, Pd, Pt, alloys thereof, and combinations thereof. Here, a first metal layer of Ru is wet etched, and a silicon-containing protective layer 420 (e.g., a Si source) is deposited over the tantalum hard mask and the metal layer 411. Note that although the silicon-containing protective layer 420 is provided, this layer may be optional in some embodiments, particularly those in which the etching chemistry used during modification includes silicon. Note that the substrate of FIG. 4A is similar to FIG. 3C, but omits the tantalum barrier layer for ease of illustration. Although specific examples of layers are shown in FIG. 4A, any suitable metal may be provided under the hard mask, and the hard mask may be of any composition. Additionally, any suitable protective layer 420 may be used in embodiments of the present disclosure, and such protective layer is not limited to a silicon-containing layer as shown in FIG. 4A.

[0056] Returning to FIG. 2, in step 206, the substrate is exposed to a halogen-containing reactant to modify the surface of the substrate. In various embodiments, in step 206, the substrate is exposed to a plasma containing a group IV element (e.g., silicon) and a halogen. That is, in various embodiments, a silicon- and halogen-containing plasma is used in step 206 without a prior deposition of a protective layer, or a halogen-containing reactant is used in step 206 after a protective layer is deposited. One advantage of using a silicon- and halogen-containing plasma instead of depositing a protective layer is that it allows for a reduction in the number of steps required to achieve layer-by-layer etching. Thus, the metal surface can be etched without first depositing a protective layer, which streamlines the process for patterning the MRAM stack.

[0057] The silicon and halogen-containing plasma may be generated by introducing a silicon and halogen-containing gas, such as a halosilane, and igniting the plasma. In some embodiments, the plasma is remotely generated. In some embodiments, the plasma is generated in situ. The plasma may be generated using either an ICP plasma or a CCP plasma.

[0058] The plasma may be generated using a plasma power of about 100 watts (W) to about 900 W. The exposure may be for a time sufficient to adsorb at least 60%, at least 70%, at least 80%, at least 90%, or 100% of the substrate surface. The temperature during this step may be about 60° C. to about 200° C. The chamber pressure during this step may be about 1 milliTorr (mTorr) to about 500 mTorr. The flow rate of the silicon- and halogen-containing precursor may be about 5 standard cubic centimeters per minute (sccm) to about 200 sccm. In some embodiments, a carrier gas such as helium may be used. The flow rate of the carrier gas may be about 50 sccm to about 500 sccm. In some embodiments, the silicon- and halogen-containing precursor may include helium. In some embodiments, a bias may be provided. In some embodiments, the bias may be pulsed. The bias may be in the range of 100 V to 2000 V.

[0059] Non-limiting examples of Si precursors include SiH4, SixRy (where R is Cl, F, Br, or I), and Si i H j R kOptionally, x is an integer between 1 and 10, and y=2x+2. In some embodiments, the substituents on the silicon atom of the silane include at least one halogen, and the remaining substituents are any one or more of hydrogen, chlorine, fluorine, bromine, and iodine. The silane may be a cyclosilane or a linear silane. Any suitable halosilane may be used. The halosilane includes at least one halogen group and may or may not include hydrogen and / or carbon groups. Examples of halosilanes include iodosilane, bromosilane, chlorosilane, and fluorosilane. Although halosilanes, particularly fluorosilanes, may form reactive halide species during plasma generation to etch silicon materials, in some embodiments, the halosilane may not be introduced into the chamber during plasma generation to reduce the formation of reactive halide species from the halosilane. Specific examples of chlorosilanes include tetrachlorosilane, trichlorosilane, dichlorosilane, monochlorosilane, chloroallylsilane, chloromethylsilane, dichloromethylsilane, chlorodimethylsilane, chloroethylsilane, t-butylchlorosilane, di-t-butylchlorosilane, chloroisopropylsilane, chloro-sec-butylsilane, t-butyldimethylchlorosilane, thexyldimethylchlorosilane, SiHCl-(N(CH3)2)2, and the like.

[0060] In FIG. 4G, a cobalt-containing surface (such as CoPt) is exposed to a silicon- and halogen-containing plasma generated using SiCl4, optionally in a helium environment. Without being limited to a particular theory, it is believed that the plasma dissociates the SiCl4 molecules to generate chlorine and Si-Cl species. As shown in FIG. 4H, a pulsed bias is applied to etch the cobalt-containing surface, generating volatile CoSiCl xSpecies are formed. The bias is pulsed with a particular duty cycle to enhance the synergistic effect of the ALE reaction. The bias may be applied with a voltage between 100V and 2000V. The duty cycle is the time that the bias is ON during a period. The bias may be pulsed between an ON state and an OFF state, or between a high state and a low state. The high state may have a voltage between about 200V and about 2000V. The low state may have a voltage between about 0V or just 0V and about 200V. It is understood that the bias pulse may include repeated periods, each of which may last for a duration T. The duration T includes the duration of the pulse ON time (duration of the ON state of the bias) and the duration of the bias OFF time (duration of the OFF state of the bias) during a given period. The pulse frequency is understood as 1 / T. For example, if the bias pulse has a period T=100 μs, then the frequency is 1 / T=1 / 100 μs, or 10 kilohertz (kHz). The duty cycle or duty ratio is the fraction or percentage of time T during which the bias is ON, and the pulse ON time divided by T is the duty cycle or duty ratio. For example, if the bias pulse has a period T=100 μs, then a pulse ON time of 70 μs (duration of the bias ON state for a period of 70 μs) and a pulse OFF time of 30 μs (duration of the bias OFF state for a period of 30 μs) would result in a duty cycle of 70%. Figure 7 shows an example of experimental data obtained by varying the bias voltage, comparing the etch rate from exposure to SiCl4-He to the etch rate from helium sputtering of a CoPt surface using bias pulses alone, as well as the overall synergistic percentage of these processes. Overall, the bias pulse reduces the sputtering rate and increases the SiCl4 chemical etching component.

[0061] Figure 4I shows the SiCl x Plasma-assisted SiCl x FIG. 1 is a diagram showing an example of SiCl adsorbed on a cobalt surface.x The plasma is ignited and the reactive species produced adsorb onto the cobalt surface. In some embodiments, a bias is applied during this adsorption operation. In FIG. 4J, a bias is used to introduce activated argon, which removes the modified surface, as shown in FIG. 4K. The result is the volatile metal silo complex by-product CoSiCl. x 4L shows an example of a volatile metal silo complex by-product that can be formed according to certain embodiments of the present disclosure. The silo complex includes at least one metal atom, at least one silicon atom, and at least one halogen atom.

[0062] In some embodiments, the halogen-containing reactant does not include silicon atoms. In many such embodiments, the silicon source is delivered through a protective layer of silicon-containing material. Such silicon-free halogen-containing reactants may include boron halogen-containing gases, halogen-containing gases, halide gases, and combinations thereof. Examples of these include BCl3, boron tribromide (BBr3), boron triiodide (BI3), Cl2, fluorine (F2), bromine (Br2), and iodine (I2). An example gas combination may be BCl3 / Cl2. The halogen-containing reactant may react with and / or adsorb to the protective layer. For example, a protective layer of silicon may react with the halogen-containing reactant to form a silicon halide on the surface of the substrate. Note that in some embodiments, the halogen-containing reactant may saturate at least about 90% of the substrate, or at least about 99% of the substrate. In some embodiments, the halogen-containing reactant may conformally adsorb to the surface of the substrate. As an example, chlorine atoms and / or molecules may adsorb onto the surface of the silicon-containing protective layer.

[0063] 4B is an exemplary schematic diagram illustrating how chlorine molecules 450a of Cl2 react with the protective layer 420 and adsorb to the surface of the protective layer 420 to form an adsorbed layer 450b on the surface. In the exemplary substrate 400 shown in FIG. 4B, the arrows indicate the direction in which the Cl2 molecules 450a move toward the surface of the substrate 400 and adsorb to or react with the surface of the substrate 400. The bias may be provided at a power of less than about 100V or less than about 60V (e.g., about 50V).

[0064] In step 208 of FIG. 2, the substrate is exposed to an activation gas to etch the modified surface of the substrate. In various embodiments, the activation gas may include one or more inert gases, such as argon, carbon dioxide, ammonia, hydrogen-containing gas, and combinations thereof. In step 208, an activation source, such as a plasma, is generated to activate the activation gas, and the activated activation gas is provided to etch the substrate. In various embodiments, the activated activation gas is provided by at least one of forming a plasma from the activation gas, forming an ion beam from the activation gas, and thermally activating the activation gas. In step 208 of FIG. 2, the surface perpendicular to the direction of the bias etch, on which the halogen-containing compound is adsorbed, may be completely etched. In some embodiments, a low bias may be applied to perform directional etching of the substrate. For example, the bias may be provided at a power of less than about 100 V (e.g., about 50 V). The power of the plasma may be about 500 W to about 1500 W.

[0065] In FIG. 4C, the etched compound including silicon chloride 470 is removed from the horizontal surfaces of the field region of the tantalum hard mask, and the deposited conformal or protective layer 420 is removed to reveal the exposed metal layer 411. Note that, as shown in FIG. 4C, a portion of the protective layer deposited on the sidewalls of the hard mask and the first metal layer (here Ta and Ru, respectively) remains on the sidewalls. This residual protective layer may act as a continuous protective layer for the hard mask from damage or degradation due to any by-products that may be generated by the etching reaction.

[0066] As a result, the substrate of FIG. 3C after steps 206 and 208 may have the structure shown in FIG. 3D. As shown in FIG. 3D, a directional etch may be performed such that a portion of the protective layer 322 remains on the sidewalls of the feature while one or more layers below it (e.g., the tantalum barrier layer 313 and most of the CoFe free layer 311) are etched. Note that in various embodiments, the CoFe free layer 311 is not completely etched because the dielectric layer 309 is easily etched away and prevents the etching from proceeding to the sides of the feature. For example, if the substrate includes a MgO-containing dielectric layer 309 adjacent to the free layer 311, the free layer 311 may be etched such that about 0 Å to about 10 Å remains on the substrate. Note that in various embodiments, the various steps are performed in cycles to etch away these layers of the substrate.

[0067] For example, as shown in FIG. 2, steps 206-208 may be optionally repeated at step 210. In some embodiments, the repetition of steps 206 and 208 may constitute one cycle. For example, in some embodiments, steps 206 and 208 may be repeated two or more cycles. Each cycle may be performed to etch about 1 Å to about 10 Å per cycle, such as about 6 Å per cycle. Thus, in some embodiments, the substrate shown in FIG. 3C may be etched using cycles of steps 206 and 208 on the surface of the substrate perpendicular to the direction of the directional etch performed by the application of the bias. For example, as shown in FIG. 3C, steps 206 and 208 may be repeated to etch the conformal or protective layer 320, the tantalum barrier layer 313, and most of the CoFe / CoFeB free layer 311. As mentioned above, the cycle of steps 206 and 208 may be stopped before completely etching the CoFe / CoFeB free layer 311 to protect the MgO dielectric layer 309, or may be continued until the MgO dielectric layer 309 is completely etched.

[0068] In FIG. 3E, step 208 may be performed without exposing the substrate to a halogen-containing gas to etch a thin layer of the CoFe / CoFeB free layer 311 and etch the MgO dielectric layer 309. In some embodiments, step 208 is performed by exposing the substrate to a non-halogen-containing gas. In various embodiments, the dielectric layer is etched by sputtering argon gas with a bias to avoid performing a harsh etch chemistry on the dielectric layer. In some embodiments, applying a harsh etch chemistry to the dielectric layer may etch the dielectric layer below the mask, which may cause degradation and device failure issues. In some embodiments, a bias is applied during the dielectric etch. For example, the bias may be provided with a power of less than about 100V (e.g., about 50V).

[0069] 4D-4F are schematic diagrams of an exemplary etching mechanism when steps 206 and 208 of FIG. 2 are repeated at step 210, following FIG. 4C. FIG. 4D shows a substrate 400 on which step 206 has been repeated. After the metal layer 411 is exposed in FIG. 4C, the substrate is exposed to Cl2 450a in FIG. 4D to modify its surface. As shown, Cl2 may adsorb or react with the surface of the substrate 400 to form an adsorbed layer of chlorine 450b. Note that since the protective layer 420 from the previous deposition of the silicon-containing material remains on the sidewall, some of the chlorine 450b may adsorb or react with the protective layer 420, and some of the chlorine 450b may adsorb or react with the metal surface 411.

[0070] FIG. 4E shows the substrate after step 208 has been repeated. As shown, argon (e.g., an activated gas) 440 is introduced to the substrate and a plasma is ignited to etch the substrate. In various embodiments, a bias is applied to directionally etch the substrate, as indicated by the arrows in FIG. 4E. The presence of the silicon-containing protective layer 420 causes a complex 475 to form between the adsorbed chlorine 450b and the metal of the metal surface 411. It should be noted that not all complexes 475 have the same chemical structure, although in this example, the protective layer 420 provides silicon to form volatile species 475 that can be purged from the chamber in which the substrate is processed. In various embodiments, the protective layer 420 may additionally or alternatively include other materials, such as titanium, germanium, or other materials that react with metals and halide and / or halogen gases to form volatile species.

[0071] In some embodiments, during ALE etching with Si, a SiO2 / SiN protective layer (such as protective layer 420 in FIG. 4A) is deposited on the MRAM metal surface. The Si-doped metal surface (shown in FIG. 4B) is then activated with BCl3 / Cl2 gas (such as molecular chlorine 450a) to form an adsorbed layer of chlorine (450b). A directional Ar ion beam of Ar gas (440) bombards the modified layer, breaking it in the process and allowing new bonds to form, ultimately forming volatile etch products (M-SiCl x ) (475) is desorbed into the gas phase.

[0072] In summary, an exemplary activation reaction may be as follows:

number

[0073] An exemplary desorption / recombination reaction may be as follows:

number

[0074] M-SiCl x The stability and volatility of the composite allows it to withstand Ar sputter desorption without decomposing to the metallic form, thereby reducing or avoiding sidewall redeposition.

[0075] The embodiments of the present disclosure include depositing a material that reacts with a halide and / or halogen-containing gas and a metal to form a volatile species. The material can be, for example, a silicon-containing material, a titanium-containing material, a germanium-containing material, a tin-containing material, a carbon-containing material, and combinations thereof. In some embodiments, the deposited material can be a silicon-containing material, such as amorphous silicon, polysilicon, silicon oxide, silicon nitride, and the like. In some embodiments, the deposited material can be titanium or titanium oxide.

[0076] The embodiments of the present disclosure are also suitable for etching a variety of other materials, including fixed layers (CoPt, CoPd, PtMn), as well as Co, Fe, Mn, Pt, Ru, and Ta. The principles of the present disclosure are applicable to all other first, second, and third row transition metals (e.g., group IV, V, and VI transition metals), including metals such as Cu. Other stable gaseous compounds, such as those in the same group IV (e.g., Ge and Sn), may exhibit similar behavior.

[0077] Besides Si, other group IV elements in the periodic table (e.g., C, Ge, Sn) can be used to form similar volatile etching products, e.g., M-CCl x Stable volatile species such as M-GeClX, M-SnClX, etc. can also be formed in the plasma. These reactants can be introduced as halide gases such as CClX, SiClX, GeClX, and SnClX (where X is a halogen (e.g., F, Cl, or Br with various stoichiometric ratios)) or other sources that allow deposition of these elements onto the MRAM metal surface.

[0078] Activation, formation, and desorption of volatile metal etch products may be accomplished by methods other than ALE. In some embodiments, methods such as reactive ion etching (RIE), electron cyclotron resonance etching (ECR), or thermal desorption and UV processes may be used. Embodiments of the present disclosure may be integrated with wet etching and / or reactive ion etching processes.

[0079] 4F shows the substrate after the layer of metal surface 411 has been etched. Note that portions of protective layer 420 may also be etched as steps 206 and 208 are performed in various cycles.

[0080] Thus, steps 204-210 may be optionally repeated at step 212 of Figure 2. In this manner, after forming a first conformal material at step 204, a second conformal material is deposited on the substrate at step 204 by repeating the process to provide additional material that reacts with the halide and / or halogen-containing gas and metal of the substrate to form volatile species.

[0081] 3F illustrates an example substrate corresponding to step 212. As shown, step 204 is repeated to further deposit a second protective layer 324 over the substrate, which may serve to further protect the Ta barrier layer 313, the CoFe free layer 311, and the etched MgO dielectric layer 309.

[0082] Thus, steps 206 and 208 may be repeated (also in cycles) until the remainder of the substrate is etched down to the etch stop layer. FIG. 3G shows the substrate after etching, where steps 206 and 208 have been repeated in cycles to etch the CoPt pinning layer 307, the second Ru metal layer 305, and the TaN barrier layer 303. Note that the substrate 300 shown has protective layers 322 and 324 remaining on the sidewalls. In various embodiments, these layers may be reduced or removed after fabrication of the stack. In some embodiments, some or a portion of these layers may be etched when practicing embodiments of the present disclosure.

[0083] While this disclosure is not limited by any theory, it is believed that the deposition-etch mechanism of MRAM metals (e.g., Co, Fe, Mn, Pd, and Pt) can proceed as follows: This mechanism involves the introduction of Si during ALE with Cl and Ar (e.g., provided by BCl3 and / or Cl2) to dry chemically etch these metals without redepositing them on the sidewalls. As discussed above, without being limited by any particular theory, the presence of halide and / or halogen-containing gases and Si or other materials that react with the metals may result in the formation of Co-SiCl. x , Fe-SiCl x It is believed that volatile etch products such as argon, argon dioxide, and argon gas are formed. These products have a high partial pressure in the etch chamber and can be easily evacuated.

[0084] [Device] In the following, an inductively coupled plasma (ICP) reactor that may be suitable for use in atomic layer etching (ALE) and atomic layer deposition (ALD) processes in certain embodiments is described. Such an ICP reactor is also described in U.S. Patent Application Publication No. 2014 / 0170853, entitled "IMAGE REVERSAL WITH AHM GAP FILL FOR MULTIPLE PATTERNING," filed December 10, 2013, which is incorporated herein by reference in its entirety for all purposes. Although an ICP reactor is described herein, it should be understood that in some embodiments, a capacitively coupled plasma reactor may be used.

[0085] FIG. 5 is a schematic cross-sectional view of an inductively coupled plasma integrated etch and deposition apparatus 500 suitable for carrying out certain embodiments herein. An example of such an apparatus is the Kiyo® Reactor manufactured by Lam Research Corp. (Fremont, Calif.). The inductively coupled plasma apparatus 500 includes an overall process chamber 524 defined by a chamber wall 501 and a window 511. The chamber wall 501 may be made of stainless steel or aluminum. The window 511 may be made of quartz or other dielectric material. An optional internal plasma grid 550 divides the overall process chamber into an upper subchamber 502 and a lower subchamber 503. In most embodiments, the plasma grid 550 may be removed, thereby utilizing the chamber space of the subchambers 502 and 503. A chuck 517 is disposed near the interior bottom surface of the lower subchamber 503. The chuck 517 is configured to receive and hold a semiconductor substrate or wafer 519 on which the etch and deposition processes are performed. The chuck 517 may be an electrostatic chuck that supports the wafer 519 when placed thereon. In some embodiments, an edge ring (not shown) surrounds the chuck 517. The top surface of the edge ring is approximately coplanar with the top surface of the wafer 519 when placed on the chuck 517. The chuck 517 further includes an electrostatic electrode for chucking and dechucking the wafer 519. For this purpose, a filter and DC clamp power supply (not shown) may be provided. Other control systems may also be provided for lifting the wafer 519 from the chuck 517. The chuck 517 may be charged by an RF power supply 523. The RF power supply 523 is connected to a matching circuit 521 via a connection 527. The matching circuit 521 is connected to the chuck 517 via a connection 525. In this manner, the RF power supply 523 is connected to the chuck 517.

[0086] The elements for plasma generation include a coil 533 disposed above the window 511. In some embodiments, a coil is not used in the embodiments of the present disclosure. The coil 533 is made of a conductive material and includes at least one complete turn. The example coil 533 shown in FIG. 5 includes three turns. A cross section of the coil 533 is symbolized, with the "X" coils rotating into the page and the "●" coils rotating toward the page. The elements for plasma generation further include an RF power source 541 configured to provide RF power to the coil 533. The RF power source 541 is typically connected to a matching circuit 539 via a connection 545. The matching circuit 539 is connected to the coil 533 via a connection 543. In this manner, the RF power source 541 is connected to the coil 533. An optional Faraday shield 549 is disposed between the coil 533 and the window 511. The Faraday shield 549 is maintained at a distance from the coil 533. The Faraday shield 549 is positioned directly above the window 511. The coil 533, the Faraday shield 549, and the window 511 are configured to be approximately parallel to one another. The Faraday shield 549 may prevent metals or other species from depositing on the window 511 of the process chamber 524.

[0087] Process gases (e.g., halide gases, halogen-containing gases, silicon and halogen-containing gases, germanium and halogen-containing gases, tin and halogen-containing gases, silicon tetrachloride, chlorine, argon, silicon tetrachloride, oxygen, nitrogen, etc.) may be flowed into the process chamber through one or more main gas inlets 560 located in the upper subchamber 502 and / or through one or more side gas inlets 570. Similarly, similar gas inlets, not shown, may be used to supply process gases to the capacitively coupled plasma processing chamber. A vacuum pump (e.g., a one or two stage mechanical dry pump and / or turbomolecular pump 540) may be used to draw process gases from the process chamber 524 and maintain pressure within the process chamber 524. For example, the vacuum pump may be used to evacuate the lower subchamber 503 during the ALD purge step. A valve-controlled conduit may be used to fluidly connect the vacuum pump to the process chamber 524 to selectively control application of a vacuum environment by the vacuum pump. This may be accomplished by a closed loop controlled flow control device such as a throttle valve (not shown) or a pendulum valve (not shown) during plasma process processing. Similarly, a vacuum pump and valve controlled fluid connections to a capacitively coupled plasma processing chamber may be used.

[0088] During operation of the apparatus 500, one or more process gases may be provided through the gas inlets 560 and / or 570. In certain embodiments, the process gas may be provided only through the main gas inlet 560 or only through the side gas inlet 570. In some cases, the illustrated gas inlets may be replaced with more complex gas inlets (e.g., one or more showerheads). The Faraday shield 549 and / or optional grid 550 may include internal channels and holes that allow the supply of process gases to the process chamber 524. Either or both of the Faraday shield 549 and optional grid 550 may function as a showerhead to supply process gases. In some embodiments, a liquid vaporization supply system may be located upstream of the process chamber 524. In this case, once the liquid reactant or precursor is vaporized, the vaporized reactant or precursor is introduced into the process chamber 524 through the gas inlets 560 and / or 570.

[0089] Radio frequency power is supplied to the coil 533 from an RF power source 541, causing an RF current to flow through the coil 533. The RF current flowing through the coil 533 generates an electromagnetic field around the coil 533. This electromagnetic field generates an induced current in the upper subchamber 502. Physical and chemical interactions of the various ions and radicals generated with the wafer 519 etch features in the wafer 519 and deposit layers on the wafer 519.

[0090] When a plasma grid 550 is used in both the upper subchamber 502 and the lower subchamber 503, the induced current acts on the gas in the upper subchamber 502 to generate an electron-ion plasma in the upper subchamber 502. The optional internal plasma grid 550 limits the number of hot electrons in the lower subchamber 503. In some embodiments, the apparatus 500 is designed and operated such that the plasma in the lower subchamber 503 is an ion-ion plasma.

[0091] Both the upper electron-ion plasma and the lower ion-ion plasma may contain positive and negative ions, but the ion-ion plasma has a greater proportion of negative ions than positive ions. Volatile etch and / or deposition by-products may be removed from the lower sub-chamber 503 via port 522. The chuck 517 disclosed herein may operate at elevated temperatures ranging from about 10° C. to about 250° C. The temperature depends on the process step and the specific recipe.

[0092] The tool 500 may be coupled to equipment (not shown) when installed in a clean room or manufacturing facility. The equipment includes plumbing to provide process gases, vacuum, temperature control, and environmental particle control. These equipment will be coupled to the tool 500 when the tool 500 is installed in the target manufacturing facility. Additionally, the tool 500 may be coupled to a transfer chamber that robotically transfers semiconductor wafers into and out of the tool 500 using conventional automation.

[0093] In some embodiments, a system controller 530 (which may include one or more physical or logical controllers) controls some or all of the operation of the process chamber 524. The system controller 530 may include one or more memory devices and one or more processors. In some embodiments, the apparatus 500 includes a switching system for controlling flow rates and times when performing embodiments of the present disclosure. In some embodiments, the apparatus 500 may have a switching time of up to about 500 ms, or up to about 750 ms. The switching time may depend on the flow chemistry, the selected recipe, the reactor configuration, and other factors.

[0094] In some implementations, the system controller 530 is part of a system, which may be part of the examples described above. Such systems may include semiconductor processing equipment, including one or more processing tools, one or more chambers, one or more processing platforms, and / or specific processing components (such as a wafer pedestal and gas flow systems). These systems may be integrated with electronics to control the operation of the system before, during, and after processing of a semiconductor wafer or substrate. Electronics may be integrated into the system controller 530 to control various components or subparts of one or more systems. The system controller 530 may be programmed to control any of the processes disclosed herein depending on the processing parameters and / or type of system. These processes include supply of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow settings, fluid supply settings, position and motion settings, wafer loading and unloading from the tool, and wafer loading and unloading from other transfer tools and / or load locks connected or associated with the particular system.

[0095] Broadly, the system controller 530 may be defined as an electronic device having various integrated circuits, logic, memory, and / or software to receive instructions, send instructions, control operations, enable cleaning operations, enable endpoint measurements, etc. The integrated circuits may include chips as firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors or microcontrollers that execute the program instructions (e.g., software). The program instructions may be instructions communicated to the controller as various individual settings (or program files) that define the operating parameters for performing a particular process on or for a semiconductor wafer or for the system. In some embodiments, the operating parameters may be part of a recipe defined by a process engineer to accomplish one or more processing steps in the manufacture and removal of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or wafer dies.

[0096] In some implementations, the system controller 530 may be part of or coupled to a computer, where the computer is integral to the system, coupled to the system, or otherwise networked to the system, or a combination thereof. For example, the controller may reside on the "cloud" or in all or part of a fab host computer system. This allows remote access of wafer processing. The computer may enable remote access to the system to monitor the progress of a manufacturing process, examine past manufacturing process history, or examine trends or performance indicators from multiple manufacturing processes, change parameters of a current process, set up a process step following a current process, or start a new process. In some examples, a process recipe may be provided to the system from a remote computer (e.g., a server) over a network, where the network may include a local network or the Internet. The remote computer may include a user interface that allows for entry or programming of parameters and / or settings. These parameters and / or settings are then communicated from the remote computer to the system. In some examples, the system controller 530 receives instructions as data, where the data specifies parameters for each process step to be performed in one or more operations. It should be understood that these parameters may be specific to the type of process being performed and the type of tool the controller is configured to cooperate with or control. Thus, as described above, the system controller 530 may be distributed, such as by having one or more individual controllers that are networked together and operate toward a common purpose, such as the process and control described herein. One example of a distributed controller for such a purpose includes one or more integrated circuits mounted on the chamber that communicate with one or more integrated circuits located remotely (e.g., at the platform level or as part of a remote computer).These integrated circuits work together to control the process in the chamber.

[0097] Non-limiting examples of systems include a plasma etch chamber or module, a deposition chamber or module, a spin rinse chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an ALD chamber or module, an ALE chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing system that may be associated with or usable in the manufacturing and / or production of semiconductor wafers.

[0098] As described above, depending on one or more process steps being performed by the tool, the controller may communicate with one or more of other tool circuits or tool modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, another controller, or tools used in material transport to and from wafer containers to tool locations and / or load ports within a semiconductor manufacturing factory.

[0099] FIG. 6 illustrates a semiconductor process cluster architecture with various modules in communication with a Vacuum Transfer Module (VTM) 638. The arrangement of various modules that "transfer" wafers between multiple storage facilities and process modules may be referred to as a "cluster tool architecture" system. An airlock 630, also known as a load lock or transfer module, in communication with the VTM 638, which in turn in communication with four processing modules 620a-620d. The processing modules 620a-620d may be individually optimized to perform various manufacturing processes. As an example, the processing modules 620a-620d may be implemented to perform substrate etching, deposition, ion implantation, wafer cleaning, sputtering, and / or other semiconductor processes. In some embodiments, ALD and ALE are performed in the same module. In some embodiments, ALD and ALE are performed in different modules in the same tool. One or more of the substrate etching processing modules (any of 620a-620d) may be implemented as disclosed herein. That is, they may be implemented to perform conformal film deposition, selective film deposition by ALD, etching patterns, and other suitable functions according to embodiments of the present disclosure. Airlock 630 and processing modules 620a-620d may be referred to as "stations." Each station includes a facet 636 that interfaces the station with a VTM 638. Within each facet, sensors 1-18 detect the passage of wafer 626 as it moves between the respective stations.

[0100] A robot 622 transfers wafers 626 between stations. In one embodiment, the robot 622 has one arm, and in another embodiment, the robot 622 has two arms, each arm with an end effector 624 to pick a wafer, such as wafer 626, for transfer. A front-end robot 632 in an atmospheric transfer module (ATM) 640 is used to transfer wafers 626 from a cassette or front opening unified pod (FOUP) 634 in a load port module (LPM) 642 to an airlock 630. A module center 628 in a process module 620a-620d provides one location for depositing wafers 626. An aligner 644 in the ATM 640 aligns the wafer.

[0101] In an exemplary processing method, a wafer is placed in one of the FOUPs 634 in the LPM 642. The front-end robot 632 transfers the wafer from the FOUP 634 to the aligner 644, which properly centers the wafer 626 before etching or processing. After alignment, the wafer 626 is moved by the front-end robot 632 into the airlock 630. The airlock 630 provides environmental matching between the ATM 640 and the VTM 638, allowing the wafer 626 to move between the two pressure environments without being damaged. From the airlock 630, the wafer 626 is moved by the robot 622 through the VTM 638 to one of the processing modules 620a-620d. To accomplish this wafer movement, the robot 622 uses end effectors 624 on each of its arms. Once the wafer 626 has been processed, it is moved by the robot 622 from the processing modules 620a-620d to the airlock 630. From here, the wafer 626 may be moved by the front-end robot 632 to one of the FOUPs 634 or to the aligner 644.

[0102] It should be noted that the computer controlling the movement of the wafers may be located within the cluster structure, may be located outside the cluster structure at the production site, or may be located at a remote location and connected to the cluster structure via a network. The controller described above with reference to Figure 5 may be implemented in the tool of Figure 6.

[0103] [experiment] [Experiment 1] In experiments, CoPt surfaces were modified by exposure to SiCl4-He plasma, and the modified surfaces were then exposed to biased activated helium and sputtered with bias pulses only. Such experiments were performed at various bias voltages to evaluate the etch rate of the CoPt surface. The synergistic effect of these etching processes was also confirmed. In some embodiments, the synergistic effect of ALE is 65%-80%.

[0104] Figure 7 shows experimental data obtained by varying the bias voltage, comparing the etch rate from exposure to SiCl4-He with that from helium sputtering of a CoPt surface using bias pulses alone, and showing the overall synergistic percentage of these processes. Overall, the bias pulse reduces the sputtering rate and increases the SiCl4 etching chemical component.

[0105] 8 is a schematic diagram illustrating another example of a plasma processing chamber system 800 that can be used in an embodiment. The plasma processing chamber system 800 includes a plasma reactor 802. The plasma reactor 802 includes a plasma processing confinement chamber 804 therein. A plasma power supply 806 regulated by a plasma matching network 808 supplies power to a transformer coupled plasma (TCP) coil 810 located near a dielectric induced power window 812, which inductively couples power to generate a plasma 814 in the plasma processing confinement chamber 804. A top 872 extends from a chamber wall 876 of the plasma processing confinement chamber 804 to the dielectric induced power window 812 to form a top ring. The top 872 is angled with respect to the chamber wall 876 and the dielectric induced power window 812 such that the interior angles between the top 872 and the chamber wall 876 and between the top 872 and the dielectric induced power window 812 are greater than 90 degrees and less than 180 degrees. As shown, the top 872 provides a sloped ring near the top of the plasma processing confinement chamber 804. The TCP coil (top power) 810 may be configured to generate a uniform diffusion profile in the plasma processing confinement chamber 804. For example, the TCP coil 810 may be configured to generate an annular power distribution in the plasma 814. The dielectric induction power window 812 is provided to pass energy from the TCP coil 810 to the plasma processing confinement chamber 804 while isolating the TCP coil 810 from the plasma processing confinement chamber 804. A wafer bias voltage power supply 816 regulated by a bias matching network 818 provides power to the electrode 820 to set a bias voltage for the substrate 866. The substrate 866 is supported by the electrode 820. A controller 824 controls the plasma power supply 806 and the wafer bias voltage power supply 816.

[0106] The plasma power source 806 and the wafer bias voltage power source 816 may be configured to operate at a particular radio frequency, such as, for example, 13.56 megahertz (MHz), 27 MHz, 2 MHz, 60 MHz, 400 kilohertz (kHz), 2.54 gigahertz (GHz), or a combination thereof. The plasma power source 806 and the wafer bias voltage power source 816 may be appropriately sized to provide various ranges of power to achieve desired process performance. For example, in one embodiment, the plasma power source 806 may provide power in the range of 50-5000 watts, and the wafer bias voltage power source 816 may provide bias voltage in the range of 20-2000 volts (V). Furthermore, the TCP coil 810 and / or the electrode 820 may be comprised of two or more sub-coils or sub-electrodes. Also, the TCP coil 810 is a type of electrode for providing RF power into the confinement chamber 804. The sub-coils or sub-electrodes may be powered from a single power source or from multiple power sources.

[0107] 8, the plasma processing chamber system 800 further includes a gas source / gas supply mechanism 830. In this embodiment, the gas source 830 includes a halogen-containing gas source 832, an activated gas source 833, and a fluorine-containing gas source 834. 834, a group IV element-containing gas source 836, and a dielectric etch gas source 838. Here, the halogen-containing gas includes an element selected from the group consisting of silicon, germanium, carbon, titanium, and tin. The gas source 830 is in fluid communication with the plasma processing confinement chamber 804 via a gas inlet, such as a gas injector 840. The gas injector 840 may be located at any suitable location within the plasma processing confinement chamber 804 and may be in any form for injecting gas. However, preferably, the gas inlet may be configured to generate a "tunable" gas injection profile. The adjustable gas injection profile allows for independent adjustment of gas flow to multiple zones within the plasma processing confinement chamber 804. More preferably, the gas injector 840 is mounted to the dielectric-induced power window 812. The gas injector 840 may be mounted on, within, or form part of the dielectric-induced power window 312. Process gases and by-products are removed from the plasma processing confinement chamber 804 via a pressure control valve 842 and a pump 844. The pressure control valve 842 and pump 844 also function to maintain a particular pressure within the plasma processing confinement chamber 804. The pressure control valve 842 can maintain a pressure of less than 1 torr during processing. An edge ring 860 is positioned around the substrate 866. The gas source / gas delivery mechanism 830 is controlled by a controller 824. In one embodiment, a Kiyo manufactured by Lam Research Corp. (Fremont, Calif.) may be used.

[0108] FIG. 9 is a high-level block diagram of a computer system 900 suitable for implementing the controller 824 of FIG. 8 used in the embodiments. A computer system may have many physical forms ranging from integrated circuits, printed circuit boards, and small handheld devices to large supercomputers. The computer system 900 includes one or more processors 902 and may further include an electronic display device 904 (for displaying images, text, and other data), a main memory 906 (e.g., random access memory (RAM)), a storage device 908 (e.g., a hard disk drive), a removable storage device 910 (e.g., an optical disk drive), a user interface device 912 (e.g., a keyboard, touch screen, keypad, mouse or other pointing device, etc.), and a communication interface 914 (e.g., a wireless network interface). The communication interface 914 allows software and data to be transferred between the computer system 900 and external devices via a link. The system may also include a communication infrastructure 916 (e.g., a communication bus, crossover bar, or network) to which the above-mentioned devices / modules are connected.

[0109] Information transferred through communications interface 914 may be in the form of signals, such as electronic, electromagnetic, optical, or other signals, that communications interface 914 can receive over a communications link carrying the signals, which may be implemented using wire or cable, fiber optics, telephone lines, cellular phone links, radio frequency links, and / or other communications channels. It is contemplated that such communications interfaces may enable one or more processors 902 to receive information from a network and output information to a network in the course of performing the method steps described above. Additionally, method embodiments may be performed solely by the processor or may be performed over a network, such as the Internet, in conjunction with a remote processor that shares a portion of the processing.

[0110] The term "non-transitory computer-readable medium" generally refers to media such as main memory, secondary memory, removable storage, and storage devices (such as hard disks, flash memory, disk drive memory, CD-ROMs, and other forms of persistent memory), and should not be construed to include transitory objects such as carrier waves or signals. Examples of computer code include machine code, such as code produced by a compiler, and files containing high-level language code that are executed by a computer using an interpreter. A computer-readable medium may also be computer code transmitted by a computer data signal embodied in a carrier wave and representing a sequence of instructions executable by a processor.

[0111] Such a computer readable medium may include computer readable code for exposing a substrate located within the chamber to a halogen-containing gas containing an element selected from the group consisting of silicon, germanium, carbon, titanium, and tin, and igniting a plasma to modify a surface of the substrate to form a modified surface (Step 206). The computer readable medium may further include computer readable code for exposing the substrate to an activated activation gas to etch at least a portion of the modified surface (Step 208).

[0112] In another embodiment, an ion beam processing chamber may be used. In one embodiment, a substrate having a memory stack is placed in the ion beam processing chamber. Ion beam etching is performed by flowing a halogen-containing gas containing an element selected from the group consisting of silicon, germanium, carbon, titanium, and tin into the ion beam processing chamber. The halogen-containing gas is turned into a plasma to modify the surface of the memory stack of the substrate, forming a modified surface of the stack of the substrate. While the halogen-containing gas is flowed into the ion beam processing chamber to be turned into a plasma, an activated activation gas is provided to etch the modified surface. In this embodiment, the activation gas is argon. The argon gas is activated by turning it into an ion beam toward the substrate.

[0113] In another embodiment, a Capacitively Coupled Plasma (CCP) chamber may be used. In one embodiment, a substrate having a memory stack is placed in the CCP chamber. Etching is performed by flowing a halogen-containing gas containing an element selected from the group consisting of silicon, germanium, carbon, titanium, and tin into the CCP chamber. The halogen-containing gas is turned into a plasma to modify the surface of the memory stack of the substrate, forming a modified surface of the stack of the substrate. While the halogen-containing gas is flowed into the CCP chamber to be turned into a plasma, an activated activation gas is provided to etch the modified surface. In this embodiment, the activation gas is argon. The argon gas is activated by CCP energy, and a bias is applied to accelerate the activated argon gas toward the substrate.

[0114] [Conclusion] Although the above embodiments have been described in some detail for the purpose of clarity of understanding, it is apparent that some modifications and variations may be made within the scope of the appended claims. It should be noted that there are many alternative ways to implement the processes, systems and devices of the present embodiments. Therefore, the present embodiments are merely illustrative and do not limit the present disclosure. The embodiments are not limited to the details described herein. The present disclosure includes the following application examples: [Application example 1] 1. A method comprising: a) exposing a substrate disposed in a chamber to a halogen-containing gas containing an element selected from the group consisting of silicon, germanium, carbon, titanium, and tin and igniting a plasma to modify a surface of the substrate to form a modified surface; b) exposing the substrate to an activated gas to etch at least a portion of the modified surface; A method comprising: [Application example 2] The method according to Application Example 1, the halogen-containing gas is silicon tetrachloride; method. [Application example 3] The method according to Application Example 1, The halogen-containing gas is selected from the group consisting of chlorosilanes, bromosilanes, iodosilanes, hydrochlorosilanes, and fluorosilanes. method. [Application example 4] The method according to Application Example 1, The exposing the substrate to the activated activation gas includes applying a bias. method. [Application example 5] The method according to Application Example 4, The bias is pulsed. method. [Application Example 6] The method according to Application Example 4, The bias is applied at a voltage of 100 V to 2000 V. method. [Application Example 7] The method according to Application Example 1, exposing the substrate to the halogen-containing gas and igniting the plasma includes applying a bias. method. [Application Example 8] The method according to Application Example 1, exposing the substrate to the activated activation gas to produce a volatile metal silo composite; method. [Application Example 9] The method according to Application Example 1, Prior to step a), further comprising depositing a layer of Group IV element-containing material onto the substrate. method. [Example 10] The method according to Application Example 1, exposing the substrate to the activated activation gas and etching at least a portion of the modified surface, thereby bombarding the modified surface with ions, the ion bombardment forming volatile by-products, the volatile by-products being complexes including halogens, elements from the substrate, and at least one of silicon, germanium, carbon, titanium, and tin; method. [Application Example 11] The method according to Application Example 1, The steps a) and b) are carried out simultaneously. method. [Application Example 12] The method according to Application Example 1, In a multiple cycle atomic layer etching process, step a) is performed before step b). method. [Application Example 13] The method according to Application Example 1, The activated gas is selected from the group consisting of a plasma formed from an activated gas, and an ion beam formed from the activated gas. method. [Example 14] The method according to Application Example 1, Step b) includes providing an ion beam during step a). method. [Example 15] The method according to Application Example 14, The ion beam is an argon ion beam. method. [Example 16] The method according to Application Example 1, the substrate comprises one or more layers of metallic material, the metallic material of at least one of the one or more layers being selected from the group consisting of Group IV transition metals, Group V transition metals, Group VI transition metals, and combinations thereof; method. [Application Example 17] The method according to Application Example 16, a material of at least one of the one or more layers of the substrate comprises a dielectric material; method. [Example 18] The method according to Application Example 1, further comprising etching one or more layers on the substrate by reactive ion etching. method. [Example 19] The method according to Application Example 1, the substrate includes one or more metal layers, a free layer, a dielectric barrier layer, and a fixed layer, the dielectric barrier layer being disposed between the free layer and the fixed layer, and the free layer, the dielectric barrier layer, and the fixed layer being disposed between the one or more metal layers; method. [Example 20] 1. An apparatus for etching features in a substrate, comprising: A plasma chamber; a supply system for supplying gas to the plasma chamber; one or more gas sources for supplying said gas to said delivery system; at least one RF generator; a controller controllably connected to the one or more gas sources and the at least one RF generator, controlling the supply system to flow a halogen-containing gas containing an element selected from the group consisting of silicon, germanium, carbon, titanium, and tin from the one or more gas sources to the plasma chamber; controlling the at least one RF generator to ignite a plasma from the one or more gas sources to modify a surface of the substrate to form a modified surface; controlling the supply system to flow an activated gas from the one or more gas sources to the plasma chamber; a controller including one or more processors configured to control the delivery system to flow the activated gas from the one or more gas sources into the plasma chamber to etch at least a portion of the modified surface; 13. An apparatus comprising: [Example 21] The device according to application example 20, the one or more gas sources include a gas source of silicon tetrachloride; Device. [Example 22] The device according to application example 20, the one or more gas sources include at least one of a chlorosilane, a bromosilane, an iodosilane, a hydrochlorosilane, and a fluorosilane gas source; Device. [Example 23] The device according to application example 20, a bias voltage supply; The controller is further configured to control the bias voltage power supply to activate the activation gas. Device. [Example 24] The device according to application example 20, a bias voltage supply; The controller is further configured to control the bias voltage power supply to apply a bias during ignition of the plasma. Device.

Claims

1. 1. A method comprising: a) exposing a substrate disposed in a chamber to a halogen-containing gas containing an element selected from the group consisting of silicon, germanium, carbon, titanium, and tin and igniting a plasma to modify a surface of the substrate to form a modified surface; b) exposing the substrate to an activated gas to etch at least a portion of the modified surface; Including, The method of claim 1, wherein the modified surface is bombarded with ions by exposing the substrate to the activated activation gas and etching at least a portion of the modified surface, the ion bombardment forming volatile by-products, the volatile by-products being complexes comprising halogens, elements from the substrate, and at least one of silicon, germanium, carbon, titanium, and tin.

2. 2. The method of claim 1 , the halogen-containing gas is silicon tetrachloride; method.

3. 2. The method of claim 1 , The halogen-containing gas is selected from the group consisting of chlorosilanes, bromosilanes, iodosilanes, hydrochlorosilanes, and fluorosilanes. method.

4. 2. The method of claim 1 , The exposing the substrate to the activated activation gas includes applying a bias. method.

5. 5. The method of claim 4, The bias is pulsed. method.

6. 5. The method of claim 4, The bias is applied at a voltage of 100 V to 2000 V. method.

7. 2. The method of claim 1 , exposing the substrate to the halogen-containing gas and igniting the plasma includes applying a bias. method.

8. 2. The method of claim 1 , exposing the substrate to the activated activation gas to produce a volatile metal silo composite; method.

9. 2. The method of claim 1 , prior to step a), further comprising depositing a layer of Group IV element-containing material onto the substrate. method.

10. 2. The method of claim 1 , Steps a) and b) are carried out simultaneously; method.

11. 2. The method of claim 1 , In a multiple cycle atomic layer etching process, step a) is performed before step b). method.

12. 2. The method of claim 1 , The activated gas is selected from the group consisting of a plasma formed from an activated gas and an ion beam formed from the activated gas. method.

13. 2. The method of claim 1 , Step b) includes providing an ion beam during step a). method.

14. 14. The method of claim 13, The ion beam is an argon ion beam. method.

15. 2. The method of claim 1 , the substrate comprises one or more layers of metallic material, the metallic material of at least one of the one or more layers being selected from the group consisting of Group IV transition metals, Group V transition metals, Group VI transition metals, and combinations thereof; method.

16. 16. The method of claim 15, a material of at least one of the one or more layers of the substrate comprises a dielectric material; method.

17. 2. The method of claim 1 , further comprising etching one or more layers on the substrate by reactive ion etching. method.

18. 2. The method of claim 1 , the substrate includes one or more metal layers, a free layer, a dielectric barrier layer, and a fixed layer, the dielectric barrier layer being disposed between the free layer and the fixed layer, and the free layer, the dielectric barrier layer, and the fixed layer being disposed between the one or more metal layers; method.

19. 1. An apparatus for etching features in a substrate, comprising: A plasma chamber; a supply system for supplying gas to the plasma chamber; one or more gas sources for supplying said gas to said delivery system; At least one RF generator; a controller controllably connected to the one or more gas sources and the at least one RF generator, controlling the supply system to flow a halogen-containing gas containing an element selected from the group consisting of silicon, germanium, carbon, titanium, and tin from the one or more gas sources to the plasma chamber; controlling the at least one RF generator to ignite a plasma from the one or more gas sources to modify a surface of the substrate to form a modified surface; controlling the supply system to flow an activated gas from the one or more gas sources to the plasma chamber; a controller including one or more processors configured to control the delivery system to flow the activated gas from the one or more gas sources into the plasma chamber to etch at least a portion of the modified surface; Including, the modified surface is bombarded with ions by exposing the substrate to an activated activation gas and etching at least a portion of the modified surface, the ion bombardment forming volatile by-products, the volatile by-products being complexes comprising halogens, elements from the substrate, and at least one of silicon, germanium, carbon, titanium, and tin.

20. 20. The apparatus of claim 19, the one or more gas sources include a gas source of silicon tetrachloride; Device.

21. 20. The apparatus of claim 19, the one or more gas sources include at least one of a chlorosilane, a bromosilane, an iodosilane, a hydrochlorosilane, and a fluorosilane gas source; Device.

22. 20. The apparatus of claim 19, a bias voltage supply; The controller is further configured to control the bias voltage power supply to activate the activation gas. Device.

23. 20. The apparatus of claim 19, a bias voltage supply; The controller is further configured to control the bias voltage power supply to apply a bias during ignition of the plasma. Device.

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