Semiconductor Device

Abstract

To provide a semiconductor device that can output a digital signal including information other than incidence light.SOLUTION: A semiconductor device 100 comprises: a plurality of first signal generation units 22a that are arranged in a plurality of rows and a plurality of columns corresponding to a plurality of pixels which output signals according to light injection, and that respectively output first digital signals according to outputs from corresponding pixels; a plurality of second signal generation units 22b that are arranged corresponding to at least a portion of the plurality of rows and the plurality of columns, and that respectively output second digital signals having predetermined digital values; and a read-out unit 114 that outputs a signal based on at least one of the first digital signals and the second digital signals output from a portion selected of the plurality of first signal generation units and the plurality of second signal generation units.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] There is known a semiconductor device that outputs a digital signal according to a count value of photons incident on a photoelectric conversion element such as an avalanche photodiode. Patent Document 1 discloses a semiconductor device in which a plurality of pixels are arranged, each of which includes an avalanche photodiode and outputs a digital signal according to the frequency of receiving photons. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2019-9768 A Summary of the Invention [Problem to be solved by the invention]

[0004] In Patent Document 1, no consideration is given to outputting a digital signal including information other than information based on incident light from a semiconductor device.

[0005] SUMMARY OF THE PRESENT EMBODIMENT An object of the present invention is to provide a semiconductor device capable of outputting a digital signal including information other than information based on incident light. [Means for solving the problem]

[0006] According to one aspect of the present invention, there is provided a semiconductor device comprising: a plurality of first signal generation units arranged in a plurality of rows and a plurality of columns corresponding to a plurality of pixels that output signals in response to incidence of light, each outputting a first digital signal in response to an output from a corresponding pixel; a plurality of second signal generation units that are shielded from light, arranged corresponding to at least a portion of the plurality of rows and the plurality of columns, each outputting a second digital signal having a predetermined digital value; a plurality of third signal generation units that are arranged corresponding to the plurality of light-shielded pixels, each outputting a fourth digital signal in response to an output from the corresponding pixel; and a readout unit that outputs a signal based on at least one of the first digital signal and the second digital signal output from a selected portion of the plurality of first signal generation units and the plurality of second signal generation units, each of the plurality of pixels including an avalanche photodiode; the second signal generation unit is arranged between the plurality of first signal generation units and an end of a chip on which the plurality of signal generation units are provided, and the second signal generation unit is arranged between the first signal generation unit and the third signal generation unit. 。 Effect of the Invention

[0007] According to the present invention, it is possible to provide a semiconductor device capable of outputting a digital signal including information other than information based on incident light. [Brief description of the drawings]

[0008] [Figure 1] 1 is an example of a block diagram of a semiconductor device according to a first embodiment. [Diagram 2] 2 is an example of an equivalent circuit diagram of a pixel circuit region according to the first embodiment. [Diagram 3] 3 is a conceptual diagram for explaining an output signal of a signal generating unit according to the first embodiment. FIG. [Figure 4] 4 is an example of a timing diagram in a normal mode of the semiconductor device according to the first embodiment. [Diagram 5] 4 is an example of a timing chart in a test mode of the semiconductor device according to the first embodiment. [Figure 6] 13 is an example of a timing chart in a test mode of the semiconductor device according to the second embodiment. [Figure 7] 13 is an example of an equivalent circuit diagram of a pixel circuit region according to the third embodiment. [Figure 8] 13 is an example of a timing diagram for explaining a counting operation in a signal processing circuit and a signal generating circuit according to the third embodiment. [Figure 9] FIG. 13 is a conceptual diagram for explaining an output signal of the semiconductor device according to the fourth embodiment. [Figure 10] FIG. 13 is an example of a block diagram of a semiconductor device according to a fifth embodiment. [Figure 11] FIG. 13 is a configuration diagram of a semiconductor device according to a sixth embodiment. [Figure 12] FIG. 13 is an example of a block diagram of a sensor chip according to a sixth embodiment. [Figure 13] FIG. 13 is an example of a block diagram of a circuit chip according to a sixth embodiment. [Figure 14] 13 is an example of an equivalent circuit diagram of a pixel region according to the sixth embodiment. [Figure 15] 13 is an example of a cross-sectional view of a semiconductor device according to a sixth embodiment. [Figure 16] FIG. 13 is a block diagram showing an example of the configuration of an imaging system according to a seventh embodiment. [Figure 17] FIG. 13 is a diagram illustrating an example of the configuration of an imaging system and a moving object according to an eighth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The same elements or corresponding elements in multiple drawings are denoted by the same reference numerals, and the description thereof may be omitted or simplified.

[0010] [First embodiment] 1 is an example of a block diagram of a semiconductor device 100 according to this embodiment. In FIG. 1, the semiconductor device 100 includes a pixel circuit region 22 and a readout circuit region .

[0011] The pixel circuit region 22 includes a first pixel circuit region 22a and a second pixel circuit region 22b. The first pixel circuit region 22a includes a plurality of pixel units 103 arranged two-dimensionally across a plurality of rows and a plurality of columns. The pixel units 103 include a photoelectric conversion element that outputs a signal according to incident light. In the example shown in FIG. 1, the first pixel circuit region 22a includes 25 pixel units 103 arranged in five rows from the first row to the fifth row and five columns from the first column to the fifth column. In FIG. 1, symbols indicating row numbers and column numbers are written in boxes indicating the pixel units 103. For example, the pixel unit 103 arranged in the first row and the fourth column is written as "S14". The number of rows and columns of the pixel units 103 included in the first pixel circuit region 22a is not particularly limited.

[0012] The second pixel circuit region 22b includes a plurality of signal generating units 104 arranged in one row and one column along the first pixel circuit region 22a. In the example shown in FIG. 1, the second pixel circuit region 22b includes eleven signal generating units 104 arranged in each column of the 0th row and each row of the 0th column. In FIG. 1, symbols indicating column numbers and row numbers are written in boxes indicating the signal generating units 104. The signal generating units 104 arranged in the 0th row, 0th column to 5th column are written as "S00" to "S05". The signal generating units 104 arranged in the 1st row to 5th row of the 0th column are written as "S10" to "S50". In this way, the plurality of signal generating units 104 are arranged corresponding to at least a part of the plurality of rows and the plurality of columns of the plurality of pixel units 103. The arrangement of the number of rows, the number of columns, etc. of the second pixel circuit region 22b is not limited to that shown in the figure. Since the second pixel circuit region 22b does not include the pixel section 103, it may be optically shielded from light by a light shielding layer or the like.

[0013] The readout circuit region 23 (readout section) includes a vertical scanning circuit 110, a column circuit 112, a horizontal scanning circuit 111, a control pulse generating section 115, and a signal output circuit 114. A plurality of control lines 116 are arranged in each row of a plurality of pixel sections 103 and signal generating sections 104 in the pixel circuit region 22, extending in a first direction (vertical direction in FIG. 1). The plurality of control lines 116 are respectively connected to the pixel sections 103 and the signal generating sections 104 arranged in the first direction, forming a common signal line. The first direction in which the control lines 116 extend may be referred to as a row direction or a horizontal direction. Note that in FIG. 1, each of the control lines 116 is indicated by a reference symbol with a row number. For example, the control line 116 in the first row is indicated as "VSEL[1]".

[0014] The control lines 116 of each row are connected to the vertical scanning circuit 110. The vertical scanning circuit 110 supplies control signals for driving the pixel units 103 and the signal generating units 104 to the pixel units 103 and the signal generating units 104 via the control lines 116.

[0015] A signal line 113 is arranged in each column of a plurality of pixel units 103 and signal generation units 104 in the pixel circuit region 22, extending in a second direction (horizontal direction in FIG. 1) intersecting the first direction. The signal line 113 is connected to the pixel units 103 and signal generation units 104 arranged in the second direction, respectively, and forms a common signal line. The second direction in which the signal line 113 extends may be referred to as a column direction or a vertical direction.

[0016] In FIG. 1, each of the signal lines 113 is denoted by a reference symbol with a column number. For example, the signal line 113 in the fourth column is denoted by "POUT4". Each of the signal lines 113 includes n signal lines for transmitting an n-bit digital signal. The signal lines 113 are connected to column circuits 112. The column circuits 112 are provided corresponding to each column of a plurality of pixel units 103 and signal generation units 104 in the pixel circuit region 22, and are connected to the signal lines 113 of the corresponding columns. The column circuits 112 have a function of holding signals read out from the pixel units 103 and signal generation units 104 via the signal lines 113 of the corresponding columns.

[0017] The horizontal scanning circuit 111 supplies the column circuits 112 with control signals for reading out signals from the column circuits 112. The horizontal scanning circuit 111 supplies control signals to the column circuits 112 of each column via a control line 117. The column circuits 112 that receive the control signals from the horizontal scanning circuit 111 output the signals they hold to the signal output circuit 114 via the horizontal output line HSIG. Note that in FIG. 1, each of the control lines 117 is labeled with a symbol indicating the column number. For example, the control line 117 for the fourth column is labeled "HSEL[4]". The horizontal output line HSIG includes n signal lines for transmitting n-bit digital signals.

[0018] The signal output circuit 114 outputs a signal corresponding to the output from the pixel circuit region 22 as an output signal SOUT of the semiconductor device 100. The control pulse generating unit 115 is driven by an external input clock signal MCLK, and supplies control signals that control the operations of the vertical scanning circuit 110, the horizontal scanning circuit 111, and the column circuit 112 and the timing of these operations. Note that at least some of the control signals that control the operations of the vertical scanning circuit 110, the horizontal scanning circuit 111, and the column circuit 112 and the timing of these operations may be supplied from outside the semiconductor device 100.

[0019] Fig. 2 is an example of an equivalent circuit diagram of the pixel circuit region 22 in Fig. 1. For simplification, Fig. 2 shows four pixel units 103 and five signal generation units 104 arranged from the 0th row to the 2nd row and the 0th column to the 2nd column.

[0020] Each of the plurality of pixel units 103 includes an avalanche photodiode (hereinafter, APD) 201 which is a photoelectric conversion unit, a quench element 202, a signal processing circuit 211, and a selection circuit 212.

[0021] When light is incident on the APD 201, a charge pair is generated by photoelectric conversion according to the incident light. A voltage VL (first voltage) is supplied to the anode of the APD 201. A voltage VH (second voltage) higher than the voltage VL supplied to the anode is supplied to the cathode of the APD 201. A reverse bias voltage is supplied to the anode and cathode of the APD 201 so that the APD 201 performs avalanche multiplication. By supplying such a voltage, the charge generated by the incident light causes avalanche multiplication, and an avalanche current is generated. There are two operation modes when a reverse bias voltage is supplied: a Geiger mode in which the APD 201 is operated with a potential difference between the anode and cathode greater than the breakdown voltage, and a linear mode in which the APD 201 is operated with a potential difference between the anode and cathode close to or less than the breakdown voltage. An APD operated in the Geiger mode is called a SPAD.

[0022] The quench element 202 is connected between a power supply that supplies a voltage VH and the cathode of the APD 201. The quench element 202 has a function of converting a change in avalanche current occurring in the APD 201 into a voltage signal. The quench element 202 functions as a load circuit (quench circuit) during signal multiplication by avalanche multiplication, and has a function of suppressing avalanche multiplication by suppressing the voltage supplied to the APD 201 (quench operation).

[0023] The signal processing circuit 211 (first signal generating unit) has a function of counting potential changes of the cathode of the APD 201 obtained when photons are detected. This function can be realized, for example, by the signal processing circuit 211 being provided with a counter circuit that counts pulses generated by potential changes of the cathode. This allows the signal processing circuit 211 to output a count value (first digital signal) according to the number of photons incident on the APD 201. The signal processing circuit 211 initializes the counter circuit according to a control signal input via the control line 213.

[0024] The selection circuit 212 controls electrical connection / disconnection between the signal processing circuit 211 and the signal line 113 by a control signal supplied from the vertical scanning circuit 110 in Fig. 1 via a control line 214. The selection circuit 212 includes, for example, a switch that controls electrical connection / disconnection, a buffer circuit for outputting a signal, and the like.

[0025] In this embodiment, the pixel unit 103 has a function of outputting a count value of photons incident on the APD 201 as a digital signal, but is not limited thereto. The signal processing circuit 211 may include a time-to-digital converter (hereinafter, TDC) and a memory. In this case, the pixel unit 103 is typically a pixel for forming an image, but when used for TOF (Time of Flight), it does not necessarily have to form an image. In other words, the pixel unit 103 may be a pixel for measuring the time when light arrives and the amount of light.

[0026] Each of the signal generating units 104 includes a signal generating circuit 215 and a selection circuit 212. The signal generating circuit 215 (second signal generating unit) is configured to output a digital signal (second digital signal) having a digital value of a predetermined n bits (n is a natural number). This digital signal can be used, for example, to inspect wiring, circuit operation, and the like in the readout circuit region 23. The signal generating circuit 215 also performs processing related to signal generation, such as initialization, in response to a control signal input via a control line 213. The selection circuit 212 of the signal generating unit 104 controls electrical connection and non-connection between the signal generating circuit 215 and the signal line 113 by a control signal supplied via a control line 214 from the vertical scanning circuit 110 in FIG. 1.

[0027] In this way, a digital signal having a count value output from the signal processing circuit 211 or a predetermined n-bit digital value output from the signal generation circuit 215 of a row selected by the vertical scanning circuit 110 is output to the signal line 113. These signals are stored in the column circuit 112 and are output to the outside of the semiconductor device 100 via the signal output circuit 114 in response to the scanning of the horizontal scanning circuit 111.

[0028] Here, with reference to Fig. 3(a) to Fig. 3(d), a specific example of a predetermined digital value output from the signal generating circuit 215 will be described. Fig. 3(a) to Fig. 3(d) are conceptual diagrams for explaining the output signal of the signal generating unit 104 according to this embodiment. Fig. 3(a) to Fig. 3(d) show the value of an n-bit digital signal output from the signal generating circuit 215. In this example, the digital signal has a plurality of bits (i.e., n is an integer of 2 or more). In addition, "MSB" in the figure indicates the most significant bit, and "LSB" in the figure indicates the least significant bit. In addition, in the following description, "kth bit" means the bit at the kth position counting from the least significant bit. In other words, the LSB in Fig. 3(a) to Fig. 3(d) is the first bit (i.e., the odd-numbered bit), and the MSB in Fig. 3(a) to Fig. 3(d) is the nth bit. Furthermore, the digital signal in this embodiment is assumed to be of positive logic, with a low level corresponding to 0 and a high level corresponding to 1, but it may be of the opposite negative logic.

[0029] Fig. 3(a) is an example where all bits are 0 (low level). Fig. 3(b) is an example where all bits are 1 (high level). In this way, all bits of the digital signal output from the signal generating circuit 215 can be at the same level.

[0030] Fig. 3(c) is an example where all odd-numbered bits are 0 and all even-numbered bits are 1. Fig. 3(d) is an example where all odd-numbered bits are 1 and all even-numbered bits are 0. In this way, the digital signal output from the signal generating circuit 215 may alternate between high and low levels between bits.

[0031] The signal based on the incident light is unlikely to be regular as described above. Therefore, by using a digital signal having a regular bit value as the inspection signal, it is possible to avoid confusion between the signal based on the incident light and the inspection signal. In addition, because the bit value is regular, when the output inspection signal fluctuates due to a defect in the wiring, circuit operation, etc. in the readout circuit region 23, it is easy to detect the occurrence of the fluctuation.

[0032] The above-mentioned digital signals are merely examples, and other types of signals may be used as long as they are in a predefined format that allows the receiving side to identify them as test signals.

[0033] The digital signals output by the signal generating units 104 in the second pixel circuit region 22b may not all have the same value. For example, the digital signals output by the signal generating units 104 may have different values ​​for each row. Each of the signal generating circuits 215 may be configured to selectively output one of the multiple values.

[0034] 4 and 5 are timing diagrams for explaining the operation of the semiconductor device 100 of this embodiment. The semiconductor device 100 of this embodiment is configured to operate in a normal mode (first mode) and an inspection mode (second mode). In the normal mode, the semiconductor device 100 does not output an inspection signal corresponding to the output from the multiple signal generating units 104, but outputs a pixel signal corresponding to the output from the multiple pixel units 103. In the inspection mode, the semiconductor device 100 outputs an inspection signal corresponding to the output from the multiple signal generating units 104. FIG. 4 is an example of a timing diagram in the normal mode, and FIG. 5 is an example of a timing diagram in the inspection mode. FIGS. 4 and 5 show the timing of signals supplied from the vertical scanning circuit 110 to the control lines VSEL[0] to VSEL[5] and the timing of signals supplied from the horizontal scanning circuit 111 to the control lines HSEL[0] to HSEL[5]. In addition, FIGS. 4 and 5 show the output timing of the output signal SOUT and the position of the pixel unit 103 or the signal generating unit 104 corresponding to the output signal SOUT.

[0035] First, an example of operation in normal mode will be described with reference to Fig. 4. At time t1, the potential of the control line VSEL[1] becomes high level, and then at time t2, the potential of the control line VSEL[1] becomes low level. As a result, during the period from time t1 to time t2, signals are output from the multiple pixel units 103 in the first row and are held in the column circuit 112 via the signal lines 113 corresponding to each column.

[0036] At time t3, the potential of the control line HSEL[1] becomes high level, and then at time t4, the potential of the control line HSEL[1] becomes low level. As a result, during the period from time t3 to time t4, a signal is output from the column circuit 112 of the first column to the signal output circuit 114. The signal output circuit 114 outputs an output signal SOUT including a pixel signal corresponding to the output from the pixel unit 103 (S11) of the first row and first column.

[0037] At time t5, the potential of the control line HSEL[2] becomes high level, and then at time t6, the potential of the control line HSEL[2] becomes low level. As a result, during the period from time t5 to time t6, a signal is output from the column circuit 112 of the second column to the signal output circuit 114. The signal output circuit 114 outputs an output signal SOUT including a pixel signal corresponding to the output from the pixel unit 103 (S12) of the first row, second column.

[0038] The signal output process from the column circuits 112 of the third and subsequent columns is also repeated during periods from time t7 to time t8, from time t9 to time t10, and from time t11 to time t12. That is, the signal output circuit 114 sequentially outputs output signals SOUT including pixel signals corresponding to the outputs from the pixel units 103 (S13 to S15) of the first row, third column to the first row, fifth column.

[0039] At time t13, the potential of the control line VSEL[2] becomes high level, and then at time t14, the potential of the control line VSEL[2] becomes low level. As a result, during the period from time t13 to time t14, signals are output from the multiple pixel units 103 in the second row and held in the column circuit 112 via the signal lines 113 corresponding to each column.

[0040] After time t15, similarly to the period from time t3 to time t12, output signals SOUT including pixel signals corresponding to the output from the pixel units 103 (S21 to S25) of each column in the second row are sequentially output. Similarly, for the third row and onwards, output signals SOUT including pixel signals corresponding to the output of the pixel units 103 in the first pixel circuit region 22a are sequentially output for each row and column. Thus, in the normal mode, the semiconductor device 100 outputs pixel signals corresponding to the output from the multiple pixel units 103, but does not output inspection signals corresponding to the output from the multiple signal generating units 104. In this way, during normal times when no inspection is performed, the output of the inspection signals is omitted, thereby speeding up processing such as readout.

[0041] Next, an example of the operation in the inspection mode will be described with reference to Fig. 5. At time t21, the potential of the control line VSEL[0] becomes high level, and then at time t22, the potential of the control line VSEL[0] becomes low level. As a result, during the period from time t21 to time t22, signals are output from the multiple signal generating units 104 in the 0th row and are held in the column circuit 112 via the signal lines 113 corresponding to each column.

[0042] At time t23, the potential of the control line HSEL[0] becomes high level, and then at time t24, the potential of the control line HSEL[0] becomes low level. As a result, during the period from time t23 to time t24, a signal is output from the column circuit 112 of the 0th column to the signal output circuit 114. The signal output circuit 114 outputs an output signal SOUT including a test signal corresponding to the output from the signal generating unit 104 (S00) of the 0th row and 0th column.

[0043] At time t25, the potential of the control line HSEL[1] becomes high level, and then at time t26, the potential of the control line HSEL[1] becomes low level. As a result, during the period from time t25 to time t26, a signal is output from the column circuit 112 of the first column to the signal output circuit 114. The signal output circuit 114 outputs an output signal SOUT including a test signal corresponding to the output from the signal generating unit 104 (S01) of the 0th row and the 1st column.

[0044] The signal output process from the column circuits 112 of the second and subsequent columns is also repeated during periods from time t27 to time t28, from time t29 to time t30, from time t31 to time t32, and from time t33 to time t34. That is, the signal output circuit 114 sequentially outputs output signals SOUT including inspection signals corresponding to the outputs from the signal generation units 104 (S02 to S05) of the 0th row, 2nd column to the 0th row, 5th column.

[0045] At time t35, the potential of the control line VSEL[1] becomes high level, and then at time t36, the potential of the control line VSEL[1] becomes low level. As a result, during the period from time t35 to time t36, signals are output from the signal generation unit 104 in the 1st row and 0th column and the multiple pixel units 103 in the 1st row, and are held in the column circuit 112 via the signal lines 113 corresponding to each column.

[0046] At time t37, the potential of the control line HSEL[0] becomes high level, and then at time t38, the potential of the control line HSEL[0] becomes low level. As a result, during the period from time t37 to time t38, a signal is output from the column circuit 112 of the 0th column to the signal output circuit 114. The signal output circuit 114 outputs an output signal SOUT including a test signal corresponding to the output from the signal generating unit 104 (S10) of the 1st row and 0th column.

[0047] At time t39, the potential of the control line HSEL[1] becomes high level, and then at time t40, the potential of the control line HSEL[1] becomes low level. As a result, during the period from time t39 to time t40, a signal is output from the column circuit 112 of the first column to the signal output circuit 114. The signal output circuit 114 outputs an output signal SOUT including a pixel signal corresponding to the output from the pixel unit 103 (S11) of the first row and first column.

[0048] The signal output process from the column circuits 112 of the second and subsequent columns is also repeated during periods from time t41 to time t42, from time t43 to time t44, from time t45 to time t46, and from time t47 to time t48. That is, the signal output circuit 114 sequentially outputs output signals SOUT including pixel signals corresponding to the outputs from the pixel units 103 (S12 to S15) of the first row, second column to the first row, fifth column.

[0049] At time t49, the potential of the control line VSEL[2] becomes high level, and then at time t50, the potential of the control line VSEL[2] becomes low level. As a result, during the period from time t49 to time t50, signals are output from the signal generation unit 104 in the 2nd row and 0th column and the multiple pixel units 103 in the 2nd row, and are held in the column circuit 112 via the signal lines 113 corresponding to each column.

[0050] After time t51, similarly to the period from time t37 to time t48, output signals SOUT including inspection signals or pixel signals corresponding to the output from the signal generating unit 104 (S20) or pixel units 103 (S21 to S25) of each column in the second row are sequentially output. Similarly, for the third row and onwards, output signals SOUT including inspection signals or pixel signals corresponding to the output from the signal generating unit 104 in the second pixel circuit region 22b or the pixel units 103 in the first pixel circuit region 22a are sequentially output for each row and column. In this way, in the inspection mode, the semiconductor device 100 outputs both pixel signals corresponding to the output from the multiple pixel units 103 and inspection signals corresponding to the output from the multiple signal generating units 104.

[0051] In this manner, the semiconductor device 100 of the present embodiment can operate in the inspection mode. In the inspection mode, the semiconductor device 100 outputs signals including inspection signals corresponding to the outputs from the multiple signal generating units 104 arranged along the first pixel circuit region 22a. At this time, the multiple signal generating units 104 are configured to output predetermined digital signals as exemplified in FIG. 3. By checking whether or not the digital signal output in the inspection mode matches the above-mentioned predetermined digital signal, it is possible to inspect the state of an element present on the path through which the predetermined digital signal passes, for example, the wiring or circuit operation state in the readout circuit region 23.

[0052] In this manner, in the inspection mode, the present embodiment can output an inspection signal not based on incident light, thus providing the semiconductor device 100 capable of outputting a digital signal including information other than information based on incident light.

[0053] When the digital signal for inspection is based on incident light, the value of the digital signal varies depending on the amount of incident light, which may make it difficult to perform a proper inspection. Even in this case, it is possible to generate a proper inspection signal by generating a digital signal for inspection with a constant amount of incident light, but special processing is required for the inspection, which may make the inspection process complicated. In addition, performing complicated inspection may require a long inspection time. This problem may become more pronounced when the inspection target includes an avalanche photodiode that is highly sensitive to incident light. In contrast, the inspection signal output by the semiconductor device 100 of this embodiment is a digital signal having a predetermined digital value that does not depend on incident light, which simplifies the inspection. Therefore, according to this embodiment, a semiconductor device 100 that allows for simplified inspection is provided.

[0054] Furthermore, in this embodiment, in the inspection mode, the semiconductor device 100 can output both pixel signals corresponding to outputs from the multiple pixel units 103 and inspection signals corresponding to outputs from the multiple signal generating units 104. This allows pixel signals to be output in the inspection mode as in the normal mode, so that inspection based on the inspection signals can be performed in parallel with the output of pixel signals.

[0055] The above-mentioned inspection may be performed, for example, in an inspection process for inspecting the quality of the semiconductor device 100 during the manufacturing process of the semiconductor device 100. In this case, the inspection process may be performed on the finished semiconductor device 100 or on a semi-finished semiconductor device 100. The above-mentioned inspection may be performed to inspect the state of the semiconductor device 100 when it is used after shipment.

[0056] It is preferable that the multiple signal generating units 104 are arranged so as to correspond to all rows of the multiple pixel units 103, as shown in Fig. 1. With this configuration, it is possible to inspect the row selection function in the readout circuit region 23 for all rows. It is also preferable that the multiple signal generating units 104 are arranged so as to correspond to all columns of the multiple pixel units 103, as shown in Fig. 1. With this configuration, it is possible to inspect the signal readout function in the readout circuit region 23 for all columns. However, it is not essential that the multiple signal generating units 104 are arranged so as to correspond to all rows or all columns of the multiple pixel units 103.

[0057] [Second embodiment] This embodiment is a modified example of the operation timing in the inspection mode in the first embodiment. In this embodiment, the configuration other than the operation timing in the inspection mode is the same as in the first embodiment, so a description thereof will be omitted.

[0058] Fig. 6 is an example of a timing diagram in the inspection mode of the semiconductor device 100 according to this embodiment. The operation from time t21 to time t34 in Fig. 6 is similar to the operation from time t21 to time t34 in Fig. 5, and therefore a description thereof will be omitted. That is, during this period, the signal output circuit 114 sequentially outputs output signals SOUT including inspection signals corresponding to the outputs from the signal generating units 104 (S00 to S05) in the 0th row, 0th column to the 0th row, 5th column.

[0059] At time t61, the potential of the control line VSEL[1] becomes high level, and then at time t62, the potential of the control line VSEL[1] becomes low level. As a result, during the period from time t61 to time t62, signals are output from the signal generation unit 104 in the 1st row and 0th column and the multiple pixel units 103 in the 1st row, and are held in the column circuit 112 via the signal lines 113 corresponding to each column.

[0060] At time t63, the potential of the control line HSEL[0] becomes high level, and then at time t64, the potential of the control line HSEL[0] becomes low level. As a result, during the period from time t63 to time t64, a signal is output from the column circuit 112 of the 0th column to the signal output circuit 114. The signal output circuit 114 outputs an output signal SOUT including a test signal corresponding to the output from the signal generating unit 104 (S10) of the 1st row and 0th column.

[0061] At time t65, the potential of the control line VSEL[2] becomes high level, and then at time t66, the potential of the control line VSEL[2] becomes low level. As a result, during the period from time t65 to time t66, signals are output from the signal generation unit 104 in the 2nd row and 0th column and the multiple pixel units 103 in the 2nd row, and are held in the column circuit 112 via the signal lines 113 corresponding to each column.

[0062] At time t67, the potential of the control line HSEL[0] becomes high level, and then at time t68, the potential of the control line HSEL[0] becomes low level. As a result, during the period from time t67 to time t68, a signal is output from the column circuit 112 of the 0th column to the signal output circuit 114. The signal output circuit 114 outputs an output signal SOUT including a test signal corresponding to the output from the signal generation unit 104 (S20) of the 2nd row and 0th column.

[0063] Similarly, for the third row and thereafter, output signals SOUT including inspection signals corresponding to the outputs of the signal generating sections 104 in the second pixel circuit regions 22b are output sequentially for each row.

[0064] In the operation timing of this embodiment, in the inspection mode, the semiconductor device 100 does not output pixel signals from the multiple pixel units 103, but outputs only inspection signals corresponding to the outputs from the multiple signal generating units 104. This makes it possible to reduce the number of signals to be output, and therefore, according to this embodiment, a semiconductor device 100 is provided that can further simplify inspection. Furthermore, in cases where the signal output time is a bottleneck in the inspection time, the inspection time can be shortened by applying the operation timing of this embodiment to reduce the number of signals to be output.

[0065] [Third embodiment] This embodiment is a modified example of the pixel circuit region 22 in the first embodiment. In this embodiment, the circuit configuration of the pixel circuit region 22 and the configuration other than the signal supplied to the counter circuit included in the circuit are the same as those in the first embodiment, and therefore the description will be omitted.

[0066] 7 is an example of an equivalent circuit diagram of the pixel circuit region 22 according to the present embodiment. In this embodiment, the signal generation circuit 215 provided in each of the multiple signal generation units 104 has a function of counting pulses of a control signal input via a signal line 216. This function can be realized, for example, by providing the signal generation circuit 215 with a counter circuit that counts pulses. In addition, the signal generation circuit 215 initializes the count value held in response to the control signal input via the control line 213. In each row, the signal line 216 is commonly connected to the signal generation circuits 215 in the same row. In addition, in each row, the control line 213 is commonly connected to the signal generation circuits 215 and the signal processing circuit 211 in the same row.

[0067] FIG. 8(a) is an example of a timing diagram for explaining the counting operation in the signal processing circuit 211 according to this embodiment, and FIG. 8(b) is an example of a timing diagram for explaining the counting operation in the signal generating circuit 215 according to this embodiment.

[0068] First, the operation of the signal processing circuit 211 will be described with reference to Fig. 8(a). Fig. 8(a) shows a signal RST supplied to the control line 213, a cathode potential VPD of the APD 201, and a count value PCNT output from the signal processing circuit 211. In Fig. 8(a), the cathode potential VPD is shown with a voltage VH applied to the cathode and a count threshold value Vt by dashed lines.

[0069] At time t81, when the signal RST becomes high level, the signal processing circuit 211 is reset, and the count value PCNT becomes 0. Thereafter, at time t82 after the signal RST becomes low level, when a photon is incident on the APD 201, the cathode potential VPD drops due to avalanche multiplication. When the cathode potential VPD becomes lower than the threshold value Vt, the count value PCNT changes from 0 to 1. Similarly, when another photon is incident on the APD 201 at time t83, the count value PCNT changes from 1 to 2, and when another photon is incident on the APD 201 at time t84, the count value PCNT changes from 2 to 3. In this way, the signal processing circuit 211 counts the number of changes in the cathode potential of the APD 201 that occur when a photon is detected.

[0070] Next, the operation of the signal generating circuit 215 will be described with reference to Fig. 8(b). Fig. 8(b) shows a signal RST supplied to a control line 213, a signal CCK supplied to a signal line 216, and a count value SCNT output from the signal generating circuit 215.

[0071] At time t91, when the signal RST goes high, the signal generating circuit 215 is reset and the count value SCNT becomes 0. Thereafter, at time t92 after the signal RST goes low, when the signal CCK goes high, the count value SCNT changes from 0 to 1. Similarly, at subsequent times t93, t94, t95, t96, and t97, the count value SCNT increases by 1 each time the signal CCK transitions from low to high. In this manner, the signal generating circuit 215 counts the number of pulses of the signal CCK.

[0072] In the configuration of this embodiment, the semiconductor device 100 can set the value of the inspection signal to be output according to the count number of pulses included in the pulse signal supplied to the signal line 216. As a result, the semiconductor device 100 can be controlled during inspection to appropriately set the value of the inspection signal, and therefore, according to this embodiment, a semiconductor device 100 is provided that can improve the flexibility of the inspection signal.

[0073] [Fourth embodiment] This embodiment is a modified example of the output signal SOUT in the first embodiment. In this embodiment, the circuit configuration of the pixel circuit region 22 is similar to that in the first embodiment, and therefore a description thereof will be omitted.

[0074] 9(a) and 9(b) are conceptual diagrams for explaining the output signal SOUT from the semiconductor device 100 according to this embodiment. In the first embodiment, the output signal SOUT is either an inspection signal or a pixel signal, but in this embodiment, the output signal SOUT is a signal in which an additional signal such as an inspection signal is combined with a pixel signal.

[0075] As shown in FIG. 9(a), the output signal SOUT is an n-bit digital signal in which the additional signal and the pixel signal are combined. As in the first embodiment, the pixel signal is a signal corresponding to the output from the pixel unit 103, and the additional signal is a signal corresponding to the output from the signal generating unit 104. The additional signal may provide additional information to the output signal. As in the first embodiment, the additional signal may also be used as a test signal. The additional signal may also be, for example, a signal indicating the address of the pixel circuit region 22. The process of combining the additional signal and the pixel signal may be performed, for example, in the column circuit 112.

[0076] FIG. 9(b) is an example of an output signal SOUT (third digital signal) in which a pixel signal corresponding to the output from the pixel unit 103 (S43) in the fourth row and third column is combined with an additional signal indicating the address of this pixel signal. Each of the signal generating units 104 in the second pixel circuit region 22b outputs a value corresponding to the position of the corresponding row or column. Here, as an example, the pixel unit 103 (S40) outputs "4" ("100" in binary notation), and the pixel unit 103 (S03) outputs "3" ("011" in binary notation). The output signal SOUT is an n-bit digital signal, and the upper 6 bits are the additional signal. Furthermore, the upper 3 bits of the additional signal are assigned to a signal indicating the row number, and the lower 3 bits are assigned to a signal indicating the column number. At this time, as shown in FIG. 9(b), the value of the additional signal is "100011" in binary notation. This additional signal indicates that the address of the pixel signal is the fourth row and the third column. The information indicated by the additional signal may be address information of only a row or only a column, or may be unique information other than address information.

[0077] According to this embodiment, the semiconductor device 100 can output a pixel signal to which additional information has been added. If the additional information is an address, information on the address of the pixel unit 103 to which the pixel signal has been output can be obtained from the additional signal.

[0078] [Fifth embodiment] This embodiment is a modified example of the pixel circuit region 22 in the first embodiment. In this embodiment, the configuration other than the arrangement of the pixel unit 103 and the signal generation unit 104 in the pixel circuit region 22 is the same as in the first embodiment, so a description thereof will be omitted.

[0079] FIG. 10 is an example of a block diagram of the semiconductor device 100 according to the present embodiment. The pixel circuit region 22 includes a first pixel circuit region 22a, a second pixel circuit region 22b, and a third pixel circuit region 22c. The first pixel circuit region 22a includes a plurality of pixel units 103 arranged two-dimensionally across a plurality of rows and a plurality of columns. The pixel units 103 include photoelectric conversion elements that output signals according to incident light. In the example shown in FIG. 10, the first pixel circuit region 22a includes 16 pixel units 103 arranged in four rows from the second row to the fifth row and four columns from the second column to the fifth column. As in FIG. 1, in FIG. 10, symbols indicating row numbers and column numbers are written in boxes indicating the pixel units 103. The number of rows and columns of the pixel units 103 included in the first pixel circuit region 22a is not particularly limited.

[0080] The second pixel circuit region 22b includes a plurality of signal generation units 104 arranged in one row and one column along the first pixel circuit region 22a. In the example shown in Fig. 10, the second pixel circuit region 22b includes eleven signal generation units 104 arranged in each column of the first row and each row of the first column. As in Fig. 1, in Fig. 10, symbols indicating row numbers and column numbers are written in boxes indicating the signal generation units 104. Note that the arrangement of the number of rows, columns, etc. of the second pixel circuit region 22b is not limited to that shown in the figure.

[0081] The third pixel circuit region 22c is disposed along the second pixel circuit region 22b on the opposite side to the first pixel circuit region 22a. In other words, the second pixel circuit region 22b is disposed between the first pixel circuit region 22a and the third pixel circuit region 22c. The pixel section 103 of the third pixel circuit region 22c includes a photoelectric conversion element that outputs a signal according to incident light, similar to the pixel section 103 of the first pixel circuit region 22a. In the example shown in FIG. 10, the third pixel circuit region 22c includes nine pixel sections 103 disposed in the 0th column, the 2nd column to the 5th column, and the 0th column.

[0082] The second pixel circuit region 22b and the third pixel circuit region 22c are optically shielded from light by a light shielding layer or the like. As a result, light is not incident on the pixel units 103 (third signal generating units) in the third pixel circuit region 22c, and these pixel units 103 can output a black level reference signal (fourth digital signal). By processing such as subtracting the signal output from the pixel units 103 in the third pixel circuit region 22c from the signal output from the pixel units 103 in the first pixel circuit region 22a, the black level can be corrected and noise can be reduced.

[0083] In this embodiment, a light-shielded second pixel circuit region 22b is disposed between a first pixel circuit region 22a capable of detecting incident light and a third pixel circuit region 22c outputting a reference signal for a black level. The second pixel circuit region 22b has a function of outputting a digital signal including information other than information based on the incident light. Furthermore, the second pixel circuit region 22b has a function of a dummy pixel that reduces the influence of a decrease in accuracy of a reference signal caused by light incident on the first pixel circuit region 22a being diffracted and incident on the third pixel circuit region 22c. Therefore, according to this embodiment, a semiconductor device 100 capable of performing black level correction with high accuracy is provided.

[0084] [Sixth embodiment] This embodiment is an example of the configuration of a semiconductor device 100 that is configured by stacking a plurality of chips. In this embodiment, a description of elements common to the first embodiment will be omitted.

[0085] Fig. 11 is an example of a configuration diagram of a semiconductor device 100 according to this embodiment. Fig. 11 illustrates a schematic configuration of the semiconductor device 100 in the form of an exploded perspective view. The semiconductor device 100 includes a sensor chip 11 and a circuit chip 21 which are stacked. The sensor chip 11 and the circuit chip 21 are electrically connected to each other. The sensor chip 11 includes a pixel region 12. The circuit chip 21 includes a pixel circuit region 22 and a readout circuit region 23. The readout circuit region 23 is disposed outside the pixel circuit region 22 in the circuit chip 21.

[0086] FIG. 12 is an example of a block diagram of the sensor chip 11 according to the present embodiment. The pixel region 12 of the sensor chip 11 includes a plurality of pixels 101 arranged two-dimensionally across a plurality of rows and a plurality of columns. Each of the plurality of pixels 101 includes a photoelectric conversion unit 102 including an APD. In the example shown in FIG. 12, the pixel region 12 includes 25 pixels 101 arranged in five rows from the first row to the fifth row and five columns from the first column to the fifth column. In FIG. 12, symbols indicating row numbers and column numbers are written in boxes indicating the pixels 101. For example, the pixel 101 arranged in the first row and the fourth column is written as "P14". The number of rows and columns of the pixels 101 included in the pixel region 12 is not particularly limited.

[0087] 13 is an example of a block diagram of a circuit chip 21 according to this embodiment. The circuit chip 21 includes a first pixel circuit region 22a, a second pixel circuit region 22b, and a readout circuit region 23. Note that the configuration of the readout circuit region 23 is similar to that of the first embodiment, and therefore a description thereof will be omitted.

[0088] The first pixel circuit region 22a includes a plurality of pixel units 105 arranged two-dimensionally across a plurality of rows and a plurality of columns. In the example shown in FIG. 13, the first pixel circuit region 22a includes 25 pixel units 105 arranged in five rows from the first row to the fifth row and five columns from the first column to the fifth column. In FIG. 13, symbols indicating row numbers and column numbers are written in boxes indicating the pixel units 105. For example, the pixel unit 105 arranged in the first row and the fourth column is written as "C14". The number of rows and columns of the pixel units 105 included in the first pixel circuit region 22a is not particularly limited.

[0089] The second pixel circuit region 22b includes a plurality of signal generating units 106 arranged in one row and one column along the first pixel circuit region 22a. In the example shown in FIG. 13, the second pixel circuit region 22b includes eleven signal generating units 106 arranged in each column of the 0th row and each row of the 0th column. In FIG. 13, symbols indicating column numbers and row numbers are written in boxes indicating the signal generating units 106. The signal generating units 106 arranged in the 0th row, 0th column to 5th column are written as "C00" to "C05". The signal generating units 106 arranged in the 1st row to 5th row of the 0th column are written as "C10" to "C50". Note that the arrangement of the number of rows, the number of columns, etc. of the second pixel circuit region 22b is not limited to that shown in the figure.

[0090] Fig. 14 is an example of an equivalent circuit diagram of the pixel region 12 according to the present embodiment. For simplification, Fig. 14 shows four pixel units 105 and five signal generation units 106 arranged from the 0th row to the 2nd row and the 0th column to the 2nd column.

[0091] 14, each of the plurality of pixel units 105 is electrically connected to the pixel 101. More specifically, a connection node between the quench element 202 and the signal processing circuit 211 of each of the plurality of pixel units 105 is electrically connected to the cathode of the APD 201 of the pixel 101. Other circuit configurations are similar to those of the first embodiment, and therefore description thereof will be omitted.

[0092] As in the first embodiment, the semiconductor device 100 of this embodiment is configured to operate in a normal mode in which pixel signals corresponding to outputs from multiple pixel units 105 are output, and in an inspection mode in which inspection signals corresponding to outputs from multiple signal generating units 106 are output.

[0093] Note that the circuit configuration in FIG. 14 is similar to that in FIG. 2 of the first embodiment, but as in FIG. 7 of the third embodiment, a signal line 216 may be provided and a signal generating circuit 215 may have a function of counting pulses of a control signal input via the signal line 216.

[0094] 15 is an example of a cross-sectional view of a semiconductor device 100 according to this embodiment. The semiconductor device 100 has a sensor chip 11 and a circuit chip 21. The sensor chip 11 and the circuit chip 21 are bonded to each other at a bonding surface 150.

[0095] The sensor chip 11 has a substrate 154 (second substrate), which is, for example, a silicon substrate. In the substrate 154, a surface on which a wiring layer is formed is defined as a main surface 155, and the opposite surface is defined as a back surface 156. The sensor chip 11 has a multilayer wiring structure 157 including a first wiring layer 171 and a second wiring layer 172 on the upper portion of the main surface 155 side of the substrate 154. Here, the wiring of the first wiring layer 171 and the wiring of the second wiring layer 172 are connected by, for example, a plug made of a conductor such as tungsten. Similarly, the gate electrode of the MOS transistor formed in the sensor chip 11 and the wiring of the first wiring layer 171 are also connected by, for example, a plug.

[0096] The substrate 154 is provided with, for example, a P-type well 160. In the well 160, an active region and a non-active region (field region) are divided by an element isolation region 163. An N-type region 161 and a P-type region 162 that constitute an APD 201 are provided in the well 160. A color filter layer 180 is provided on the back surface 156 side of the substrate 154. A microlens 181 is provided below the color filter layer 180 in correspondence with the APD 201.

[0097] The circuit chip 21 has a substrate 254 (first substrate). The substrate 254 is also, for example, a silicon substrate. The substrate 254 has a main surface 255 and a back surface 256. The substrate 254 of the circuit chip 21 has a multilayer wiring structure 257 including a first wiring layer 271 and a second wiring layer 272 on the upper part of the main surface 255 side. Here, the wiring of the first wiring layer 271 and the wiring of the second wiring layer 272 are connected by, for example, a plug made of a conductor such as tungsten. Similarly, the gate electrode of the MOS transistor formed in the circuit chip 21 and the wiring of the first wiring layer 271 are also connected by, for example, a plug.

[0098] An element isolation region 263 disposed on the main surface 255 side of the substrate 254 separates an active region from an inactive region. A well 270 is formed in the substrate 254. A plurality of transistors each having a gate electrode 266, a source / drain region 265, an N-type well region 264, and a P-type well region 267 are formed in the well 270. That is, a plurality of PMOS transistors each having an N-type well region 264 and a plurality of NMOS transistors each having a P-type well region 267 are formed in the substrate 254.

[0099] The wiring of the second wiring layer 172, which is the uppermost layer of the multilayer wiring structure 157, and the wiring of the second wiring layer 272, which is the uppermost layer of the multilayer wiring structure 257, are in contact with each other at the bonding surface 150. This ensures electrical connection between these wirings.

[0100] A part of the second wiring layer 272 constitutes a terminal electrode 280. The terminal electrode 280 is an electrical connection portion for driving the semiconductor device 100 and extracting a signal. The terminal electrode 280 is electrically connected to the sensor chip 11 and the circuit in the circuit chip 21 via the wiring of the first wiring layer 271.

[0101] In the semiconductor device 100 of this embodiment, the pixel circuit region 22 including the signal generating unit 104 and the readout circuit region 23 are arranged on the circuit chip 21. In the inspection mode, the circuit chip 21 of the semiconductor device 100 outputs a signal including an inspection signal corresponding to the output from the multiple signal generating units 104 arranged along the first pixel circuit region 22a. In addition, the semiconductor device 100 has a terminal electrode 280 on the circuit chip 21 side. That is, in the inspection mode, the function of the element provided on the sensor chip 11 is not required. Therefore, according to this embodiment, a semiconductor device 100 is provided that can inspect the circuit chip 21 before it is bonded to the sensor chip 11.

[0102] 15, through holes are provided in the sensor chip 11 at portions that correspond to the terminal electrodes 280 of the circuit chip 21 when bonded. As a result, according to this embodiment, a semiconductor device 100 is provided that can inspect the circuit chip 21 even after it is bonded to the sensor chip 11.

[0103] [Seventh embodiment] An imaging system according to a seventh embodiment of the present invention will be described with reference to Fig. 16. Fig. 16 is a block diagram showing a schematic configuration of an imaging system 500 according to this embodiment. The imaging device 10 shown in Fig. 16 is a photoelectric conversion device having the semiconductor device 100 described in the first to sixth embodiments. That is, the imaging system 500 according to this embodiment is an example of a photoelectric conversion system to which the photoelectric conversion device including the semiconductor device 100 described in the first to sixth embodiments can be applied.

[0104] The imaging system 500 according to this embodiment is not particularly limited, but can be applied to, for example, digital still cameras, digital camcorders, camera heads, copiers, fax machines, mobile phones, vehicle-mounted cameras, observation satellites, and the like.

[0105] 16, the imaging system 500 has the imaging device 10, a lens 502, an aperture 504, a barrier 506, a signal processing unit 508, a timing generating unit 520, and an overall control / calculation unit 518. The imaging system 500 also has a memory unit 510, a recording medium control I / F unit 516, and an external I / F unit 512.

[0106] The lens 502 is for forming an optical image of a subject in an imaging area of ​​the imaging device 10. The aperture 504 is for varying the amount of light that has passed through the lens 502. The barrier 506 is for protecting the lens 502. The imaging device 10 outputs a signal based on the optical image formed by the lens 502 to a signal processing unit 508.

[0107] The signal processing unit 508 performs desired processing, correction, data compression, and the like on the signal output from the imaging device 10. The processing performed by the signal processing unit 508 includes generation of image data, processing for acquiring distance information to a subject, and the like. The signal processing unit 508 may be mounted on a board constituting the imaging device 10, or may be mounted on a separate board. Also, a part of the functions of the signal processing unit 508 may be mounted on a board constituting the imaging device 10, and another part of the functions of the signal processing unit 508 may be mounted on a separate board.

[0108] The timing generating unit 520 is for outputting various timing signals to the imaging device 10 and the signal processing unit 508. The overall control / calculation unit 518 is a control unit that manages the overall driving and calculation processing of the imaging system 500. Here, control signals such as timing signals may be input from outside the imaging system 500, and the imaging system 500 only needs to have at least the imaging device 10 and the signal processing unit 508 that processes signals output from the imaging device 10.

[0109] The memory unit 510 is a frame memory unit for temporarily storing image data. The recording medium control I / F unit 516 is an interface unit for recording to and reading from the recording medium 514. The external I / F unit 512 is an interface unit for communicating with an external computer or the like. The recording medium 514 is a removable recording medium such as a semiconductor memory for recording or reading imaging data.

[0110] In this manner, an imaging system 500 to which the semiconductor device 100 according to the first to sixth embodiments is applied is provided.

[0111] [Eighth embodiment] 17(a) and 17(b) are diagrams showing the configuration of an imaging system 600 and a moving body according to this embodiment. FIG. 17(a) shows an example of an imaging system 600 related to an on-vehicle camera. The imaging system 600 has an imaging device 10 which is an example of a photoelectric conversion device including the semiconductor device 100 described in any one of the first to sixth embodiments. The imaging system 600 has an image processing unit 612 which performs image processing on a plurality of image data acquired by the imaging device 10, and a parallax calculation unit 614 which calculates parallax (phase difference of parallax images) from the plurality of image data acquired by the imaging system 600. The imaging system 600 also has a distance measurement unit 616 which calculates a distance to an object based on the calculated parallax, and a collision determination unit 618 which determines whether or not there is a possibility of collision based on the calculated distance. Here, the parallax calculation unit 614 and the distance measurement unit 616 are examples of distance information acquisition means which acquire distance information to an object. That is, the distance information is information on the parallax, the defocus amount, the distance to the object, and the like. The collision determination unit 618 may determine the possibility of a collision using any of these pieces of distance information. The distance information acquisition means may be realized by dedicated hardware or a software module. In addition, it may be realized by a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination of these.

[0112] The imaging system 600 is connected to a vehicle information acquisition device 620, and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The imaging system 600 is also connected to a control ECU 630, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the judgment result of the collision judgment unit 618. That is, the control ECU 630 is an example of a moving body control means that controls a moving body based on distance information. The imaging system 600 is also connected to an alarm device 640 that issues an alarm to the driver based on the judgment result of the collision judgment unit 618. For example, when the judgment result of the collision judgment unit 618 indicates that there is a high possibility of a collision, the control ECU 630 performs vehicle control to avoid a collision and reduce damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 640 warns the user by sounding an alarm, displaying alarm information on a screen of a car navigation system, etc., vibrating a seat belt or steering wheel, etc.

[0113] In this embodiment, the surroundings of the vehicle, for example, the front or rear, are captured by the imaging system 600. Fig. 17(b) shows the configuration of the imaging system 600 when capturing an image of the area in front of the vehicle (imaging range 650). The vehicle information acquisition device 620 sends an instruction to operate the imaging system 600 to perform imaging.

[0114] In this manner, an imaging system 600 and a moving object to which the semiconductor device 100 according to the first to sixth embodiments is applied are provided.

[0115] In the above description, an example of control to avoid collision with other vehicles has been described, but the present invention can also be applied to control of automatic driving by following other vehicles, control of automatic driving to avoid going out of a lane, etc. Furthermore, the imaging system is not limited to vehicles such as the vehicle itself, but can be applied to moving bodies (moving devices) such as ships, aircraft, industrial robots, etc. In addition, the imaging system can be applied not only to moving bodies, but also to a wide range of devices that use object recognition, such as an intelligent transport system (ITS).

[0116] [Modified embodiment] The present invention is not limited to the above-described embodiment, and various modifications are possible. For example, it should be understood that the present invention can be applied to an embodiment in which a part of the configuration of any of the embodiments is added to another embodiment, or an embodiment in which a part of the configuration of any of the embodiments is replaced with a part of the configuration of another embodiment.

[0117] The present invention can also be realized by a process in which a program for implementing one or more of the functions of the above-described embodiments is supplied to a system or device via a network or a storage medium, and one or more processors in a computer of the system or device read and execute the program. The present invention can also be realized by a circuit (e.g., ASIC) that implements one or more of the functions.

[0118] It should be noted that the above-mentioned embodiments are merely examples of the implementation of the present invention, and the technical scope of the present invention should not be interpreted as being limited by these embodiments. In other words, the present invention can be implemented in various forms without departing from its technical concept or main features. [Explanation of symbols]

[0119] 22a First pixel circuit region 22b second pixel circuit region 23 Readout circuit area 100 Semiconductor device 103, 105 Pixel unit 104, 106 Signal generation unit

Claims

1. a plurality of first signal generating units arranged in a plurality of rows and a plurality of columns corresponding to a plurality of pixels that output signals in response to incidence of light, each of which outputs a first digital signal in response to an output from a corresponding pixel; a plurality of second signal generating units that are shielded from light, that are arranged corresponding to at least a portion of the plurality of rows and the plurality of columns, and that output second digital signals each having a predetermined digital value; a plurality of third signal generating units arranged corresponding to a plurality of light-shielded pixels, each of which outputs a fourth digital signal in response to an output from the corresponding pixel; a readout unit that outputs a signal based on at least one of the first digital signal and the second digital signal output from a selected portion of the plurality of first signal generation units and the plurality of second signal generation units; having Each of the plurality of pixels includes an avalanche photodiode; the second signal generating unit is disposed between the plurality of first signal generating units and an end portion of a chip on which the plurality of signal generating units are provided, The second signal generating unit is disposed between the first signal generating unit and the third signal generating unit. A semiconductor device comprising:

2. The second signal generating units are arranged to correspond to all of the rows.

2. The semiconductor device according to claim 1,

3. The second signal generating units are arranged to correspond to all of the columns.

3. The semiconductor device according to claim 1, wherein the first insulating layer is a conductive layer.

4. the second digital signal having a plurality of bits; All of the plurality of bits are at the same level.

4. The semiconductor device according to claim 1, wherein the first insulating layer is a first insulating layer.

5. the second digital signal having a plurality of bits; Among the plurality of bits, all even-numbered bits are at a high level and all odd-numbered bits are at a low level, or all even-numbered bits are at a low level and all odd-numbered bits are at a high level.

4. The semiconductor device according to claim 1, wherein the first insulating layer is a first insulating layer.

6. Each of the second signal generating units generates the second digital signal based on a count number of pulses included in an input control signal.

4. The semiconductor device according to claim 1, wherein the first insulating layer is a first insulating layer.

7. The readout unit does not output the second digital signal in a first mode and outputs the second digital signal in a second mode.

7. The semiconductor device according to claim 6.

8. The readout unit outputs the first digital signal in both the first mode and the second mode.

8. The semiconductor device according to claim 7,

9. The readout unit outputs the first digital signal in the first mode and does not output the first digital signal in the second mode.

8. The semiconductor device according to claim 7,

10. The second mode is an inspection mode for inspecting the readout unit.

10. The semiconductor device according to claim 7, wherein the first insulating layer is a first insulating layer.

11. the plurality of first signal generating units, the plurality of second signal generating units, and the readout unit are disposed on a first substrate; The plurality of pixels are disposed on a second substrate.

11. The semiconductor device according to claim 10.

12. The readout unit outputs a third digital signal obtained by combining the first digital signal and the second digital signal.

7. The semiconductor device according to claim 1, wherein the first insulating layer is a conductive layer.

13. The third digital signal includes information indicating an address of a first signal generating unit that outputs the first digital signal.

13. The semiconductor device according to claim 12.

14. Further comprising a first substrate; The first signal generating units, the second signal generating units, and the readout unit are disposed on the first substrate.

14. The semiconductor device according to claim 1, wherein the first insulating layer is a first insulating layer.

15. A terminal electrode for outputting a signal from the readout unit to the outside is disposed on the first substrate.

15. The semiconductor device according to claim 14.

16. Further comprising a second substrate; The plurality of pixels are disposed on the second substrate.

16. The semiconductor device according to claim 14, wherein the first and second electrodes are electrically connected to each other.

17. the first substrate and the second substrate are stacked on each other, Each of the plurality of pixels that outputs a signal in response to the incidence of the light is electrically connected to a corresponding one of the plurality of first signal generating units.

17. The semiconductor device according to claim 16.

18. Each of the plurality of first signal generating units includes a counter circuit that counts a change in the potential of the avalanche photodiode.

18. The semiconductor device according to claim 1,

19. Correcting a black level based on the first digital signal and the fourth digital signal.

19. The semiconductor device according to claim 1,

20. A photoelectric conversion device including the semiconductor device according to claim 1 ; a signal processing unit that processes a signal output from the photoelectric conversion device; A photoelectric conversion system comprising:

21. A mobile object, A photoelectric conversion device including the semiconductor device according to claim 1 ; a distance information acquiring means for acquiring distance information to an object from a parallax image based on a signal from the photoelectric conversion device; a control means for controlling the moving object based on the distance information; A moving object comprising:

Images