Semiconductor drive circuit and power conversion device

Abstract

To reduce a voltage drop in reverse current conduction of a semiconductor element, which for example occurs during a dead time period of a power conversion device, and thereby, reduce a reverse conducting loss.SOLUTION: A power conversion device (e.g., a PFC circuit in a converter) comprises: an AC power supply 21; a rectification circuit 22; a choke coil 23; an L-level side semiconductor element (e.g., a switching element) 24; an H-level side semiconductor element (e.g., a switching element) 25 for synchronization rectification; and drive circuits 26 and 27 that perform on / off driving of the switching elements 24 and 25. The drive circuit 26 or 27 changes a bias amount of negative bias for turning off the switching element 24 or 25 on the basis of information on the likelihood of occurrence of erroneous ignition of the switching element 24 or 25 (e.g., information on the magnitude of an input current Ii).SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor drive circuit that drives a semiconductor element for synchronous rectification, and a power conversion device that uses the semiconductor drive circuit. [Background technology]

[0002] A power conversion device is a device that converts electrical energy, such as from alternating current (AC) to direct current (DC), from DC to AC, or AC frequency conversion, or DC power conversion. Various devices are known, such as an AC / DC converter, a DC / AC inverter, a DC / DC converter, and a converter with a power factor correction circuit (hereinafter referred to as a "PFC circuit").

[0003] Patent Document 1 describes a power conversion device (for example, a DC power supply device equipped with a PFC circuit and a DC / DC converter). As semiconductor elements constituting the DC / DC converter, the document describes examples of normally-off GaN transistors and SiC transistors using compound semiconductors. In particular, GaN transistors have better electrical and physical characteristics than Si transistors, and are attracting attention as high-power, small-sized, low-loss power semiconductor elements. Patent documents 2 and 3 describe a semiconductor drive circuit in which normally-off type GaN transistors, SiC transistors, etc. are connected in series as semiconductor elements, an arm formed of an upper arm and a lower arm, and a drive circuit for driving these semiconductor elements. Patent Document 4 describes a power supply circuit having a bridge-configured main switching unit made of field-effect transistors (hereinafter referred to as "FETs"), which are semiconductor elements, a transformer that drives the gates of the FETs, and a drive unit that is connected to a primary winding of the transformer and drives the primary winding.

[0004] 4(a), (b), and (c) are diagrams showing a conventional PFC circuit similar to the PFC circuit in a converter described in Patent Document 1 etc., where (a) is an overall circuit diagram of the PFC circuit, (b) is a circuit diagram of the drive circuit in (a), and (c) is an output voltage waveform diagram of the drive circuit.

[0005] This PFC circuit has a rectifier circuit 2 that performs full-wave rectification of AC power supplied from an AC power source 1, and a choke coil 3 and a switching element 4, which are semiconductor elements on the low level (hereinafter referred to as "L level") side, which are connected in series to the output side of the rectifier circuit 2. A series circuit of a switching element 5, which is a semiconductor element on the high level (hereinafter referred to as "H level") side for synchronous rectification, and a smoothing capacitor 8 is connected in parallel to the switching element 4. A load 9 is connected to both electrodes of the capacitor 8. The switching elements 4 and 5 are, for example, composed of normally-off GaN transistors, and their gates (G) are driven by drive circuits 6 and 7. The normally-off GaN transistor is turned off when the gate is at L level (for example, 0 V or less) and turned on when it is at H level.

[0006] When the switching element 4 is on and the switching element 5 is off, a current flows from the AC power source 1 to the rectifier circuit 2 to the choke coil 3 to the switching element 4 to the rectifier circuit 2 to the AC power source 1. When the switching element 4 is off and the switching element 5 is on, a current flows from the AC power source 1 to the rectifier circuit 2 to the choke coil 3 to the switching element 5 to the capacitor 8 and the load 9 to the rectifier circuit 2 to the AC power source 1. As a result, the AC power of the AC power source 1 is rectified by the rectifier circuit 2, and the power is boosted through the choke coil 3, the switching element 4, and the switching element 5, smoothed by the capacitor 8, and supplied to the load 9. The current is controlled by turning the switching element 4 on and off, and the switching element 5 is turned on and off in synchronization with this, so that the current is synchronized with the power supply voltage and the waveform of the current flowing through the choke coil 3 is made closer to a sine wave. The sum of the current flowing through the switching element 4 and the forward current of the switching element 5 for synchronous rectification becomes the current flowing through the choke coil 3.

[0007] The drive circuits 6 and 7 in FIG. 4(b) have the same circuit configuration and are composed of a Zener circuit having a DC power supply 11, a resistor 12, a Zener diode 13, and a capacitor 14, and a pulse signal source 15. The Zener circuit generates a Zener voltage Vz higher than 0V and supplies it to the sources (S) of the switching elements 4 and 5. The pulse signal source 15 inputs an output control signal that, for example, makes the voltage error between the target voltage and the output voltage zero, and pulse-width modulates (hereinafter referred to as "PWM") the output control signal with a carrier wave to generate a drive pulse GP with a peak value Vh higher than 0V and supplies it to the gates (G) of the switching elements 4 and 5. As shown in FIG. 4(c), in the output voltage waveform of the drive circuits 6 and 7, the Zener voltage Vz corresponds to the negative bias amount of the gates when the switching elements 4 and 5 are off. The output voltage of the drive circuits 6 and 7 complementarily turns on and off the switching elements 4 and 5 with a certain dead time.

[0008] FIG. 5 is an operational waveform diagram of the PFC circuit of FIG. Vgs1 is the gate-source voltage of switching element 4 composed of a GaN transistor, Vgs2 is the gate-source voltage of switching element 5 composed of a GaN transistor, Id2 is the reverse drain current flowing from the source to the drain of switching element 5, and Vds2 is the drain-source voltage of switching element 5. td is the dead time when both gate-source voltages Vgs1 and Vgs2 of the two switching elements 4 and 5 become L level.

[0009] 5, when switching element 4 is on due to the H level of gate-source voltage Vgs1 and switching element 5 is off due to the L level of gate-source voltage Vgs2, current flows from AC power supply 1 → rectifier circuit 2 → choke coil 3 → switching element 4 → rectifier circuit 2 → AC power supply 1. In this state, when the gate-source voltage Vgs1 falls to the L level and switching element 4 is turned off, and a transition is made to the dead time td period in which the gate-source voltages Vgs1 and Vgs2 of switching elements 4 and 5 are both at the L level, a reverse conduction current flows from the source to the drain of switching element 5, and the drain-source voltage Vds2 falls to the L level of 0V or less, causing a reverse conduction voltage drop ΔV.

[0010] Similarly, when the switching element 5 is turned on by the H level of the gate-source voltage Vgs2 and the switching element 4 is turned off by the L level of the gate-source voltage Vgs1, a current flows from the AC power supply 1 → rectifier circuit 2 → choke coil 3 → switching element 5 → capacitor 8 and load 9 → rectifier circuit 2 → AC power supply 1. In this state, when the gate-source voltage Vgs2 falls to the L level and the switching element 5 is turned off, and a transition is made to the dead time td period in which both the gate-source voltages Vgs1 and Vgs2 of the switching elements 4 and 5 are at the L level, a reverse conduction current flows from the source to the drain of the switching element 5, and the drain-source voltage Vds2 falls to the L level of 0V or less, causing a reverse conduction voltage drop ΔV.

[0011] The GaN transistors constituting the switching elements 4 and 5 are used as elements capable of high-speed switching, but have a low gate threshold and may cause false ignition due to noise, etc. A specific example of false ignition is when the gate voltage of the switching element 5 of the PFC circuit, which is hard switching other than zero-volt switching (hereinafter referred to as "ZVS"), suddenly changes in the drain voltage, causing the gate voltage to rise via the drain-gate parasitic capacitance in the switching element 5, and when this voltage exceeds the gate threshold, false ignition occurs. As a countermeasure to this, the gate voltage of the switching element 5 when it is off can be negatively biased to prevent false ignition. [Prior art documents] [Patent documents]

[0012] [Patent Document 1] International Publication No. 2012 / 153676 [Patent Document 2] International Publication No. 2013 / 046420 [Patent Document 3] China Patent Application Publication No. 102611288 [Patent Document 4] Japanese Unexamined Patent Publication No. 1-122373 Summary of the Invention [Problem to be solved by the invention]

[0013] The GaN transistors constituting the switching elements 4 and 5 of the PFC circuit in Figure 4 have the characteristic that when current flows from source to drain (reverse conduction), the negative gate bias is added to the original source-drain voltage drop. Therefore, when current flows from source to drain of the switching element 5 (reverse conduction) during the dead time td, as in the case of the switching element 5 for synchronous rectification in the PFC circuit, there is a drawback in that the conduction loss increases due to the reverse conduction voltage drop ΔV, as shown in Figure 5. [Means for solving the problem]

[0014] The semiconductor driver circuit of the present invention includes a semiconductor element for synchronous rectification and a driver circuit for driving the semiconductor element on and off. The driver circuit is configured to detect a condition that causes the semiconductor element to be easily turned on. The magnitude of the input current to the semiconductor element is Based on this, the amount of negative bias for turning off the semiconductor element is changed. a threshold current of the input current is set in advance based on information on the input current and a voltage change amount of the drain-source voltage of the semiconductor element, and when the input current is larger than the threshold current, the bias amount of the negative bias for turning the semiconductor element into an off state is increased, and when the input current is smaller than the threshold current, the bias amount of the negative bias for turning the semiconductor element into an off state is decreased. , characterized in that Another semiconductor driver circuit of the present invention comprises a semiconductor element for synchronous rectification, and a driver circuit for driving the semiconductor element on / off, and the driver circuit changes an amount of negative bias for turning off the semiconductor element based on the magnitude of an input current to the semiconductor element as information indicating that erroneous firing of the semiconductor element is likely to occur, depending on the magnitude of the input current. The drive circuit has a pulse signal source that supplies a drive pulse GP of a peak value Vh to the gate of the semiconductor element, and switchably supplies a short-circuited or negative bias output voltage between the pulse signal source and the source of the semiconductor element. The drive circuit includes an NPN transistor, a resistor connected to the collector and base of the NPN transistor, a Zener diode connected to the base of the NPN transistor and ground, a normally-off switch connected in parallel to the Zener diode and turned on by a control signal, a DC power supply connected to the collector of the NPN transistor and the ground, and a step-down circuit connected to the emitter of the NPN transistor and the ground and consisting of a capacitor and a resistor, the emitter being connected to the source of the semiconductor element. . The drive circuit includes an NPN transistor, an operational amplifier connected to the base of the NPN transistor, a DC power supply connected to the collector of the NPN transistor and ground, and a step-down circuit connected to the emitter of the NPN transistor and the ground and consisting of a capacitor and a resistor, the emitter being connected to the source of the semiconductor element. . The semiconductor drive circuit is a circuit including a converter having the semiconductor element. The semiconductor element is an element using a compound semiconductor.

[0015] The power conversion device of the present invention is characterized by using the semiconductor drive circuit. Effect of the Invention

[0016] According to the present invention, when there is a low possibility of erroneous firing due to noise caused by hard switching, the amount of negative bias for turning off the semiconductor element is changed based on information on the likelihood of erroneous firing of the semiconductor element occurring. This reduces the voltage drop that occurs during the dead time of the power conversion device when the semiconductor element conducts reverse current, thereby reducing reverse conduction loss. [Brief description of the drawings]

[0017] [Figure 1] FIG. 1 shows a power conversion device (for example, a PFC circuit in a converter) according to a first embodiment of the present invention. [Diagram 2] Operation waveform diagram of the PFC circuit in Figure 1(a) [Diagram 3] FIG. 1 shows a power conversion device (for example, a PFC circuit in a converter) according to a second embodiment of the present invention. [Figure 4] Diagram showing a conventional PFC circuit [Diagram 5] Operation waveform diagram of the PFC circuit in Figure 4(a) DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] The mode for carrying out the invention will become apparent from the following description of the preferred embodiment when read in conjunction with the accompanying drawings, which are for illustrative purposes only and are not intended to limit the scope of the invention. EXAMPLES

[0019] (Configuration of Example 1) 1(a), (b), and (c) are diagrams showing a power conversion device (e.g., a PFC circuit in a converter) in a first embodiment of the present invention, where (a) is an overall circuit diagram of the PFC circuit, (b) is a circuit diagram of a drive circuit in (a), and (c) is an output voltage waveform diagram of the drive circuit.

[0020] The PFC circuit of FIG. 1(a) has a rectifier circuit 22 that performs full-wave rectification of AC power supplied from an AC power source 21, and a choke coil 23 and an L-level semiconductor element (e.g., switching element) 24 connected in series to the output side of the rectifier circuit 22. A series circuit of an H-level semiconductor element (e.g., switching element) 25 for synchronous rectification and a smoothing capacitor 28 is connected in parallel to the switching element 24. A load 29 is connected to both electrodes of the capacitor 28. The switching elements 24 and 25 are, for example, normally-off GaN transistors, and their gates (G) are complementarily turned on / off by drive circuits 26 and 27 with a certain dead time in between. In the normally-off GaN transistor, when the gate is at the L level (e.g., 0 V or less), the drain (D) and source (S) are turned off, and when the gate is at the H level, the drain-source is turned on.

[0021] A current detection means (e.g., a shunt resistor) 30a is connected in series to the choke coil 23, and a current detection circuit 30 is connected to the shunt resistor 30a. The current detection circuit 30 is a circuit that detects an input current Ii flowing through the choke coil 23 through the shunt resistor 30a, and a comparator 31 is connected to the output side of the current detection circuit 30. The comparator 31 is a circuit that compares the magnitude of the detected input current Ii with a threshold current Ith, and when the input current Ii is larger than the threshold current Ith, it determines that the input current Ii is a "large current", and when the input current Ii is smaller than the threshold current Ith, it determines that the input current Ii is a "small current", and outputs a current determination signal S31. Two insulating circuits 32 and 33 are connected to the output side of the comparator 31. Each of the isolation circuits 32, 33 isolates the current determination signal S31, outputs an L level control signal S32, S33 when the input current Ii is a "large current", and outputs an H level control signal S32, S33 when the input current Ii is a "small current", and feeds back to each of the drive circuits 26, 27, respectively, and is composed of a pulse transformer, an isolation amplifier, a high-side driver, etc.

[0022] The drive circuits 26 and 27 in FIG. 1(b) have the same circuit configuration and are composed of a DC power supply 41, a resistor 42, a Zener diode 43, a normally-off switch 44 that is turned on by an H-level control signal S32 (S33) and turned off by an L-level control signal S32 (S33), an NPN transistor 45, a capacitor 46, a dropper circuit that is a step-down circuit having a discharge resistor 47 for the capacitor 46, and a pulse signal source 48.

[0023] As shown in FIG. 1(c), when the isolation circuit 32 (33) outputs an L-level control signal S32 (S33), the switch 44 is in an off state. A Zener voltage Vz of the Zener diode 43, which is higher than 0V, is applied to the base of the transistor 45, and a DC output voltage (Vz-Vbe) of the dropper circuit is generated at the emitter of the transistor 45 (where Vbe is the base-emitter voltage of the transistor 45). The output voltage (Vz-Vbe) is supplied to the source (S) of the switching element 24 (25). The pulse signal source 48 has a function of inputting an output control signal that reduces the voltage error between the target voltage and the output voltage to zero, and PWMing the output control signal with a carrier wave such as a triangular wave to generate a drive pulse GP with a peak value Vh higher than 0V and supplying it to the gate (G) of the switching element 24 (25).

[0024] When the isolation circuit 32 (33) outputs an H-level control signal S32 (S33), the switch 44 turns on and shorts the base of the transistor 45. As a result, the transistor 45 turns off, and the output voltage (Vz-Vbe) of the dropper circuit supplied to the source of the switching element 24 (25) is discharged at the discharge time constant of the capacitor 46 and the discharge resistor 47, and accordingly, the amount of negative bias (Vz-Vbe) of the gate when the switching element 24 (25) is off is reduced.

[0025] (Operation of Example 1) Figure 2 is an operational waveform diagram of the PFC circuit in Figure 1(a). Vgs1 is the gate-source voltage of switching element 24 composed of a GaN transistor, Vgs2 is the gate-source voltage of switching element 25 composed of a GaN transistor, Id2 is the forward drain current flowing from the drain to the source of switching element 25, and Vds2 is the drain-source voltage of switching element 25. td1 and td2 are dead times when both gate-source voltages Vgs1 and Vgs2 of two switching elements 24 and 25 become L level.

[0026] The PFC circuit in FIG. 1 operates as follows (1) to (3) in periods T1 to T3 shown in FIG. (1) Period T1: When the switching element 24 transitions from on to off, the switching element 25 transitions from off to on, and the input current Ii is a large current greater than the threshold current Ith. Because the input current Ii is a large current larger than the threshold current Ith, the switch 44 in the drive circuits 26, 27 is turned off by the L-level control signals S32, S33 output from the insulation circuits 32, 33. Therefore, the drive circuits 26, 27 output a rectangular wave voltage whose H level is (Vh-Vz) and whose L level is a negative bias (Vz-Vbe) lower than 0 V. When switching element 24 is turned on by gate-source voltage Vgs1 at the H level and switching element 25 is turned off by gate-source voltage Vgs2 at the L level, a current flows through the AC power supply 21 → rectifier circuit 22 → shunt resistor 30a → choke coil 23 → switching element 24 → rectifier circuit 22 → AC power supply 21.

[0027] In this state, the gate-source voltage Vgs1 falls to the L level, turning off the switching element 24, and transition to a dead time td1 period occurs in which both the gate-source voltages Vgs1 and Vgs2 of the switching elements 24 and 25 are at the L level. Then, a reverse conduction current flows from the source to the drain of the switching element 25, and a current flows through the path of the AC power source 21 → the rectifier circuit 22 → the shunt resistor 30a → the choke coil 23 → the switching element 25 → the capacitor 28 and the load 29 → the rectifier circuit 22 → the AC power source 21. As a result, the AC power of the AC power source 21 is rectified by the rectifier circuit 22, and the power is boosted through the choke coil 23, the switching element 24, and the switching element 25, smoothed by the capacitor 28, and supplied to the load 29. When the reverse conduction current flows from the source to the drain of the switching element 25, the drain-source voltage Vds2 falls to the L level below 0 V, causing a reverse conduction voltage drop ΔV.

[0028] After the dead time td1 has elapsed, the switching element 24 is in the off state, but the gate-source voltage Vgs2 rises to the H level, and the reverse conduction voltage drop ΔV decreases. As a result, a current continues to flow through the AC power supply 21 → rectifier circuit 22 → shunt resistor 30a → choke coil 23 → switching element 25 → capacitor 28 and load 29 → rectifier circuit 22 → AC power supply 21. Next, the gate-source voltage Vgs2 falls to the L level, turning off the switching element 25, and when the period transitions to the dead time td2 period in which the gate-source voltages Vgs1, Vgs2 of the switching elements 24, 25 are both at the L level, a reverse conducting current flows from the source to the drain of the switching element 25, the drain-source voltage Vds2 falls to the L level of 0 V or less, causing a reverse conducting voltage drop ΔV.

[0029] (2) Period T2: When the switching element 24 transitions from on to off, the switching element 25 transitions from off to on, and the input current Ii changes to a small current smaller than the threshold current Ith. After the dead time td2 period has elapsed, the switching element 25 is in the off state, but the gate-source voltage Vgs1 rises to the H level, turning on the switching element 24. As a result, a current flows through the AC power supply 21 → rectifier circuit 22 → shunt resistor 30a → choke coil 23 → switching element 24 → rectifier circuit 22 → AC power supply 21. When the switching element 24 turns on, gate noise NS is generated in the gate-source voltage Vgs2. At this time, since the gate-source voltage Vgs2 of the switching element 25 is negatively biased, it does not exceed the gate threshold value and does not cause false ignition, the drain current Id2 does not flow (0 A), and the drain-source voltage Vds2 becomes the H level.

[0030] When the gate-source voltage Vgs1 falls to the L level (=0V) to turn off switching element 24 and the gate-source voltages Vgs1, Vgs2 of switching elements 24, 25 both enter the L level dead time td1 period, a reverse conduction current flows from the source to the drain of switching element 25, and the drain-source voltage Vds2 falls to the L level of 0V or less, causing a reverse conduction voltage drop ΔV. After the dead time td1 has elapsed, the switching element 24 is in the off state, but the gate-source voltage Vgs2 rises to the H level and the switching element 25 is turned on. As a result, the drain current Id2 of the switching element 25 changes from a negative value to a positive value. The drain-source voltage Vds2 of the switching element 25 is maintained at 0V.

[0031] When the input current Ii becomes a small current smaller than the threshold current Ith, the switch 44 in the drive circuits 26, 27 is turned on by the H-level control signals S32, S33 output from the isolation circuits 32, 33. Then, in the drive circuits 26, 27, the amount of negative gate bias (Vz-Vbe) decreases due to the discharge time constant of the capacitor 46 and the discharge resistor 47, and the gate-source voltage Vgs1 of the switching element 24 rises to 0 V, and the gate-source voltage Vgs2 of the switching element 25 rises. When the gate-source voltage Vgs2 falls to the L level (=0 V) to turn off the switching element 25 and a transition occurs to the dead time td2 period in which the gate-source voltages Vgs1, Vgs2 of the switching elements 24, 25 are both at the L level, the positive drain current Id2 flowing through the switching element 25 causes the drain-source voltage Vds2 of the switching element 25 to rise from 0 V. Therefore, after the dead time td2 period has elapsed, the voltage change amount ΔVds of the drain-source voltage Vds2 of the switching element 25 decreases when the switching element 24 transitions from off to on.

[0032] (3) Period T3: When the switching element 24 transitions from on to off, the switching element 25 transitions from off to on, and the input current Ii is a small current smaller than the threshold current Ith. After the dead time td2 period has elapsed, switching element 25 is in the off state, but the gate-source voltage Vgs1 rises to the H level, turning on switching element 24. As a result, the drain current Id2 flowing through switching element 25 becomes 0 A, and the drain-source voltage Vds2 becomes the H level. At this time, the voltage change ΔVds of the drain-source voltage Vds2 of switching element 25 is small, so the gate voltage is prevented from rising via the drain-gate parasitic capacitance in switching element 25.

[0033] While the gate-source voltage Vgs2 of the switching element 25 remains at 0 V, the gate-source voltage Vgs1 falls to the L level (=0 V) to turn off the switching element 24, and when the dead time td1 period begins in which the gate-source voltages Vgs1, Vgs2 of the switching elements 24, 25 are both at the L level, a negative drain current Id2 flows through the switching element 25, and the drain-source voltage Vds2 falls to the L level below 0 V. The reverse conduction voltage drop ΔV that occurs at this time is smaller than in the periods T1 and T2. Thereafter, the gate-source voltage Vgs2 rises to the H level, and the same operation as above is repeated.

[0034] (Effects of Example 1) In the PFC circuit of FIG. 1, when the input current Ii is small (i.e., when the amplitude of the input sine wave current is small), before the gate of the switching element 24 on the L level side becomes H level, the drain voltage (i.e., drain-source voltage Vds2) of the switching element 25 on the H level side is charged by the input current Ii flowing through the choke coil 23. This reduces the voltage change ΔVds of the drain voltage (i.e., drain-source voltage Vds2) of the switching element 25 when the switching element 24 is turned on, and noise NS is less likely to occur at the gate of the switching element 25. Based on information about the input current Ii, the amount of negative bias (Vz-Vbe) on the gate of the switching element 25 is reduced when the current is small. As a result, when there is a low possibility of false firing due to noise or the like caused by hard switching, by reducing the amount of negative bias (Vz-Vbe) of the gate when the switching element 25 is off, it is possible to reduce the reverse conduction voltage drop ΔV that occurs during the dead time td1 period of the PFC circuit when reverse current flows from the source to the drain, and reduce the reverse conduction loss. EXAMPLES

[0035] (Configuration of Example 2) 3(a), (b), and (c) are diagrams showing a power conversion device (e.g., a PFC circuit in a converter) in a second embodiment of the present invention, where (a) is an overall circuit diagram, (b) is a circuit diagram of a drive circuit in (a), and (c) is an output voltage waveform diagram of the drive circuit. In Fig. 3, elements common to those in Fig. 1 of the first embodiment are given the same reference numerals.

[0036] 3(a) in the second embodiment, an operational amplifier (hereinafter referred to as an "op-amp") 34 is provided instead of the comparator 31 in the PFC circuit in FIG. 1(a) in the first embodiment. The op-amp 34 has a function of outputting a current determination signal S34 proportional to the magnitude of the input current Ii detected by a current detection circuit 30 similar to that in the first embodiment to isolation circuits 32 and 33 similar to that in the first embodiment. The isolation circuits 32 and 33 are configured to insulate the input current determination signal S34, output control signals S32 and S33 at levels corresponding to the magnitude of the input current Ii, and feed back the control signals to the drive circuits 26 and 27.

[0037] In the driving circuit 26 (27) of FIG. 3(b) in the present embodiment 2, an operational amplifier 49 is provided instead of the resistor 42, the Zener diode 43, and the switch 44 in the driving circuit 26 (27) of the embodiment 1. The operational amplifier 49 is a circuit that changes the base voltage Vic of the transistor 45 constituting the dropper circuit based on the control signal S32 (S33) output from the insulating circuit 32 (33) and having a level corresponding to the magnitude of the input current Ii. A voltage (Vic-Vbe) (where Vbe is the base-emitter voltage of the transistor 45) is output from the emitter of the transistor 45 and is supplied to the source (S) of the switching element 24 (25) in FIG. 3(a). A driving pulse GP having a peak value Vh output from a pulse signal source 48 is supplied to the gate (G) of the switching element 24 (25).

[0038] (Operation of Example 2) In the PFC circuit of Fig. 3(a), the operational amplifier 34 outputs a current determination signal S34 proportional to the magnitude of the input current Ii to the isolation circuit 32 (33). The isolation circuit 32 (33) insulates the current determination signal S34 and outputs a control signal S32 (S33) as shown in Fig. 3(c) at a level according to the magnitude of the input current Ii to the operational amplifier 49. Then, the base voltage Vic of the transistor 45 output from the operational amplifier 49 changes, and the output voltage (Vic-Vbe) of the dropper circuit output from the emitter of the transistor 45 changes, so that the amount of gate negative bias (Vic-Vbe) supplied to the switching element 24 (25) can be linearly (freely) adjusted.

[0039] (Effects of Example 2) In the drive circuit 26 (27) of the first embodiment, the switch 44 only switches between the presence and absence of a negative bias on the gate, and does not have a function for adjusting the voltage level of the negative bias, but the circuit configuration is simple. In contrast, the drive circuit 26 (27) of the second embodiment can adjust the amount of negative bias (Vic-Vbe) on the gate when the switch is off by changing the output voltage (Vic-Vbe) of the dropper circuit. This makes it possible to adjust the amount of negative bias to a level that does not cause the gate to erroneously fire, for example, depending on the magnitude of noise, etc.

[0040] (Modification of Examples 1 and 2) The present invention is not limited to the above-mentioned first and second embodiments, and various applications and modifications are possible. The applications and modifications include, for example, the following (a) to (d). (a) The present invention is also applicable to semiconductor elements such as switching elements, such as Si transistors other than normally-off GaN transistors, or diodes. (b) In the first and second embodiments, for example, when the input current Ii is small, the amount of negative bias applied to the gate for turning off the switching element 24 or 25 may be increased. Even with such a modification, substantially the same effects as those of the first and second embodiments can be achieved.

[0041] (c) Information regarding the likelihood of erroneous ignition of the switching elements 24, 25 occurring may be detected from the input voltage or the like other than information regarding the magnitude of the input current Ii. (d) The present invention can be applied to other power conversion devices such as AC / DC power supply circuits and chopper circuits other than the PFC circuit in a converter. [Explanation of symbols]

[0042] 21 AC power supply 22 Rectifier circuit 23 Choke coil 24,25 Switching elements 26,27 Drive circuit 28 Capacitor 29 Load 30 Current detection circuit 31 Comparator 32,33 Isolation circuits 34 Operational Amplifiers

Claims

1. A semiconductor element for synchronous rectification; A drive circuit for turning on and off the semiconductor element; In a semiconductor driving circuit comprising: The drive circuit includes: changing an amount of a negative bias for turning off the semiconductor element based on a magnitude of an input current to the semiconductor element as information indicating that erroneous firing of the semiconductor element is likely to occur; a threshold current of the input current is set in advance based on information on the input current and a voltage change amount of the drain-source voltage of the semiconductor element; When the input current is greater than the threshold current, an amount of the negative bias for turning off the semiconductor element is increased; When the input current is smaller than the threshold current, the amount of the negative bias for turning off the semiconductor element is reduced. A semiconductor driver circuit comprising:

2. A semiconductor element for synchronous rectification; A drive circuit for turning on and off the semiconductor element; In a semiconductor driving circuit comprising: The drive circuit includes: based on the magnitude of an input current to the semiconductor element as information on the likelihood of false turn-on of the semiconductor element, a bias amount of a negative bias for turning off the semiconductor element is changed according to the magnitude of the input current; A semiconductor driver circuit comprising:

3. The drive circuit comprises: a pulse signal source that supplies a drive pulse GP having a peak value Vh to a gate of the semiconductor element; switchably supplying a short-circuit or negative bias output voltage between the pulse signal source and a source of the semiconductor device; 3. The semiconductor driver circuit according to claim 1, wherein the first and second input terminals are connected to each other.

4. The drive circuit includes an NPN transistor, a resistor connected to the collector and base of the NPN transistor, a Zener diode connected to the base of the NPN transistor and ground, a normally-off switch connected in parallel to the Zener diode and turned on by a control signal, a DC power supply connected to the collector of the NPN transistor and the ground, and a step-down circuit connected to the emitter of the NPN transistor and the ground and consisting of a capacitor and a resistor; The emitter is connected to the source of the semiconductor element.

2. The semiconductor drive circuit according to claim 1.

5. The drive circuit includes an NPN transistor, an operational amplifier connected to the base of the NPN transistor, a DC power supply connected to the collector of the NPN transistor and ground, and a step-down circuit consisting of a capacitor and a resistor connected to the emitter of the NPN transistor and the ground, The emitter is connected to the source of the semiconductor element.

3. The semiconductor drive circuit according to claim 2.

6. The semiconductor drive circuit includes: A circuit including a converter having the semiconductor element.

6. The semiconductor driver circuit according to claim 1,

7. The semiconductor device is It is an element using compound semiconductors.

7. The semiconductor driver circuit according to claim 1, wherein the first and second electrodes are electrically connected to the first and second electrodes.

8. A semiconductor driving circuit according to any one of claims 1 to 7 is used. A power conversion device comprising:

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