Integrated circuit margin measurement and failure prediction apparatus

Abstract

A semiconductor integrated circuit (IC) is provided that can predict failure of each individual IC based on fingerprint sampling on appropriate IC paths. A semiconductor integrated circuit (IC) includes a signal path combiner including a plurality of input paths and an output path. The IC includes a delay circuit having an input electrically connected to the output path, the delay circuit delaying the input signal by a variable delay time to output the delayed signal path. The IC may include a first storage circuit electrically connected to the output path and a second storage circuit electrically connected to the delayed signal path. The IC includes a comparison circuit that compares the output of the signal path combiner with the delayed signal, the comparison circuit including a comparison output that provides a comparison data signal to at least one mitigation circuit.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of priority to U.S. Provisional Patent Application No. 62 / 586,423, filed November 15, 2017, the entire contents of which are incorporated herein by reference.

[0002] The present invention relates to the field of integrated circuits. [Background technology]

[0003] An integrated circuit (IC) can contain analog and digital electronic circuits on a flat semiconductor substrate, such as a silicon wafer. Printing tiny transistors onto a substrate using photolithography techniques to create complex circuits of billions of transistors in a very small area allows ICs to be used to design modern electronic circuits at low cost and with high performance. ICs are produced on assembly lines in factories called foundries, which share the production of ICs, such as complementary metal-oxide semiconductor (CMOS) ICs. Digital ICs contain billions of transistors arranged in functional and / or logic units on a wafer, with data paths interconnecting the functional units to transfer data values ​​between them. As used herein, the term "data path" refers to a parallel series of electronic connections or paths for transferring data signals between functional / logic units of an IC. Each data path may include a specific number of bit paths, such as 64, 128, or 256. During the IC design process, the timing of functional units is adjusted so that each functional unit can typically complete its required processing within one clock cycle. Safety factors may be used to account for manufacturing variations in individual ICs and possible changes, such as degradation, over the planned life of the IC.

[0004] The degradation of an IC's transistors over time is called aging. For example, transistor degradation over time can lead to a gradual reduction in switching speed, which can even cause complete circuit failure if it exceeds the design's safety factor. Typically, the design process incorporates these delays to ensure that an IC will not fail during its normal lifetime, but environmental and usage conditions (heat, voltage, current, humidity, etc.) can accelerate the aging process.

[0005] IC transistors, such as bipolar transistors and metal-oxide-semiconductor field-effect transistors (MOSFETs), are sometimes used in digital ICs and function as electrical switches. For example, a MOSFET may have four terminals: a body, a gate, a source, and a drain, although the source and body are typically electrically connected. A voltage applied to the gate can determine the amount of current that flows between the source and drain. A thin layer of dielectric material electrically insulates the gate, and an electric field applied to the gate can change the conductivity of the underlying semiconductor channel between the source and drain.

[0006] In use, charge carriers with more energy than the average charge carrier (such as electrons in a negative or n-channel MOSFET, or holes in a positive or p-channel MOSFET) can escape from the conductive channel between the source and drain and become trapped in the insulating dielectric. This process, called hot carrier injection (HCI), can ultimately accumulate charge in the dielectric layer, thereby increasing the voltage required for transistor operation. As the threshold voltage increases, the transistor's switching delay can increase.

[0007] Another aging mechanism occurs when a voltage is applied to the gate, a phenomenon known as bias temperature instability (BTI). BTI can cause problems such as charge buildup in the dielectric, but some of this effect disappears naturally when that gate voltage is removed. This recovery occurs within a few microseconds, making it difficult to observe when the transistor is stressed, and the resulting effect can only be measured after the stress is removed.

[0008] Another aging mechanism comes into play when the voltage applied to the gate can create electrically active defects in the dielectric, known as traps. If the traps become so numerous, these charge traps can combine to form a complete short circuit between the gate and the current channel. This type of failure is called oxide breakdown, or time-dependent dielectric breakdown. Unlike other aging mechanisms that result in a gradual degradation of performance, dielectric breakdown can lead to catastrophic failure of the transistor, causing the IC to malfunction.

[0009] Additionally, a phenomenon called electromigration can damage the copper or aluminum connections that hold transistors together or link them to the outside world. Electromigration can occur when a surge of current causes metal atoms to break free from an electrical connection, allowing them to flow along with electrons. This depletes some atoms of metal upstream and causes metal to build up downstream. Thinning of the upstream metal increases the electrical resistance of the connection, potentially resulting in an open circuit. Downstream buildup can cause the metal to bulge from its designated track.

[0010] Another reliability-related issue in ICs is a phenomenon called stress migration, which is used to describe the flow of metal atoms under the influence of mechanical stress.

[0011] Furthermore, defects, such as unmodeled phenomena and random manufacturing defects, can cause timing degradation of signal paths over time. Some defects may not appear during testing, verification, initial operation, etc.; for example, a die / IC / product may pass all screening procedures during testing. For example, a via containing a manufacturing defect, such as less than complete metal coverage, will increase its resistance over time and, at some point, cause timing failures in logic paths. For example, random manufacturing defects can appear anywhere in an IC, incorporating many different types and levels of defects, so it may not be possible to design in safety factors to mitigate these defects. On the other hand, aspects of embodiments of the disclosed technology may predict failures of each individual IC based on fingerprint sampling at appropriate IC paths, enabling preemptive replacement, corrective and preventative measures, user notification, compensation, and other measures to mitigate failures within the IC and extend its time life.

[0012] The foregoing examples of the related art and limitations associated therewith are intended to be illustrative and not exhaustive. Other limitations of the related art will become apparent to those skilled in the art upon reading the specification and studying the drawings. Summary of the Invention

[0013] The following embodiments and aspects thereof are described and illustrated in conjunction with systems, tools, and methods that are meant to be exemplary and illustrative, not limiting in scope.

[0014] According to one embodiment, a semiconductor integrated circuit (IC) according to the claims is provided. It may include a signal path combiner including a plurality of input paths and an output path. The IC includes a delay circuit having an input electrically connected to the output path, the delay circuit delaying the input signal by a variable delay time to output the delayed signal path. The IC may include a first storage circuit electrically connected to the output path and a second storage circuit electrically connected to the delayed signal path. The IC includes a comparison circuit that compares the outputs of the first and second storage circuits, the comparison circuit having a second output path electrically connected to one or more mitigation circuits.

[0015] In some embodiments, the mitigation circuit is one or more of the group consisting of a notification circuit, a timing delay measurement (or estimation) circuit, a data transmission circuit, an IC anti-aging compensation circuit, and a failure analysis circuit.

[0016] In some embodiments, the signal path combiner is one or more of the group consisting of a logical XOR combiner, a Hamming parity combiner, and a multiplexer.

[0017] In some embodiments, the variable delay time is set in integer multiples in increments equal to the IC's clock period divided by the signature vector size, where the signature vector size is between 1 and 100,000.

[0018] In some embodiments, the mitigation circuitry is data transmission circuitry electronically connected to a computerized server, the computerized server configured to receive the multiple instances of the comparison data signal, perform a failure prediction analysis of the comparison data signal, and send a notification to the mitigation module when the failure prediction analysis predicts failure of the IC within a predefined time period.

[0019] In some embodiments, at least some of the comparison data signals are generated at multiple values ​​of variable delay time.

[0020] In some embodiments, at least some of the comparison data signals are generated from multiple instances of one or more values ​​from a plurality of values ​​of the variable delay time.

[0021] In some embodiments, the failure prediction analysis includes one or more of machine learning analysis, trend analysis, multiple object tracking analysis, and multivariate analysis.

[0022] In some embodiments, the failure prediction analysis includes receiving comparative data signals from a plurality of different ICs.

[0023] In some embodiments, the failure prediction analysis includes receiving failure prediction analysis results from a plurality of different ICs.

[0024] In a further aspect that may be combined with any embodiment described herein, there is provided a semiconductor integrated circuit (IC) comprising: a signal path combiner including a plurality of input paths and an output, the output being based on a combination of respective signals received on each input path; a delay circuit having an input electrically connected to the output of the signal path combiner, the delay circuit delaying the input signal by a variable delay time to output a delayed signal; and a comparison circuit arranged to provide a comparison output based on a comparison of the output of the signal path combiner and the delayed signal, the comparison output being provided to at least one mitigation circuit in the form of a comparison data signal.

[0025] In some embodiments, the mitigation circuit is at least one circuit from the group consisting of a notification circuit, a timing delay measurement circuit, a data transmission circuit, an IC anti-aging compensation circuit, and a failure analysis circuit.

[0026] Optionally, the signal path combiner is at least one of the group consisting of a logical XOR combiner, a Hamming parity combiner, and a multiplexer.

[0027] In one embodiment, the IC further comprises a first internal storage circuit electrically connected to the output of the signal path combiner and arranged to provide the stored output of the signal path combiner as a first input to the comparison circuit, and a second internal storage circuit electrically connected to the delayed signal and arranged to provide the delayed signal as a second input to the comparison circuit.

[0028] In a particular embodiment, the signal path combiner is a first signal path combiner arranged to receive the plurality of signals from a first data source, and the comparison circuit is a first comparison circuit. The IC may then further comprise: a second signal path combiner including a plurality of input paths and an output, the output of the second signal path combiner being based on a combination of respective signals received on each input path, the signal being received from a second data source; a multiplexer configured to receive the output of the first signal path combiner, the output of the second signal path combiner, and a selection signal and to selectively output the output of the first signal path combiner or the output of the second signal path combiner based on the selection signal, the output of the multiplexer being provided as an input to the delay circuit; a second comparison circuit arranged to provide a second comparison output based on a comparison of the output of the second signal path combiner and the delayed signal; and an OR gate arranged to receive the first comparison output and the second comparison output as inputs and provide an output as a comparison data signal to the at least one mitigation circuit.

[0029] The IC optionally further comprises a first comparison storage circuit arranged to receive the first comparison output and controlled by a first clock signal, and a second comparison storage circuit arranged to receive the second comparison output and controlled by a second clock signal, the first comparison storage circuit arranged to provide the first comparison output as a first input to the OR gate, and the second comparison storage circuit arranged to provide the second comparison output as a second input to the OR gate.

[0030] In some embodiments, the variable delay time is set in integer multiples in increments equal to the IC's clock period divided by the signature vector size, where the signature vector size is between 1 and 100,000.

[0031] In an embodiment, the mitigation circuit is a data transmission circuit electronically connected to a computerized server configured to receive a plurality of instances of the comparison data signals, perform a failure prediction analysis of the comparison data signals, and send a notification to the mitigation module when the failure prediction analysis predicts failure of the IC within a predefined time period. Optionally, at least some of the comparison data signals are generated with a plurality of values ​​of the variable delay time. Preferably, at least some of the comparison data signals are generated from a plurality of instances of at least one value of the plurality of values ​​of the variable delay time.

[0032] In certain embodiments, the failure prediction analysis includes at least one of machine learning analysis, trend analysis, multiple object tracking analysis, and multivariate analysis.

[0033] In an embodiment, the failure prediction analysis includes receiving comparative data signals from a plurality of different ICs.

[0034] In some embodiments, the failure prediction analysis includes receiving failure prediction analysis results from a plurality of different ICs.

[0035] In some embodiments, each of the multiple input paths of the signal path combiner is configured to receive one of a signal from a respective data source within the IC, a signal from a memory circuit, and a signal from one of the multiple logic circuits grouped by a clock enable.

[0036] In another aspect (which may be combined with any other embodiment described herein), a method is contemplated for using a semiconductor integrated circuit (IC), the method including: combining respective signals received on each of a plurality of input paths at a signal path combiner to provide an output; delaying the output of the signal path combiner by a variable delay time at a delay circuit to output a delayed signal; comparing the output of the signal path combiner and the delayed signal to provide a comparison output; and providing the comparison output as a comparison data signal to at least one mitigation circuit.

[0037] In some embodiments, the mitigation circuit is at least one circuit from the group consisting of a notification circuit, a timing delay measurement circuit, a data transmission circuit, an IC anti-aging compensation circuit, and a failure analysis circuit.

[0038] In an embodiment, the signal path combiner is at least one of the group consisting of a logical XOR combiner, a Hamming parity combiner, and a multiplexer.

[0039] Optionally, the method further includes storing the output of the signal path combiner in a first internal storage circuit and providing the stored output of the signal path combiner from the first internal storage circuit as a first input to the comparison circuit, and storing the delayed signal in a second internal storage circuit and providing the delayed signal from the second internal storage circuit as a second input to the comparison circuit.

[0040] In a particular embodiment, the signal path combiner is a first signal path combiner that receives a plurality of signals from a first data source, and the comparison circuit is a first comparison circuit. Next, the method may further include combining respective signals received on each of the plurality of input paths at a second signal path combiner to provide an output, where the signals are received from a second data source; receiving an output of the first signal path combiner, an output of the second signal path combiner, and a selection signal at a multiplexer, and selectively outputting the output of the first signal path combiner or the output of the second signal path combiner based on the selection signal, where the delaying step delays the output of the first signal path combiner or the output of the second signal path combiner by a variable delay time in the delay circuit to output a delayed signal, where the output of the multiplexer is provided as an input to the delay circuit; comparing the output of the second signal path combiner with the delayed signal to provide a second comparison output; and receiving the first comparison output and the second comparison output as inputs at an OR gate, and outputting the comparison data signal as an output from the OR gate to the at least one mitigation circuit.

[0041] In some embodiments, the method further includes receiving the first comparison output at a first comparison storage circuit controlled by a first clock signal, receiving the second comparison output at a second comparison storage circuit controlled by a second clock signal, providing the first comparison output from the first comparison storage circuit as a first input to an OR gate, and providing the second comparison output from the second comparison storage circuit as a second input to the OR gate.

[0042] In an embodiment, the variable delay time is set in integer multiples of increments equal to the IC's clock period divided by a factor between 1 and 100,000.

[0043] In some embodiments, the mitigation circuitry is data transmission circuitry electronically connected to a computerized server, and the method further includes receiving a plurality of instances of the comparison data signals at the computerized server, performing a failure prediction analysis of the comparison data signals at the computerized server, and sending a notification from the computerized server to the mitigation module when the failure prediction analysis predicts failure of the IC within a predefined time period. Optionally, at least some of the comparison data signals are generated with a plurality of values ​​of the variable delay time. Preferably, at least some of the comparison data signals are generated from a plurality of instances of at least one value of the plurality of values ​​of the variable delay time.

[0044] In some embodiments, the failure prediction analysis includes at least one of machine learning analysis, trend analysis, multiple object tracking analysis, and multivariate analysis.

[0045] In a particular embodiment, the failure prediction analysis includes receiving comparative data signals from a plurality of different ICs.

[0046] In an embodiment, the failure prediction analysis includes receiving failure prediction analysis results from a plurality of different ICs.

[0047] Optionally, each of the plurality of input paths of the signal path combiner is configured to receive one of a signal from a respective data source within the IC, a signal from a memory circuit, and a signal from one of the plurality of logic circuits grouped by clock enable.

[0048] In an embodiment, the method is performed at an initial operation of the IC. Then, the method may further include measuring a timing delay of the IC based on the comparison data signal provided to the mitigation circuit.

[0049] In some embodiments, the method further includes repeating the combining, delaying, and comparing steps for each of a plurality of delay times to provide a plurality of comparison outputs, and determining a signature of the IC based on the plurality of comparison outputs. Optionally, the method further includes tracking changes in the signature of the IC over time.

[0050] In addition to the exemplary aspects and embodiments described above, further aspects and embodiments will become apparent by reference to the figures and by study of the following detailed descriptions. [Brief explanation of the drawings]

[0051] Exemplary embodiments are illustrated in the referenced figures. Dimensions of components and features shown in the figures have generally been chosen for convenience and clarity of presentation and are not necessarily shown to scale. The figures are as follows:

[0052] [Figure 1] 1 shows a schematic of a computerized system for IC margin measurement and failure prediction. [Figure 2] 1 shows a flowchart of a method for IC margin measurement and failure prediction. [Figure 3] An XOR-type circuit diagram for IC margin measurement and failure prediction is shown. [Figure 3A] An XOR-type circuit diagram for IC margin measurement and failure prediction is shown. [Figure 3B] An XOR-type circuit diagram for IC margin measurement and failure prediction is shown. [Figure 4] A MUX-based circuit diagram for IC margin measurement and failure prediction is shown. [Figure 5] The circuit diagram for the anti-IC aging mode is shown below. [Figure 6] Shows timing diagrams of signal delays for IC margin measurement and failure prediction. [Figure 7] 1 shows a graph of error versus cycle time for the first experiment. [Figure 8]10 shows a graph of error versus cycle time for the second experiment. [Figure 9] Shows timing diagrams of two signal delays for IC margin measurement and failure prediction. [Figure 10] 10 shows a graph of error versus cycle time for the third experiment. [Figure 11] A margin map of the unit is shown. DETAILED DESCRIPTION OF THE INVENTION

[0053] Disclosed herein are methods and devices for determining and predicting future failures of individual integrated circuits. Also disclosed are timing delay margin measurement circuits for an IC from its first operation and / or over time (e.g., from its first operation or any period thereafter). Dedicated circuits (which may be detectors), such as failure prediction circuits (FPCs) or margin measurement and failure prediction circuits (MFPCs), are placed at selected points along one or more data paths of a digital integrated circuit (e.g., one or more FPCs or MFPCs per data path), each coupling multiple individual data paths into a smaller number of test paths. By splitting each test signal in two and applying a delay circuit to one of the split signal paths, a fingerprint or signature of the delay of each path of the data path may be obtained during each clock cycle of the functional unit. As used herein, the terms "fingerprint" and / or "signature" refer to a signal strength profile, such as a vector, series, etc., resulting from measuring the timing delay margin of a combination of signals in the data path. For each clock cycle of the functional unit, the output data path may have a different data value. Thus, during each clock cycle, different combinations of logic paths within the functional units may be tested, generating different fingerprints. By collecting a large number of fingerprints over time, a data set of fingerprints may be analyzed. Analysis of the fingerprint data set may determine performance and / or predict future failures of individual ICs.

[0054] Generally speaking, a semiconductor integrated circuit (IC) is contemplated, comprising: a signal path combiner having a plurality of input paths (e.g., for receiving signals at data sources or data paths from memory circuits and / or from logic circuits grouped by clock enables) and an output, the output being based on a combination of the respective signals received at each input path; a delay circuit having an input electrically connected to the output of the signal path combiner, the delay circuit delaying the input signal by a variable delay time and outputting the delayed signal; and a comparison circuit arranged to provide a comparison output based on a comparison of the output of the signal path combiner with the delayed signal, the comparison output being provided to at least one mitigation circuit as a comparison data signal. The combination of the signal path combiner, delay circuit, and comparison circuit may provide an FPC or MFPC.

[0055] Methods for using such ICs are also contemplated (wherein using may include, for example, one or more of operation, analysis, and configuration). For example, this may include a method of using a semiconductor integrated circuit (IC). The method may include combining respective signals received on each of a plurality of input paths at a signal path combiner to provide an output; delaying the output of the signal path combiner by a variable delay time at a delay circuit to output a delayed signal; comparing the output of the signal path combiner and the delayed signal to provide a comparison output; and providing the comparison output to at least one mitigation circuit as a comparison data signal.

[0056] It is also contemplated that the combining, delaying, and comparing steps may be repeated for each of multiple delay times. In this manner, multiple comparison outputs may be provided. An identifying characteristic (i.e., a signature or fingerprint) of the IC may thereby be determined based on the multiple comparison outputs. Multiple such fingerprints may be determined by repeating this process at different clock cycles. The fingerprint may then be tracked at different times, for example, by tracking changes in the fingerprint over time (using intervals at least the length of time it takes to determine a single fingerprint, and preferably longer).

[0057] Further optional method features may be provided that correspond to steps performed by any of the features described with reference to the IC. Examples of these are described below. Specific embodiments are also described below, but further reference is made to the generalized meaning or terminology of this disclosure.

[0058] Note that a datapath is just one example of a design style that can be handled by an FPC or MFPC; other examples could be memory circuits (FPC / MFPC is located at the output of the memory) or other logic circuits that are grouped together for a specific clock.

[0059] Optionally, aspects of the embodiments described herein may be applied to reliability issues in IC performance, such as aging, latent defects that manifest in the design and cause degradation, intra-IC / inter-IC manufacturing variations, and inter-fab manufacturing variations. The described techniques discover timing delay variations from any source or cause, predict future failures before an IC failure causes device / system failure, and enable corrective and preventative action before a specific IC failure. While reliability issues such as aging and electromigration are used here as examples, the techniques may also be applied to latent defects such as random defects, systematic defects, and unknown defects.

[0060] Optionally, the delay may be varied in small time steps to generate one or more time delay sweeps and associated fingerprints for each different time delay. The sweeps may be analyzed to determine the behavior of individual ICs or to predict future failures of the ICs.

[0061] Optionally, one or more data sets (e.g., signals on an IC) may be combined and analyzed to determine operational delays for each path of a data path (or equivalent signal path), each logical processing path of a functional unit, etc.

[0062] Optionally, one or more data sets may be statistically analyzed to predict future failure of the IC. For example, IC degradation trends may be analyzed with one or more delay margins measured using the failure prediction circuitry, such as by analyzing minimum delay margin changes over time.

[0063] Optionally, machine learning may be used to analyze one or more data sets to monitor IC failures, predict future IC failures, and the like.

[0064] Optionally, one or more data sets may be analyzed to design future ICs.

[0065] Optionally, one or more sweeps may be combined and analyzed to determine the operational delay for each path of a data path, each logical processing path of a functional unit, and so on.

[0066] Optionally, one or more sweeps may be statistically analyzed to predict future failures of the IC, for example, regression analysis of one or more sweeps to determine changes in timing delays, and extrapolation to timing delay failure values ​​to determine time to failure.

[0067] Optionally, machine learning may be used to analyze one or more sweeps to monitor IC failures, predict future IC failures, and the like.

[0068] Optionally, one or more delay time sweeps may be analyzed to design future ICs, where the future ICs are designed to avoid the failure of previous ICs.

[0069] Optionally, machine learning may be used at the beginning of the chip's life to analyze one or more sweeps, for example, using a timing delay margin signature or IC fingerprint at the beginning of the chip's life. The signature or fingerprint may be used for chip outlier detection / screening, i.e., a particular IC is given a unique ID and signature compared to other ICs that can detect anomalies on a large manufacturing scale.

[0070] Reference is now made to Figures 1 and 2, which schematically illustrate a computerized system 100 and method flowcharts (200 and 210), respectively, for IC failure prediction and logic path margin measurement during IC testing (at the tester or system level). System 100 includes an IC 150, a computer 101A, and a data interface connection 140 connecting the two. IC 150 includes multiple functional units (at 151, 152, 153, etc.) and data paths (at 141, 142A, 142B, 143A, 143B, etc.) between them, which may include synthesis logic. IC 150 includes margin measurement and failure prediction circuits (MFPCs; at 131, 132, 133, etc.) for capturing signals from the data paths (at 142A, 143A, etc.) and determining at least some delay timings from each data path. The MFPC 131, 132, or 133 combines (201) signals from the data paths and tests (202) one or more delays of the combined signals. The IC 150 includes a data interface for connecting to the data interface connection 140 and transmitting (202) the delay timing to the computer 101A. The delay timing data collected for multiple signals in the data paths and / or for multiple delay values, such as by varying (204) the delay, may be considered a fingerprint of the delay timing.

[0071] The computer 101A includes one or more hardware processors 101B, a user interface 120, and a non-transitory computer-readable storage medium 102. The storage medium includes program code, such as an MFPC data receiver 102A, an IC aging analyzer 102B, and an IC failure predictor 102C, that, when executed on the hardware processor(s) 101B, causes the hardware processor(s) 101B to receive (211) signal delay data (i.e., fingerprints) using a data interface 110, such as using the MFPC data receiver 102A. The IC aging analyzer 102B analyzes (212) the fingerprints, and the IC failure predictor 102C notifies (213) an operator of status, failure predictions, preventive measures, etc., such as using the user interface 120.

[0072] Optionally, the delay timing is analyzed by circuitry (not shown) in IC 150 to determine when clock and / or logic modifications (206) on IC 150 will improve the life of IC 150 before failure. Optionally, the delay timing is analyzed by circuitry (not shown) in IC 150 and notifications (206) are issued regarding status or failure prediction.

[0073] Optionally, a delay timing fingerprint may be generated by IC testing (tester or system) to extract a time-zero margin map of the data path of a particular unit.

[0074] The fingerprint may be analyzed during initial operation and monitored over the life of the IC to determine when a predicted failure is likely to occur. For example, a defect degradation gradient analysis may determine the future time of failure of the IC. For example, the minimum margin of the fingerprint may be analyzed, plotting the minimum margin over time, and extrapolating the plot to a margin delay of zero to determine the predicted time to failure.

[0075] Now, refer to Figure 3, which shows an XOR-type circuit diagram for IC failure prediction. The XOR component (XOR1) combines signals from the 64, 128, 256, 512, etc. data paths into a single signal, XOR1_out. XOR1_out is fed to a first flip-flop FF2 and a delay line D2. The delayed XOR1_out is fed to a second flip-flop FF1. FF1 and FF2 are activated by clock clk_3, and their outputs, XOR, are combined in XOR2. XOR2_out is logic 1 at every delay, and at clk_d1, either XOR1_out or XOR1_out_d2 is logic 1.

[0076] Thus, multiple instances of clk_d1 and / or multiple values ​​of D1 may determine timing delay data, and thus a timing delay fingerprint, of delays along the data path of combinational logic FU1. By analyzing these timing delays over time, the MFPC may detect which paths in FU1 are degrading and / or aging fastest, potentially causing failure of IC 150.

[0077] The output signal of XOR1 can be considered a compression of the input signal, maintaining the minimum timing margin delay of the input signal of the data path. If the minimum margin of the input signal is smaller than the delay associated with D2, the output of XOR2 is logic 1. Therefore, XOR1 can be a parity checker, i.e., the output is logic 1 if the parity of the input signal is logic 1. Each rising edge of the compression signal (XOR1 output) can be associated with one rising edge of the input signal. In the simple case where the minimum timing delay margin is associated with only one input, the last rising or falling transition of the XOR1 output represents the minimum margin. This concept can be proven through mathematical proofs described below and event-based simulations. Special cases, such as when some signals have a margin smaller than D2 or when multiple signals switch simultaneously, can be proven through simulations.

[0078] As generally stated above, the IC may further comprise a first internal storage circuit electrically connected to the output of the signal path combiner and arranged to provide the stored signal path combiner output as a first input to the comparison circuit, and a second internal storage circuit electrically connected to the delayed signal and arranged to provide the delayed signal as a second input to the comparison circuit, although such configuration is optional, as will be explained below.

[0079] Reference is now made to Figure 3A, which shows a different version of an XOR-type circuit diagram for IC failure prediction compared to that shown in Figure 3. The data path shown in Figure 3A has essentially the same structure as that shown in Figure 3. In this version, the XOR component XOR1a combines signals from the 64, 128, 256, 512, etc. data paths into a single output signal XOR1a. out Binds to XOR1a out is supplied as a first input to the second XOR circuit XOR2a and in parallel to a delay line D2, the output of which provides a second input to the second XOR circuit XOR2a. out The delayed output signal from the flip-flop FF1b is supplied to the flip-flop FF1b, which is activated by the clock (clk1a). The second output signal XOR2a out is a logic 1 for each delay, and the two inputs of the second XOR circuit, XOR2a, are in different logic states at the time of clk1a.

[0080] Reference is now made to FIG. 3B, which illustrates yet another version of an XOR-type circuit diagram for IC failure prediction compared to that shown in FIG. 3. In this version, two XOR-type failure prediction circuits are provided that use one delay line circuit. In other words, two data paths are provided, each of which may conform to that shown in FIG. 3 or FIG. 3A. The first failure prediction circuit includes a first XOR component XOR1a driven by a set of parallel input signals from the first data path (as described with reference to FIG. 3 or FIG. 3A above), a second XOR component XOR2a, and a first flip-flop clocked by a first clock signal clk1a. FF1a The second fault prediction circuit comprises a third XOR component XOR1b, a fourth XOR component XOR2b, and a fourth XOR component XOR3b, which are driven by a set of parallel input signals from the second data path (as described with reference to FIG. 3 or FIG. 3A above), and a fourth XOR component XOR4b, which is clocked by a second clock signal clk1b. 2 and a flip-flop FF1b. The common delay line D2 provides two fault prediction circuits by selecting, in time-shared mode, via a multiplexer mux, whether the output of the first XOR component XOR1a or the output of the third XOR component XOR1b is provided as input to the common delay line D2. This is controlled using a selection signal In / out sel. The configuration of each of the two fault prediction circuits is otherwise as shown in Figure 3A. A first flip-flop FF1b, clocked by a first clock signal clk1a FF1aThe outputs of the first XOR component XOR1a and the output of the second flip-flop FF1b, which is clocked by the second clock signal clk1b, are provided as inputs to an OR gate to generate the output signal MT-out. When a multiplexer mux connects the output of the first XOR component XOR1a to the input of the delay line D2, the output signal MT-out is a logic 1 for each delay if the two inputs of the second XOR component XOR2a are in different logic states at the time of the first clock signal clk1a. When a multiplexer mux connects the output of the third XOR component XOR1b to the input of the delay line D2, the output signal MT-out is a logic 1 for each delay if the two inputs of the fourth XOR component XOR2b are in different logic states at the time of the second clock signal clk1b.

[0081] Generally speaking, the signal path combiner may be considered to be a first signal path combiner arranged to receive multiple signals from a first data source (which may be a data path or other set of signals as described herein), and the comparison circuit may be considered to be a first comparison circuit. The IC may then be considered to further include a second signal path combiner including multiple input paths and an output, the output of the second signal path combiner being based on a combination of the respective signals received on each input path, the signal being received from the second data source. A multiplexer may then be provided that receives the output of the first signal path combiner and the output of the second signal path combiner and is configured to selectively output the output of the first signal path combiner or the output of the second signal path combiner based on a received selection signal. The output of the multiplexer may be provided as an input to a delay circuit (such that the delay circuit is common to both the first and second signal path combiners). The IC may further include a second comparison circuit arranged to provide a second comparison output based on a comparison of the output of the second signal path combiner and the delayed signal (which may thereby be common to both the first and second comparison circuits). The OR gate may further be arranged to receive the first comparison output and the second comparison output as inputs and to provide an output as a comparison data signal to the at least one mitigation circuit.Referring to the method aspect, this may further include combining respective signals received on each of the plurality of input paths at a second signal path combiner to provide an output, where the signals are received from a second data source; receiving an output of the first signal path combiner, an output of the second signal path combiner, and a selection signal at a multiplexer and selectively outputting the output of the first signal path combiner or the output of the second signal path combiner based on the selection signal, where the delaying step delays the output of the first signal path combiner or the output of the second signal path combiner by a variable delay time in the delay circuit to output a delayed signal; comparing the output of the second signal path combiner with the delayed signal to provide a second comparison output; and receiving the first comparison output and the second comparison output as inputs at an OR gate and outputting the comparison data signal as an output from the OR gate to at least one mitigation circuit.

[0082] Optionally, a first comparison storage circuit controlled by a first clock signal may be arranged to receive the first comparison output. In turn, a second comparison storage circuit controlled by a second clock signal (which may be the same as or different from the first clock signal) may be arranged to receive the second comparison output. The first comparison storage circuit is advantageously arranged to provide the first comparison output as a first input to an OR gate, and the second comparison storage circuit is arranged to provide the second comparison output as a second input to the OR gate.

[0083] Reference is now made to FIG. 4, which shows a MUX-type circuit diagram for IC fault prediction. A multiplexer (Mux_sel) is used to select one or more data paths, which are then subjected to delay-timing fingerprint detection as described herein. The advantage of a MUX-type MFPC is that one signal at a time is selected for delay timing, so faults may be detected with less data (such as a dedicated analysis circuit in the IC). Optionally, a MUX / XOR-type hybrid MFPC may be used, which combines some of the advantages of each type of MFPC.

[0084] Reference is now made to FIG. 5, which shows a circuit diagram for an anti-IC aging mode. This diagram illustrates an anti-aging technique that deactivates the XOR circuit when the MFPC circuit is not enabled, i.e., when the MFPC clock is gated. When the circuit is disabled, constant logic delays increase circuit degradation due to NBTI effects, etc. To mitigate NBTI degradation, the XOR circuit is switched on each time the MFPC clock is gated. Alternatively, each signal is individually monitored for margin degradation. FIG. 5 is just one example of an alternative embodiment of circuit modifications that may be performed to compensate for IC circuit degradation and / or aging. Many other circuit examples may be used.

[0085] The techniques disclosed herein can be extended to other types of logic paths / signals, path lengths, and different types of generating and sampling electronic elements. For example, phase paths, latch-based logic paths, gated clock logic paths, and falling-edge-timed logic signals of flip-flops (FFs) can be used. For example, embodiments may detect hold faults (minimum delay) caused by delay degradation of a clock path. In this example, a new delay path (e.g., D4) is placed between the clock of FF1 and FF2, and the D4 delay value delays the clock of FF2.

[0086] The MFPC is always on or activated by an enable signal. For example, the enable signal represents the logical OR of the enable signals corresponding to the group of FFs sampled by the MFPC. When the enable is low, the MFPC may enter anti-IC aging mode detection and use a dedicated clock to switch the MFPC, mitigating the NBTI aging effect.

[0087] If the MFPC covers a large logic region (FU) of the IC, the MFPC may be used as a timing delay margin signature or fingerprint of the IC in its initial operation. Over time, the MFPC may measure the margin signature at various times to analyze and detect the time gradient of the IC's degradation / aging. Different gradient functions may be associated with different types of defects and degradation modes.

[0088] Optionally, the signature includes multiple overlapping delay margins, with several critical timing delay margins identified as having different time gradients, each analyzed separately to predict future IC failures. For example, a nonlinear spatiotemporal correlation method may be used to simultaneously track multiple timing delay margins from a set of signatures or fingerprints, with each signature or fingerprint representing a one-dimensional vector of all overlapping timing delays. For example, a transformation of the multiple one-dimensional vectors may be performed to generate a two- or higher-dimensional data representation. See, for example, Laube et al., "Analyzing Relative Motion within Groups of Trackable Moving Point Objects," in Lecture Notes in Computer Science (Egenhofer et al. - editors - Geographic Information Science, GIScience 2002), vol. 2478 (Springer, Berlin, Heidelberg), pp. 132-144, published in 2002, which is incorporated by reference in its entirety.

[0089] As the performance of a semiconductor integrated circuit degrades over time, the progression of physical defects can gradually increase the delay time of the IC's circuitry. If the delay time exceeds the IC's clock cycle time, the IC may fail. While existing defect detection techniques can sometimes detect defects after they have occurred, preventive maintenance is performed when significant failures are predicted. This is particularly important for applications where the cost of failure is high (e.g., autonomous vehicles), the cost of replacement is high (e.g., satellite IC failure), or the cost of product image failure is high (e.g., resulting in a negative user experience). Embodiments of integrated circuits (ICs) using the techniques disclosed herein include failure prediction circuits and systems that can warn of impending failures before they occur.

[0090] For example, in the general sense above, the variable delay time may be set in integer multiples in increments equal to the IC's clock period divided by a factor (the "signature vector size"), preferably between 1 and 100,000.

[0091] In some embodiments, the fault prediction circuit is comprised of a pair of storage components (e.g., flip-flops) that both receive data signals output from multiple paths of the IC, such as data paths, memory paths, and logic paths. To reduce overhead, the data signals are reduced before being stored in the two storage components using a Hamming code, parity code, other error correction techniques, or the like. The two storage components differ from each other in terms of data signal input timing, clock signal input timing, input signal phase, input logic threshold of the data signal, etc. For example, a variable timing circuit is used to delay the signal to one of the flip-flops.

[0092] The FPC or MFPC further includes electronic components that determine (a) whether the outputs from the two storage components match or mismatch, and (b) how close the delay between the mismatched outputs is to the IC's clock cycle time.

[0093] In operation, after a match or mismatch of the signal outputs is determined (such as using the XOR component), the fault prediction circuit increases the input timing, clock signal input timing, or input logic threshold of one of the storage components, and a match or mismatch of the outputs is again determined. This cycle may be repeated in small increments.

[0094] A log is maintained of the relative lengths of detected delays to clock cycle times, as well as the increments of storage components used. Analysis such as trend detection, combinatorial analysis, machine learning, regression analysis, and anomaly detection may be performed on the log data to estimate when degradation of the IC may lead to IC failure, such as when the shortest logic path delay exceeds the subsequent clock cycle time.

[0095] This measurement and / or estimation may be utilized in several ways. A warning may be issued to the user of the system in which the IC is implemented, indicating the margin (how close the delay is to the IC's clock cycle time) or estimated time to failure. Additionally, an agent may prescribe operational changes to the IC, such as clock speed or voltage reduction, which may postpone failure and extend the IC's lifespan.

[0096] By using fewer components to continuously monitor logic circuits at the datapath output, resources such as IC area and power may be saved compared to existing techniques.

[0097] For example, input signals are compressed (packed into Hamming space) to generate Hamming codes. Hamming codes may be used for higher-order error detection, correction, and / or prediction processes. For example, an XOR-type circuit may be used to combine all data path signals into two unified signal paths that implement modulo 4 logic operations. Other types of compressed (source) codes may be used in addition or instead.

[0098] As mentioned above, generally speaking, the signal path combiner (or at least one of the signal path combiners) can be understood to include at least one of a logical XOR combiner (as shown in FIG. 3 or FIG. 3A), a Hamming parity combiner, and a multiplexer.

[0099] This technique may be extended to other types of logic paths and sequential elements of sampling, for example: Phase pass Latched logic path Gated Clock Logic Path ●Fall-type logic path for data path signals ●Memory input / output

[0100] The failure prediction circuitry may be always on or may be activated by an enable signal that represents the logical OR of the signals in the data path. When enable is low, the failure prediction circuitry uses a dedicated clock to switch the circuitry, mitigating aging effects.

[0101] An integrated circuit may implement a large number of synchronization and timing-sensitive logic circuits. Increased circuit delay due to physical degradation can result in timing violations and affect the functionality of the circuit. Physical degradation can be due to aging effects or defects introduced during use. A failure prediction circuit may track logic delay margins over time and predict failures due to physical delay degradation.

[0102] Thus, as described above, generally speaking, the mitigation circuitry can be considered to be at least one circuit from the group consisting of notification circuitry (e.g., configured to generate notification 206 or 213), timing delay measurement (or estimation) circuitry (e.g., for providing a timing delay output), data transmission circuitry, IC anti-aging compensation circuitry (e.g., as described with reference to FIG. 5 above), and failure analysis circuitry.

[0103] If the mitigation circuit is a data transmission circuit, it may be electronically connected to a computerized server. The computerized server is then advantageously configured to receive multiple instances of the comparison data signal (e.g., for different times and / or different data sources). This allows the computerized server to perform a failure prediction analysis of the comparison data signal. Optionally, if the failure prediction analysis predicts failure of the IC within a predefined time, it may send a notification to the mitigation module (e.g., an IC anti-aging compensation circuit). At least some of the comparison data signals may be generated at multiple values ​​of the variable delay time, and / or at least some of the comparison data signals may be generated from multiple instances of at least one value from multiple values ​​of the variable delay time. Optionally, the failure prediction analysis includes at least one of machine learning analysis, trend analysis, multiple-object tracking analysis, and multivariate analysis. Advantageously, the failure prediction analysis includes receiving the comparison data signals and / or failure prediction analysis results from multiple different ICs.

[0104] The fault prediction circuitry advantageously continuously monitors a large number of logic circuits, such as datapath signals on the outputs of functional units of an IC, using a small IC area and power.

[0105] In some embodiments, a computer algorithm may be used to determine the number of fault prediction circuits within a unit for each predefined coverage. Design data, such as memory circuits and flip-flop circuits within the unit, may be used. A computer algorithm may also be used to automatically identify FPC or MFPC circuits for each unit clock gate signal and automatically set the input signal size per FPC or MFPC circuit for optimal performance (maximum instance coverage with the minimum number of FPCs or MFPCs).

[0106] In some embodiments, delays within the fault prediction circuitry may be calibrated. This may be done to provide accurate margin results at time zero (during test) due to an ultra-fast correlation path to design data. One calibration method may use pre-Si estimators based on post-Si on-die sensors (agents) to convert pre-Si measured FPC or MFPC circuit margins into worst-case margins for the monitored endpoints (FFs).

[0107] Generally speaking, this may involve measuring or estimating a timing delay (particularly during initial or time-zero operation) of the IC based on a comparison data signal provided to the mitigation circuit. The timing delay may be based on multiple comparison outputs (which may be contained in a single comparison data signal or multiple comparison data signals), and may be determined, for example, by repeating the combining, delaying, and comparing steps for each of multiple delay times.

[0108] In some embodiments, the delay through X1..Xn+Xor1A+Xor2A is balanced with the delay applied to the clock used for the output flip-flop (D3) to minimize calibration shift.

[0109] In some embodiments, timing margin data for large-scale logic circuits within a unit or die, such as digital logic circuits, extracted at time zero may be tracked and compared over time. Tracking may detect and / or predict timing failures due to IC delay changes and / or aging. Referring now to FIG. 11 , a unit margin map diagram is shown. This is an example of a unit margin map that represents a fingerprint of unit margin at the beginning of life (the margin is expressed in equivalent buffer delays). The signature may be used for chip outlier detection / screening. In other words, a specific IC is given a unique ID, and the signature is compared to other ICs, enabling anomaly detection on a large manufacturing scale. The margin map can be tracked over time to measure margin signatures at various times and analyze and detect the time gradient of IC degradation or aging. Different gradient functions may be associated with different types of defects and degradation modes.

[0110] In some embodiments, die margin data can be collected and used in the die classification and anomaly detection process. This is done by collecting margin data for units within the die and using ML algorithms to build an estimation function based on on-die sensors. More details are described in U.S. Provisional Patent Application No. 62 / 675,986, entitled "INTEGRATED CIRCUIT PROFILING AND ANOMALY DETECTION," filed April 16, 2018, the entire contents of which are incorporated herein by reference.

[0111] In some embodiments, the margin data can be analyzed for each particular running application to generate application-based frequency / power binning.

[0112] Below is a mathematical proof that can rely on the assumption that all paths are independent. For simplicity, the proof is performed using the circuit described in Figure 3. The proof is also valid for the circuit described in Figure 3A under the assumption that XOR2a is symmetric. This assumption can be relaxed, with appropriate modifications, if necessary, in the case of at least some dependent paths. Let any time be denoted by t, and the paths

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[0113] For any time interval, the MUX-based MFPC can be considered a special case of the XOR-based MFPC. Therefore, the mathematical proofs for the XOR-based version below also apply to the MUX-based version.

[0114] Experimental results The following are the results of the simulation experiment.

[0115] Now, refer to Figure 6, which shows a timing diagram of signal delays for IC failure prediction. The signal definition can be Di≈U(Xi, Xi+di), and P{V(Si)=1,tj}=P{V(Si)=0,tj}=½. Figure 6 shows the event-based simulation description using the simulation setup. ●XOR1 monitored 256 input paths. The data length of each path is 10 4 It was a clock cycle. ●The clock cycle time is defined as 100 time units. ●A signal [Si] was generated for each path [i] (detailed explanation is on the next page). Each path [i] is defined by two constants [Xi] and [di] that determine the delay per clock cycle. ●[Xi] was plotted on each path with a uniform distribution between 25 and 50 time units. ●[di] was plotted with a uniform distribution between 0 and 25 time units for each pass. ●For signal i, the switching time of each cycle is drawn uniformly in the range (Xi, Xi+di). • Therefore, the margin of signal i is [100-Xi-di].

[0116] Experiments were performed for each value of D2, where D2 is defined in units of time and the D2 delay value was swept through values ​​with the resolution needed to resolve the signature's individual timing delay margin, such as a resolution of a fraction of a clock period. For each D2 value, XOR2 output transitions may be counted and the counts plotted against the margin timing value threshold. The margin threshold on the X-axis may be 100-D2, and the Y-axis may be the number of 1s at the XOR2 output observed at a particular D2 value. If XOR1(t=100)≠XOR1(=D2), then XOR2=1

[0117] Refer now to Figure 7, which shows a graph of error versus cycle time for the first experiment. The solid line represents the MFPC output at time zero (no degradation), and the dashed line represents the MFPC output after degradation. The minimum margin was equal to 25 time units, such as [100-75], and MaxD2 at failure was 75 time units. In the degradation scenario, the margin of one path was reduced by 15 time units (the margin was uniformly distributed, and the maximum value was moved by 15 time units), and the MFPC detected the change in margin. Here, the minimum margin was equal to 10 time units, such as [100-75-15], and MaxD2 at failure was 90 time units. The graph shows that the count of the XOR2 output gradually decreases to zero. For each D2 in the range [75-90]: P(XOR2=1)=P(change, delay>D2)=0.5*(90-(100-D2)) / (di+15)

[0118] Reference is now made to Figure 8, which shows a graph of error versus cycle time for the second experiment. The solid line represents the MFPC output at time zero (no degradation), and the dashed line represents the MFPC output after degradation. The minimum margin for all paths with [Xi + di > 70] (margin < 30) was increased by 15 time units, as performed for five signal paths. The minimum margin was equal to 25 time units, such as [100 - 75], and MaxD2 at failure was 75 time units. The MFPC detected the margin change, and the minimum margin was equal to 10 time units, such as [100 - 75 - 15], and MaxD2 at failure was 90 time units. The count at the XOR2 output gradually decreased to zero. The probability of failure increased with the number of paths.

[0119] Now refer to Figure 9 (top diagram), which shows a timing diagram of two signal delays for IC failure prediction. Multiple signals are switched simultaneously, with equal delays and logic values ​​used in each cycle. The duplicated signals are implemented with minimal margin. The maximum value of [Xi+di] is shown, and the delay of the duplicated path is increased by 15 time units. Both paths implement the same degradation.

[0120] Reference is now made to Figure 10, which shows a graph of error versus cycle time for the third experiment. The solid line represents no degradation, the dashed line (similar to the solid line) represents the first degradation scenario (upper line in Figure 9), and the dash-dotted line represents the second degradation scenario (lower line in Figure 9) in which the delay of one of the replicated paths is increased by an additional 5 time units. Note that the delay of the replicated signal is 5 time units less than the base signal. The two paths are logically identical but have different timing degradations. The minimum margin was equal to 25 time units, e.g., [100 - 75]. In the first degradation scenario (dashed line), the system does not detect a change in margin. MaxD2 at failure corresponds to 75 time units in both scenarios. In the second degradation scenario (dashed line), the system detects a change in margin. MaxD2 at failure was 95 time units.

[0121] Throughout this application, various embodiments of the invention may be presented in a range format. It should be understood that the description in range format is merely for convenience and brevity and should not be construed as an inflexible limitation on the scope of the invention. Accordingly, the description of a range should be considered to have specifically disclosed all possible subranges and individual numerical values ​​within that range. For example, a description of a range such as 1 to 6 is considered to have specifically disclosed subranges such as 1 to 3, 1 to 4, 1 to 5, 2 to 4, 2 to 6, 3 to 6, etc., as well as individual numbers within that range, e.g., 1, 2, 3, 4, 5, 6. This applies regardless of the breadth of the range.

[0122] Whenever a numerical range is given herein, it is meant to include any recited number (fractional or integer) within the range given. The phrases "ranging between" a first denoted number and a second denoted number and "ranging between" a first denoted number and a second denoted number are used interchangeably herein and are meant to include the first and second denoted numbers and all fractional and integer numbers therebetween.

[0123] In the description and claims of this application, the words "comprise," "include," and "have," and each of their forms, do not necessarily limit the members in a list with which the word may be associated. Furthermore, in the event of a conflict between this application and any document incorporated by reference, it is hereby intended that the present application shall control.

[0124] It should be noted that the use of nouns, such as general nouns, proper nouns, named nouns, etc., for clarity of reference in this disclosure does not imply that embodiments of the invention are limited to a single embodiment, and that while many configurations of the disclosed components may be used to describe some embodiments of the invention, other configurations may be derived from these embodiments in different configurations.

[0125] For clarity, not all of the features of the practices described herein are shown and described. Of course, the development of any such actual implementation will require making numerous implementation-specific decisions to achieve the developer's particular goals, such as adhering to application- and business-related constraints, and these particular goals will vary from implementation to implementation and developer to developer. Moreover, it will be appreciated that such a development effort may be complex and time-consuming, but would nevertheless be a routine undertaking of engineering for those of ordinary skill in the art having the benefit of this disclosure.

[0126] It is expected that, based on the teachings of this disclosure, one skilled in the art will be able to easily practice the present invention. The description of the various embodiments provided herein is believed to provide sufficient insight and detail into the present invention to enable one skilled in the art to practice the present invention. Moreover, it is specifically contemplated that the various features and embodiments of the present invention described above can be used alone as well as in various combinations.

[0127] Conventional and / or modern circuit design and layout tools may be used to implement the present invention. The specific embodiments described herein, particularly the various thicknesses and compositions of the various layers, are illustrative of example embodiments and should not be considered to limit the present invention to such specific implementation choices. Thus, multiple instances may be provided for components described herein as single instances.

[0128] While circuits and physical structures are generally inferred, in modern semiconductor design and manufacturing, physical structures and circuits may be embodied in computer-readable descriptive forms suitable for use in subsequent design, test, or manufacturing stages, as well as in the resulting manufactured semiconductor integrated circuits. Accordingly, claims directed to conventional circuits or structures may be read based on computer-readable encodings and representations thereof, whether embodied in a medium or combined with an appropriate reading facility, consistent with that specific language to enable the manufacture, testing, or design improvement of the corresponding circuits and / or structures. fruit Structures and functions presented as separate components in exemplary configurations may be implemented as combined structures or components. The present invention is intended to include circuits, systems of circuits, associated methods, and computer-readable medium encodings of such circuits, systems, and methods, all of which are described herein and defined in the appended claims. As used herein, computer-readable medium includes at least disk, tape, or other magnetic, optical, semiconductor (e.g., flash memory card, ROM), or electronic medium, as well as network, wired, wireless, or other communication medium.

[0129] The foregoing detailed description has described only a few of the many possible implementations of the present invention. For this reason, this detailed description is intended to be illustrative and not limiting. Variations and modifications of the embodiments disclosed herein may be made based on the description set forth herein without departing from the scope and spirit of the present invention. It is only the following claims, including all equivalents, that are intended to define the scope of the present invention. In particular, while preferred embodiments are described in the context of several specific circuit designs for semiconductor ICs, the teachings of the present invention are believed to be advantageous for use in other types of semiconductor IC circuits. Furthermore, the techniques described herein may be applied to other types of circuit applications. Accordingly, other variations, modifications, additions, and improvements may be included within the scope of the present invention, as defined by the following claims.

[0130] Embodiments of the present invention may be used to manufacture, produce, and / or assemble integrated circuits and / or products based on integrated circuits.

[0131] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0132] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may be executed in the reverse order, depending on the functionality involved. It should also be noted that each block in the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, may be implemented by a special-purpose hardware-based system that performs the specified functions or operations or executes a combination of dedicated hardware and computer instructions.

[0133] The description of various embodiments of the present invention has been presented for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. Combinations of features and / or aspects disclosed herein are possible between different embodiments of the FPC or MFPC or even between other features of other designs and / or drawings of other features. The terminology used herein has been selected to best explain the principles of the embodiments, practical applications, or technical improvements over technology found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. 1. A semiconductor integrated circuit (IC), comprising: a data path comprising parallel bit paths, each of the parallel bit paths terminating in a flip-flop; a signal path combiner comprising: (a) a plurality of input paths; and (b) an output, the output providing a signal based on a combination of a plurality of respective signals received on each of the input paths, the input paths being each connected to an input of a different one of the flip-flops of the data path, such that each of the plurality of signals received on the input paths is a respective signal received by each flip-flop of the data path; a delay circuit having (a) an output and (b) an input electrically connected to the output of the signal path combiner, the delay circuit being configured to apply different respective delays at different times to signals received from the output of the signal path combiner at the input of the delay circuit to provide different delayed signals at the output of the delay circuit representative of the different respective delays; A comparison circuit, providing comparison outputs based on comparing different ones of the signal path combiner outputs and the delayed signals, respectively; providing said comparison output as at least one comparison data signal; A comparison circuit arranged as follows: An IC comprising:

2. The IC of claim 1 , wherein the signal path combiner is selected from the group consisting of a logical XOR combiner, a Hamming parity combiner, and a multiplexer.

3. the signal path combiner is the logical XOR combiner, and the IC a first flip-flop connected to receive (a) an input from an output of the logical XOR combiner in parallel with the delay circuit, and (b) a clock signal; a second flip-flop coupled to receive (a) the output of the delay circuit, and (b) the clock signal; an XOR component connected to receive (a) the output of the first flip-flop, and (b) the output of the second flip-flop; The IC of claim 2 , further comprising:

4. The XOR component includes: the output of the logical XOR combiner; and One of the delayed signals 4. The IC of claim 3, further configured to output a logic 1 when only one of

5. 3. The IC of claim 2, wherein the signal path combiner is a Hamming parity combiner, the Hamming parity combiner configured to compress signals received on the input paths into a Hamming space.

6. 3. The IC of claim 2, wherein the signal path combiner is a multiplexer configured to select one or more of the signals on the input paths for delay by the delay circuit.

7. a first internal storage circuit electrically connected to an output of the signal path combiner and arranged to provide the stored output of the signal path combiner as a first input to the comparison circuit; a second internal storage circuit electrically connected to receive each of the delayed signals and arranged to provide each stored delayed signal as a second input to the comparison circuit; The IC of claim 1 further comprising:

8. the signal path combiner is a first signal path combiner arranged to receive a plurality of signals from a first data source, the comparison circuit is a first comparison circuit, and the IC a second signal path combiner having a second set of input paths and an output, the output being based on a combination of respective signals received on each of the second set of input paths from a second data source; and a multiplexer configured to receive an output of the first signal path combiner, an output of the second signal path combiner, and a selection signal and to selectively output the output of the first signal path combiner or the output of the second signal path combiner based on the selection signal, the output of the multiplexer being provided as an input to the delay circuit; a second comparison circuit arranged to provide a second set of comparison outputs based on a comparison of the output of the second signal path combiner and the delayed signal; an OR gate arranged to receive as inputs a first comparison output of the first comparison circuit and a second comparison output of the second comparison circuit and provide as the at least one comparison data signal; The IC of claim 1 further comprising:

9. The IC is a first comparison storage circuit disposed to receive the first comparison output and controlled by a first clock signal; a second comparison storage circuit disposed to receive each of the second comparison outputs and controlled by a second clock signal; Further equipped with 9. The IC of claim 8, wherein the first compare storage circuit is arranged to provide each of the first compare outputs as a first input to the OR gate, and the second compare storage circuit is arranged to provide each of the second compare outputs as a second input to the OR gate.

10. The IC of claim 1 , further comprising: circuitry configured to measure a minimum delay margin among delay margins of input paths of the signal path combiner.

11. 11. The IC of claim 10, wherein the circuitry configured to measure the minimum delay margin is further configured to predict future failures of the IC based on analyzing changes in the minimum delay margin over time.

12. The IC of claim 11 , further comprising: circuitry configured to perform clock and / or logic corrections to extend the life of the IC prior to a predicted future failure of the IC.

13. 1. A system comprising: A computerized server; 2. The IC of claim 1, a data transmission circuit configured to transmit the at least one comparison data signal to the computerized server; a circuit configured to perform clock and / or logic corrections to extend the life of the IC prior to failure of the IC; An IC further comprising: A system comprising: The computerized server includes: receiving the at least one comparison data signal; performing a failure prediction analysis of the at least one comparison data signal; When the failure prediction analysis predicts a failure of the IC within a predefined time, sending a notification to a circuit configured to perform the clock correction and / or the logic correction, such that each circuit performs the clock correction and / or the logic correction to extend the life of the IC. The system is configured as follows.

14. 1. A method performed by a semiconductor integrated circuit (IC), the IC comprising a data path having parallel bit paths, each of the parallel bit paths terminating in a flip-flop, the method comprising: combining a plurality of respective signals received on each of a plurality of input paths of a signal path combiner to provide a signal at an output of the signal path combiner, the input paths being respectively connected to inputs of different ones of the flip-flops of the data paths, whereby each of the plurality of signals received on the input paths is a respective signal received by each flip-flop of the data paths; operating a delay circuit having (a) an output and (b) an input electrically connected to the output of the signal path combiner, said operating comprising applying different respective delays at different times to signals received from the output of the signal path combiner at the input of the delay circuit to provide different delayed signals at the output of the delay circuit representative of the different respective delays; operating a comparison circuit to compare each of a plurality of outputs of the signal path combiner with a different one of the delayed signals to provide a comparison output; providing said comparison output as at least one comparison data signal; A method comprising:

15. 15. The method of claim 14, wherein the signal path combiner is selected from the group consisting of a logical XOR combiner, a Hamming parity combiner, and a multiplexer.

16. the signal path combiner is the logical XOR combiner, and the method comprises: operating a first flip-flop to receive (a) an input from an output of the logical XOR combiner in parallel with the delay circuit, and (b) a clock signal; operating a second flip-flop to receive (a) an output of the delay circuit, and (b) the clock signal; Operate an XOR component to receive (a) an output of the first flip-flop, and (b) an output of the second flip-flop; The method of claim 15 further comprising:

17. The operation of the XOR component is as follows: the output of the logical XOR combiner; and One of the delayed signals 17. The method of claim 16, further configured to output a logic one when only one of is at logic one during the clock signal.

18. 16. The method of claim 15, wherein the signal path combiner is the Hamming parity combiner, the method further comprising compressing signals received on the input paths into a Hamming space using the Hamming parity combiner.

19. 16. The method of claim 15, wherein the signal path combiner is the multiplexer, the method further comprising using the multiplexer to select one or more of the signals on the input paths for delay by the delay circuit.

20. storing an output of the signal path combiner in a first internal storage circuit and providing the stored output of the signal path combiner from the first internal storage circuit as a first input to the comparison circuit; storing the delayed signal in a second internal storage circuit and providing the stored delayed signal from the second internal storage circuit as a second input to the comparison circuit; The method of claim 14 further comprising:

21. The signal path combiner is a first signal path combiner that receives a plurality of signals from a first data source, the comparison circuit is a first comparison circuit, and the method includes: combining, at a second signal path combiner, each signal received on each input path of a second set of input paths from a second data source; receiving an output of the first signal path combiner, an output of the second signal path combiner, and a selection signal at a multiplexer, and selectively outputting the output of the first signal path combiner or the output of the second signal path combiner from the multiplexer based on the selection signal; providing an output of the multiplexer as an input to the delay circuit, whereby delaying an output of the signal path combiner comprises delaying an output of the first signal path combiner or an output of the second signal path combiner; comparing the output of the second signal path combiner and the delayed signal in a second comparison circuit to provide a second set of comparison outputs; an OR gate receiving a first comparison output of the first comparison circuit and a second comparison output of the second comparison circuit to provide the at least one comparison data signal; The method of claim 14 further comprising:

22. receiving each of the first compare outputs in a first compare and store circuit controlled by a first clock signal; receiving each of the second compare outputs in a second compare and store circuit controlled by a second clock signal; providing each of the first compare outputs from the first compare storage circuit as a first input to the OR gate; providing each of the second compare outputs from the second compare storage circuit as a second input to the OR gate; 22. The method of claim 21 further comprising:

23. 15. The method of claim 14, further comprising measuring a minimum delay margin among delay margins of input paths of the signal path combiner.

24. 24. The method of claim 23, further comprising predicting future failures of the IC based on analyzing changes in the minimum delay margin over time.

25. 25. The method of claim 24, further comprising performing clock and / or logic corrections to extend the life of the IC prior to a predicted future failure of the IC.

26. A computer-readable medium having stored thereon a computer-readable encoding of a semiconductor integrated circuit (IC), the IC comprising: a data path comprising parallel bit paths, each of the parallel bit paths terminating in a flip-flop; a signal path combiner comprising: (a) a plurality of input paths; and (b) an output, the output providing a signal based on a combination of a plurality of respective signals received on each of the input paths, the input paths being each connected to an input of a different one of the flip-flops of the data path, such that each of the plurality of signals received on the input paths is a respective signal received by each flip-flop of the data path; a delay circuit having (a) an output and (b) an input electrically connected to the output of the signal path combiner, the delay circuit being configured to apply different respective delays at different times to signals received from the output of the signal path combiner at the input of the delay circuit to provide different delayed signals at the output of the delay circuit representative of the different respective delays; A comparison circuit, providing comparison outputs based on comparing different ones of the signal path combiner outputs and the delayed signals, respectively; providing said comparison output as at least one comparison data signal; A comparison circuit arranged as follows:

13. A computer-readable medium comprising:

27. The computer-readable medium of claim 26, wherein the signal path combiner is selected from the group consisting of a logical XOR combiner, a Hamming parity combiner, and a multiplexer.

28. The signal path combiner is the logical XOR combiner, and the IC comprises: a first flip-flop connected to receive (a) an input from an output of the logical XOR combiner in parallel with the delay circuit, and (b) a clock signal; a second flip-flop coupled to receive (a) the output of the delay circuit, and (b) the clock signal; an XOR component connected to receive (a) the output of the first flip-flop, and (b) the output of the second flip-flop; 30. The computer readable medium of claim 27, further comprising:

29. The XOR component comprises: the output of the logical XOR combiner; and One of the delayed signals 30. The computer-readable medium of claim 28, further configured to output a logic one when only one of is a logic one during the clock signal.

30. The computer-readable medium of claim 27, wherein the signal path combiner is a Hamming parity combiner, the Hamming parity combiner being configured to compress signals received on the input paths into a Hamming space.

31. The computer-readable medium of claim 27, wherein the signal path combiner is a multiplexer configured to select one or more of the signals of the input path with respect to a delay by the delay circuit.

32. A first internal storage circuit electrically connected to an output of the signal path combiner and arranged to provide a stored output of the signal path combiner as a first input to the comparison circuit; a second internal storage circuit electrically connected to receive each of the delayed signals and arranged to provide each stored delayed signal as a second input to the comparison circuit; 27. The computer readable medium of claim 26, further comprising:

33. The signal path combiner is a first signal path combiner arranged to receive a plurality of signals from a first data source, the comparison circuit is a first comparison circuit, and the IC is a second signal path combiner having a second set of input paths and an output, the output being based on a combination of respective signals received on each of the second set of input paths from a second data source; and a multiplexer configured to receive an output of the first signal path combiner, an output of the second signal path combiner, and a selection signal and to selectively output the output of the first signal path combiner or the output of the second signal path combiner based on the selection signal, the output of the multiplexer being provided as an input to the delay circuit; a second comparison circuit arranged to provide a second set of comparison outputs based on a comparison of the output of the second signal path combiner and the delayed signal; an OR gate arranged to receive as inputs a first comparison output of the first comparison circuit and a second comparison output of the second comparison circuit and provide as the at least one comparison data signal; 27. The computer readable medium of claim 26, further comprising:

34. The IC, a first comparison storage circuit disposed to receive the first comparison output and controlled by a first clock signal; a second comparison storage circuit disposed to receive each of the second comparison outputs and controlled by a second clock signal; Further equipped with 34. The computer-readable medium of claim 33, wherein the first comparison storage circuit is arranged to provide each of the first comparison outputs as a first input to the OR gate, and the second comparison storage circuit is arranged to provide each of the second comparison outputs as a second input to the OR gate.

35. The computer-readable medium of claim 26, further comprising circuitry configured to measure a minimum delay margin among delay margins of input paths of the signal path combiner.

36. The computer-readable medium of claim 35, wherein the circuitry configured to measure the minimum delay margin is further configured to predict future failures of the IC based on analyzing changes in the minimum delay margin over time.

37. The computer-readable medium of claim 36, further comprising circuitry configured to perform clock and / or logic corrections to extend the life of the IC prior to a predicted future failure of the IC.

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