MEMORY, MEMORY CONTROL METHOD, AND MEMORY SYSTEM

Abstract

An embodiment of the present disclosure provides a memory and a control method thereof, the memory including a storage array and a peripheral circuit, the storage array including a plurality of storage planes, each of the storage planes including a storage block composed of storage cells, the peripheral circuit being connected to the storage array and configured to control the plurality of storage planes to perform asynchronous operations, the peripheral circuit including at least one state machine, each of the state machines being corresponding to at least one of the plurality of storage planes, the state machine being connected to a memory interface and being capable of receiving control commands related to the asynchronous operations of each of the corresponding storage planes in parallel from the memory interface, and each of the state machines being capable of independently processing the control commands received thereby to obtain control information of the corresponding storage plane.

Description

[Technical field]

[0001] The embodiments of the present disclosure relate to a memory, a memory control method, and a memory system. [Background technology]

[0002] Semiconductor storage devices are being applied more and more widely in various electronic devices. For example, non-volatile semiconductor memory is being applied in cellular phones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and various other electronic devices. With the development of information technology, the amount of data used in these devices is also increasing rapidly, which drives the storage capacity of larger flash memory and promotes faster speed. In order to meet the needs of the market, NAND flash memory technology is developing rapidly, and NAND flash memory chips are often packaged with multiple NAND dies under the package level, thereby increasing the capacity of the NAND flash memory chip. In addition, an operation supporting asynchronous multi-plane independent (AMPI) reading has also been proposed to realize independent reading control of different memory planes.

[0003] However, in order to avoid contention for processing resources of the control commands, serial processing is required for the control commands of different storage planes, which results in a relatively slow overall processing speed, redundant waiting times, and lowers the overall memory access efficiency. Summary of the Invention [Problem to be solved by the invention]

[0004] The embodiments of the present disclosure provide a memory, a memory control method, and a memory system. [Means for solving the problem]

[0005] In a first aspect, an embodiment of the present disclosure provides a memory, comprising: a storage array; and peripheral circuitry; the storage array includes a plurality of storage planes, each of the storage planes including a storage block made up of storage cells; the peripheral circuitry is connected to the storage array and configured to control a plurality of the storage planes to perform asynchronous operations; At least one state machine (STM) is included in the peripheral circuit; Each of the state machines is configured to correspond to at least one of the multiple memory surfaces, the state machines are connected to a memory interface, and can receive control commands related to asynchronous operations of each corresponding memory surface in parallel from the memory interface, and each of the state machines can obtain control information of the corresponding memory surface by independently processing the control commands it receives.

[0006] In some embodiments, the peripheral circuitry is configured to control asynchronous operations on a plurality of the storage surfaces according to control information of a plurality of the state machines.

[0007] In some embodiments, the state machine is further configured to set a parameter according to the control command; There is at least a partial overlap between the time periods occupied by at least two of the state machines processing the control commands and setting the parameter settings.

[0008] In some embodiments, the peripheral circuitry comprises: The system further includes a sequence calculation module connected to a plurality of the state machines and configured to specify a processing order for the control information by the peripheral circuit according to the control information of the plurality of the state machines.

[0009] In some embodiments, the state machine specifically: configured to send a processing request to the sequence operation module according to the control command; The sequence operation module specifically includes: The processing order is determined according to the processing requests sent from a plurality of state machines.

[0010] In some embodiments, the peripheral circuitry further includes a hardware computing module and a plurality of microprocessing units; the hardware operation module is connected to the sequence operation module and configured to sequentially identify control parameters corresponding to the control information according to the processing order; The plurality of microprocessing units each correspond to a respective storage surface, are connected to the hardware computing module, and are each connected to a corresponding one of the storage surfaces, and the plurality of microprocessing units are configured to perform asynchronous operations on each of the storage surfaces in accordance with the control parameters.

[0011] In some embodiments, at least one of the state machines is further coupled to a respective one of the microprocessing units and configured to provide an enable signal to the microprocessing unit upon receiving the control command.

[0012] In some embodiments, the plurality of microprocessing units further comprises: configured to transmit state information to the corresponding state machine after completing a control operation on the storage surface based on one of the control commands; The state machine is further configured to receive a next control command after receiving the state information sent from the corresponding microprocessing unit.

[0013] In some embodiments, the peripheral circuitry further comprises a main processor; The main processor is connected to the memory interface and the multiple microprocessing units, and is configured to receive status information sent from the multiple microprocessing units, and send overall status information determined according to the multiple status information to the memory interface, where the overall status information is used to indicate that all of the multiple microprocessing units have completed control operations based on a set of control commands.

[0014] In some embodiments, the general purpose microprocessor is further configured to receive a reset command, where the reset command is used to reset the operation of each storage plane in the memory.

[0015] In some embodiments, at least one of the state machines is further coupled to a respective one of a plurality of the storage surfaces and configured to transmit address information to a corresponding one of the storage surfaces in accordance with the control command.

[0016] In some embodiments, the asynchronous operations include asynchronous multi-plane independent read operations.

[0017] In some embodiments, the storage array is a three-dimensional flash memory storage array.

[0018] In some embodiments, the number of storage surfaces includes at least four.

[0019] In a second aspect, an embodiment of the present disclosure further provides a method for controlling a memory, the method being performed by a peripheral circuit in the memory, the peripheral circuit including at least one state machine, the method comprising: at least one state machine in said memory receiving control commands associated with asynchronous operations for each storage surface in said memory in parallel, each of said state machines corresponding to at least one of said plurality of storage surfaces; and independently processing each of the control commands received by the state machine to obtain control information for the corresponding storage surface.

[0020] In some embodiments, the method further comprises: The method further includes controlling the peripheral circuitry to perform asynchronous operations on the plurality of storage surfaces based on the control information acquired by the state machine.

[0021] In some embodiments, the method further comprises: The method further includes a step of the state machines setting parameters according to the control commands, wherein there is at least a partial overlap between time periods occupied by at least two of the state machines processing the control commands and setting the parameters.

[0022] In some embodiments, the step of controlling the peripheral circuitry to perform asynchronous operations on the plurality of storage surfaces based on the control information includes: determining a processing order for the control information according to the control information acquired by the state machine; sequentially processing the control information according to the processing order; and controlling asynchronous operations on the plurality of storage surfaces according to the processed control information.

[0023] In some embodiments, the step of determining a processing order for the control information according to the control information provided by the state machine comprises: A sequence operation module in the peripheral circuit receives processing requests transmitted by the plurality of state machines based on the control command; The sequence calculation module specifies a processing order for the control information based on the processing request.

[0024] In some embodiments, the step of sequentially processing the control information according to the processing order comprises: The hardware operation module in the peripheral circuit includes a step of sequentially specifying control parameters corresponding to the control information in accordance with the processing order according to the control information provided from the state machine.

[0025] In some embodiments, the step of controlling asynchronous operations on the plurality of storage surfaces in accordance with the processed control information comprises: The method includes controlling a plurality of microprocessing units in the peripheral circuit to perform asynchronous operations on corresponding memory surfaces according to the control parameters, the plurality of microprocessing units corresponding to a plurality of memory surfaces, respectively.

[0026] In some embodiments, the method further comprises: The method further includes providing an enable signal to the microprocessing unit when the state machine receives the control command.

[0027] In some embodiments, the method further comprises: after the microprocessing unit finishes a control operation on the control surface based on one of the control information, sending state information to a corresponding one of the state machines; receiving a next control command after the state machine receives the state information sent from the corresponding microprocessing unit.

[0028] In some embodiments, the method further comprises: The method further includes a step of a main processor in the peripheral circuit receiving status information sent from the multiple microprocessing units and sending overall status information to a memory interface, the overall status information being used to indicate that all of the multiple microprocessing units have completed control operations based on a set of control commands.

[0029] In some embodiments, the method further comprises: receiving a reset command by the main processor; and resetting operation of each storage surface in said memory in accordance with said reset command.

[0030] In some embodiments, the method further comprises: The state machine further includes sending address information to the corresponding storage planes according to the control commands, respectively.

[0031] In a third aspect, embodiments of the present disclosure further provide a memory system, comprising: any one of the above memory types; and a controller; The controller is coupled to the memory, the controller being configured to send control commands to the memory via a memory interface of the memory.

[0032] In some embodiments, the memory system is a solid state drive (SSD) or a storage card.

[0033] One or more embodiments are illustratively illustrated by pictures in corresponding drawings, which figures are not to be construed as limiting the extent to which they may be rendered, unless otherwise specified. [Brief description of the drawings]

[0034] [Figure 1A] FIG. 1 is a structural schematic diagram of a system provided by an embodiment of the present disclosure. [Figure 1B] FIG. 2 is a structural schematic diagram of a memory card provided by an embodiment of the present disclosure. [Figure 1C] FIG. 1 is a structural schematic diagram of a solid-state drive provided by an embodiment of the present disclosure. [Figure 1D] FIG. 2 is a structural schematic diagram of a memory provided by an embodiment of the present disclosure, including a memory cell array and peripheral circuits. [Figure 1E]FIG. 2 is a structural schematic diagram of a memory provided by an embodiment of the present disclosure, including a memory cell array and peripheral circuits. [Figure 1F] FIG. 2 is a structural schematic diagram of a control logic unit in a peripheral circuit of a memory provided by an embodiment of the present disclosure; [Figure 2A] FIG. 2 is a structural schematic diagram of a memory provided by an embodiment of the present disclosure. [Figure 2B] FIG. 2 is a schematic diagram illustrating the principle of queue separation between a memory interface and a state machine in a memory provided by an embodiment of the present disclosure. [Diagram 3] FIG. 2 is a structural schematic diagram of a memory provided by an embodiment of the present disclosure. [Figure 4] FIG. 2 is a structural schematic diagram of a memory provided by an embodiment of the present disclosure. [Diagram 5] FIG. 2 is a structural schematic diagram of a memory provided by an embodiment of the present disclosure. [Figure 6] 1 is a flowchart of a memory control method provided by an embodiment of the present disclosure. [Figure 7] FIG. 2 is a structural schematic diagram of a memory provided by an embodiment of the present disclosure. [Figure 8] FIG. 2 is a diagram illustrating the principle of a memory control method according to an embodiment. [Figure 9] FIG. 4 is a timing diagram of a memory control method according to an embodiment. [Figure 10] FIG. 2 is a diagram illustrating the principle of a memory control method according to an embodiment. [Figure 11] FIG. 2 is a structural schematic diagram of a memory provided by an embodiment of the present disclosure. [Figure 12] FIG. 2 is a signal timing diagram in a memory control method provided by an embodiment of the present disclosure. [Figure 13] FIG. 2 is a principle diagram illustrating a memory control method provided by an embodiment of the present disclosure. [Figure 14] 1 illustrates a way-level processing principle of a control command queue in a memory control method provided by an embodiment of the present disclosure. [Figure 15] FIG. 15 is a timing diagram of each signal based on FIG. [Figure 16]1 illustrates an information exchange principle between a plurality of state machines, a sequence computing module, and a hardware computing module in a memory control method provided in an embodiment of the present disclosure. [Figure 17] FIG. 17 is a schematic diagram of the time periods required for each process illustrated on the basis of FIG. 16. [Figure 18] FIG. 2 is a timing diagram of a memory control method provided by an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0035] In order to facilitate understanding of the present disclosure, the present disclosure will now be described more fully with reference to the accompanying drawings. In the drawings, a first embodiment of the present disclosure is given. However, the present disclosure can be realized in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and complete.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art. In this specification, the terms used in the specification of the present disclosure are only for describing specific examples and are not intended to limit the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0037] 1A, an embodiment of the present disclosure illustrates an exemplary system 10, which may include a host 20 and a storage system 30, where the exemplary system 10 may include, but is not limited to, a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory 34, and the host 20 may be a processor (e.g., a central processing unit (CPU)) or a system on a chip (SoC) (e.g., an application processor (AP)) of the electronic device.

[0038] In an embodiment of the present disclosure, the host 20 may be configured to transmit data to or receive data from the storage system 30. Here, the storage system 30 may include a controller 32 and one or more memories 34. Here, the memories 34 may include, but are not limited to, NAND Flash Memory, Vertical NAND Flash Memory, NOR Flash Memory, Dynamic Random Access Memory (DRAM), Ferroelectric Random Access Memory (FRAM), Magnetoresistive Random Access Memory (MRAM), Phase Change Random Access Memory (PCRAM), Resistive Random Access Memory (RRAM), and Nano Random Access Memory (NRAM).

[0039] Meanwhile, the controller 32 may be coupled to the memory 34 and the host 20 and is used to control the memory 34. Illustratively, the controller may be designed for use in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash memory drives, or other media for use in electronic devices, such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the controller may also be designed for use in high duty cycle environments, such as SSDs or embedded multimedia cards (eMMCs), which are used as data storage devices and enterprise storage arrays in mobile devices, such as smartphones, tablet computers, laptop computers, etc. Additionally, the controller may manage data in the memory and communicate with the host. The controller may be configured to control operations such as reading, erasing, and programming the memory, and may be configured to manage various functions related to data stored or to be stored in the memory, including, but not limited to, bad block management, garbage collection, logical to physical address translation, and wear leveling, and may be configured to process error correction codes (ECC) on data read from or written to the memory. The controller may also perform any other suitable functions, such as formatting the memory, or communicate with external devices (e.g., host 20 in FIG. 1A) according to a particular communication protocol.Illustratively, the controller can communicate with external devices via at least one of a variety of interface protocols, such as, for example, a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, and a Firewire protocol.

[0040] In the embodiment of the present disclosure, the controller and one or more memories may be integrated into various types of storage devices, for example, included in the same package (e.g., Universal Flash Memory Storage (UFS) package or eMMC package). That is, the storage system can be implemented and packaged into different types of terminal electronic products. As shown in FIG. 1B, the controller 32 and the single memory 34 may be integrated into a memory card 40. The memory card 40 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), and UFS, etc. The memory card 40 may further include a memory card connector 42 that couples the memory card 40 to a host (e.g., the host 20 in FIG. 1A). In another embodiment shown in FIG. 1C, the controller 32 and the multiple memories 34 may be integrated into an SSD 50. SSD 50 may further include an SSD connector 52 that couples SSD 50 to a host (e.g., host 20 in FIG. 1A). In some embodiments, the storage capacity and / or operating speed of SSD 50 is greater than the storage capacity and / or operating speed of memory card 40.

[0041] It is necessary to explain that the memory according to the embodiment of the present disclosure may be a semiconductor memory, which is a solid-state electronic device for storing data information fabricated using a semiconductor integrated circuit process. Illustratively, FIG. 1D is a schematic diagram of an optional kind of memory 60 according to the embodiment of the present disclosure. Here, the memory 60 may be the memory 34 in FIGS. 1A-1C. As shown in FIG. 1D, the memory 60 may include a storage array 110, a peripheral circuit 120 coupled to the storage array 110, and the like. Here, the storage array 110 may be a NAND flash memory storage cell array, where the storage cells are provided in the form of an array of NAND storage strings 66, each of which extends vertically above a substrate (not shown). In some embodiments, each of the NAND storage strings 66 may include a plurality of storage cells coupled in series and stacked vertically. Here, each of the storage cells maintains a continuous analog value, such as a voltage or charge, which is determined by the number of electrons trapped within the storage cell area. It should be noted that each storage cell in the storage array 110 may be a floating gate type storage cell including a floating gate transistor, or a charge trapping type storage cell including a charge trapping transistor.

[0042] In embodiments of the present disclosure, the memory cells may be single level cells (SLC) that have two possible memory states and thus can store one bit of data. For example, a first memory state "0" may correspond to a first voltage range and a second memory state "1" may correspond to a second voltage range. In other embodiments, each memory cell is a multi level cell (MLC) that can store more than a single bit of data in more than four memory states. For example, an MLC may store two bits per cell, three bits per cell (also called a triple level cell (TLC)), or four bits per cell (also called a quad level cell (QLC)). Each MLC may be programmed to have a range of possible nominal memory values. Illustratively, with two bits of data stored in each MLC, the MLC may be programmed to assume one of three possible programming levels from an erased state by writing one of three possible nominal memory values ​​to the memory cell, where a fourth nominal memory value may be used for the erased state.

[0043] In the embodiment of the present disclosure, the peripheral circuit 120 may be coupled to the memory cell array via bit lines (BL), word lines (WL), source lines, source select gates (SSG), and drain select gates (DSG). Here, the peripheral circuit may include any suitable analog, digital, and hybrid signal circuitry that is used to facilitate operation of the memory cell array by applying voltage and / or current signals to and sensing voltage and / or current signals from individual target memory cells via the bit lines, word lines, sources, SSG, and DSG. Additionally, the peripheral circuit 120 may further include various types of peripheral circuits formed using Metal-Oxide-Semiconductor (MOS) technology. Exemplarily, as shown in FIG. 1E, the peripheral circuit 120 includes a page buffer / sense amplifier 71, a column decoder / bit line driver 72, a row decoder / word line driver 73, a voltage generator 74, a control logic unit 75, a register 76, an interface 77, and a data bus 78. As should be understood, the peripheral circuitry 120 may be the same as the peripheral circuitry 120 in FIG. 1D, and in some other embodiments, the peripheral circuitry 120 may further include additional peripheral circuitry not shown in FIG. 1E.

[0044] In the embodiment of the present disclosure, the control logic unit included in the peripheral circuit may be used to receive a control command sent from an external host device, perform corresponding processing on the control command, obtain signals required for executing the control command, and transmit them to row decoders / word line drivers, column decoders / bit line drivers, and page buffers / sense amplifiers, etc., to finally realize an operation corresponding to the control command. As shown in FIG. 1F, the control logic unit 80 in the peripheral circuit 120 of the embodiment of the present disclosure may include a general-purpose micro-processing unit 81 (MP MCU), a hardware processing module 82, and multiple core micro-processing units 83 (core mcu), etc. The control logic unit 80 can communicate with an external host (e.g., the host 20 in FIG. 1A) through an interface 77. Illustratively, the control logic unit 80 may be the same as the control logic unit 75 in FIG. 1E, and in some other embodiments, the control logic unit 80 may include other circuit structures and connection interfaces not shown in FIGS. 1E and 1F. In the embodiment of the present disclosure, the control logic unit 80 of the peripheral circuit 120 may further include n state machines 121 used to realize asynchronous processing of received control commands.

[0045] Specifically, FIG. 2A is a structural block diagram of a memory provided by an embodiment of the present disclosure, the memory 100 including a storage array 110 and a peripheral circuit 120; The storage array 110 includes a plurality of storage planes 111, each of which includes a storage block made up of storage cells; the peripheral circuitry 120 is connected to the storage array 110 and configured to control the plurality of storage planes 111 to operate asynchronously; Here, the peripheral circuit 120 includes at least one state machine 121, Each of the plurality of state machines 121 is set up corresponding to at least one of the plurality of memory surfaces 111, the plurality of state machines 121 are connected to a memory interface I / F, and can receive control commands related to the asynchronous operation of each corresponding memory surface 111 in parallel from the memory interface I / F, and each of the plurality of state machines 121 can independently process the control commands it receives to obtain the control information of the corresponding memory surface 111.

[0046] In the embodiment of the present disclosure, the memory 100 may be a volatile memory, a non-volatile memory, including a read-only memory, a random memory, etc. The memory 100 may be the memory 34 in the above-mentioned FIG. 1A to FIG. 1C, or the memory 60 in FIG. 1D. The memory in the embodiment of the present disclosure can independently perform memory operations including multiple storage planes, such as reading, programming, and erasing. In the following, a flash memory (NAND) will be described as an example.

[0047] The memory 100 may include one or more NAND dies, and may be packaged with the peripheral circuit 120 into a flash memory chip. The NAND die may include an array of memory cells, and each memory cell may store data by storing an electric charge. When performing a read operation, a voltage is applied to the word line in which the selected memory cell is located by controlling the gate, and then the on-state of the corresponding memory cell is detected by the sensing circuit, so that data can be read. When performing a write operation, an electric charge is stored in the floating gate of the memory cell, so that the on-voltage of the memory cell can be adjusted, and different data can be stored.

[0048] In memory 100, the distribution of memory cells may be arranged as a number of memory blocks, where a memory block may be the smallest cell that is erased at the same time. The memory cells may be further arranged as a number of memory planes 111, where each memory plane 111 includes a number of memory blocks and associated row / column control circuitry. Each memory plane 111 may include a two-dimensional (2D) or three-dimensional (3D) memory structure.

[0049] In the embodiment of the present disclosure, the peripheral circuit 120 of the memory 100 may include at least a plurality of state machines 121 and other logic circuits 122 connected to the state machines. Here, the other logic circuits 122 are part or all of the logic circuits other than the state machines 121 in the peripheral circuit 120, and may include, for example, a microprocessing unit and a hardware processing module. The other logic circuits 122 are connected to each memory surface 111 in the memory 100 and are used to control each memory surface 111 to perform asynchronous operations based on the control command after being processed by the state machine. Here, the peripheral circuit 120 of the memory 100 may be part or all of the peripheral circuit 70 in FIG. 1E. Exemplarily, the peripheral circuit 120 may include at least the control logic unit 75 in the peripheral circuit 70 in FIG. 1E, or may include the control logic unit 80 in FIG. 1F. Furthermore, the function of the memory interface I / F in the embodiments of the present disclosure is to transmit control commands provided from an externally connected host (e.g., host 20 shown in FIG. 1A) to each state machine 121 for processing, and the memory interface I / F may be part or all of interface 77 in FIG. 1E or 1F above, or may be an independent interface different from interface 77, and is not limited thereto.

[0050] The other logic circuit 122 is connected to each memory plane 111 through a corresponding interface, and can perform read, write or erase operations on each memory block in the memory plane 111, and can control the multiple memory planes to perform asynchronous operations, such as AMPI operations, asynchronous programming operations, and asynchronous erase operations. In addition to providing clock signals for different asynchronous operations, the other logic circuit 122 can also provide various voltage or current signals and provide functions such as sensing. To support rapid read operations, the other logic circuit 122 can be further configured to support Asynchronous Multi-plane Independent (AMPI) read operations. The AMPI read is an extended type of read operation that can support independent asynchronous read operations simultaneously between different memory planes 111. The other logic circuit 122 can also be further configured to support asynchronous multi-plane programming operations, asynchronous multi-plane erase operations, and hybrid operations of various other asynchronous operations.

[0051] Taking the AMPI read operation as an example, command processing of other logic circuits 122 is also generally an asynchronous operation, and sequential queuing processing is performed for the asynchronous control commands of each memory plane 111. This causes the processing time to be too long, and sequential processing after receiving the control command causes the waiting time of the memory plane 111 corresponding to the control command processed later to be too long, so that the processing time of the entire memory 100 is relatively long.

[0052] Therefore, the embodiment of the present disclosure employs multiple state machines 121 corresponding to the memory planes 111 to process control commands. Here, the number of the multiple state machines 121 may be the same as the number of the memory planes 111, and each state machine 121 corresponds to the memory plane 111 one-to-one. In another embodiment, the number of the multiple state machines 121 may be less than the number of the memory planes 111, and one state machine 121 may correspond to one or more memory planes 111. Here, the state machine 121 corresponding to the memory plane 111 refers to the state machine 121 being used to process control commands for the specified memory plane 111. If one state machine 121 corresponds to only one memory plane 111, the state machine 121 is only used to process control commands for the corresponding memory plane 111. Exemplarily, the memory planes of the memory in the embodiment of the present disclosure may include four, six, eight, or more.

[0053] In the embodiment of the present disclosure, the state machine 121 is connected to the memory interface I / F and can receive a control command for the corresponding memory surface 111. The state machine 121 performs analysis processing on the control command using a hardware circuit, or sets parameters and the like required to execute an operation corresponding to the control command.

[0054] Here, the memory interface I / F may be connected to an external host device (for example, the host 20 shown in FIG. 1A), and the memory interface I / F may include a bus interface such as several control signal lines, a clock signal line, and a data signal line. The host device can realize the control of the memory 100 by sending a control command. Exemplarily, as shown in FIG. 1A, the host 20 exchanges commands with the storage system 30 through a communication interface, and the controller 32 in the storage system 30 can transmit the control command sent from the host 20 to the memory 34 (i.e., the memory 100 shown in FIG. 2A in the above embodiment), and send it to another logic circuit 122 through the memory interface I / F in the above embodiment. In the control command, some address information may be carried, such as which storage surface 111 the control command is for. According to these address information, the corresponding state machine 121 can receive the control command and feedback a response message, etc. Then, after the state machine 121 processes the control command, it provides a corresponding signal to the other logic circuit 122 to realize the control of the storage surface 111.

[0055] The multiple state machines 121 are independently installed hardware structures, so they can process control commands in parallel. If multiple control commands for different storage planes 111 are received at the same time or within the same period, the multiple state machines 121 can process them in parallel and transmit them to other logic circuits 122. Then, the other logic circuits 122 control them sequentially. The purpose of doing so is to divide the conventional control command queue into multiple small queues by the multiple state machines 121 for parallel processing, so that the control commands in each queue can be queued independently, thereby improving the overall queuing efficiency. In the embodiment of the present disclosure, the more the number of storage planes 111, the more obvious the effect of the state machine 121 performing asynchronous processing to shorten the overall processing time.

[0056] In addition, in the embodiment of the present disclosure, the multiple state machines 121 may be respectively connected to a memory interface I / F, as shown in Fig. 2A. The memory interface I / F may include multiple connection terminals, each of which is respectively connected to a state machine 121, and each of which can transmit different control commands to the state machine 121 connected thereto.

[0057] 2B illustrates the principle of the memory interface I / F separating command queues and transferring them between state machines. Specifically, a plurality of state machines 121 are respectively connected to the memory interface I / F, and the memory interface I / F can divide the received control command queue into a plurality of queues according to the number of state machines 121, and sequentially transfer the control command queues to the state machines 121 according to the queue order. In FIG. 2B, if one control command is processed in the current state of each state machine 121, in the next state, the memory interface I / F receives and processes the next control command waiting in the corresponding queue.

[0058] The above technical means allows the control commands to be separated according to ways and processed by different state machines in the form of multiple queues, thereby realizing way-level-based processing, whereas in some other embodiments, the general-purpose microprocessor (MP MCU) performs chip-level serial processing for all control commands, i.e., serial processing is performed directly by the control logic of the memory chip through one total queue.

[0059] As can be appreciated, the way-level based processing of control commands in the embodiments of the present disclosure can effectively reduce the length of time required to process control commands and reduce the wait or idle time of individual memory planes, as compared to a general purpose microprocessor performing chip-level serial processing of all control commands, thereby improving the overall memory operation rate.

[0060] In some embodiments, the peripheral circuitry 120 is configured to control the multiple storage planes 111 to perform asynchronous operations according to control information from the multiple state machines 121. In the embodiment of the present disclosure, the multiple state machines 121 process control commands related to the asynchronous operations of the corresponding storage planes 111 to obtain the control information, after which the peripheral circuitry 120 can control each storage plane 111 to perform asynchronous operations according to the control information.

[0061] Here, the processing of each piece of control information by the peripheral circuit 120 may be serial processing, for example, other logic circuits 122 in the peripheral circuit 120 receive control information provided from the multiple state machines 121, process the control information according to a certain order, and transfer the control information to the different storage planes 111, thereby realizing control over the different storage planes 111. Illustratively, the processing of the control information by the peripheral circuit 120 may include realizing asynchronous operation over each storage plane 111 by issuing signals such as voltage and current required for asynchronous operation to each storage plane 111 according to the control information.

[0062] In the embodiment of the present disclosure, the peripheral circuit 120 performs hardware processing based on the control information, thereby performing asynchronous operations corresponding to the control commands.

[0063] In some embodiments, the state machine 121 is further configured to set parameters according to the control command; Here, there is at least a partial overlap between the time periods during which at least two of the plurality of state machines 121 are occupied in processing the control command and performing the parameter setting.

[0064] In the embodiment of the present disclosure, the state machine 121 can further be used to perform parameter setting, and can perform corresponding parameter setting according to different control commands. Since multiple state machines 121 can process in parallel, the time when the multiple state machines 121 analyze the control commands and perform parameter setting can overlap with each other, that is, different state machines 121 can perform their respective analysis and setting processes simultaneously.

[0065] In this manner, the time difference between initiating execution of operations between different storage planes 111 can be reduced, further reducing the overall length of time for processing the memory 100 .

[0066] In some embodiments, as shown in FIG. 3, the peripheral circuit 120 includes: The control information processing device further includes a sequence calculation module connected to the plurality of state machines and configured to determine a processing order of the control information according to the control information of the plurality of state machines.

[0067] Because the peripheral circuit 120 still needs to serially process the control information corresponding to each control command, in the embodiment of the present disclosure, a sequence calculation module 131 is added to sequence the control information obtained by processing by the state machine 121 and determine the processing order of each control information.

[0068] That is, after the multiple state machines 121 perform shunt queuing and related processing for the control command, the sequence calculation module 131 is used to realize queuing for the control information.

[0069] After determining the processing order of the control information, the sequence calculation module 131 sequentially instructs the peripheral circuit 120 to execute corresponding control commands based on the control information, thereby facilitating the rational utilization of control resources in the peripheral circuit 120 and reducing resource contention.

[0070] In some embodiments, the state machine 121 specifically: configured to send a processing request to the sequence operation module 131 according to the control command; The sequence calculation module 131 specifically includes: The state machine 121 is configured to specify the order in which the peripheral circuit 120 processes the control information according to the processing requests transmitted from the plurality of state machines 121 .

[0071] In the embodiment of the present disclosure, the state machine 122 can send a processing request to the sequence computing module 131 according to the control command, which requests the sequence computing module 131 to perform sequencing processing.

[0072] The processing request may include information on the storage surface corresponding to the control command to be processed, such as the number and address of the storage surface, and may also include information on some operation types, etc. The sequence calculation module 131 uses this information to order the received control information, and the peripheral circuit 120 processes the control information based on the ordering, and further performs asynchronous operations on each storage surface.

[0073] In some embodiments, as shown in FIG. 4, the peripheral circuit 120 further includes a hardware computing module 132 and a plurality of microprocessing units 133; the hardware calculation module 132 is connected to the sequence calculation module 131, and is configured to sequentially specify control parameters corresponding to the control information according to the processing order; The plurality of microprocessing units 133 respectively correspond to each memory surface 111, are connected to the hardware calculation module 133, and are respectively connected to the corresponding memory surface 111, and the plurality of microprocessing units 133 are configured to perform asynchronous operations on each memory surface 111 according to the control parameters.

[0074] In the embodiment of the present disclosure, the hardware calculation module 132 in the peripheral circuit 120 is used to determine various signals required to perform asynchronous operations on the memory surface 111 according to the control information, including calculating the voltage, current and corresponding timing changes required for various operations. The hardware calculation module 132 is a serial process, so the hardware calculation module 132 can perform corresponding processing according to the processing order provided by the sequence calculation module 131.

[0075] Also, the hardware calculation module 132 needs to provide control parameters to the microprocessing unit 133 (Core MCU). The microprocessing unit 133 is connected to each memory surface 111, and each microprocessing unit 133 may control one memory surface 111 independently. In some embodiments, one microprocessing unit 133 may control multiple memory surfaces 111.

[0076] The hardware calculation module 132 transmits the control parameters to the corresponding microprocessing unit 133, which then realizes control over the memory surface 111. The microprocessing unit 133 may be connected to the memory surface 111 via a control bus, which may include various logic circuit connections with the memory surface 111, including word lines, bit lines, selection lines, control lines, etc. connected to each memory cell.

[0077] In some embodiments, each of the state machines 121 is further coupled to a corresponding one of the microprocessing units 133 and configured to provide an enable signal to the microprocessing unit 133 upon receiving the control command.

[0078] In the embodiment of the present disclosure, the working state of each microprocessing unit 133 can be synchronized with the working state of state machine 121 through communication between them. In this way, when state machine 121 receives a new control command, it can enable microprocessing unit 133 through an enable signal, so that microprocessing unit 133 can make corresponding preparations for the upcoming control operation, and at the same time, can also achieve functions such as clock synchronization.

[0079] In some embodiments, state machine 121 may correspond one-to-one with microprocessing units 133, thereby solely communicating with and enabling each individual microprocessing unit 133. In other embodiments, state machine 121 may correspond to multiple microprocessing units 133, and communicate with and enable multiple microprocessing units 133.

[0080] In some embodiments, the plurality of microprocessing units 133 further comprises: configured to transmit state information to the corresponding state machine 121 after completing a control operation on the storage surface 111 based on one of the control commands; The state machine 121 is further configured to receive a next control command after receiving the state information sent from the corresponding microprocessing unit 133 .

[0081] In addition, the communication connection between each microprocessing unit 133 and state machine 121 may also be used for microprocessing unit 133 to inform state machine 121 of its own processing status, and if microprocessing unit 133 is in an active state, it can provide one type of status information, and the state machine can temporarily stop processing the next control command or temporarily not receive the next control command. If microprocessing unit 133 is in an idle state, it can provide another type of status information, and the state machine 121 can enable microprocessing unit 133 to receive the next control command and perform the next operation.

[0082] Illustratively, microprocessing unit 133 may output a signal to state machine 121, where if the signal is in a high state, it indicates that the current microprocessing unit 133 is in an active state, and if the signal is in a low state, it indicates that the current microprocessing unit 133 is in an idle state.

[0083] In this way, resource contention can be further reduced, processing efficiency can be improved, and the possibility of operational errors caused by resource contention can be reduced.

[0084] In some embodiments, as shown in FIG. 5, the peripheral circuit 120 further includes a main processor 134, The main processor 134 is connected to the memory interface I / F and the multiple microprocessing units 133, and is configured to receive status information sent from the multiple microprocessing units 133, and send overall status information determined according to the multiple status information to the memory interface I / F, where the overall status information is used to indicate that all of the multiple microprocessing units 133 have completed control operations based on a set of control commands.

[0085] Here, the main processor 134 is connected to the memory interface I / F and can directly receive some external control commands. Exemplarily, the main processor 134 may be realized by a general-purpose microprocessor. The main processor 134 may also be connected to a plurality of microprocessing units 133 and can execute control for each memory surface 111 in the memory 100 by software. Therefore, the main processor 134 can be used to flexibly control the memory surface 111 in cooperation with the state machine 121. When performing some function extensions or debugging, the main processor 134 can be utilized to realize some functions, or the main processor 134 can be used when serial processing needs to be performed for each control command.

[0086] In the embodiment of the present disclosure, each microprocessing unit 133 can send its own status information to the main processor 134, and if all the microprocessing units 133 are in an idle state, the main processor 134 can indicate that the memory 100 is in an idle state by sending the overall status information to the memory interface I / F. In this way, the external host machine can easily perform some other control overall control on the memory 100, or perform operations such as reset and refresh on the memory 100.

[0087] Here, the total status information may include status information provided from each microprocessing unit 133, or may be information generated according to the status information provided from each microprocessing unit 133 and used to indicate that the memory state is idle.

[0088] In some embodiments, the main processor is further configured to receive a reset command, where the reset command is used to reset the operation of each storage plane 111 in the memory 100 .

[0089] In an embodiment of the present disclosure, if one wishes to reset memory 100, a reset command can be sent to main processor 134 via the interface of memory 100. Upon receiving the reset command, main processor 134 can perform a reset operation on each storage surface 111.

[0090] It should be noted that the reset operation can be performed at any time, for example, when each storage surface 111 is in an idle state, the reset operation can be performed on each storage surface 111. Further, for example, when storage surface 111 is performing a read / write operation, if a reset command is received, the current read / write operation can be stopped and a reset operation can be performed, where the reset operation can include releasing the charge of each node, zeroing or normalizing the signals on each signal line, etc.

[0091] In some embodiments, the plurality of state machines 121 are further coupled to the plurality of storage surfaces 111, respectively, and configured to transmit address information to the corresponding storage surface 111 according to the control command.

[0092] In an embodiment of the present disclosure, the multiple state machines 121 may further be connected to multiple storage planes 111, for example, connected to the multiple storage planes 111 via an address bus. The state machine 121 can send address information to the storage planes 111 via the address bus, including information such as row address information and column address information of the target storage block, or the target storage block. If the state machines 121 correspond one-to-one to the storage planes 111, the address information sent from each state machine only needs to include address information of the corresponding storage cell in the storage plane 111, and does not need to include address information of the storage plane.

[0093] As shown in FIG. 6 , an embodiment of the present disclosure further provides a control method for a memory, the method being performed by a peripheral circuit in the memory, the peripheral circuit including at least one state machine, the method comprising: a step S101 in which a state machine in the memory receives control commands associated with asynchronous operations on each storage plane in the memory in parallel, where each of the state machines is configured to correspond to at least one of the plurality of storage planes; Step S102 includes the state machine independently processing each of the received control commands to obtain corresponding storage surface control information.

[0094] In the memory in the embodiment of the present disclosure, at least one state machine is included, and different state machines may correspond to different memory planes. Exemplarily, one state machine may correspond to one memory plane or multiple memory planes. The multiple state machines are connected to the memory interface and can receive control commands related to asynchronous operations for each memory plane transferred from the memory interface. The multiple state machines can receive and process the control commands in parallel, which can reduce the latency of related circuits and improve the utilization of processing resources compared to a method of serially processing control commands related to asynchronous operations, thereby improving processing efficiency and reducing processing delays.

[0095] In some embodiments, the method further comprises: The method further includes controlling the peripheral circuitry to perform asynchronous operations on the plurality of storage planes based on the control information.

[0096] The plurality of state machines can receive the control command and analyze it to obtain corresponding control information. The analysis of the control command by the plurality of state machines can be performed in parallel, so that the analysis of the control command for the plurality of different storage planes can be completed synchronously.

[0097] After the multiple state machines complete the analysis of the control command, they can respectively transmit the control information obtained after the analysis to other logic circuits of the peripheral circuit, and then perform asynchronous operations on the memory plane.

[0098] In some embodiments, the method further comprises: The method further includes a step of the state machines setting parameters according to the control commands, wherein there is at least a partial overlap between the time periods occupied by at least two of the state machines processing the control commands and setting the parameters.

[0099] In the embodiments of the present disclosure, the multiple state machines further perform parameter setting according to the control command, and since the multiple state machines can process in parallel, the times when the multiple state machines analyze the control command and perform parameter setting may overlap with each other, that is, different state machines can perform their respective analysis and setting processes simultaneously.

[0100] Compared to a method in which a general-purpose processor performs serial analysis processing on control commands related to asynchronous operations and peripheral circuits wait for individual control commands to perform control operations sequentially, the above method in the embodiments of the present disclosure can reduce the time difference between starting to execute operations between different memory planes, and further reduce the overall processing time of the memory.

[0101] In some embodiments, the step of controlling the peripheral circuitry to perform asynchronous operations on the plurality of storage surfaces based on the control information includes: determining a processing order for the control information by the peripheral circuitry according to the control information provided by the plurality of state machines; sequentially processing the control information according to the processing order; and controlling asynchronous operations on the plurality of storage surfaces in accordance with the processed control information.

[0102] In the embodiment of the present disclosure, the state machine performs analysis processing and parameter setting for each control command, and then the peripheral circuit can perform corresponding control operations for each storage surface. Since other logic circuits in the peripheral circuit can perform serial operations, the control commands of the multiple state machines can be sequentially executed by these logic circuits after being ordered. The peripheral circuit can process the corresponding control information according to the processing order for each control command, and then sequentially control the corresponding storage surface to perform asynchronous operations.

[0103] In some embodiments, the step of determining a processing order for the control information in accordance with the control information provided by the plurality of state machines comprises: A sequence operation module in the peripheral circuit receives processing requests transmitted by the plurality of state machines based on the control command; The sequence calculation module specifies a processing order for the control information based on the processing request.

[0104] In the embodiment of the present disclosure, the sequence operation can be performed by a sequence operation module in the controller. The state machines can send processing requests to the sequence operation module according to the control commands received and analyzed. The sequence operation module performs corresponding ordering on the control information corresponding to the control commands according to the processing requests, and processes the control information according to the ordering, so as to perform asynchronous operations on different control storage planes.

[0105] In some embodiments, the step of sequentially processing the control information according to the processing order comprises: The hardware operation module in the peripheral circuit includes a step of sequentially specifying control parameters corresponding to the control information in accordance with the processing order according to the control information provided from the state machine.

[0106] In the embodiment of the present disclosure, the processing order specified by the sequence computing module may be provided to a hardware computing module, which is used to calculate control parameters such as required voltage, current and corresponding timing according to a specific control command. The hardware computing module is a serial processing module, so the hardware computing module can perform corresponding processing according to the processing order provided by the sequence computing module.

[0107] In some embodiments, the step of controlling the plurality of storage surfaces to perform asynchronous operations in accordance with the control information after processing comprises: The method includes controlling a plurality of microprocessing units in the peripheral circuit to perform asynchronous operations on corresponding memory surfaces according to the control parameters, where the plurality of microprocessing units respectively correspond to the plurality of memory surfaces.

[0108] The hardware computing module can provide control parameters to the microprocessing units. The microprocessing units are connected to each storage surface, and each microprocessing unit may independently control one storage surface. Multiple microprocessing units can be used to perform asynchronous operations on multiple storage surfaces.

[0109] In some alternative embodiments, one microprocessing unit may control multiple storage surfaces.

[0110] The hardware calculation module transmits the control parameters to the corresponding micro-processing unit, which then realizes control over the memory surface. The micro-processing unit may be connected to the memory surface via a control bus, which may include various logic circuit connections to the memory surface, including word lines, bit lines, select lines, and control lines connected to each memory cell.

[0111] In this way, the microprocessing unit can perform corresponding operations on each storage surface according to the control parameters provided by the hardware computing module, and further achieve the result of executing the control command.

[0112] In some embodiments, the method further comprises: The plurality of state machines further includes providing an enable signal to the microprocessing unit upon receiving the control command.

[0113] In the embodiment of the present disclosure, the working state of each microprocessing unit and the working state of the state machine can be synchronized through communication between them. In this way, when the state machine receives a new control command, it can enable the microprocessing unit through an enable signal, so that the microprocessing unit can prepare accordingly for the upcoming control operation, and at the same time, it can also achieve functions such as clock synchronization.

[0114] In the embodiment of the present disclosure, after receiving a control command, the state machine may send an enable signal to the corresponding microprocessing unit to put the microprocessing unit into a waiting state, and after completing an operation such as analysis on the control command, the state machine may send an enable signal to the corresponding microprocessing unit so that the microprocessing unit begins to receive information such as corresponding control parameters and performs an operation on the storage surface.

[0115] In some embodiments, the method further comprises: after the microprocessing unit completes a control operation on the control surface based on one of the control information, sending state information to the corresponding state machine; receiving a next control command after the state machine receives the state information sent from the corresponding microprocessing unit.

[0116] In the embodiment of the present disclosure, the microprocessing unit may be connected to a corresponding state machine, and the microprocessing unit can enter an idle state after completing the control operation of one control command, and at this time, send state information to the state machine, so that the state machine can continue to accept the next control command and continue to perform corresponding analysis processing, etc.

[0117] In some embodiments, the method further comprises: The method further includes a step of a main processor in the peripheral circuit receiving status information sent from the multiple microprocessing units and sending overall status information to a memory interface, where the overall status information is used to indicate that all of the multiple microprocessing units have completed control operations based on a set of control commands.

[0118] Each of the multiple microprocessing units can transmit their respective status information to the main processor, and the main processor can perform overall management. When the status information of the multiple microprocessing units indicates that they are all in an idle state, it means that the memory is in an idle state as a whole, and at this time, the overall status information can be transmitted to the memory interface.

[0119] In this manner, a host to which the memory is connected can easily determine the state of the memory and perform other control operations.

[0120] In some embodiments, the method further comprises: receiving a reset command by the main processor; and resetting operation of each storage surface in the memory in accordance with the reset command.

[0121] The main processor can receive a reset command from the memory interface and perform a reset operation on each storage surface. The reset operation can be performed at any time, for example, the reset operation can be performed on each storage surface when each storage surface is in an idle state. Further, for example, if a reset command is received when a storage surface is performing a read or write operation, the current read or write operation can be stopped and a reset operation can be performed. Here, the reset operation can include releasing the charge of each node, zeroing or normalizing the signals on each signal line, etc.

[0122] In some embodiments, the method further comprises: The method further includes the step of each of the plurality of state machines sending address information to a corresponding one of the storage planes according to the control command.

[0123] In embodiments of the present disclosure, the state machines may also send address information directly to the memory plane, which is used to indicate the specific address of the memory cell that the control command is to operate on, so that the controller can easily perform the corresponding operation on the memory plane.

[0124] The present disclosure further provides the following examples.

[0125] In one embodiment, the memory 200 shown in Figure 7 includes a general purpose controller 201 (MP MCU), a hardware processing module 202 (HW Calc), and core micro-processing units 203a, 203b, 203c, and 203d corresponding to multiple memory planes. The micro-processing units 203 and the memory planes are connected via data buses (cbus0-3). The memory interface 205 (nand if) is connected to a synchronization module 206 (sync). The hardware processing module 202 and the general purpose controller 201 are further connected to each memory plane via address buses (mbus0-3) to provide address information.

[0126] After the control command (cmd) enters through the memory interface 205, it can be clock-synchronized by the synchronization module 206 and transmitted to the command sequence processing module 207 (cmd_seq). The command sequence processing module 207 transmits each control command to the general-purpose controller 201 in order by serial processing. The hardware processing module 202 calculates the necessary control parameters, and the general-purpose controller 201 can enable the micro-processing unit 203. Then, the micro-processing unit 203 can execute the control operation for each memory surface.

[0127] However, since the general-purpose controller performs command analysis by software, it can only perform serial processing, and control commands for each way must wait for each other to avoid resource contention between the general-purpose controller and the hardware processing module 202. This method has a low utilization rate, and can only perform a read or write operation at one time, and cannot simultaneously read and / or write from multiple memory planes. Also, since the bus line width is 8 bits, the degree of parallelism is relatively low.

[0128] As shown in FIG. 8, the Y direction represents the multi-way control commands for different storage planes, and the X direction represents the queue depth of the control commands for each storage plane. Each control command (w0-w3) must be sequentially processed in a time-division serial manner, and can be operated only when the micro-processing unit corresponding to one control command is in an idle state. For a micro-processing unit in a busy state, the corresponding control command must be put into a waiting state. Each queue is processed according to the order of priority from high to low, and when it is the turn to process a control command at one queue position, a logical operation process, for example, an "AND operation" process, can be performed according to the state value of the micro-processing unit corresponding to the queue. For example, when it is the turn of a control command at the queue [0] [1] position, if the control command to be processed exists at that position and the state value is "1" (idle state), it can be processed, and if the state value is "0" (busy state), it will wait for processing.

[0129] As shown in Figure 9, after the control commands (w0-w3) are entered, the general-purpose controller processes the four-way control commands (way0-way3), and the processing time interval between the control commands corresponding to two different storage planes is tAsync, and the processing time length of each way is also tAsync correspondingly. Subsequent commands need to wait for tRCBSY, and the general-purpose controller continues to receive the next control command.

[0130] For different control commands, the corresponding read time length tR may also be different. After the time length of the read operation corresponding to the first set of control commands, the next waiting control command can be processed. Thus, the later waiting control command needs to wait for a longer time, which causes the overall operation efficiency to be low. The processing order and state of each control command may be illustrated in FIG. 10.

[0131] In the above example, the read operation is performed on a 4-way AMPI. If a 6-way AMPI is used to perform the read operation, a larger delay will occur and the command processing queue will be more complicated.

[0132] Therefore, the embodiment of the present disclosure provides a method and memory structure for parallel processing of control commands. As shown in FIG. 11, the read operation of the 6-way AMPI can be analyzed and processed in parallel by different state machines (STM0-STM5), and can generate waveform information defined by the electrical design rules corresponding to the corresponding memory plane, such as waveform information of the read operation, by controlling one of the corresponding multiple microprocessing units (core mcu0-5). In addition, the sequence calculation unit and the hardware processing unit realize parameter setting, etc. In this way, the one-dimensional serial processing method is changed to a two-dimensional parallel processing method by processing the control commands of different memory planes in parallel in multiple independent queues. This can effectively improve the processing efficiency and reduce resource contention.

[0133] 12 shows the processing timing of each state machine and the corresponding state timing of the microprocessing unit (core_done_grp). The processing period of each state machine may include overlapping periods, i.e., different control commands are processed in parallel. The processing period of each state machine includes overlapping periods, and therefore the time difference tAsync between each way of processing a control command is shorter than the situation where there is no overlap between the processing periods.

[0134] The state of the main controller (MP MCU) can be triggered to enter the AMPI operation state when receiving one control command. Then the state machine executes the processing of the control command, so that the main controller can enter the sleep state. After multiple micro-processing units complete the operation, they can send corresponding status information to the general-purpose controller, and the rising edge of the waveforms such as core_done_grp0-2 shown in FIG. 12 indicates that the corresponding micro-processing units complete the operation. At this time, the main controller MP MCU can wake up and issue total status information, which is used to indicate that all micro-processing units have completed the operation, and is the rising edge of the waveform of all_core_done shown in FIG. 12, and at this time the main controller MP MCU can exit the current AMPI operation state.

[0135] The main controller may also be used to perform a reset operation, and after receiving a reset command (cmd_ff), the main controller will wake up and control the memory to interrupt the AMPI read operation, for example, to terminate the parallel processing operation of each way of each corresponding memory plane.

[0136] In the embodiment of the present disclosure, the command queue and resource allocation are processed respectively, thereby realizing parallel processing of multiple command queues by the state machine, and reducing the processing time of way-level commands. The resource queues are queued by adopting a sequence calculation module to process resource contention that may occur in the hardware processing module at the chip level, and there is no need to wait for the analysis of the control command, so that the contention time is very short and the queue depth is reduced, thereby improving the overall processing efficiency, as shown in FIG. 13. Exemplarily, a command sequence can be subjected to chip-level resource calculation on the one hand, and can be divided into multiple queues in the memory interface on the other hand, and provided to the corresponding state machines through way-level processing respectively. As shown in FIG. 13, the command sequence that has undergone chip-level resource calculation can be subjected to queue separation and enter different queues in the memory interface, for example, cmd_xx_grp0-5 have a total of six queues. Here, cmd_xx refers to different command types, such as a read command cmd_rd or a write command cmd_wr. The multiple queues of the memory interface are each connected to a different state machine (for example, stm0 to stm5 shown in FIG. 13), and each control command is transferred to the state machine according to the queue order.

[0137] FIG. 14 shows the way-level processing principle of the control command queue, and FIG. 15 shows the timing of each signal corresponding to FIG. 14. As shown in FIG. 14, the queues of multiple types of control commands (cmd_30_grpX...cmd_3d_grpX) can specify the next set of command sequences to be processed through state selection. For example, a command sequence (ampi_cmd_read_grpX) that should perform an ampi read operation is specified as the sequence to be processed, asynchronous processing (sync) is performed, and the sequence is transferred to the corresponding state machine stm_x. As shown in FIG. 15, the period from when the state machine is enabled (stm_en_pulse_grpX signal) to when the state machine sends an ampi processing reset signal (ampi_rst_grpX signal) is the period in which the state machine and the controller perform arithmetic processing on the control command, and the processing time difference tAsync between each state machine is included in this period. The period from when the ampi processing is reset to when the memory is prepared (core_cache_rdy_grpX signal) is the waiting time tRCBSY required before executing an instruction. After the memory is ready, the operation for the control command, such as a read operation, can be performed, and the corresponding time length is tR. Also, the cotre_done_grpX signal indicates that each micro-processing unit (mcuX) is in an available state, that is, the operation of the previous control command is completed. In Fig. 15, mp_mcu_clk is the clock signal of the main processor, and each of the above signals may be triggered by the rising edge or falling edge of the clock signal, and cache_rbn_grpX is the trigger signal for transmitting the control command.

[0138] FIG. 16 illustrates the information exchange process between multiple state machines (STMs), a sequence calculation module (calc seq), and a hardware calculation module (hw cale). FIG. 17 illustrates the time period required for the processing process. As shown in FIG. 16 and FIG. 17, the state machines STMs perform parallel processing on the received control command, and then transmit the processing request (stm_request[x]) and the processing request type (stm_request_typ_grpX[1:0]) of each state machine to the calculation processing module within one clock period (1clk) of the calculation request stage. Next, the calculation processing module checks the control information to be processed next by calculating based on the order of the queue (queue[1:0][5:0]) in FIG. 16 within one clock cycle (1clk), and if it determines that the current control information (seq_acknowledge[x]=1) is to be processed, it transmits the relevant control information to the hardware calculation module (hw call) for calculation processing, and if the current control information needs to wait for processing (seq_acknowledge[x]=0), it waits one clock cycle (1clk) before making a decision. The processing by the hardware processing module (hw call) may require multiple clock cycles, for example, serial processing of 4clk, and then the state machine is reset (set stm_request_rst[x]), after which the state machine continues parallel processing of the next control command.

[0139] FIG. 18 is a state diagram of control for each storage plane in an embodiment of the present disclosure. As shown in FIG. 18, after the control command (w0 to w3) for each storage plane is input, different state machines receive the control command in sequence and perform corresponding processing. t1 to t3 in FIG. 18 represent different setting processes, covering the period required for read setting. As can be seen from FIG. 18, the time difference tAsync for processing the control command between each way is only a part of the time required for the entire read setting, and therefore, compared with the situation shown in FIG. 9, the overall processing time is shortened.

[0140] It should be understood that "one embodiment" or "an embodiment" referred to throughout the specification means that a particular feature, structure, or characteristic associated with the embodiment is included in at least one embodiment of the present disclosure. Thus, "in one embodiment" or "in one embodiment" appearing in various places throughout the specification do not necessarily refer to the same embodiment. Furthermore, these particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that in various embodiments of the present disclosure, the magnitude of the numbers of each of the above steps does not mean the order of execution, and the execution order of each step should be specified by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The numbers of the above embodiments of the present disclosure are merely for description purposes and do not represent the superiority or inferiority of the embodiments.

[0141] It should be clarified that, in this specification, the terms "comprise", "including", or any other variation thereof, are intended to cover a non-exclusive inclusion, whereby a process, method, article, or apparatus that comprises a set of elements not only includes those elements, but also includes other elements not expressly listed, or includes elements inherent to such process, method, article, or apparatus. In the absence of a more restrictive context, an element qualified by the phrase "comprises a..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0142] In some embodiments provided by the present disclosure, it should be understood that the disclosed devices and methods may be realized in other ways. The above-described device embodiments are merely schematic. For example, the division of the above units is merely a division of logical functions, and may have other division methods when actually realized, for example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not implemented. In addition, the coupling or direct coupling or communication connection between each component shown or discussed may be an indirect coupling or communication connection via some interfaces, devices or units, and may be of electrical, mechanical or other types.

[0143] The above units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, may be located in one place or distributed among multiple network units, and some or all of the units may be selected according to actual needs to realize the objective of the technical means of this embodiment.

[0144] In addition, each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, each unit may be a single unit on its own, two or more units may be integrated into one unit, and the integrated units may be realized in the form of hardware or in the form of hardware and software functional units.

[0145] The above are merely embodiments of the present disclosure, and the scope of protection of the present disclosure is not limited thereto, and those skilled in the art can easily think of modifications or replacements within the technical scope disclosed in the present disclosure, all of which should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be in accordance with the scope of protection of the above claims. [Explanation of symbols]

[0146] 10. System 20 Host 30 Memory Systems 32 Controller 34 Memory 40 Memory Card 42 Memory card connector 52 SSD connector 60 Memory 66 NAND storage strings 70 Peripheral circuits 71 Sense Amplifier 72-bit line drive 73 Word Line Drive 74 Voltage Generator 75 Control Logic Unit 76 Registers 77 Interface 78 Data Bus 80 Control Logic Unit 81 General-purpose microprocessing unit 82 Hardware Processing Module 83 core microprocessing unit 100 Memory 110 Storage Array 111 Memory surface 120 Peripheral Circuits 121 State Machines 131 Sequence Calculation Module 132 Hardware Calculation Module 133 Micro Processing Unit 133 Hardware Calculation Module 134 Main Processor 200 Memory 201 General-purpose controller 202 Hardware Processing Module 203 Micro Processing Unit 205 Memory Interface 206 Synchronization Module 207 Command sequence processing module

Claims

1. A memory comprising a storage array and peripheral circuitry; the storage array includes a plurality of storage planes, each of the storage planes including a storage block made up of storage cells; the peripheral circuitry is connected to the storage array and configured to control a plurality of the storage planes to perform asynchronous operations; a plurality of state machines are included in the peripheral circuitry; Each of the state machines is provided corresponding to at least one of the plurality of storage surfaces, the state machines are connected to a memory interface, and can receive control commands related to asynchronous operation of each corresponding storage surface from the memory interface in parallel, and each of the state machines can independently process the control commands received thereby to obtain control information of the corresponding storage surface; The peripheral circuit further includes a sequence calculation module connected to a plurality of the state machines and configured to specify a processing order for the control information by the peripheral circuit according to control information of the plurality of the state machines.

2. The memory of claim 1 , wherein the peripheral circuitry is configured to control a plurality of the storage planes to perform asynchronous operations according to control information of a plurality of the state machines.

3. the state machine is further configured to set parameters according to the control commands; 2. The memory of claim 1, wherein there is at least a partial overlap between the time periods occupied by at least two of said state machines processing said control commands and performing said parameter settings.

4. Specifically, the state machine: configured to send a processing request to the sequence operation module according to the control command; The sequence operation module specifically includes: The memory of claim 1 , configured to determine the processing order according to the processing requests sent from a plurality of state machines.

5. The peripheral circuit further includes a hardware computing module and a plurality of microprocessing units; the hardware operation module is connected to the sequence operation module and configured to sequentially identify control parameters corresponding to the control information according to the processing order; 2. The memory of claim 1, wherein the plurality of microprocessing units correspond respectively to respective storage surfaces, are connected to the hardware computing module, and are each connected to a corresponding one of the storage surfaces, and the plurality of microprocessing units are configured to perform asynchronous operations on the respective one of the storage surfaces in accordance with the control parameters.

6. 6. The memory of claim 5, wherein each of said state machines is further coupled to a corresponding one of said microprocessing units and configured to provide an enable signal to said microprocessing unit upon receiving said control command.

7. The plurality of microprocessing units further include: configured to transmit state information to a corresponding one of the state machines after completing a control operation on the storage surface based on one of the control commands; The memory of claim 6 , wherein the state machine is further configured to receive a next control command after receiving the state information transmitted from a corresponding microprocessing unit.

8. The peripheral circuit further includes a main processor; 6. The memory of claim 5, wherein the main processor is connected to the memory interface and the plurality of microprocessing units, and configured to receive status information transmitted from the plurality of microprocessing units, and to transmit to the memory interface aggregate status information determined according to the plurality of status information, the aggregate status information being used to indicate that all of the plurality of microprocessing units have completed control operations based on a set of control commands.

9. A method for controlling a memory, the method being performed by a peripheral circuit in the memory, the peripheral circuit including a plurality of state machines, the method comprising: a plurality of said state machines in said memory receiving control commands in parallel relating to asynchronous operations on respective storage surfaces in said memory, each of said state machines being associated with at least one of said plurality of storage surfaces; independently processing each of the control commands received by the state machine to obtain corresponding storage surface control information; and controlling the peripheral circuitry to perform asynchronous operations on the plurality of storage surfaces based on the control information acquired by the state machine; The step of controlling the peripheral circuit to perform asynchronous operations on the plurality of storage surfaces based on the control information includes: determining a processing order for the control information according to the control information acquired by the state machine; sequentially processing the control information according to the processing order; and controlling the plurality of storage surfaces to perform asynchronous operations in accordance with the processed control information. How memory is controlled.

10. The method comprises:

10. The method of claim 9, further comprising the step of: said state machines setting parameter settings according to said control commands, wherein there is at least a partial overlap between time periods occupied by at least two of said state machines processing said control commands and setting said parameter settings.

11. The step of determining a processing order for the control information according to the control information provided by the state machine includes: A sequence operation module in the peripheral circuit receives processing requests transmitted by the plurality of state machines based on the control command; The method of claim 9 , further comprising: the sequence computation module determining a processing order for the control information based on the processing request.

12. The step of sequentially processing the control information in accordance with the processing order includes: a hardware operation module in the peripheral circuit sequentially specifying a control parameter corresponding to the control information according to the processing order in accordance with the control information provided by the state machine; the step of controlling asynchronous operations on the plurality of storage surfaces in accordance with the processed control information includes:

12. The method of claim 11, further comprising the step of controlling a plurality of microprocessing units in the peripheral circuit to perform asynchronous operations on corresponding memory planes according to the control parameters, the plurality of microprocessing units corresponding to a plurality of memory planes, respectively.

13. The method comprises: The method of claim 12 , further comprising the step of providing an enable signal to the microprocessing unit when the state machine receives the control command.

14. The method comprises: after the microprocessing unit finishes a control operation on a control surface based on one of the control information, sending state information to a corresponding one of the state machines; 14. The method of claim 13, further comprising the step of: receiving a next control command after the state machine receives the state information sent from the corresponding microprocessing unit.

15. The method comprises:

13. The method of claim 12, further comprising a step of a main processor in the peripheral circuit receiving status information transmitted from the multiple microprocessing units and transmitting overall status information to a memory interface, the overall status information being used to indicate that all of the multiple microprocessing units have completed control operations based on a set of control commands.

16. 1. A memory system comprising: A memory according to any one of claims 1 to 8 and a controller, The memory system, wherein the controller is coupled to the memory, the controller configured to send control commands to the memory via a memory interface of the memory.

17. 17. The memory system of claim 16, wherein the memory system is a solid state drive SSD or a storage card.

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