High-frequency wave suppression device

Abstract

This high harmonic suppression device comprises: a power converter that is connected to a system line between an AC system and a load, and that generates AC voltage and outputs the result to the system line; and a control means that detects a high harmonic component of load current flowing in the system line, determines a target value for compensating current to be added to the load current in order to suppress the high harmonic component, multiplies the target value by a gain based on the impedance between the system line and the power converter, thereby determines the compensating voltage required to supply compensating voltage corresponding to the target value to the system line, and causes the compensating voltage to be generated and output by the power converter.

Description

[Technical field]

[0001] An embodiment of the present invention relates to a harmonic suppression device that suppresses harmonics. [Background technology]

[0002] When a load with nonlinear characteristics, such as a diode rectifier, is connected to an AC system, harmonic components are generated in the current that flows through the load (load current). Because this harmonic current adversely affects other loads through the AC system, how to suppress it is an important issue.

[0003] As a countermeasure, there is a harmonic suppression device that supplies a compensation current to be added to the load current to suppress harmonics to the system line between the AC system and the load. This harmonic suppression device calculates the deviation between the target value of the compensation current and the compensation current that actually flows, calculates the compensation voltage required to supply the compensation current by proportional-integral calculation (feedback control) using the deviation as input, and supplies the compensation voltage to the system line. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 1-227630 [Patent Document 2] Patent No. 5713044 Summary of the Invention [Problem to be solved by the invention]

[0005] Harmonics contain high frequency components. In order to suppress high frequency components, it is necessary to increase the gain of the proportional and integral calculations. However, increasing the gain can cause delays and resonance, making the control unstable. As a result, it can actually lead to an increase in harmonics.

[0006] An object of an embodiment of the present invention is to provide a harmonic suppression device that can reliably suppress even harmonics that include high frequency components. [Means for solving the problem]

[0007] The harmonic suppression device of claim 1 comprises: a power converter connected to a system line between an AC system and a load, generating an AC voltage and outputting it to the system line; and control means for detecting harmonic components of a load current flowing through the system line, determining a target value of a compensation current to be added to the load current in order to suppress the harmonic components, multiplying the target value by a gain based on the impedance between the system line and the power converter to determine a compensation voltage required to supply a compensation current of the target value to the system line, and causing the power converter to generate and output the compensation voltage. The control means includes: first detection means for detecting the load current; extraction means for extracting low-frequency components of the load current detected by the first detection means; first calculation means for detecting harmonic components contained in the load current by subtracting the low-frequency components extracted by the extraction means from the load current detected by the first detection means, and calculating a target value of a compensation current to be added to the load current in order to suppress the harmonic components; second calculation means for calculating a target value of a compensation voltage required to supply a compensation current of a target value calculated by the first calculation means to the system line by multiplying the target value calculated by the first calculation means by a gain including an impedance between the system line and the power converter and a time derivative term with respect to the target value; and drive means for driving the power converter in accordance with the target value calculated by the second calculation means, thereby generating and outputting a compensation voltage of the target value by the power converter. When the impedance is an interconnection reactor Lac, the gain is the product "Lac×(d / dt)" of the interconnection reactor Lac and the time differential term "d / dt" with respect to the target values ​​Icu', Icv', and Icw'; when the impedance is an interconnection reactor Lac and a resistor R, the gain is "Lac×(d / dt)+R" obtained by adding the product of the interconnection reactor Lac and the time differential term "d / dt" to the resistor R; when the impedance is an LCL filter constituted by an interconnection reactor Lac, a filter capacitor Cf, and a filter reactor Lf, the gain is the product "(Lac+Lf)×(d / dt)" of the interconnection reactor Lac, the filter reactor Lf, and the time differential term "d / dt". [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram showing the configuration of each embodiment. [Diagram 2] FIG. 2 is a block diagram showing the configuration of a control unit according to the first embodiment. [Diagram 3] FIG. 3 is a block diagram showing a configuration of a feedback control unit in FIG. [Figure 4] FIG. 4 is a block diagram showing a configuration of a modified example of FIG. [Diagram 5] FIG. 5 is a block diagram showing the configuration of a control unit according to the second embodiment. [Figure 6] FIG. 6 is a diagram showing waveforms of two-phase AC voltage, load current, system current, and compensation current in each embodiment. [Figure 7] FIG. 7 is a diagram showing the waveforms of the system current and the d-axis and q-axis components of the compensation current in FIG. [Figure 8] FIG. 8 is a diagram showing, for reference, the waveform of a conventional grid current and the waveforms of the d-axis component and q-axis component of a compensation current. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] [1] A first embodiment of the present invention will be described with reference to the drawings. As shown in FIG. 1, a load 3 is connected to system lines (power supply lines) Lu, Lv, and Lw of a three-phase AC system (including a three-phase AC power source, a power system, a power distribution system, etc.) 1 via a system impedance 2.

[0010] The load 3 includes a three-phase rectifier circuit 4 that full-wave rectifies the AC voltages (system voltages) Eu, Ev, and Ew of the three-phase AC system 1 by a bridge connection of diodes 4a to 4f, which are loads having nonlinear characteristics, a DC capacitor 6 connected to the output terminal of the three-phase rectifier circuit 4 via a DC reactor 5, and an inverter 7 connected across the DC capacitor 6. The inverter 7 converts the voltage of the DC capacitor 6 into an AC voltage of a predetermined frequency by switching, and outputs the AC voltage as drive power for, for example, a compressor motor of an air conditioner.

[0011] A harmonic suppression device 10 of the present embodiment is connected to a position between a system impedance 2 and a load 3 in the system lines Lu, Lv, and Lw.

[0012] The harmonic suppression device 10 includes a passive filter 11 for system interconnection, a power converter 12 connected to system lines Lu, Lv, Lw via this passive filter 11, a detector (first detection means) 13 arranged between the connection position of the passive filter 11 on the system lines Lu, Lv, Lw and the load 3, for detecting AC voltages Eu, Ev, Ew of the three-phase AC system 1 and currents (called load currents) ILu, ILv, ILw flowing through the load 3, a detector (second detection means) 14 arranged between the connection between the passive filter 11 and the power converter 12, for detecting compensation currents (also called output currents) Icu, Icv, Icw supplied from the power converter 12 to the system lines Lu, Lv, Lw, and a control unit (control means) 15 for controlling the power converter 12 in accordance with the detection results of these detectors 13, 14.

[0013] The passive filter 11 is, for example, an interconnection reactor arranged for each phase of the system lines Lu, Lv, Lw, or an LCL filter that combines an inductor and a capacitor and is arranged for each phase of the system lines Lu, Lv, Lw.

[0014] The power converter 12 is, for example, a three-phase two-level converter, and includes a switching circuit 12a having a plurality of semiconductor switch elements, a DC capacitor 12b connected between both ends of the switching circuit 12a, and a voltage detector 12c that detects the voltage Vco of the DC capacitor 12b, and generates a three-phase voltage according to a command (request) from the control unit 15 by switching the switching circuit 12a and energizing the DC capacitor 12b accompanying the switching, and outputs the voltage to the system lines Lu, Lv, and Lw. The compensation currents Icu, Icv, and Icw generated by the three-phase voltage are supplied from the power converter 12 to the system lines Lu, Lv, and Lw, thereby suppressing harmonic components contained in the load currents ILu, ILv, and ILw.

[0015] The control unit 15 detects harmonic components contained in the load currents ILu, ILv, ILw detected by the detector 13, determines target values ​​Icu', Icv', Icw' of compensation currents Icu, Icv, Icw to be added to the load currents ILu, ILv, ILw in order to suppress the harmonic components, multiplies the target values ​​Icu', Icv', Icw' by a gain G based on the impedance Z between the system lines Lu, Lv, Lw and the power converter 12, and determines compensation voltages Vcu, Vcv, Vcw required to supply the compensation currents Icu, Icv, Icw of the target values ​​Icu', Icv', Icw' to the system lines Lu, Lv, Lw, and causes the compensation voltages Vcu, Vcv, Vcw to be generated and output by the power converter 12.

[0016] The compensation currents Icu, Icv, Icw to be added to the load currents ILu, ILv, ILw in order to suppress harmonic components are, specifically, currents to be added to the load currents ILu, ILv, ILw in order to make the load currents ILu, ILv, ILw as close as possible to a sine wave synchronized with the AC voltages Eu, Ev, Ew.

[0017] The impedance Z between the system lines Lu, Lv, Lw and the power converter 12 is the ratio of voltage to current in the electric circuit between the system lines Lu, Lv, Lw and the power converter 10, and is determined by the impedance of the passive filter 11 present between the connection between the system lines Lu, Lv, Lw and the power converter 12. The impedance of the passive filter 11 is generally composed of one or a combination of a grid-connection reactor Lac, a filter reactor Lf, a filter capacitor Cf and a resistor R.

[0018] A specific configuration of the control unit 15 is shown in FIG. The values ​​of the load currents ILu, ILv, ILw detected by the detector 13 are supplied to a low-pass filter (extraction means) 21 and a calculation unit (first calculation means) 22. The low-pass filter 21 extracts low-frequency components from the values ​​of the load currents ILu, ILv, ILw detected by the detector 13. The calculation unit 22 detects harmonic components contained in the load currents ILu, ILv, ILw by subtracting the low-frequency components extracted by the low-pass filter 21 from the values ​​of the load currents ILu, ILv, ILw detected by the detector 13. Then, the calculation unit 22 calculates target values ​​(command values) Icu', Icv', Icw' of the compensation currents Icu, Icv, Icw to be added to the load currents ILu, ILv, ILw to suppress the detected harmonic components. The calculation results are supplied to a differential calculation unit (second calculation means) 23.

[0019] The differential calculation unit 23 preliminarily holds a predetermined gain G including the impedance Z between the system lines Lu, Lv, Lw and the power converter 12, and multiplies the target values ​​Icu', Icv', Icw' calculated by the calculation unit 22 by that gain to calculate target values ​​Vcu', Vcv', Vcw' of compensation voltages Vcu, Vcv, Vcw required for compensation currents Icu, Icv, Icw of the target values ​​Icu', Icv', Icw' to be supplied to the system lines Lu, Lv, Lw.

[0020] The gain G is set based on the impedance Z. Specifically, it includes the impedance Z and also includes a time differential term "d / dt" with respect to the target values ​​Icu', Icv', and Icw'. For example, if the impedance Z is the interconnection reactor Lac, the product "Lac×(d / dt)" of the interconnection reactor Lac and the time differential term "d / dt" with respect to the target values ​​Icu', Icv', and Icw' is set as the gain G. In this case, Vcu'=[Lac×(dIcu' / dt)], Vcu'=[Lac×(dIcv' / dt)], and Vcw'=[Lac×(dIcw' / dt)] are obtained as the target values ​​Vcu', Vcv', and Vcw' of the compensation voltages Vcu, Vcv, and Vcw.

[0021] If the impedance Z is the interconnection reactor Lac and the reactor resistance R, the gain G is "Lac×(d / dt)+R", which is the product of the interconnection reactor Lac and the time differential term "d / dt" for the target values ​​Icu´, Icv´, Icw´, plus the resistance R. In this case, the target values ​​Vcu´, Vcv´, Vcw´ of the compensation voltages Vcu, Vcv, Vcw are obtained as Vcu´=[Lac×(dIcu´ / dt)+R], Vcu´=[Lac×(dIcv´ / dt)+R], Vcw´=[Lac×(dIcw´ / dt)+R].

[0022] In addition, if the passive filter is an LCL filter consisting of an interconnection reactor Lac, a filter capacitor Cf, and a filter reactor Lf, the time differential term "d / dt" and the third-order differential term "d 3 / dt 3 "Using the product "(Lac+Lf)×(d / dt)+Lac×Lf×Cf×(d 3 / dt 3)" is the gain G. However, since the purpose of the filter capacitor Cf is to remove the switching ripple component, the third derivative term can be ignored. In this case, the target values ​​Vcu', Vcv', Vcw' of the compensation voltages Vcu, Vcv, Vcw are obtained as Vcu'=[(Lac+Lf)×(dIcu' / dt)], Vcu'=[(Lac+Lf)×(dIcv' / dt)], Vcw'=[(Lac+Lf)×(dIcw' / dt)].

[0023] When implementing differential calculations in a digital controller, it is common to combine an appropriate LPF and implement it as an inexact differential, taking into account the calculation time.

[0024] The calculated target values ​​Vcu', Vcv', Vcw' are supplied to a pulse width modulation circuit (PWM; driving means) 25 via an adder 24. The pulse width modulation circuit 25 generates and outputs a plurality of gate signals (on and off signals) for driving the switching circuit 12a of the power converter 12 by pulse width modulating a sine wave voltage having the same frequency as the AC voltages Eu, Ev, Ew detected by the detector 13 with the target values ​​Vcu', Vcv', Vcw'.

[0025] These gate signals drive each switch element of the switching circuit 12a of the power converter 12 on and off, so that compensation voltages Vcu, Vcv, Vcw of target values ​​Vcu', Vcv', Vcw' are output from the power converter 12. In conjunction with this output, compensation currents Icu, Icv, Icw of target values ​​Icu', Icv', Icw' flow from the power converter 12 to the system lines Lu, Lv, Lw. These compensation currents Icu, Icv, Icw suppress the harmonic components contained in the load currents ILu, ILv, ILw.

[0026] FIG. 6 shows the waveforms of AC voltages Eu, Ev extracted from two phases in the three-phase AC system 1, the waveforms of load currents ILu, ILv, the waveforms of system currents Iu, Iv in the three-phase AC system 1, and the waveforms of compensation currents Icu, Icv.

[0027] As described above, the harmonic components contained in the load currents ILu, ILv, ILw are detected, the target values ​​Icu', Icv', Icw' of the compensation currents Icu, Icv, Icw to be added to the load currents ILu, ILv, ILw to suppress the harmonic components are calculated, and the compensation voltages Vcu, Vcv, Vcw required for the compensation currents Icu, Icv, Icw of the target values ​​Icu', Icv', Icw' to be supplied to the system lines Lu, Lv, Lw can be directly obtained from the target values ​​Icu', Icv', Icw' by multiplying the target values ​​Icu', Icv', Icw' by the gain G. Therefore, it is possible to obtain appropriate compensation voltages Vcu, Vcv, Vcw that can sufficiently deal with harmonics including high frequency components without causing delay or resonance as in the conventional device that must increase the gain of the proportional-integral calculation.

[0028] In other words, in conventional harmonic suppression devices that obtain compensation voltages through proportional and integral calculations, the gain of the proportional and integral calculations must be increased to deal with harmonics that contain high frequency components, which causes delays and resonance, making the control unstable and actually resulting in an increase in harmonics. However, by directly determining the compensation voltages Vcu, Vcv, and Vcw from the target values ​​Icu', Icv', and Icw', even harmonics that contain high frequency components can be reliably suppressed.

[0029] 7 shows an enlarged view of the waveforms of the grid currents Iu and Iv in this embodiment, and also shows one compensation current Icu in this embodiment divided into a d-axis component waveform and a q-axis component waveform that is electrically out of phase with the d-axis component by 90 degrees. According to this embodiment, the d-axis component and the q-axis component can be made to appropriately follow their respective target values.

[0030] On the other hand, in the case of a conventional device that obtains a compensation voltage by proportional-integral calculation, the compensation current does not properly follow the target value, as shown in Fig. 8, and this appears as large harmonic noise in the waveforms of the system currents Iu and Iv. This embodiment can eliminate such a problem.

[0031] 2, in order to deal with unnecessary fluctuations in the AC voltages Eu, Ev, Ew, the values ​​of the AC voltages Eu, Ev, Ew detected by the detector 13 are supplied to an adder 24, which adds the values ​​of the AC voltages Eu, Ev, Ew to the target values ​​Vcu', Vcv', Vcw'. The target values ​​Vcu', Vcv', Vcw' passed through the adder 24 are supplied to a pulse width modulation circuit 25. This makes it possible to eliminate the problem of unnecessary fluctuations in the AC voltages Eu, Ev, Ew being superimposed on the compensation voltages Vcu, Vcv, Vcw.

[0032] In addition, in order to deal with unexpected disturbances to the compensation currents Icu, Icv, and Icw and errors in the assumed impedance Z, and further to maintain the voltage Vco of the DC capacitor 12b in the power converter 12 at a constant standard value, a calculation unit (third calculation means) 26, a calculation unit (fourth calculation means) 27, a voltage control unit 28, and a feedback control unit 30 are added to the control unit 15, as shown in FIG. 2.

[0033] The calculation unit 26 calculates deviations (Icu'-Icu), (Icv'-Icv), (Icw'-Icw) between the target values ​​Icu', Icv', Icw' calculated by the calculation unit 22 and the actual compensation currents Icu, Icv, Icw detected by the detector 14. The calculation unit 27 calculates a deviation ΔVco between a predetermined standard value Vcos for the voltage Vco of the capacitor 12b in the power converter 12 and the actual voltage Vco of the capacitor 12b detected by the voltage detector 12c of the power converter 12.

[0034] A voltage control unit 28 obtains a correction value ΔIco to be added to the obtained deviations (Icu'-Icu), (Icv'-Icv), and (Icw'-Icw) in order to maintain the voltage Vco of the capacitor 12b constant at the standard value Vcos by multiplying the deviation ΔVco obtained by the calculation unit 27 by a predetermined voltage control gain. The calculation unit 26 outputs the deviations ΔIcu, ΔIcv, and ΔIcw obtained by adding the correction value ΔIco to the obtained deviations.

[0035] The feedback control unit 30 obtains correction values ​​ΔVcu′, ΔVcv′, ΔVcw′ to be added to the target values ​​Vcu′, Vcv′, Vcw′ calculated by the differential calculation unit 23 by proportional calculation or proportional-integral calculation using the deviations ΔIcu, ΔIcv, ΔIcw output from the calculation unit 26 as input so that the deviations ΔIcu, ΔIcv, ΔIcw obtained by the calculation unit 26 become zero. The obtained correction values ​​ΔVcu′, ΔVcv′, ΔVcw′ are added to the target values ​​Vcu′, Vcv′, Vcw′ in the adder 24. This makes it possible to obtain stable and appropriate compensation voltages Vcu, Vcv, Vcw that can maintain the voltage Vco of the capacitor 12b in the power converter 12 at a constant standard value without being significantly affected by unexpected disturbances to the compensation currents Icu, Icv, Icw or errors in the assumed impedance Z.

[0036] As shown in FIG. 3, for example, this feedback control unit 30 accumulates the deviations ΔIcu, ΔIcv, ΔIcw supplied from the calculation unit 26 while retaining and integrating them for each period of the AC voltages Eu, Ev, Ew using a loop configuration consisting of an adder 31, a holding unit 32, and an integration unit (LPF) 33, and multiplies this accumulation result by a predetermined repetition gain Krc for repetitive control in a multiplication unit 34. In the subsequent addition unit 35, this multiplication result is added to the deviations ΔIcu, ΔIcv, ΔIcw supplied from the calculation unit 26. Then, the feedback control unit 30 multiplies the deviations ΔIcu, ΔIcv, ΔIcw that have passed through the adder 35 by a proportional gain Kp in the proportional calculation unit 36, and in parallel multiplies them by an integral gain Ki / s in the integral calculation unit 37, and adds up the results of these multiplications in the adder 38, thereby determining correction values ​​ΔVcu', ΔVcv', ΔVcw' to be added to the target values ​​Vcu', Vcv', Vcw' calculated by the differential calculation unit 23 so that the deviations ΔIcu, ΔIcv, ΔIcw obtained by the calculation unit 26 become zero.

[0037] The deviations ΔIcu, ΔIcv, ΔIcw are held, integrated, and accumulated for each period of the AC voltages Eu, Ev, Ew, and the accumulated results are multiplied by a repetition gain Krc to reduce periodic errors in the deviations ΔIcu, ΔIcv, ΔIcw.

[0038] 4, the feedback control section 30 may be configured such that the integration result obtained by the loop configuration of an adder 31, a holder 32, and an integrator (LPF) 33 is multiplied by a repetition gain Krc in a multiplier 34, and then lead compensation processing is applied to the multiplication result by a loop configuration of a lead compensator 41 and an adder 42. By applying the lead compensation processing, the delay time of the processing by the proportional and integral calculations of a proportional calculation section 36 and an integral calculation section 37 can be compensated for.

[0039] [2] The configuration of a control unit 15 in the second embodiment of the present invention is shown in FIG. A band elimination filter (first band elimination means) 51 and a holding unit 52 are sequentially arranged on a signal path from the calculation unit 22 that calculates the target values ​​Icu', Icv', Icw' to the differential calculation unit 23 that calculates the target values ​​Icu', Icv', Icw'. Furthermore, a band elimination filter (second band elimination means) 52 is arranged on a signal path from the detector 14 that detects the values ​​of the compensation currents Icu, Icv, Icw to the calculation unit 26 that determines the deviations ΔIcu, ΔIcv, ΔIcw.

[0040] When the passive filter 11 on the output side of the power converter 12 is an LCL filter, the band elimination filter 51 eliminates a predetermined frequency band from the target values ​​Icu', Icv', Icw' calculated by the calculation unit 22 in order to avoid resonance in the LCL filter. If resonance occurs in the LCL filter, unintended harmonic components may be superimposed on the compensation currents Icu, Icv, Icw output from the power converter 12, so the resonance is avoided by band elimination processing on the target values ​​Icu', Icv', Icw'.

[0041] In order to compensate for the deviation between the target values ​​Icu', Icv', Icw' and the actual compensation currents Icu, Icv, Icw caused by control delays and detection delays, the holding unit 52 sequentially holds the target values ​​Icu', Icv', Icw' that have passed through the band elimination filter 51 during one period of the AC voltages Eu, Ev, Ew.

[0042] The band elimination filter 52 is, for example, a notch filter, and removes a predetermined frequency band from the compensation currents Icu, Icv, Icw detected by the detector 14 in order to eliminate the problem of harmonic components being superimposed on the compensation currents Icu, Icv, Icw detected by the detector 14, which is caused by the adoption of the feedback control unit 30, and to eliminate the problem of the harmonic components being amplified by the gain of the feedback control unit 30.

[0043] [3] Variations In each of the above embodiments, a three-phase two-level converter is used as the power converter 12, but the present invention is not limited to this and a multilevel converter may also be used.

[0044] The control of the control unit 15 may be configured to perform control of a d-axis component having the same phase as the phase of the AC voltages Eu, Ev, Ew and control of a q-axis component electrically shifted in phase by 90 degrees from the d-axis component by using a rotational coordinate transformation based on the phase of the AC voltages Eu, Ev, Ew. This makes it possible to remove interference terms between the phases in the power converter 12 and between the d-axis and q-axis. By performing a rotational coordinate transformation on the load currents ILu, ILv, ILw, it is possible to extract only the DC amount from the load currents ILu, ILv, ILw including harmonic components and subtract it from the original load currents ILu, ILv, ILw to obtain the target values ​​Icu', Icv', Icw' of the load currents ILu, ILv, ILw.

[0045] In addition, the above-mentioned embodiments and modifications are presented as examples and are not intended to limit the scope of the invention. These embodiments and modifications can be implemented in various other forms, and various omissions, rewritings, and modifications can be made without departing from the scope of the invention. These embodiments and modifications are included in the scope of the invention and the scope of equivalents thereof as described in the claims. [Explanation of symbols]

[0046] 1...system power supply, 2...load, Lu, Lv, Lw...system line, 10...harmonic suppression device, 11...passive filter, 12...power converter, 12a...switching circuit, 12b...capacitor, 12c...voltage detector, 13, 14...detector, 15...control unit, 21...low-pass filter (extraction means), 22...calculation unit (first calculation means), 23...differential calculation unit (second calculation means), 25...pulse width modulation circuit (drive means)

Claims

1. A power converter connected to a system line between an AC system and a load, generating an AC voltage and outputting the AC voltage to the system line; a control means for detecting harmonic components of a load current flowing through the system line, determining a target value of a compensation current to be added to the load current in order to suppress the harmonic components, determining a compensation voltage required to supply a compensation current of the target value to the system line by multiplying the target value by a gain based on the impedance between the system line and the power converter, and causing the power converter to generate and output the compensation voltage; Equipped with The control means a first detection means for detecting the load current; an extracting means for extracting a low frequency component of the load current detected by the first detecting means; a first calculation means for detecting harmonic components contained in the load current by subtracting the low frequency components extracted by the extraction means from the load current detected by the first detection means, and for calculating a target value of a compensation current to be added to the load current in order to suppress the harmonic components; a second calculation means for calculating a target value of a compensation voltage required for supplying a compensation current of the target value calculated by the first calculation means to the system line by multiplying the target value calculated by the first calculation means by a gain including an impedance between the system line and the power converter and a time differential term with respect to the target value; a driving means for driving the power converter in accordance with the target value calculated by the second calculation means, thereby causing the power converter to generate and output a compensation voltage for the target value; Including, The gain is When the impedance is an interconnection reactor Lac, it is a product “Lac×(d / dt)” of the interconnection reactor Lac and the time differential term “d / dt” with respect to the target values ​​Icu′, Icv′, and Icw′, When the impedance is an interconnection reactor Lac and a resistance R, it is “Lac×(d / dt)+R”, which is the product of the interconnection reactor Lac and the time differential term “d / dt” plus the resistance R, In the case of an LCL filter including an interconnection reactor Lac, a filter capacitor Cf, and a filter reactor Lf, the impedance is the product “(Lac+Lf)×(d / dt)” of the interconnection reactor Lac, the filter reactor Lf, and the time differential term “d / dt”, Harmonic suppression device.

2. a passive filter for grid connection provided between the grid line and the power converter; Further comprising: The harmonic suppression device according to claim 1 .

3. The control means a second detection means for detecting a compensation current supplied from the power converter to the system line; a third calculation means for calculating a deviation between a target value calculated by the first calculation means and a value of the compensation current detected by the second detection means; a feedback control means for calculating a correction value to be added to the target value calculated by the second calculation means by a proportional calculation or a proportional-integral calculation using the deviation calculated by the third calculation means as an input so that the deviation calculated by the third calculation means becomes zero; an adding means for adding a correction value obtained by the feedback control means to a target value calculated by the second calculation means; Further comprising: The harmonic suppression device according to claim 1 .

4. the feedback control means accumulates the deviation calculated by the third calculation means while retaining and integrating it for each cycle of the AC voltage of the AC system, multiplies the accumulated result by a predetermined repetition gain, adds the multiplication result to the deviation calculated by the third calculation means, and determines a correction value to be added to the target value calculated by the second calculation means by a proportional calculation or a proportional-integral calculation using the sum result as an input, so that the deviation calculated by the third calculation means becomes zero. The harmonic suppression device according to claim 3.

5. the feedback control means applies a lead compensation process to the multiplication result of the repetitive gain in order to compensate for a delay time of the process by the proportional operation or the proportional-integral operation. The harmonic suppression device according to claim 4.

6. The control means a first band removal means for removing a predetermined frequency band from the target value calculated by the first calculation means; Further comprising: the second calculation means calculates a target value of a compensation voltage required for supplying a compensation current of the target value calculated by the first calculation means to the system line by multiplying the target value that has passed through the first band removal means by the gain; The harmonic suppression device according to claim 1 .

7. The control means a holding means for successively holding the target value calculated by the first calculation means during one period of the AC voltage of the AC system; Further comprising: the second calculation means calculates target values ​​Vcu', Vcv', Vcw' of compensation voltages Vcu, Vcv, Vcw necessary for supplying the compensation current of the target value calculated by the first calculation means to the system line by multiplying the target value held by the holding means by the gain; The harmonic suppression device according to claim 1 .

8. The control means a second band removal means for removing a predetermined frequency band from the values ​​of the compensation currents Icu, Icv, and Icw detected by the second detection means; Including, the third calculation means calculates deviations ΔI, ΔI, ΔI between the target values ​​I, I, I calculated by the first calculation means and the compensation currents I, I, I processed by the second band elimination means; The harmonic suppression device according to claim 3.

9. The load includes a diode bridge rectifier circuit that rectifies the voltage of the AC system, a DC capacitor connected to an output terminal of the rectifier circuit via a DC reactor, and an inverter that converts the voltage of the DC capacitor into an AC voltage of a predetermined frequency. The harmonic suppression device according to any one of claims 1 to 8.

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