Data flow control device

Abstract

A data flow control device (100a) comprises an input / output interface conversion unit (130) that is disposed between function units (101-1, 101-2) which perform data processing, and in a case where the input / output interfaces of the function units (101-1, 101-2) are different, that converts the data output by the function unit (101-1) so that such data can be input to the function unit (101-2).

Description

[Technical Field]

[0001] The present invention relates to a data flow control device in a computer system such as an arithmetic unit. [Background technology]

[0002] Technological innovation is progressing in many fields, including machine learning, artificial intelligence (AI), and the Internet of Things (IoT), and by utilizing a variety of information and data, services are becoming more sophisticated and added value is being actively provided. Processing in these fields requires large amounts of calculation, which requires an information processing infrastructure.

[0003] For example, Non-Patent Document 1 discloses an attempt to update existing information processing infrastructure. However, it is also true that modern computer systems are unable to keep up with the rapidly increasing amount of data. Non-Patent Document 1 also points out that in order to achieve further evolution in the future, technology that surpasses Moore's Law must be established.

[0004] As a technology that goes beyond Moore's Law, for example, Non-Patent Document 2 discloses a technology called flow-centric computing. Flow-centric computing introduces a new concept in which data is moved to a location where a computing function is present and processed there, rather than the conventional computing concept of performing processing where data is located.

[0005] To realize flow-centric computing as described above, not only is a broadband communication network necessary for data movement required, but it is also necessary to efficiently control computing resources, otherwise the desired computing performance may not be achieved.

[0006] Generally, in flow-centric computing, examples have been proposed in which functions are connected to perform desired arithmetic processing. However, when the input / output interfaces of functions are different and they cannot be directly connected, no data flow control method for absorbing the differences in the interfaces between functions has been disclosed.

Prior Art Documents

Non-Patent Documents

[0007]

Non-Patent Document 1

Non-Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0008] An object of the present invention is to provide a data flow control device capable of absorbing differences in input / output interfaces when the input / output interfaces of a front-stage function unit and a rear-stage function unit are different.

Means for Solving the Problems

[0009] The data flow control device of the present invention includes an input / output interface conversion unit that is provided between two or more function units that perform data processing, and that is configured to convert output data from the function unit in the preceding stage so that the output data can be input to the function unit in the following stage when the input / output interfaces of the function unit in the preceding stage and the function unit in the following stage are different. and a placement unit configured to place the input / output interface conversion units between the function units so that the input / output interfaces between the function units are compatible based on system configuration information indicating connection relationships between the plurality of function units. Equipped with The function units are connected via a communication network, and the input / output interface conversion unit is disposed on the communication network. It is characterized by the following.

[0010] In one configuration example of the data flow control device of the present invention, the input / output interface conversion unit comprises: a conversion determination unit configured to determine whether or not to convert the output data of the upstream function unit based on input / output interface information of the upstream and downstream function units; a conversion unit configured to convert the output data of the upstream function unit so that it can be input to the downstream function unit; and an output selection unit configured to selectively output either the output data converted by the conversion unit or the unconverted output data output from the upstream function unit to the downstream function unit based on the determination result of the conversion determination unit.

[0011] In addition, in one configuration example of the data flow control device of the present invention, the conversion determination unit and the conversion unit are characterized in that when there are multiple function units in the previous stage, they are provided for each function unit in the previous stage. In addition, in one configuration example of the data flow control device of the present invention, the conversion determination unit, the conversion unit, and the output selection unit are characterized in that, when there are multiple function units in the subsequent stage, they are provided for each of the function units in the subsequent stage.

[0012] Furthermore, in one configuration example of the data flow control device of the present invention, the conversion determination unit is a clock frequency transfer determination unit configured to determine whether or not to convert the clock frequency of the output data of the upstream function unit based on input / output interface information of the upstream and downstream function units, the conversion unit is a clock transfer unit configured to convert the clock frequency of the output data of the upstream function unit to the clock frequency of the input data of the downstream function unit, and the output selection unit selectively outputs to the downstream function unit either the output data whose clock frequency has been converted by the clock transfer unit or the unconverted output data output from the upstream function unit based on the determination result of the clock frequency transfer determination unit.

[0013] In one configuration example of the data flow control device of the present invention, the conversion determination unit is a data width conversion determination unit configured to determine whether or not to convert the output data width of the upstream function unit based on input / output interface information of the upstream and downstream function units, the conversion unit is a data width conversion unit configured to convert the output data width of the upstream function unit to match the input data width of the downstream function unit, and the output selection unit selectively outputs, to the downstream function unit, either the output data whose data width has been converted by the data width conversion unit or the unconverted output data output from the upstream function unit based on the determination result of the data width conversion determination unit.

[0014] In one configuration example of the data flow control device of the present invention, the conversion determination unit is an input / output information conversion determination unit configured to determine whether or not to convert the format of the output data of the upstream function unit based on input / output interface information of the upstream and downstream function units, the conversion unit is an input / output information conversion unit configured to convert the format of the output data of the upstream function unit so that it matches the format of the input data of the downstream function unit, and the output selection unit selectively outputs, to the downstream function unit, either the output data whose format has been converted by the input / output information conversion unit or the unconverted output data output from the upstream function unit based on the determination result of the input / output information conversion determination unit. [Effects of the Invention]

[0016] According to the present invention, input / output data between function units is converted to enable a connection that allows data to be exchanged between upstream and downstream function units without interface inconsistencies. This enables connection between function units even when the upstream and downstream function units have different input / output interfaces. The present invention allows function units with any input / output interface to be designed and used, and existing function units can also be reused. Furthermore, the present invention allows function units with different input / output interfaces to be connected without changing the input / output interfaces, enabling the reuse of function units. Furthermore, the present invention eliminates the need for verification of function units when changing input / output interfaces, thereby reducing verification costs. Furthermore, the present invention allows function units to be connected without using memory, eliminating the constraints of memory data width and data write and read speeds, enabling low latency and high throughput. [Brief explanation of the drawings]

[0017] [Figure 1] FIG. 1 is a block diagram showing the configuration of a conventional data flow control device. [Figure 2] FIG. 2 is a block diagram showing the basic configuration of a data flow control device according to a first embodiment of the present invention. [Figure 3] FIG. 3 is a block diagram showing a specific example of a data flow control device according to a first embodiment of the present invention. [Figure 4] FIG. 4 is a flowchart illustrating the operation of the data flow control device according to the first embodiment of the present invention. [Figure 5] FIG. 5 is a block diagram showing the configuration of a data flow control device according to a second embodiment of the present invention. [Figure 6] FIG. 6 is a flowchart illustrating the operation of the data flow control device according to the second embodiment of the present invention. [Figure 7] FIG. 7 is a block diagram showing the configuration of a data flow control device according to a third embodiment of the present invention. [Figure 8] FIG. 8 is a flowchart illustrating the operation of the data flow control device according to the third embodiment of the present invention. [Figure 9] FIG. 9 is a block diagram showing the basic configuration of a data flow control device according to a fourth embodiment of the present invention. [Figure 10] FIG. 10 is a block diagram showing a specific example of a data flow control device according to the fourth embodiment of the present invention. [Figure 11] FIG. 11 is a flowchart illustrating the operation of the data flow control device according to the fourth embodiment of the present invention. [Figure 12] FIG. 12 is a block diagram showing the basic configuration of a data flow control device according to a fifth embodiment of the present invention. [Figure 13] FIG. 13 is a block diagram showing a specific example of a data flow control device according to the fifth embodiment of the present invention. [Figure 14] FIG. 14 is a block diagram showing a specific example of a data flow control device according to the fifth embodiment of the present invention. [Figure 15] FIG. 15 is a block diagram showing a specific example of a data flow control device according to the fifth embodiment of the present invention. [Figure 16] FIG. 16 is a block diagram showing a specific example of a data flow control device according to the fifth embodiment of the present invention. [Figure 17] FIG. 17 is a flowchart illustrating the operation of the data flow control device according to the fifth embodiment of the present invention. [Figure 18] FIG. 18 is a block diagram showing the configuration of a data flow control device according to a sixth embodiment of the present invention. [Figure 19] FIG. 19 is a flowchart illustrating the operation of the data flow control device according to the sixth embodiment of the present invention. [Figure 20] FIG. 20 is a block diagram showing the configuration of a data flow control device according to a seventh embodiment of the present invention. [Figure 21] FIG. 21 is a flowchart illustrating the operation of the arrangement unit of the data flow control device according to the seventh embodiment of the present invention. [Figure 22] FIG. 22 is a flowchart illustrating the operation of the data flow control device according to the seventh embodiment of the present invention. [Figure 23] FIG. 23 is a block diagram showing an example of the configuration of a computer that realizes the data flow control devices according to the first to seventh embodiments of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0018] [Conventional configuration] First, the configuration of a conventional data flow control device will be described with reference to Fig. 1. A conventional data flow control device 100 includes function units 101-1 and 101-2, which are arithmetic devices that perform data processing such as arithmetic operations, and a memory 102 that connects the function units 101-1 and 101-2. Examples of the function units 101-1 and 101-2 include a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), and an FPGA (Field Programmable Gate Array).

[0019] As shown in FIG. 1, a conventional data flow control device 100 generally connects function units 101-1 and 101-2 via a memory 102 that has a fixed data width and fixed data write and read speeds.

[0020] [Configuration of the first embodiment] Next, the configuration of a data flow control device according to a first embodiment of the present invention will be described with reference to Figures 2 and 3. Figure 2 is a block diagram showing the basic configuration of a data flow control device according to this embodiment, and Figure 3 is a block diagram showing a specific example of the data flow control device according to this embodiment.

[0021] The data flow control device 100a of this embodiment is a data flow type computing system that includes function units 101-1 and 101-2, which are arithmetic devices that perform data processing such as arithmetic operations, and an input / output interface conversion unit 103 that converts input / output data between the function units 101-1 and 101-2 so that the function units 101-1 and 101-2 have different input / output interfaces and can exchange data without interface inconsistencies.

[0022] The input / output interface conversion unit 103 includes a conversion determination unit 104 that determines whether or not to convert the output data of the function unit 101-1, a conversion unit 105 that converts the output data of the function unit 101-1 so that it can be input to the function unit 101-2, and an output selection unit 106 that selectively outputs either the converted output data or the unconverted output data output from the function unit 101-1 to the function unit 101-2.

[0023] The conversion of input data will now be described in detail. For example, when the clock frequencies of the data handled by function units 101-1 and 101-2 are different, clock resynchronization is required, in which input data synchronized with the clock of the preceding function unit 101-1 is output as data synchronized with the clock of the succeeding function unit 101-2. In this case, as a specific example of conversion unit 105 in Fig. 2, a clock resynchronizer 1050 consisting of a FIFO (First In, First Out) buffer that absorbs the difference in speed between function units 101-1 and 101-2 is provided. Furthermore, as a specific example of conversion determination unit 104 in Fig. 2, a clock frequency resynchronizer determination unit 1040 is provided.

[0024] If the output data width of function unit 101-1 and the input data width of function unit 101-2 are the same and the clock frequency of the output data of function unit 101-1 is higher than the clock frequency of the input data of function unit 101-2, the output speed of data from function unit 101-1 may be faster than the input data speed specified by function unit 101-2. As a result, there is a possibility that data may overflow before being input to function unit 101-2.

[0025] To prevent data overflow, for example, a FIFO buffer with a predetermined depth is used, and the input clock frequency to the FIFO buffer and the output clock frequency from the FIFO buffer are changed to convert the clock frequency of the output data of function unit 101-1 to the clock frequency of the input data of function unit 101-2. The depth of the FIFO buffer is adjusted based on the input / output conditions of function units 101-1 and 101-2 so that data overflow does not occur.

[0026] In addition, if the clock frequency of the output data of function unit 101-1 is lower than the clock frequency of the input data of function unit 101-2, the speed of the data output from function unit 101-1 will be slower than the speed of the input data specified in function unit 101-2, so it is not necessarily necessary to change the clock frequency.

[0027] Furthermore, if the input data width of function unit 101-2 is larger than the output data width of function unit 101-1, even if the clock frequency of the output data of function unit 101-1 is higher than the clock frequency of the input data of function unit 101-2, the speed of the data output from function unit 101-1 may be slower than the speed of the input data specified by function unit 101-2. In this case, it is not necessarily necessary to change the clock frequency.

[0028] On the other hand, even if the input data width of function unit 101-2 is larger than the output data width of function unit 101-1, if the clock frequency of the output data of function unit 101-1 is high and there is a large difference between the clock frequency of the input data of function unit 101-2, the output speed of the data of function unit 101-1 may be faster than the input data speed specified by function unit 101-2. As a result, there is a possibility that the data may overflow before being input to function unit 101-2.

[0029] To prevent data overflow, for example, a FIFO buffer with a predetermined depth is used, and the input clock frequency to the FIFO buffer and the output clock frequency from the FIFO buffer are changed to convert the clock frequency of the output data of function unit 101-1 to the clock frequency of the input data of function unit 101-2. The depth of the FIFO buffer is adjusted based on the input / output conditions of function units 101-1 and 101-2 so that data overflow does not occur.

[0030] In addition, if the clock frequency of the output data of function unit 101-1 is lower than the clock frequency of the input data of function unit 101-2, the speed of the data output from function unit 101-1 will be slower than the speed of the input data specified in function unit 101-2, so it is not necessarily necessary to change the clock frequency.

[0031] Furthermore, even if the clock frequency of the output data of function unit 101-1 is lower than the clock frequency of the input data of function unit 101-2, if the input data width of function unit 101-2 is smaller than the output data width of function unit 101-1 and the difference between the clock frequency of the input data of function unit 101-2 and the clock frequency of the output data of function unit 101-1 is not sufficient, the output speed of data from function unit 101-1 may be faster than the input data speed specified by function unit 101-2. This may cause data overflow before it is input to function unit 101-2.

[0032] To prevent data overflow, for example, a FIFO buffer with a predetermined depth is used, and the input clock frequency to the FIFO buffer and the output clock frequency from the FIFO buffer are changed to convert the clock frequency of the output data of function unit 101-1 to the clock frequency of the input data of function unit 101-2. The depth of the FIFO buffer is adjusted based on the input / output conditions of function units 101-1 and 101-2 so that data overflow does not occur.

[0033] In addition, if the clock frequency of the output data of function unit 101-1 is sufficiently lower than the clock frequency of the input data of function unit 101-2, the speed of the data output from function unit 101-1 will be slower than the speed of the input data specified in function unit 101-2, so it is not necessarily necessary to change the clock frequency.

[0034] As described above, when the function units 101-1 and 101-2 to be used are determined, the specifications of the input / output interfaces of the function units 101-1 and 101-2 are determined. Based on the specifications of the input / output interfaces, an input / output interface conversion unit 103 is provided to connect the function units 101-1 and 101-2.

[0035] The difference between the data flow control device 100 of the conventional embodiment shown in Fig. 1 is that the data flow control device 100a of this embodiment includes an input / output interface conversion unit 103. The input / output interface conversion unit 103 converts input / output data between the function units 101-1 and 101-2 so that the function units 101-1 and 101-2 can be connected to each other without interface inconsistencies, thereby enabling connection between the function units 101-1 and 101-2 even if the function units 101-1 and 101-2 have different input / output interfaces.

[0036] A conventional data flow control device 100 uses memory 102 for connection between function units 101-1 and 101-2. On the other hand, in this embodiment, by providing an input / output interface conversion unit 103 that converts input / output data between function units 101-1 and 101-2, it is possible to connect function units 101-1 and 101-2 without using memory, even if the input / output interfaces of function units 101-1 and 101-2 are different.

[0037] In this embodiment, a function unit for any input / output interface can be designed and used, and existing function units can also be reused. Furthermore, in this embodiment, function units with different input / output interfaces can be connected without changing the input / output interfaces, allowing for the reuse of function units. Furthermore, in this embodiment, verification of function units accompanying changes in input / output interfaces is not required, reducing verification costs. Furthermore, in this embodiment, function units can be connected without using memory, eliminating the constraints on processing speed due to the memory data width and data write and read speeds, enabling low latency and high throughput.

[0038] [Operation of the first embodiment] Next, the operation of the data flow control device 100a of this embodiment will be described with reference to Fig. 4. In a data flow computing system, when two or more function units have different input / output interfaces, the data flow control device 100a of this embodiment converts input / output data to establish a connection that allows data to be exchanged between the function units without interface inconsistencies.

[0039] First, the function unit 101-1 performs data processing such as arithmetic processing, and then outputs the data resulting from the processing.

[0040] Next, input / output interface conversion unit 103 converts input / output data between function units 101-1 and 101-2 so as to establish a connection that allows data to be exchanged between function units 101-1 and 101-2 having different input / output interfaces without interface inconsistency.

[0041] Specifically, the clock frequency transfer determination unit 1040 of the input / output interface conversion unit 103 acquires input / output interface information of the function units 101-1 and 101-2 (step S100 in FIG. 4). The input / output interface information (communication protocol) includes, for example, a data format, a clock frequency of data, and information on a data communication procedure.

[0042] If the clock frequency transfer determination unit 1040 can obtain the input / output interface information from the function units 101-1 and 101-2, it may do so. If the input / output interface information of the function units 101-1 and 101-2 is registered in an external management device (not shown), the clock frequency transfer determination unit 1040 may obtain the input / output interface information from the management device.

[0043] Next, the clock frequency resynchronization determining unit 1040 determines whether or not to convert the output data of the function unit 101-1 based on the acquired input / output interface information (step S101 in FIG. 4). In this embodiment, a case will be described in which the clock frequencies of the data handled by the function units 101-1 and 101-2 are different.

[0044] If the clock frequency of the output data of the function unit 101-1 is higher than the clock frequency of the input data of the function unit 101-2 (YES in step S101), the clock frequency resynchronization determination unit 1040 determines to convert the output data of the function unit 101-1 (step S102 in FIG. 4).If the clock frequency of the output data of the function unit 101-1 is lower than the clock frequency of the input data of the function unit 101-2 (NO in step S101), the clock frequency resynchronization determination unit 1040 determines not to convert the output data of the function unit 101-1 (step S103 in FIG. 4).

[0045] Clock transfer unit 1050, which is made up of a FIFO buffer, performs clock transfer, converting the clock frequency of the output data of function unit 101-1 to the clock frequency of the input data of function unit 101-2 (step S104 in FIG. 4). Note that, in order to accommodate various clock frequencies based on input / output interface information, clock transfer unit 1050 preferably includes an internal variable clock oscillator that can set the input clock frequency to the FIFO buffer to the clock frequency of the output data of function unit 101-1 and can set the output clock frequency from the FIFO buffer to the clock frequency of the input data of function unit 101-2.

[0046] Based on the determination result of the clock frequency resynchronization determination unit 1040, the output selection unit 106 selectively outputs either the output data whose clock frequency has been converted by the clock resynchronization unit 1050 or the unconverted output data output from the function unit 101-1 (step S105 in FIG. 4). If the clock frequency resynchronization determination unit 1040 determines that the output data of the function unit 101-1 should be converted, the output selection unit 106 outputs the output data whose clock frequency has been converted by the clock resynchronization unit 1050 to the function unit 101-2. On the other hand, if the clock frequency resynchronization determination unit 1040 determines that the output data of the function unit 101-1 should not be converted, the output selection unit 106 outputs the unconverted output data output from the function unit 101-1 to the function unit 101-2.

[0047] The function unit 101-2 performs data processing such as arithmetic operations on the data input from the input / output interface conversion unit 103.

[0048] [Effects of the first embodiment] As described above, the input / output interface conversion unit 103 of this embodiment converts input / output data between the function units 101-1 and 101-2 so that the function units 101-1 and 101-2 can be connected to each other without interface mismatches, thereby enabling connection between the function units 101-1 and 101-2 even if the function units 101-1 and 101-2 have different input / output interfaces.

[0049] In this embodiment, a function unit for any input / output interface can be designed and used, and existing function units can also be reused. Furthermore, in this embodiment, function units with different input / output interfaces can be connected without changing the input / output interfaces, allowing for the reuse of function units. Furthermore, in this embodiment, verification of function units accompanying changes in input / output interfaces is not required, reducing verification costs. Furthermore, in this embodiment, function units can be connected without using memory, eliminating the constraints on processing speed due to the memory data width and data write and read speeds, enabling low latency and high throughput.

[0050] In this embodiment, it is determined that the output data of function unit 101-1 is to be converted only when the clock frequency of the output data of function unit 101-1 is higher than the clock frequency of the input data of function unit 101-2. However, it goes without saying that the output data of function unit 101-1 may also be converted when the clock frequency of the output data of function unit 101-1 is lower than the clock frequency of the input data of function unit 101-2.

[0051] [Configuration of the second embodiment] Next, a second embodiment of the present invention will be described. Fig. 5 is a block diagram showing the configuration of a data flow control device according to this embodiment. A data flow control device 100b of this embodiment is provided with function units 101-1 and 101-2, which are arithmetic devices that perform data processing such as arithmetic operations in a data flow computing system, and an input / output interface conversion unit 103b that converts input / output data between the function units 101-1 and 101-2 so as to establish a connection that enables data exchange without interface inconsistency between the function units 101-1 and 101-2, which have different input / output interfaces.

[0052] The input / output interface conversion unit 103b includes a conversion determination unit (104 in FIG. 2) that determines whether or not to convert the output data of the function unit 101-1, a conversion unit (105 in FIG. 2) that converts the output data of the function unit 101-1 so that it can be input to the function unit 101-2, and an output selection unit 106b that selectively outputs either the converted output data or the unconverted output data output from the function unit 101-1 to the function unit 101-2.

[0053] The conversion of input data will now be described in detail. When the output data width of function unit 101-1 and the input data width of function unit 101-2 are different, it is necessary to adjust the output data width of function unit 101-1 to the input data width of function unit 101-2. In this case, as a specific example of conversion unit 105 in Fig. 2, a data width conversion unit 1051 made up of, for example, a FIFO buffer is provided, which converts the data width so that the output data width of function unit 101-1 matches the input data width of function unit 101-2. Furthermore, as a specific example of conversion determination unit 104 in Fig. 2, a data width conversion determination unit 1041 is provided.

[0054] When the clock frequency of the output data of function unit 101-1 and the clock frequency of the input data of function unit 101-2 are the same and the output data width of function unit 101-1 is larger than the input data width of function unit 101-2, data width conversion is performed by providing a FIFO buffer that absorbs the speed difference in order to divide the data output by function unit 101-1 in one clock cycle into multiple clock cycles and input it to function unit 101-2.

[0055] Furthermore, if the clock frequency of the output data of function unit 101-1 and the clock frequency of the input data of function unit 101-2 are the same but the output data width of function unit 101-1 is smaller than the input data width of function unit 101-2, a FIFO buffer is provided to absorb the speed difference and convert the data width so that the data output by function unit 101-1 over multiple clock cycles is aggregated into one clock cycle and input to function unit 101-2. The depth of the FIFO buffer is adjusted based on the input / output conditions of function units 101-1 and 101-2 to prevent data overflow.

[0056] As described above, when the function units 101-1 and 101-2 to be used are determined, the specifications of the input / output interfaces of the function units 101-1 and 101-2 are determined. An input / output interface conversion unit 103b is provided to connect the function units 101-1 and 101-2 based on the specifications of the input / output interfaces.

[0057] [Operation of the second embodiment] Next, the operation of the data flow control device 100b of this embodiment will be described with reference to Fig. 6. In a data flow computing system, when two or more function units have different input / output interfaces, the data flow control device 100b of this embodiment converts input / output data to establish a connection that allows data to be exchanged between the function units without interface inconsistencies.

[0058] First, the function unit 101-1 performs data processing such as arithmetic processing, and then outputs the data resulting from the processing.

[0059] Next, the input / output interface conversion unit 103b converts input / output data between the function units 101-1 and 101-2 so as to establish a connection that allows data to be exchanged between the function units 101-1 and 101-2, which have different input / output interfaces, without interface inconsistency.

[0060] Specifically, the data width conversion determination unit 1041 of the input / output interface conversion unit 103b acquires input / output interface information of the function units 101-1 and 101-2 (step S200 in FIG. 6). As in the first embodiment, the data width conversion determination unit 1041 may acquire the input / output interface information from the function units 101-1 and 101-2, or from an external management device.

[0061] Next, the data width conversion determination unit 1041 determines whether or not to convert the output data of the function unit 101-1 based on the acquired input / output interface information (step S201 in FIG. 6). In this embodiment, a case will be described in which the data widths defined by the data formats of the input / output interface information differ between the function unit 101-1 and the function unit 101-2.

[0062] If the output data width of function unit 101-1 and the input data width of function unit 101-2 are not equal (YES in step S201), data width conversion determination unit 1041 determines to convert the output data of function unit 101-1 (step S202 in FIG. 6). On the other hand, if the output data width of function unit 101-1 and the input data width of function unit 101-2 are equal (NO in step S201), data width conversion determination unit 1041 determines not to convert the output data of function unit 101-1 (step S203 in FIG. 6).

[0063] Data width conversion unit 1051, which is made up of a FIFO buffer, converts the data width so that the output data width of function unit 101-1 matches the input data width of function unit 101-2 (step S204 in FIG. 6). Note that, since data width conversion unit 1051 can accommodate various data widths based on input / output interface information, it is desirable to include an internal controller that controls writing to and reading from the FIFO buffer.

[0064] Based on the determination result of data width conversion determination unit 1041, output selection unit 106b selectively outputs either the output data whose data width has been converted by data width conversion unit 1051 or the unconverted output data output from function unit 101-1 (step S205 in FIG. 6). If data width conversion determination unit 1041 determines that the output data of function unit 101-1 should be converted, output selection unit 106b outputs the output data whose data width has been converted by data width conversion unit 1051 to function unit 101-2. On the other hand, if data width conversion determination unit 1041 determines that the output data of function unit 101-1 should not be converted, output selection unit 106b outputs the unconverted output data output from function unit 101-1 to function unit 101-2.

[0065] The function unit 101-2 performs data processing such as arithmetic operations on the data input from the input / output interface conversion unit 103b.

[0066] [Effects of the second embodiment] As described above, the input / output interface conversion unit 103b of this embodiment converts input / output data between the function units 101-1 and 101-2 so that data can be exchanged between the function units 101-1 and 101-2 without interface mismatch. This makes it possible to connect the function units 101-1 and 101-2 even if the input / output interfaces of the function units 101-1 and 101-2 are different.

[0067] In this embodiment, a function unit for any input / output interface can be designed and used, and existing function units can also be reused. Furthermore, in this embodiment, function units with different input / output interfaces can be connected without changing the input / output interfaces, allowing for the reuse of function units. Furthermore, in this embodiment, verification of function units accompanying changes in input / output interfaces is not required, reducing verification costs. Furthermore, in this embodiment, function units can be connected without using memory, eliminating the constraints on processing speed due to the memory data width and data write and read speeds, enabling low latency and high throughput.

[0068] [Configuration of the third embodiment] Next, a third embodiment of the present invention will be described. Fig. 7 is a block diagram showing the configuration of a data flow control device according to this embodiment. A data flow control device 100c according to this embodiment is provided with function units 101-1 and 101-2, which are arithmetic devices that perform data processing such as arithmetic operations in a data flow computing system, and an input / output interface conversion unit 103c that converts input / output data between the function units 101-1 and 101-2 so as to establish a connection that enables data exchange without interface inconsistency between the function units 101-1 and 101-2, which have different input / output interfaces.

[0069] The input / output interface conversion unit 103c includes a conversion determination unit (104 in FIG. 2) that determines whether or not to convert the output data of the function unit 101-1, a conversion unit (105 in FIG. 2) that converts the output data of the function unit 101-1 so that it can be input to the function unit 101-2, and an output selection unit 106c that selectively outputs either the converted output data or the unconverted output data output from the function unit 101-1 to the function unit 101-2.

[0070] The conversion of input data will now be described in detail. When the format of the output data of function unit 101-1 differs from the format of the input data of function unit 101-2, it is necessary to adjust the format of the output data of function unit 101-1 so that it matches the format of the input data of function unit 101-2. In this case, as a specific example of conversion unit 105 in Fig. 2, an input / output information conversion unit 1052 is provided that converts the format of the output data of function unit 101-1 so that it matches the format of the input data of function unit 101-2. Furthermore, as a specific example of conversion determination unit 104 in Fig. 2, an input / output information conversion determination unit 1042 is provided.

[0071] If not all of the information in the output data of function unit 101-1 is used as input data for function unit 101-2, input / output information conversion unit 1052 extracts (parses) the parts of the output data of function unit 101-1 that are necessary as input data for function unit 101-2, and converts them to fit the format of the input data for function unit 101-2.

[0072] In addition, if it is necessary to rearrange the order of the output data of the function unit 101-1, for example, to rearrange the upper 64 bits and the lower 64 bits of the 128-bit wide data output from the function unit 101-1, the input / output information conversion unit 1052 rearranges the data and converts it to fit the format of the input data of the function unit 101-2.

[0073] As described above, when the function units 101-1 and 101-2 to be used are determined, the specifications of the input / output interfaces of the function units 101-1 and 101-2 are determined. An input / output interface conversion unit 103c is provided to connect the function units 101-1 and 101-2 based on the specifications of the input / output interfaces.

[0074] [Operation of the third embodiment] Next, the operation of the data flow control device 100c of this embodiment will be described with reference to Fig. 8. In a data flow computing system, when two or more function units have different input / output interfaces, the data flow control device 100c of this embodiment converts input / output data to establish a connection that allows data to be exchanged between the function units without interface inconsistencies.

[0075] First, the function unit 101-1 performs data processing such as arithmetic processing, and then outputs the data resulting from the processing.

[0076] Next, the input / output interface conversion unit 103c converts input / output data between the function units 101-1 and 101-2 so as to establish a connection that allows data to be exchanged between the function units 101-1 and 101-2, which have different input / output interfaces, without interface inconsistency.

[0077] Specifically, the input / output information conversion determination unit 1042 of the input / output interface conversion unit 103c acquires the input / output interface information of the function units 101-1 and 101-2 (step S300 in FIG. 8). As in the first embodiment, the input / output information conversion determination unit 1042 may acquire the input / output interface information from the function units 101-1 and 101-2, or from an external management device.

[0078] Next, the input / output information conversion determination unit 1042 determines whether or not to convert the output data of the function unit 101-1 based on the acquired input / output interface information (step S301 in FIG. 8). In this embodiment, a case will be described in which the data formats handled by the function units 101-1 and 101-2 are different.

[0079] If the format of the output data of the function unit 101-1 and the format of the input data of the function unit 101-2 are not the same (YES in step S301), the input / output information conversion determination unit 1042 determines to convert the output data of the function unit 101-1 (step S302 in FIG. 8). On the other hand, if the format of the output data of the function unit 101-1 and the format of the input data of the function unit 101-2 are the same (NO in step S301), the input / output information conversion determination unit 1042 determines not to convert the output data of the function unit 101-1 (step S303 in FIG. 8).

[0080] The input / output information conversion unit 1052 converts the format of the output data of the function unit 101-1 so that the output data conforms to the format of the input data of the function unit 101-2 (step S304 in FIG. 8).

[0081] Among the differences in data formats, the case where the output data width of function unit 101-1 and the input data width of function unit 101-2 are different is handled in the second embodiment. This embodiment handles, for example, the case where not all of the output data of function unit 101-1 is used as input data for function unit 101-2, or the case where the order of the output data of function unit 101-1 and the input data of function unit 101-1 is different. However, input / output information conversion unit 1052 may be configured to handle the case where the output data width of function unit 101-1 and the input data width of function unit 101-2 are different.

[0082] Furthermore, if there is insufficient data in the output data of the function unit 101-1 as input data for the function unit 101-2, the input / output information conversion unit 1052 can set a default value specified in the format of the input data for the function unit 101-2.

[0083] Based on the determination result of the input / output information conversion determination unit 1042, the output selection unit 106c selectively outputs either the output data whose format has been converted by the input / output information conversion unit 1052 or the unconverted output data output from the function unit 101-1 (step S305 in FIG. 8). If the input / output information conversion determination unit 1042 determines that the output data of the function unit 101-1 should be converted, the output selection unit 106c outputs the output data whose format has been converted by the input / output information conversion unit 1052 to the function unit 101-2. On the other hand, if the input / output information conversion determination unit 1042 determines that the output data of the function unit 101-1 should not be converted, the output selection unit 106c outputs the unconverted output data output from the function unit 101-1 to the function unit 101-2.

[0084] The function unit 101-2 performs data processing such as arithmetic operations on the data input from the input / output interface conversion unit 103c.

[0085] [Effects of the third embodiment] As described above, the input / output interface conversion unit 103c of this embodiment converts input / output data between the function units 101-1 and 101-2 so that data can be exchanged between the function units 101-1 and 101-2 without interface mismatch. This makes it possible to connect the function units 101-1 and 101-2 even if the input / output interfaces of the function units 101-1 and 101-2 are different.

[0086] In this embodiment, a function unit for any input / output interface can be designed and used, and existing function units can also be reused. Furthermore, in this embodiment, function units with different input / output interfaces can be connected without changing the input / output interfaces, allowing for the reuse of function units. Furthermore, in this embodiment, verification of function units accompanying changes in input / output interfaces is not required, reducing verification costs. Furthermore, in this embodiment, function units can be connected without using memory, eliminating the constraints on processing speed due to the memory data width and data write and read speeds, enabling low latency and high throughput.

[0087] [Configuration of the Fourth Embodiment] Next, a fourth embodiment of the present invention will be described. Fig. 9 is a block diagram showing the basic configuration of a data flow control device according to this embodiment, and Fig. 10 is a block diagram showing a specific example of the data flow control device according to this embodiment.

[0088] The data flow control device 100d of this embodiment is equipped with function units 101-1 and 101-2, which are arithmetic devices that perform data processing such as arithmetic operations in a data flow computing system, and an input / output interface conversion unit 103d that converts input / output data between the function units 101-1 and 101-2 so that the function units 101-1 and 101-2 have different input / output interfaces and can exchange data without interface inconsistencies.

[0089] The input / output interface conversion unit 103d includes conversion determination units 104d-1 and 104d-2 that determine whether or not to convert the output data of the function unit 101-1, conversion units 105d-1 and 105d-2 that convert the output data of the function unit 101-1 so that it can be input to the function unit 101-2, and an output selection unit 106d that selectively outputs either the converted output data or the unconverted output data output from the function unit 101-1 to the function unit 101-2.

[0090] The difference from the first to third embodiments is that, as shown in Figures 9 and 10, input / output interface conversion unit 103d has multiple functions for converting output data from function unit 101-1 so that it can be input to function unit 101-2.

[0091] The conversion of input data will now be described in detail. When the format of the output data of function unit 101-1 differs from the format of the input data of function unit 101-2, it is necessary to adjust the format of the output data of function unit 101-1 so that it matches the format of the input data of function unit 101-2. In this case, as a specific example of conversion unit 105d-1 in Fig. 9, an input / output information conversion unit 1052 is provided that converts the format of the output data of function unit 101-1 so that it matches the format of the input data of function unit 101-2. Furthermore, as a specific example of conversion determination unit 104d-1 in Fig. 9, an input / output information conversion determination unit 1042 is provided.

[0092] Furthermore, when the clock frequencies of the data handled by the function units 101-1 and 101-2 are different, clock resynchronization is required to output data synchronized with the clock of the function unit 101-2, synchronizing input data synchronized with the clock of the function unit 101-1. In this case, as a specific example of the conversion unit 105d-2 in Fig. 9, a clock resynchronizer 1050 made up of a FIFO buffer that absorbs the difference in speed between the function units 101-1 and 101-2 is provided. Furthermore, as a specific example of the conversion determination unit 104d-2 in Fig. 9, a clock frequency resynchronizer determination unit 1040 is provided.

[0093] As described above, the difference from the first to third embodiments is that it has both a function to adjust the difference in data format between function units 101-1 and 101-2 and a function to absorb the difference in clock frequency between function units 101-1 and 101-2.

[0094] If not all of the information in the output data of function unit 101-1 is used as input data for function unit 101-2, input / output information conversion unit 1052 extracts (parses) the parts of the output data of function unit 101-1 that are necessary as input data for function unit 101-2, and converts them to fit the format of the input data for function unit 101-2.

[0095] In addition, if it is necessary to rearrange the order of the output data of the function unit 101-1, for example, to rearrange the upper 64 bits and the lower 64 bits of the 128-bit wide data output from the function unit 101-1, the input / output information conversion unit 1052 rearranges the data and converts it to fit the format of the input data of the function unit 101-2.

[0096] On the other hand, if the output data width of function unit 101-1 and the input data width of function unit 101-2 are the same and the clock frequency of the output data of function unit 101-1 is higher than the clock frequency of the input data of function unit 101-2, the output speed of data from function unit 101-1 may be faster than the input data speed specified by function unit 101-2. As a result, there is a possibility that data may overflow before being input to function unit 101-2.

[0097] To prevent data overflow, for example, a FIFO buffer with a predetermined depth is used, and the input clock frequency to the FIFO buffer and the output clock frequency from the FIFO buffer are changed to convert the clock frequency of the output data of function unit 101-1 to the clock frequency of the input data of function unit 101-2. The depth of the FIFO buffer is adjusted based on the input / output conditions of function units 101-1 and 101-2 so that data overflow does not occur.

[0098] In addition, if the clock frequency of the output data of function unit 101-1 is lower than the clock frequency of the input data of function unit 101-2, the speed of the data output from function unit 101-1 will be slower than the speed of the input data specified in function unit 101-2, so it is not necessarily necessary to change the clock frequency.

[0099] Furthermore, if the input data width of function unit 101-2 is larger than the output data width of function unit 101-1, even if the clock frequency of the output data of function unit 101-1 is higher than the clock frequency of the input data of function unit 101-2, the speed of the data output from function unit 101-1 may be slower than the speed of the input data specified by function unit 101-2. In this case, it is not necessarily necessary to change the clock frequency.

[0100] On the other hand, even if the input data width of function unit 101-2 is larger than the output data width of function unit 101-1, if the clock frequency of the output data of function unit 101-1 is high and there is a large difference between the clock frequency of the input data of function unit 101-2, the output speed of the data of function unit 101-1 may be faster than the input data speed specified by function unit 101-2. As a result, there is a possibility that the data may overflow before being input to function unit 101-2.

[0101] To prevent data overflow, for example, a FIFO buffer with a predetermined depth is used, and the input clock frequency to the FIFO buffer and the output clock frequency from the FIFO buffer are changed to convert the clock frequency of the output data of function unit 101-1 to the clock frequency of the input data of function unit 101-2. The depth of the FIFO buffer is adjusted based on the input / output conditions of function units 101-1 and 101-2 so that data overflow does not occur.

[0102] In addition, if the clock frequency of the output data of function unit 101-1 is lower than the clock frequency of the input data of function unit 101-2, the speed of the data output from function unit 101-1 will be slower than the speed of the input data specified in function unit 101-2, so it is not necessarily necessary to change the clock frequency.

[0103] Furthermore, even if the clock frequency of the output data of function unit 101-1 is lower than the clock frequency of the input data of function unit 101-2, if the input data width of function unit 101-2 is smaller than the output data width of function unit 101-1 and the difference between the clock frequency of the input data of function unit 101-2 and the clock frequency of the output data of function unit 101-1 is not sufficient, the output speed of data from function unit 101-1 may be faster than the input data speed specified by function unit 101-2. This may cause data overflow before it is input to function unit 101-2.

[0104] To prevent data overflow, for example, a FIFO buffer with a predetermined depth is used, and the input clock frequency to the FIFO buffer and the output clock frequency from the FIFO buffer are changed to convert the clock frequency of the output data of function unit 101-1 to the clock frequency of the input data of function unit 101-2. The depth of the FIFO buffer is adjusted based on the input / output conditions of function units 101-1 and 101-2 so that data overflow does not occur.

[0105] In addition, if the clock frequency of the output data of function unit 101-1 is sufficiently lower than the clock frequency of the input data of function unit 101-2, the speed of the data output from function unit 101-1 will be slower than the speed of the input data specified in function unit 101-2, so it is not necessarily necessary to change the clock frequency.

[0106] As described above, when the function units 101-1 and 101-2 to be used are determined, the specifications of the input / output interfaces of the function units 101-1 and 101-2 are determined. An input / output interface conversion unit 103d is provided to connect the function units 101-1 and 101-2 based on the specifications of the input / output interfaces.

[0107] [Operation of the Fourth Example] Next, the operation of the data flow control device 100d of this embodiment will be described with reference to Fig. 11. In a data flow computing system, when two or more function units have different input / output interfaces, the data flow control device 100d of this embodiment converts input / output data to establish a connection that allows data to be exchanged between the function units without interface inconsistencies.

[0108] First, the function unit 101-1 performs data processing such as arithmetic processing, and then outputs the data resulting from the processing.

[0109] Next, the input / output interface conversion unit 103d converts input / output data between the function units 101-1 and 101-2 so as to establish a connection that allows data to be exchanged between the function units 101-1 and 101-2, which have different input / output interfaces, without interface inconsistency.

[0110] Specifically, the input / output information conversion determination unit 1042 and the clock frequency resynchronization determination unit 1040 of the input / output interface conversion unit 103d acquire the input / output interface information of the function units 101-1 and 101-2 (step S400 in FIG. 11). As in the first embodiment, the input / output information conversion determination unit 1042 and the clock frequency resynchronization determination unit 1040 may acquire the input / output interface information from the function units 101-1 and 101-2, or from an external management device.

[0111] The input / output information conversion determination unit 1042 determines whether or not to convert the output data of the function unit 101-1 based on the acquired input / output interface information (step S401 in FIG. 11). If the format of the output data of the function unit 101-1 and the format of the input data of the function unit 101-2 are not the same (YES in step S401), the input / output information conversion determination unit 1042 determines to convert the output data of the function unit 101-1 (step S402 in FIG. 11). On the other hand, if the format of the output data of the function unit 101-1 and the format of the input data of the function unit 101-2 are the same (NO in step S401), the input / output information conversion determination unit 1042 determines not to convert the output data of the function unit 101-1 (step S403 in FIG. 11).

[0112] As in the third embodiment, the input / output information conversion unit 1052 converts the format of the output data of the function unit 101-1 so that it conforms to the format of the input data of the function unit 101-2 (step S404 in FIG. 11). Note that the input / output information conversion unit 1052 may convert the data width so that the output data width of the function unit 101-1 conforms to the input data width of the function unit 101-2.

[0113] Furthermore, if there is insufficient data in the output data of the function unit 101-1 as input data for the function unit 101-2, the input / output information conversion unit 1052 can set a default value specified in the format of the input data for the function unit 101-2.

[0114] Next, the clock frequency transfer determination unit 1040 determines whether or not to convert the output data of the function unit 101-1 based on the acquired input / output interface information (step S405 in FIG. 11). If the clock frequency of the output data of the function unit 101-1 is higher than the clock frequency of the input data of the function unit 101-2 (YES in step S405), the clock frequency transfer determination unit 1040 determines to convert the output data of the function unit 101-1 (step S406 in FIG. 11). On the other hand, if the clock frequency of the output data of the function unit 101-1 is equal to or lower than the clock frequency of the input data of the function unit 101-2 (NO in step S405), the clock frequency transfer determination unit 1040 determines not to convert the output data of the function unit 101-1 (step S407 in FIG. 11).

[0115] The clock resynchronizer 1050 performs clock resynchronization, converting the clock frequency of the output data of the function unit 101-1 into the clock frequency of the input data of the function unit 101-2 (step S408 in FIG. 11).

[0116] Based on the determination results of the input / output information conversion determination unit 1042 and the clock frequency transfer determination unit 1040, the output selection unit 106d selectively outputs one of output data whose format has only been converted by the input / output information conversion unit 1052, output data whose clock frequency has only been converted by the clock transfer unit 1050, output data whose format has been converted by the input / output information conversion unit 1052 and whose clock frequency has been converted by the clock transfer unit 1050, and unconverted output data output from the function unit 101-1 (step S409 in Figure 11).

[0117] If the input / output information conversion determination unit 1042 determines that the output data of the function unit 101-1 should be converted and the clock frequency resynchronization determination unit 1040 determines that the output data of the function unit 101-1 should not be converted, the output selection unit 106d outputs the output data, whose format has been converted by the input / output information conversion unit 1052 and whose clock frequency has not been converted, to the function unit 101-2. Also, if the input / output information conversion determination unit 1042 determines that the output data of the function unit 101-1 should not be converted and the clock frequency resynchronization determination unit 1040 determines that the output data of the function unit 101-1 should be converted, the output selection unit 106d outputs the output data, whose format has been converted by the clock resynchronization unit 1050 and whose format has not been converted, to the function unit 101-2.

[0118] Furthermore, when the input / output information conversion determination unit 1042 and the clock frequency resynchronization determination unit 1040 both determine that the output data of the function unit 101-1 should be converted, the output selection unit 106d outputs to the function unit 101-2 the output data whose format has been converted by the input / output information conversion unit 1052 and whose clock frequency has been converted by the clock resynchronization unit 1050. When the output selection unit 106d determines that the input / output information conversion determination unit 1042 and the clock frequency resynchronization determination unit 1040 both determine that the output data of the function unit 101-1 should not be converted, the output selection unit 106d outputs to the function unit 101-2 the unconverted output data output from the function unit 101-1.

[0119] The function unit 101-2 performs data processing such as arithmetic operations on the data input from the input / output interface conversion unit 103d.

[0120] [Effects of the Fourth Embodiment] As described above, the input / output interface conversion unit 103d of this embodiment converts input / output data between the function units 101-1 and 101-2 so that data can be exchanged between the function units 101-1 and 101-2 without interface mismatch. This makes it possible to connect the function units 101-1 and 101-2 even if the input / output interfaces of the function units 101-1 and 101-2 are different.

[0121] In this embodiment, a function unit for any input / output interface can be designed and used, and existing function units can also be reused. Furthermore, in this embodiment, function units with different input / output interfaces can be connected without changing the input / output interfaces, allowing for the reuse of function units. Furthermore, in this embodiment, verification of function units accompanying changes in input / output interfaces is not required, reducing verification costs. Furthermore, in this embodiment, function units can be connected without using memory, eliminating the constraints on processing speed due to the memory data width and data write and read speeds, enabling low latency and high throughput.

[0122] [Configuration of the fifth embodiment] Next, a fifth embodiment of the present invention will be described. Fig. 12 is a block diagram showing the basic configuration of a data flow control device according to this embodiment, and Figs. 13 to 16 are block diagrams showing specific examples of the data flow control device according to this embodiment.

[0123] The data flow control device 100e of this embodiment is a data flow type computing system that includes function units 101-1 to 101-3, which are three or more arithmetic devices that perform data processing such as arithmetic operations, and an input / output interface conversion unit 103e that converts input / output data between the function units 101-1, 101-3 and the function unit 101-2, so as to enable a connection that enables data exchange without interface inconsistency between the function units 101-1, 101-3 and the function unit 101-2, which have different input / output interfaces.

[0124] The input / output interface conversion unit 103e includes conversion determination units 104e-1 and 104e-2 that determine whether or not to convert the output data of the function units 101-1 and 101-3, conversion units 105e-1 and 105e-2 that convert the output data of the function units 101-1 and 101-3 so that it can be input to the function unit 101-2, and an output selection unit 106e that selectively outputs either the converted output data or the unconverted output data output from the function units 101-1 and 101-3 to the function unit 101-2. The conversion determination units 104e-1 and 104e-2 and the conversion units 105e-1 and 105e-2 are provided for the preceding function units 101-1 and 101-3, respectively.

[0125] The difference from the first to fourth embodiments is that, as shown in Figures 12 to 16, the input / output interface conversion unit 103e has the function of adjusting the output data of two or more function units 101-1 and 101-3 independently as input data for the function unit 101-2.

[0126] For example, if the clock frequencies of the data handled by the function units 101-1 and 101-3 and the function unit 101-2 are different, clock resynchronization is required to output data synchronized with the clock of the function unit 101-2, synchronizing input data synchronized with the clock of the function unit 101-1 and 101-3. In this case, as shown in Figure 13, clock resynchronizers 1050-1 and 1050-2, each consisting of a FIFO buffer that absorbs the difference in speed between the function units 101-1 and 101-3 and the function unit 101-2, are provided as a specific example of the conversion units 105e-1 and 105e-2 in Figure 12. Furthermore, clock frequency resynchronization determiners 1040-1 and 1040-2 are provided as a specific example of the conversion determination units 104e-1 and 104e-2 in Figure 12.

[0127] If the output data width of function units 101-1 and 101-3 is the same as the input data width of function unit 101-2 and the clock frequency of the output data of function units 101-1 and 101-3 is higher than the clock frequency of the input data of function unit 101-2, the output speed of data from function units 101-1 and 101-3 may be faster than the input data speed specified by function unit 101-2. As a result, there is a possibility that data may overflow before being input to function unit 101-2.

[0128] To prevent data overflow, for example, a FIFO buffer with a predetermined depth is used, and the input clock frequency to the FIFO buffer and the output clock frequency from the FIFO buffer are changed to convert the clock frequency of the output data of function units 101-1 and 101-3 to the clock frequency of the input data of function unit 101-2. The depth of the FIFO buffer is adjusted based on the input / output conditions of function units 101-1 to 101-3 so that data overflow does not occur.

[0129] In addition, if the clock frequency of the output data of function units 101-1 and 101-3 is lower than the clock frequency of the input data of function unit 101-2, the speed of the data output from function units 101-1 and 101-3 will be slower than the speed of the input data specified in function unit 101-2, so it is not necessarily necessary to change the clock frequency.

[0130] Furthermore, if the input data width of function unit 101-2 is larger than the output data width of function units 101-1 and 101-3, even if the clock frequency of the output data of function units 101-1 and 101-3 is higher than the clock frequency of the input data of function unit 101-2, the speed of the data output from function unit 101-1 may be slower than the speed of the input data specified by function unit 101-2. In this case, it is not necessarily necessary to change the clock frequency.

[0131] On the other hand, even if the input data width of function unit 101-2 is larger than the output data width of function units 101-1 and 101-3, if the clock frequency of the output data of function units 101-1 and 101-3 is high and there is a large difference between this and the clock frequency of the input data of function unit 101-2, the output speed of data from function units 101-1 and 101-3 may be faster than the input data speed specified by function unit 101-2. This may cause data overflow before it is input to function unit 101-2.

[0132] To prevent data overflow, for example, a FIFO buffer with a predetermined depth is used, and the input clock frequency to the FIFO buffer and the output clock frequency from the FIFO buffer are changed to convert the clock frequency of the output data of function units 101-1 and 101-3 to the clock frequency of the input data of function unit 101-2. The depth of the FIFO buffer is adjusted based on the input / output conditions of function units 101-1 to 101-3 so that data overflow does not occur.

[0133] In addition, if the clock frequency of the output data of function units 101-1 and 101-3 is lower than the clock frequency of the input data of function unit 101-2, the speed of the data output from function unit 101-1 will be slower than the speed of the input data specified in function unit 101-2, so it is not necessarily necessary to change the clock frequency.

[0134] Furthermore, even if the clock frequency of the output data of function units 101-1 and 101-3 is lower than the clock frequency of the input data of function unit 101-2, if the input data width of function unit 101-2 is smaller than the output data width of function units 101-1 and 101-3 and the difference between the clock frequency of the input data of function unit 101-2 and the clock frequency of the output data of function units 101-1 and 101-3 is not sufficient, the output speed of data from function units 101-1 and 101-3 may be faster than the input data speed specified by function unit 101-2. This may cause data overflow before it is input to function unit 101-2.

[0135] To prevent data overflow, for example, a FIFO buffer with a predetermined depth is used, and the input clock frequency to the FIFO buffer and the output clock frequency from the FIFO buffer are changed to convert the clock frequency of the output data of function units 101-1 and 101-3 to the clock frequency of the input data of function unit 101-2. The depth of the FIFO buffer is adjusted based on the input / output conditions of function units 101-1 to 101-3 so that data overflow does not occur.

[0136] In addition, if the clock frequency of the output data of function units 101-1 and 101-3 is sufficiently lower than the clock frequency of the input data of function unit 101-2, the speed of the data output from function unit 101-1 will be slower than the speed of the input data specified in function unit 101-2, so it is not necessarily necessary to change the clock frequency.

[0137] Furthermore, when the output data width of function units 101-1 and 101-3 differs from the input data width of function unit 101-2, the output data width of function units 101-1 and 101-3 must be adjusted to match the input data width of function unit 101-2. In this case, as shown in Figure 14, as a specific example of conversion units 105e-1 and 105e-2 in Figure 12, data width conversion units 1051-1 and 1051-2, each consisting of, for example, a FIFO buffer, are provided to convert the data width so that the output data width of function units 101-1 and 101-3 matches the input data width of function unit 101-2. Furthermore, as a specific example of conversion determination units 104e-1 and 104e-2 in Figure 12, data width conversion determination units 1041-1 and 1041-2 are provided.

[0138] When the clock frequency of the output data of function units 101-1 and 101-3 is the same as the clock frequency of the input data of function unit 101-2, and the output data width of function units 101-1 and 101-3 is larger than the input data width of function unit 101-2, data width conversion is performed by providing a FIFO buffer that absorbs the speed difference, so that the data output in one clock cycle by function units 101-1 and 101-3 is divided into multiple clock cycles and input to function unit 101-2.

[0139] Furthermore, when the clock frequency of the output data of function units 101-1 and 101-3 is the same as the clock frequency of the input data of function unit 101-2, and the output data width of function units 101-1 and 101-3 is smaller than the input data width of function unit 101-2, a FIFO buffer is provided to absorb the speed difference and convert the data width so that the data output over multiple clock cycles by function units 101-1 and 101-3 is aggregated into one clock cycle and input to function unit 101-2. The depth of the FIFO buffer is adjusted based on the input / output conditions of function units 101-1 to 101-3 to prevent data overflow.

[0140] Furthermore, when the format of the output data of function units 101-1 and 101-3 differs from the format of the input data of function unit 101-2, it is necessary to adjust the format of the output data of function units 101-1 and 101-3 so that it matches the format of the input data of function unit 101-2. In this case, as shown in Fig. 15, as a specific example of conversion units 105e-1 and 105e-2 in Fig. 12, input / output information conversion units 1052-1 and 1052-2 are provided that convert the format of the output data of function units 101-1 and 101-3 so that it matches the format of the input data of function unit 101-2. Furthermore, as a specific example of conversion determination units 104e-1 and 104e-2 in Fig. 12, input / output information conversion determination units 1042-1 and 1042-2 are provided.

[0141] If not all of the information in the output data of function units 101-1 and 101-3 is used as input data for function unit 101-2, input / output information conversion units 1052-1 and 1052-2 extract (parse) the parts of the output data of function units 101-1 and 101-3 that are necessary as input data for function unit 101-2, and convert them to fit the format of the input data for function unit 101-2.

[0142] Furthermore, when it is necessary to rearrange the order of the output data of the function units 101-1 and 101-3, for example, to rearrange the upper 64 bits and the lower 64 bits of the 128-bit wide data output from the function units 101-1 and 101-3, the input / output information conversion units 1052-1 and 1052-2 rearrange the data and convert it to conform to the format of the input data of the function unit 101-2.

[0143] Furthermore, when the clock frequencies of the data handled by the function units 101-1 and 101-2 are different, clock resynchronization is required to output data synchronized with the clock of the function unit 101-2, synchronizing input data synchronized with the clock of the function unit 101-1. In this case, as shown in Figure 16, a clock resynchronizer 1050 made up of a FIFO buffer that absorbs the difference in speed between the function units 101-1 and 101-2 is provided as a specific example of the conversion unit 105e-1 in Figure 12. Furthermore, a clock frequency resynchronizer determination unit 1040 is provided as a specific example of the conversion determination unit 104e-1 in Figure 12.

[0144] Furthermore, if the format of the output data of function unit 101-3 differs from the format of the input data of function unit 101-2, it is necessary to adjust the format of the output data of function unit 101-3 so that it matches the format of the input data of function unit 101-2. In this case, as shown in Fig. 16, as a specific example of conversion unit 105e-2 in Fig. 12, an input / output information conversion unit 1052 is provided that converts the format of the output data of function unit 101-3 so that it matches the format of the input data of function unit 101-2. Also, as a specific example of conversion determination unit 104e-2 in Fig. 12, an input / output information conversion determination unit 1042 is provided.

[0145] If not all of the information in the output data of function unit 101-3 is used as input data for function unit 101-2, input / output information conversion unit 1052 extracts (parses) the parts of the output data of function unit 101-3 that are necessary as input data for function unit 101-2, and converts them to conform to the format of the input data for function unit 101-2.

[0146] In addition, if it is necessary to rearrange the order of the output data of function unit 101-3, for example, to rearrange the upper 64 bits and the lower 64 bits of the 128-bit wide data output from function unit 101-3, input / output information conversion unit 1052 rearranges the data and converts it to fit the format of the input data of function unit 101-2.

[0147] Furthermore, if the output data width of function unit 101-1 and the input data width of function unit 101-2 are the same and the clock frequency of the output data of function unit 101-1 is higher than the clock frequency of the input data of function unit 101-2, the output speed of data from function unit 101-1 may be faster than the input data speed specified by function unit 101-2, which may cause data overflow before input to function unit 101-2.

[0148] To prevent data overflow, for example, a FIFO buffer with a predetermined depth is used, and the input clock frequency to the FIFO buffer and the output clock frequency from the FIFO buffer are changed to convert the clock frequency of the output data of function unit 101-1 to the clock frequency of the input data of function unit 101-2. The depth of the FIFO buffer is adjusted based on the input / output conditions of function units 101-1 and 101-2 so that data overflow does not occur.

[0149] In addition, if the clock frequency of the output data of function unit 101-1 is lower than the clock frequency of the input data of function unit 101-2, the speed of the data output from function unit 101-1 will be slower than the speed of the input data specified in function unit 101-2, so it is not necessarily necessary to change the clock frequency.

[0150] Furthermore, if the input data width of function unit 101-2 is larger than the output data width of function unit 101-1, even if the clock frequency of the output data of function unit 101-1 is higher than the clock frequency of the input data of function unit 101-2, the speed of the data output from function unit 101-1 may be slower than the speed of the input data specified by function unit 101-2. In this case, it is not necessarily necessary to change the clock frequency.

[0151] On the other hand, even if the input data width of function unit 101-2 is larger than the output data width of function unit 101-1, if the clock frequency of the output data of function unit 101-1 is high and there is a large difference between the clock frequency of the input data of function unit 101-2, the output speed of the data of function unit 101-1 may be faster than the input data speed specified by function unit 101-2. As a result, there is a possibility that the data may overflow before being input to function unit 101-2.

[0152] To prevent data overflow, for example, a FIFO buffer with a predetermined depth is used, and the input clock frequency to the FIFO buffer and the output clock frequency from the FIFO buffer are changed to convert the clock frequency of the output data of function unit 101-1 to the clock frequency of the input data of function unit 101-2. The depth of the FIFO buffer is adjusted based on the input / output conditions of function units 101-1 and 101-2 so that data overflow does not occur.

[0153] In addition, if the clock frequency of the output data of function unit 101-1 is lower than the clock frequency of the input data of function unit 101-2, the speed of the data output from function unit 101-1 will be slower than the speed of the input data specified in function unit 101-2, so it is not necessarily necessary to change the clock frequency.

[0154] Furthermore, even if the clock frequency of the output data of function unit 101-1 is lower than the clock frequency of the input data of function unit 101-2, if the input data width of function unit 101-2 is smaller than the output data width of function unit 101-1 and the difference between the clock frequency of the input data of function unit 101-2 and the clock frequency of the output data of function unit 101-1 is not sufficient, the output speed of data from function unit 101-1 may be faster than the input data speed specified by function unit 101-2. This may cause data overflow before it is input to function unit 101-2.

[0155] To prevent data overflow, for example, a FIFO buffer with a predetermined depth is used, and the input clock frequency to the FIFO buffer and the output clock frequency from the FIFO buffer are changed to convert the clock frequency of the output data of function unit 101-1 to the clock frequency of the input data of function unit 101-2. The depth of the FIFO buffer is adjusted based on the input / output conditions of function units 101-1 and 101-2 so that data overflow does not occur.

[0156] In addition, if the clock frequency of the output data of function unit 101-1 is sufficiently lower than the clock frequency of the input data of function unit 101-2, the speed of the data output from function unit 101-1 will be slower than the speed of the input data specified in function unit 101-2, so it is not necessarily necessary to change the clock frequency.

[0157] Furthermore, as in this embodiment, when output data from a plurality of function units 101-1 and 101-3 is used as input data for a single function unit 101-2, it may be necessary to align the input timing. When it is necessary to align the timing in this way, the input / output interface conversion unit 103e may be provided with a function to align the timing in addition to the function to convert the output data from the plurality of function units 101-1 and 101-3. Specifically, an output buffer may be provided in the output selection unit 106e to align the output timing from the output selection unit 106e.

[0158] As described above, when the function units 101-1 to 101-3 to be used are determined, the specifications of the input / output interfaces of the function units 101-1 to 101-3 are determined. Based on the specifications of the input / output interfaces, an input / output interface conversion unit 103e is provided to connect the function units 101-1 to 101-3.

[0159] [Operation of the fifth embodiment] Next, the operation of the data flow control device 100e of this embodiment will be described with reference to Fig. 17. In a data flow computing system, when three or more function units have different input / output interfaces, the data flow control device 100e of this embodiment converts input / output data to establish a connection that allows data to be exchanged between the function units without interface inconsistencies. In the following explanation, the operation will be explained using the basic configuration of FIG. 12 as a representative example of FIGS.

[0160] First, the function units 101-1 and 101-3 perform data processing such as arithmetic processing, and then output the data resulting from the processing.

[0161] Next, input / output interface conversion unit 103e converts input / output data between function units 101-1, 101-3 and function unit 101-2 so that the function units 101-1, 101-3 and 101-2, which have different input / output interfaces, can be connected to each other to exchange data without interface inconsistencies.

[0162] Specifically, the conversion determination units 104e-1 and 104e-2 of the input / output interface conversion unit 103e acquire the input / output interface information of the function units 101-1 to 101-3 (step S500 in FIG. 17). As in the first embodiment, the conversion determination units 104e-1 and 104e-2 may acquire the input / output interface information from the function units 101-1 to 101-3, or may acquire it from an external management device.

[0163] The conversion determination unit 104e-1 determines whether or not to convert the output data of the function unit 101-1 based on the acquired input / output interface information (step S501 in FIG. 17). If the input / output interfaces of the function unit 101-1 and the function unit 101-2 are different (YES in step S501), the conversion determination unit 104e-1 determines to convert the output data of the function unit 101-1 (step S502 in FIG. 17). On the other hand, if the input / output interfaces of the function unit 101-1 and the function unit 101-2 are the same (NO in step S501), the conversion determination unit 104e-1 determines not to convert the output data of the function unit 101-1 (step S503 in FIG. 17).

[0164] The specific operation of the conversion determination unit 104e-1 is the operation of any one of the clock frequency resynchronization determination unit 1040, the data width conversion determination unit 1041, and the input / output information conversion determination unit 1042 described in the first to fourth embodiments. As described for the clock frequency resynchronization determination unit 1040, even when the clock frequency of the output data of the function unit 101-1 and the clock frequency of the input data of the function unit 101-2 are different, it may be determined that the output data of the function unit 101-1 should not be converted.

[0165] The conversion unit 105e-1 converts the output data of the function unit 101-1 so that it can be input to the function unit 101-2 (step S504 in FIG. 17). The specific operation of the conversion unit 105e-1 is the operation of any one of the clock resynchronizer 1050, data width converter 1051, and input / output information converter 1052 described in the first to fourth embodiments.

[0166] On the other hand, the conversion determination unit 104e-2 determines whether or not to convert the output data of the function unit 101-3 based on the acquired input / output interface information (step S505 in FIG. 17). If the input / output interfaces of the function unit 101-3 and the function unit 101-2 are different (YES in step S505), the conversion determination unit 104e-2 determines to convert the output data of the function unit 101-3 (step S506 in FIG. 17). On the other hand, if the input / output interfaces of the function unit 101-3 and the function unit 101-2 are the same (NO in step S505), the conversion determination unit 104e-2 determines not to convert the output data of the function unit 101-3 (step S507 in FIG. 17).

[0167] The specific operation of the conversion determination unit 104e-2 is the operation of any one of the clock frequency resynchronization determination unit 1040, the data width conversion determination unit 1041, and the input / output information conversion determination unit 1042 described in the first to fourth embodiments. As described for the clock frequency resynchronization determination unit 1040, even when the clock frequency of the output data of the function unit 101-3 and the clock frequency of the input data of the function unit 101-2 are different, it may be determined that the output data of the function unit 101-3 is not to be converted.

[0168] The conversion unit 105e-2 converts the output data of the function unit 101-3 so that it can be input to the function unit 101-2 (step S508 in FIG. 17). The specific operation of the conversion unit 105e-2 is the operation of any one of the clock resynchronizer 1050, data width converter 1051, and input / output information converter 1052 described in the first to fourth embodiments.

[0169] Next, the output selection unit 106e determines whether conversion determination has been completed for all of the preceding function units 101-1 and 101-3 (step S509 in FIG. 17), and if not completed, waits until conversion determination is completed.

[0170] When the conversion judgment has been completed for all of the preceding function units 101-1 and 101-3, the output selection unit 106e selectively outputs either the output data output from the function units 101-1 and 101-3 and converted by the conversion units 105e-1 and 105e-2, or the unconverted output data output from the function units 101-1 and 101-3, based on the judgment results of the conversion judgment units 104e-1 and 104e-2 (step S510 in Figure 17).

[0171] When the conversion determination units 104e-1 and 104e-2 determine that the output data of the function units 101-1 and 101-3 should be converted, the output selection unit 106e outputs the output data converted by the conversion units 105e-1 and 105e-2 to the function unit 101-2. When the conversion determination unit 104e-1 determines that the output data of the function unit 101-1 should be converted and the conversion determination unit 104e-2 determines that the output data of the function unit 101-3 should not be converted, the output selection unit 106e outputs the output data converted by the conversion unit 105e-1 and the unconverted output data output from the function unit 101-3 to the function unit 101-2.

[0172] Furthermore, if the conversion determination unit 104e-1 determines not to convert the output data of the function unit 101-1 and the conversion determination unit 104e-2 determines to convert the output data of the function unit 101-3, the output selection unit 106e outputs the unconverted output data output from the function unit 101-1 and the output data converted by the conversion unit 105e-2 to the function unit 101-2. Furthermore, if the conversion determination units 104e-1 and 104e-2 determine not to convert the output data of the function units 101-1 and 101-3, the output selection unit 106e outputs the unconverted output data output from the function units 101-1 and 101-3 to the function unit 101-2.

[0173] The function unit 101-2 performs data processing such as arithmetic operations on the data input from the input / output interface conversion unit 103e.

[0174] Although the above example shows that output data conversion determination and conversion are performed for all of the preceding function units 101-1, 101-3, it is not necessary to perform output data conversion determination and conversion for all of the preceding function units 101-1, 101-3. For example, if a preceding function unit that does not require output data conversion determination and conversion is known from an external setting, it is not necessary to perform output data conversion determination and conversion for this function unit.

[0175] [Effects of the fifth embodiment] As described above, the input / output interface conversion unit 103e of this embodiment converts input / output data between the function units 101-1, 101-3 and 101-2 to enable a connection that allows data to be exchanged between the function units 101-1, 101-3 and 101-2 without interface mismatch. This makes it possible to connect the function units 101-1, 101-3 and 101-2 even if the input / output interfaces of the function units 101-1, 101-3 and 101-2 are different.

[0176] In this embodiment, a function unit for any input / output interface can be designed and used, and existing function units can also be reused. Furthermore, in this embodiment, function units with different input / output interfaces can be connected without changing the input / output interfaces, allowing for the reuse of function units. Furthermore, in this embodiment, verification of function units accompanying changes in input / output interfaces is not required, reducing verification costs. Furthermore, in this embodiment, function units can be connected without using memory, eliminating the constraints on processing speed due to the memory data width and data write and read speeds, enabling low latency and high throughput.

[0177] Although the case where there are two function units in the preceding stage has been described, it goes without saying that this embodiment can be easily applied to a case where there are three or more function units in the preceding stage.

[0178] [Configuration of the Sixth Embodiment] Next, a sixth embodiment of the present invention will be described. Fig. 18 is a block diagram showing the configuration of a data flow control device according to this embodiment. A data flow control device 100f of this embodiment is provided with function units 101-1, 101-2, and 101-4, which are arithmetic devices that perform data processing such as arithmetic operations in a data flow computing system, and an input / output interface conversion unit 103f that converts input / output data between the function units 101-1 and 101-2 and 101-4, so as to establish a connection that enables data exchange without interface inconsistency between the function units 101-1 and 101-2 and 101-4, which have different input / output interfaces.

[0179] The input / output interface conversion unit 103f includes conversion determination units 104f-1 and 104f-2 that determine whether or not to convert the output data of the function unit 101-1, conversion units 105f-1 and 105f-2 that convert the output data of the function unit 101-1 so that it can be input to the function units 101-2 and 101-4, and output selection units 106f-1 and 106f-2 that selectively output either the converted output data or the unconverted output data output from the function unit 101-1 to the function units 101-2 and 101-4.

[0180] The conversion determination units 104f-1 and 104f-2, the conversion units 105f-1 and 105f-2, and the output selection units 106f-1 and 106f-2 are provided for the subsequent function units 101-2 and 101-4, respectively.

[0181] The difference from the first to fifth embodiments is that, as shown in FIG. 18, the input / output interface conversion unit 103f has the function of independently performing input / output interface conversion by using the output of the function unit 101-1 as input to each of two or more function units 101-2 and 101-4.

[0182] [Operation of the sixth embodiment] Next, the operation of the data flow control device 100f of this embodiment will be described with reference to Fig. 19. In a data flow computing system, when three or more function units have different input / output interfaces, the data flow control device 100f of this embodiment converts input / output data to establish a connection that allows data to be exchanged between the function units without interface inconsistencies.

[0183] First, the function unit 101-1 performs data processing such as arithmetic processing, and then outputs the data resulting from the processing.

[0184] Next, the input / output interface conversion unit 103f converts input / output data between the function unit 101-1 and the function units 101-2 and 101-4 so that the function units 101-1 and 101-2 and 101-4, which have different input / output interfaces, can be connected to each other to exchange data without interface inconsistencies.

[0185] Specifically, the conversion determination units 104f-1 and 104f-2 of the input / output interface conversion unit 103f acquire input / output interface information of the function units 101-1, 101-2, and 101-4 (step S600 in FIG. 19). As in the first embodiment, the conversion determination units 104f-1 and 104f-2 may acquire the input / output interface information from the function units 101-1, 101-2, and 101-4, or may acquire it from an external management device.

[0186] The conversion determination unit 104f-1 determines whether or not to convert the output data of the function unit 101-1 based on the acquired input / output interface information (step S601 in FIG. 19). If the input / output interfaces of the function unit 101-1 and the function unit 101-2 are different (YES in step S601), the conversion determination unit 104f-1 determines to convert the output data of the function unit 101-1 (step S602 in FIG. 19). On the other hand, if the input / output interfaces of the function unit 101-1 and the function unit 101-2 are the same (NO in step S601), the conversion determination unit 104f-1 determines not to convert the output data of the function unit 101-1 (step S603 in FIG. 19).

[0187] The specific operation of the conversion determination unit 104f-1 is the operation of any one of the clock frequency resynchronization determination unit 1040, the data width conversion determination unit 1041, and the input / output information conversion determination unit 1042 described in the first to fourth embodiments. As described for the clock frequency resynchronization determination unit 1040, even when the clock frequency of the output data of the function unit 101-1 and the clock frequency of the input data of the function unit 101-2 are different, it may be determined that the output data of the function unit 101-1 should not be converted.

[0188] The conversion unit 105f-1 converts the output data of the function unit 101-1 so that it can be input to the function unit 101-2 (step S604 in FIG. 19). The specific operation of the conversion unit 105f-1 is the operation of any one of the clock resynchronizer 1050, data width converter 1051, and input / output information converter 1052 described in the first to fourth embodiments.

[0189] On the other hand, the conversion determination unit 104f-2 determines whether or not to convert the output data of the function unit 101-1 based on the acquired input / output interface information (step S605 in FIG. 19). If the input / output interfaces of the function unit 101-1 and the function unit 101-4 are different (YES in step S605), the conversion determination unit 104f-2 determines to convert the output data of the function unit 101-1 (step S606 in FIG. 19). On the other hand, if the input / output interfaces of the function unit 101-1 and the function unit 101-4 are the same (NO in step S605), the conversion determination unit 104f-2 determines not to convert the output data of the function unit 101-1 (step S607 in FIG. 19).

[0190] The specific operation of the conversion determination unit 104f-2 is the operation of any one of the clock frequency resynchronization determination unit 1040, the data width conversion determination unit 1041, and the input / output information conversion determination unit 1042 described in the first to fourth embodiments. As described for the clock frequency resynchronization determination unit 1040, even when the clock frequency of the output data of the function unit 101-1 and the clock frequency of the input data of the function unit 101-4 are different, it may be determined that the output data of the function unit 101-1 should not be converted.

[0191] The conversion unit 105f-2 converts the output data of the function unit 101-1 so that it can be input to the function unit 101-4 (step S608 in FIG. 19). The specific operation of the conversion unit 105f-2 is the operation of any one of the clock resynchronizer 1050, data width converter 1051, and input / output information converter 1052 described in the first to fourth embodiments.

[0192] Next, the output selection units 106f-1 and 106f-2 determine whether conversion determination has been completed for all of the subsequent function units 101-2 and 101-4 (step S609 in FIG. 19), and if not completed, wait until conversion determination is completed.

[0193] When conversion determination has been completed for all of the downstream function units 101-2 and 101-4, the output selection units 106f-1 and 106f-2 selectively output either the output data output from the function unit 101-1 and converted by the conversion units 105f-1 and 105f-2, or the unconverted output data output from the function unit 101-1, based on the determination results of the conversion determination units 104f-1 and 104f-2 (step S610 in Figure 19).

[0194] If the conversion determination unit 104f-1 determines that the output data of the function unit 101-1 should be converted, the output selection unit 106f-1 outputs the output data converted by the conversion unit 105f-1 to the function unit 101-2. If the conversion determination unit 104f-2 determines that the output data of the function unit 101-1 should be converted, the output selection unit 106f-2 outputs the output data converted by the conversion unit 105f-2 to the function unit 101-4.

[0195] Furthermore, if the conversion determination unit 104f-1 determines not to convert the output data of the function unit 101-1, the output selection unit 106f-1 outputs the unconverted output data output from the function unit 101-1 to the function unit 101-2. If the conversion determination unit 104f-2 determines not to convert the output data of the function unit 101-1, the output selection unit 106f-2 outputs the unconverted output data output from the function unit 101-1 to the function unit 101-4.

[0196] The function units 101-2 and 101-4 perform data processing such as arithmetic operations on the data input from the input / output interface conversion unit 103f.

[0197] Although the above example shows that data conversion determination and conversion are performed for all of the subsequent function units 101-2, 101-4, data conversion determination and conversion do not necessarily have to be performed for all of the subsequent function units 101-2, 101-4. For example, if a subsequent function unit that does not require data conversion determination and conversion is known from an external setting, data conversion determination and conversion do not have to be performed for this function unit.

[0198] [Effects of the Sixth Embodiment] As described above, the input / output interface conversion unit 103f of this embodiment converts input / output data between the function unit 101-1 and the function units 101-2 and 101-4 so that data can be exchanged between the function unit 101-1 and the function units 101-2 and 101-4 without interface mismatch. This makes it possible to connect the function unit 101-1 with the function units 101-2 and 101-4 even if the input / output interfaces of the function unit 101-1 and the function units 101-2 and 101-4 are different.

[0199] In this embodiment, a function unit for any input / output interface can be designed and used, and existing function units can also be reused. Furthermore, in this embodiment, function units with different input / output interfaces can be connected without changing the input / output interfaces, allowing for the reuse of function units. Furthermore, in this embodiment, verification of function units accompanying changes in input / output interfaces is not required, reducing verification costs. Furthermore, in this embodiment, function units can be connected without using memory, eliminating the constraints on processing speed due to the memory data width and data write and read speeds, enabling low latency and high throughput.

[0200] Although the case where there are two subsequent function units has been described, it goes without saying that this embodiment can be easily applied to cases where there are three or more subsequent function units.

[0201] [Configuration of the Seventh Embodiment] Next, a seventh embodiment of the present invention will be described. Fig. 20 is a block diagram showing the configuration of a data flow control device according to this embodiment. A data flow control device 100g of this embodiment is a data flow computing system, and includes function units 101-1 to 101-7 which are arithmetic devices that perform data processing such as arithmetic operations, an input / output interface conversion unit 103g-1 that converts input / output data between the function units 101-1 and 101-2, an input / output interface conversion unit 103g-2 that converts input / output data between the function units 101-3 and 101-4, an input / output interface conversion unit 103g-3 that converts input / output data between the function units 101-2, 101-4 and the function units 101-5, 101-6, and an input / output interface conversion unit 103g-4 that converts input / output data between the function units 101-5, 101-6 and the function unit 101-7.

[0202] The difference from the first to sixth embodiments is that when a plurality of function units 101-1 to 101-7 are connected to create a function chain, input / output interface conversion units 103g-1 to 103g-4 are automatically placed between the function units so that the input / output interfaces of the preceding function unit and the succeeding function unit are compatible, as shown in Fig. 20. The specific configuration of the input / output interface conversion units 103g-1 to 103g-4 is similar to that of the input / output interface conversion units 103, 103b to 103f described in the first to sixth embodiments, and therefore a detailed description thereof will be omitted.

[0203] The input / output interface conversion units 103g-1 to 103g-4 are arranged by the arrangement unit 107. FIG. First, the computer system designer determines a configuration in which function units 101-1 to 101-7 required to realize a desired process (service or application) are connected in multiple stages.

[0204] The placement unit 107 acquires system configuration information that indicates the connection relationships between the function units 101-1 to 101-7, which is created by the computer system designer (step S700 in FIG. 21). Then, the placement unit 107 places input / output interface conversion units 103g-1 to 103g-4 between the function units so that function units having different input / output interfaces can be connected together, even if the designer does not explicitly specify interface conversion (step S701 in FIG. 21).

[0205] In the example of Figure 20, an input / output interface conversion unit 103g-1 is placed between function units 101-1 and 101-2, an input / output interface conversion unit 103g-2 is placed between function units 101-3 and 101-4, an input / output interface conversion unit 103g-3 is placed between function units 101-2 and 101-4 and function units 101-5 and 101-6, and an input / output interface conversion unit 103g-4 is placed between function units 101-5 and 101-6 and function unit 101-7.

[0206] Although not shown in FIG. 20, the function units are connected to each other via, for example, a communication network, and input / output interface conversion units 103g-1 to 103g-4 can be arranged on this network.

[0207] [Operation of the Seventh Embodiment] Next, the operation of the data flow control device 100g of this embodiment after the input / output interface conversion units 103g-1 to 103g-4 are arranged will be described with reference to Fig. 22. In a data flow computing system, when two or more function units have different input / output interfaces, the data flow control device 100g of this embodiment converts input / output data to establish a connection that allows data to be exchanged between the function units without interface inconsistencies.

[0208] The conversion determination unit of the input / output interface conversion unit 103g-1 acquires the input / output interface information of the function units 101-1 to 101-7 (step S800 in FIG. 22).

[0209] The conversion determination unit of the input / output interface conversion unit 103g-1 determines whether or not to convert the output data of the function unit 101-1 based on the input / output interface information of the function units 101-1 and 101-2 (step S801 in FIG. 22). The specific operation of this conversion determination unit is the operation of any one of the clock frequency resynchronization determination unit 1040, data width conversion determination unit 1041, and input / output information conversion determination unit 1042 described in the first to fourth embodiments.

[0210] The converter of the input / output interface converter 103g-1 converts the output data of the function unit 101-1 so that it can be input to the function unit 101-2 (step S804 in FIG. 22). The specific operation of this converter is the operation of any one of the clock transfer unit 1050, data width converter 1051, and input / output information converter 1052 described in the first to fourth embodiments.

[0211] Although not specifically described in the first to sixth embodiments, for example, by acquiring a unique ID assigned to each of the function units 101-1 to 101-7, the input / output interface conversion unit 103g-1 can identify the preceding function unit 101-1 and the following function unit 101-2.

[0212] The output selection unit of the input / output interface conversion unit 103g-1 selectively outputs either the output data output from the function unit 101-1 and converted by the conversion unit of the input / output interface conversion unit 103g-1, or the unconverted output data output from the function unit 101-1, based on the judgment result of the conversion judgment unit of the input / output interface conversion unit 103g-1.

[0213] The input / output interface conversion unit 103g-2 may perform the same processing as the input / output interface conversion unit 103g-1 for the function unit 101-3 at the front stage and the function unit 101-4 at the rear stage.

[0214] The input / output interface conversion unit 103g-3 performs processing for the front-stage function units 101-2 and 101-4 and the rear-stage function units 101-5 and 101-6. This processing is a combination of the input / output interface conversion unit 103e of the fifth embodiment and the input / output interface conversion unit 103f of the sixth embodiment.

[0215] The input / output interface conversion unit 103g-4 only needs to process the function units 101-5 and 101-6 in the front stage and the function unit 101-7 in the rear stage. This process is the same as that of the input / output interface conversion unit 103e in the fifth embodiment.

[0216] In the above description, input / output interface conversion units 103g-1 to 103g-4 are placed between all function units. However, if the function units between which data conversion determination and conversion are not required are known by external settings, the placement unit 107 may not need to place input / output interface conversion units between these function units.

[0217] [Effects of the Seventh Embodiment] As described above, the input / output interface conversion units 103g-1 to 103g-4 of this embodiment convert input / output data between the function unit in the preceding stage and the function unit in the following stage so that data can be exchanged between the function unit in the preceding stage without interface mismatch. This makes it possible to connect the function unit in the preceding stage and the function unit in the following stage even if the input / output interfaces of the function unit in the preceding stage and the function unit in the following stage are different.

[0218] In this embodiment, a function unit for any input / output interface can be designed and used, and existing function units can also be reused. Furthermore, in this embodiment, function units with different input / output interfaces can be connected without changing the input / output interfaces, allowing for the reuse of function units. Furthermore, in this embodiment, verification of function units accompanying changes in input / output interfaces is not required, reducing verification costs. Furthermore, in this embodiment, function units can be connected without using memory, eliminating the constraints on processing speed due to the memory data width and data write and read speeds, enabling low latency and high throughput.

[0219] [Extending the working example] Although the present invention has been described above with reference to the embodiments, the present invention is not limited to the above embodiments. Various modifications that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention. Furthermore, the embodiments can be implemented in any combination within a consistent range.

[0220] Each of the function units 101-1 to 101-7 and input / output interface conversion units 103, 103b to 103f, and 103g-1 to 103g-4 described in the first to seventh embodiments can be realized by a computer equipped with a CPU (Central Processing Unit), a storage device, and an interface, and a program that controls these hardware resources. An example of the configuration of this computer is shown in Fig. 23. The computer includes a CPU 200, a storage device 201, and an interface device (I / F) 202.

[0221] A communication network or the like is connected to the I / F 202. In such a computer, a program for realizing the data flow control method of the present invention is stored in the storage device 201. The CPU 200 executes the processes described in the first to seventh embodiments in accordance with the program stored in the storage device 201. [Industrial Applicability]

[0222] The present invention can be applied to a computer system. [Explanation of symbols]

[0223] 100a to 100g... Data flow control devices, 101-1 to 101-7... Function units, 103, 103b to 103f, 103g-1 to 103g-4... Input / output interface conversion units, 104, 104d-1, 104d-2, 104e-1, 104e-2, 104f-1, 104f-2... Conversion determination units, 105, 105d-1, 105d-2, 105e-1, 105e-2, 105f-1, 105f-2... Conversion units, 106, 106b, 106c, 106d, 10 6e, 106f-1, 106f-2...output selection unit, 107...placement unit, 1040, 1040-1, 1040-2...clock frequency resynchronization determination unit, 1050, 1050-1, 1050-2...clock resynchronization unit, 1041, 1041-1, 1041-2...data width conversion determination unit, 1051, 1051-1, 1051-2...data width conversion unit, 1042, 1042-1, 1042-2...input / output information conversion determination unit, 1052, 1052-1, 1052-2...input / output information conversion unit.

Claims

1. an input / output interface conversion unit that is provided between two or more function units that perform data processing, and that is configured to convert output data from the function unit at the previous stage so that the output data can be input to the function unit at the subsequent stage when the input / output interfaces of the function unit at the previous stage and the function unit at the subsequent stage are different; a placement unit configured to place the input / output interface conversion units between the function units so that the input / output interfaces between the function units are adapted based on system configuration information indicating a connection relationship between the plurality of function units; A data flow control device, characterized in that each function unit is connected via a communication network, and the input / output interface conversion unit is disposed on the communication network.

2. 2. The data flow control device according to claim 1, The input / output interface conversion unit includes: a conversion determination unit configured to determine whether or not to convert output data of the upstream function unit based on input / output interface information of the upstream and downstream function units; a conversion unit configured to convert output data of the function unit at the previous stage so that the output data can be input to the function unit at the subsequent stage; and an output selection unit configured to selectively output to the function unit in the subsequent stage either output data converted by the conversion unit or unconverted output data output from the function unit in the previous stage based on a judgment result of the conversion judgment unit.

3. 3. The data flow control device according to claim 2, The data flow control device according to claim 1, wherein when there are a plurality of function units in the preceding stage, the conversion determination unit and the conversion unit are provided for each of the function units in the preceding stage.

4. 3. The data flow control device according to claim 2, 2. A data flow control device according to claim 1, wherein when there are a plurality of function units in the subsequent stage, the conversion determination unit, the conversion unit, and the output selection unit are provided for each of the function units in the subsequent stage.

5. 5. The data flow control device according to claim 2, the conversion determination unit is a clock frequency reprogramming determination unit configured to determine whether or not to convert a clock frequency of output data of the upstream function unit based on input / output interface information of the upstream and downstream function units; the conversion unit is a clock transfer unit configured to convert a clock frequency of output data of the function unit at the previous stage into a clock frequency of input data of the function unit at the subsequent stage; The data flow control device is characterized in that the output selection unit selectively outputs, to the function unit in the subsequent stage, either the output data whose clock frequency has been converted by the clock transfer unit or the unconverted output data output from the function unit in the previous stage based on the judgment result of the clock frequency transfer judgment unit.

6. 5. The data flow control device according to claim 2, the conversion determination unit is a data width conversion determination unit configured to determine whether or not to convert an output data width of the upstream function unit based on input / output interface information of the upstream and downstream function units; the conversion unit is a data width conversion unit configured to convert an output data width of the function unit at the previous stage so as to match an input data width of the function unit at the subsequent stage; a data flow control device characterized in that the output selection unit selectively outputs, to the function unit in the subsequent stage, either output data whose data width has been converted by the data width conversion unit or unconverted output data output from the function unit in the previous stage based on a judgment result of the data width conversion judgment unit.

7. 5. The data flow control device according to claim 2, the conversion determination unit is an input / output information conversion determination unit configured to determine whether or not to convert a format of output data of the upstream function unit based on input / output interface information of the upstream and downstream function units; the conversion unit is an input / output information conversion unit configured to convert a format of output data of the function unit at the previous stage so as to conform to a format of input data of the function unit at the subsequent stage; The data flow control device is characterized in that the output selection unit selectively outputs to the function unit in the subsequent stage either output data whose format has been converted by the input / output information conversion unit or unconverted output data output from the function unit in the previous stage based on the judgment result of the input / output information conversion judgment unit.

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