Address-based filtering for load / store speculation

Abstract

Address-based filtering for load / store speculation includes maintaining a filtering table including table entries associated with a range of addresses; in response to receiving an order check trigger transaction, querying the filtering table using a target address of the order check trigger transaction to determine whether an instruction dependent on the order check trigger transaction previously generated the physical address; and in response to determining that the filtering table does not have an indication that the instruction dependent on the order check trigger transaction previously generated the physical address, bypassing a lookup operation in an order violation memory structure to determine whether the instruction dependent on the order check trigger transaction is currently in-flight.

Description

[Technical field]

[0001] STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT This disclosure was made with Government support under the PathForward Project with Lawrence Livermore National Security awarded by the DOE under Prime Contract No. DE-AC52-07NA27344, Subcontract No. B620717. The Government has certain rights in this disclosure. [Background technology]

[0002] Computer processors using data speculation typically allow load and store instructions in a load-store unit to complete out of program order. This data speculation requires checking memory dependencies for in-order violations to suppress in-order violation errors. These checks may require all physical address comparisons between the load or store and a subset of the in-flight stores or in-flight loads. In some memory consistency models, the checks also require comparing all physical addresses of external probes with the physical addresses of the in-flight loads. Suppressing in-order violations typically involves the use of a content addressable memory (CAM) structure. [Brief description of the drawings]

[0003] [Figure 1] FIG. 2 is a block diagram of an example system for address-based filtering for load / store speculation in accordance with an embodiment of the present disclosure. [Diagram 2] FIG. 2 is a block diagram of an example system for address-based filtering for load / store speculation in accordance with an embodiment of the present disclosure. [Diagram 3]5 is a flowchart illustrating an exemplary method for address-based filtering for load / store speculation, according to an embodiment of the present disclosure. [Figure 4] 5 is a flowchart illustrating an exemplary method for address-based filtering for load / store speculation, according to an embodiment of the present disclosure. [Diagram 5] 5 is a flowchart illustrating an exemplary method for address-based filtering for load / store speculation, according to an embodiment of the present disclosure. [Figure 6] 5 is a flowchart illustrating an exemplary method for address-based filtering for load / store speculation, according to an embodiment of the present disclosure. [Figure 7] 5 is a flowchart illustrating an exemplary method for address-based filtering for load / store speculation, according to an embodiment of the present disclosure. [Figure 8] 5 is a flowchart illustrating an exemplary method for address-based filtering for load / store speculation, according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0004] Using content addressable memory (CAM) structures and lookup operations to suppress out-of-order errors is expensive in terms of power usage. Thus, reducing the number of CAM lookups in a load store unit (LSU) reduces the overall power usage of the LSU. An embodiment of the present disclosure uses a filtering mechanism to bypass memory operations such as CAM lookups for some incoming instructions. The filtering mechanism operates by maintaining a table of entries corresponding to addresses or address ranges of previously received store or load instructions. If an incoming store instruction, load instruction, or cache probe contains a target address within a range not targeted by a previously received instruction, the incoming store instruction, load instruction, or cache probe is forwarded to completion without requiring a CAM lookup. In some embodiments, the filtering mechanism is utilized at several different stages of the LSU pipeline.

[0005] Figure 1 is a block diagram of a non-limiting exemplary computing system (152) for address-based filtering for load / store speculation in accordance with some embodiments. The computing system (152) of Figure 1 includes at least one computer processor (156) or "CPU" and random access memory (168) (RAM) connected to the processor (156) and other components of the computing system (152) via a high-speed memory bus (166) and a bus adapter (158).

[0006] Stored in RAM 168 is an operating system 154. Operating systems useful in computers with address-based filtering for load / store speculation include UNIX, Linux, Microsoft Windows, AIX, and others as would occur to one skilled in the art. Although operating system 154 in the example of FIG. 1 is shown as residing in RAM 168, many components of such software are typically also stored in non-volatile memory, such as a data storage device 170, e.g., a disk drive.

[0007] The computing system (152) of Figure 1 includes a disk drive adapter (172) coupled to the processor (156) and other components of the computing system (152) via an expansion bus (160) and a bus adapter (158). The disk drive adapter (172) connects non-volatile data storage to the computing system (152) in the form of a data storage device (170). In some embodiments, the disk drive adapter includes an integrated drive electronics (IDE) adapter, a small computer system interface (SCSI) adapter, and others as would occur to one of ordinary skill in the art. In some embodiments, the non-volatile computer memory is implemented as an optical disk drive, an electrically erasable programmable read-only memory (so-called "EEPROM" or "flash" memory), a RAM drive, or the like, as would occur to one of ordinary skill in the art.

[0008] The exemplary computing system (152) of FIG. 1 includes one or more input / output (I / O) adapters (178). The I / O adapters provide user-directed input / output through software drivers and computer hardware for controlling user input from user input devices (181), such as a keyboard and mouse, as well as output to a display device, such as a computer display screen. The exemplary computing system (152) of FIG. 1 also includes a video adapter (209), which is an example of an I / O adapter specifically designed for graphics output to a display device (180), such as a display screen or computer monitor. The video adapter (209) is connected to the processor (156) through a high-speed video bus (164), a bus adapter (158), and a frontside bus (162), which is also a high-speed bus.

[0009] The exemplary computing system (152) of FIG. 1 includes a communications adapter (167) for data communications with other computers and with a data communications network. In some embodiments, such data communications are performed serially, via an RS-232 connection, via an external bus such as a Universal Serial Bus (USB), via a data communications network such as an IP data communications network, and in other manners as would occur to one skilled in the art. Communications adapters implement a hardware level of data communications whereby one computer sends data communications to another computer, either directly or via a data communications network. In some embodiments, examples of communications adapters include modems for wired dial-up communications, Ethernet (IEEE 802.3) adapters for wired data communications, and 802.11 adapters for wireless data communications.

[0010] Figure 2 is a block diagram of a non-limiting exemplary processor (156) for address-based filtering for load / store speculation, according to some embodiments. As shown in Figure 2, the exemplary processor (156) includes a load store unit (LSU) (200), an address generation unit (202), control logic (204), a filtering table shift trigger (206), an order violation memory structure filtering table (208), and an order violation memory structure (210). The representation of the LSU (200) in Figure 2 includes elements that represent different specific structures in the LSU (200). Specifically, in some embodiments, the filtering table shift trigger (206) and the order violation memory structure (210) are applied to several different elements along the LSU (200) pipeline, as described below.

[0011] The LSU (200) is the part of the processor (156) that executes load and store instructions. The LSU (200) checks for memory dependencies and order violations when loads and stores are allowed to complete out of program order. The control logic (204) of the LSU (200) implements the functions of the LSU (200), including executing load and store instructions to completion. The control logic (204) in FIG. 2 is depicted as a separate element within the LSU (200) for purposes of illustration. In reality, the control logic (204) is a collection of operations within and between other elements on the LSU (200). The address generation unit (202) calculates physical addresses for load and store instructions and provides the physical addresses to the LSU (200) as an initial step in executing a load or store instruction.

[0012] The filtering table shift trigger (206) is a data structure used by the control logic (204) to trigger a shift in the filtering table (208). The control logic (204) monitors the filtering table shift trigger (206) for certain conditions that cause the control logic (204) to initiate a shift in the filtering table (208). The shift in the filtering table is performed to maintain parity with the memory locations targeted by the load and store instructions. In some embodiments, the filtering table shift trigger (206) is a queue that is allocated and deallocated in program order, such as a store queue (STQ) or a load tracking queue (LTQ) of the LSU (200). In some embodiments, the shift is triggered by the reuse of a particular pre-programmed slot in the queue. In some embodiments, the particular slot is pre-programmed using a basic input / output system (BIOS) setting.

[0013] The out-of-order memory structure (210) is a memory structure, such as a CAM structure, that operates as part of the memory dependency checking and out-of-order checking of the control logic. Examples of the out-of-order memory structure (210) include a store-to-load-forward (STLF) CAM, an out-of-order buffer (OOB) CAM, and a load-order queue (LOQ) CAM. Because lookup operations in these out-of-order memory structures are expensive in terms of power usage, embodiments of the present disclosure include a filtering table (208) to reduce the number of lookup operations by tracking the presence of in-flight loads and in-flight stores in a predefined physical address range in the filtering table (208) without performing full or partial address comparisons.

[0014] The STLF CAM is a memory structure used by the LSU (200) to verify that a load about to be executed has the same target address as an old store that has not yet been executed. When a load is scheduled for execution by the load-store queue (LSQ), the control logic (204) compares all entries in the STLF CAM with the target address of the load to determine whether there is a previous old store to the same target address as the target address of the load. The OOB CAM performs a similar function to the STLF CAM, but detects memory order violations between a store instruction that missed when the load was first scheduled into memory by the LSQ and a load instruction. This is possible because when the load is executed, all previous old stores may not have generated physical addresses. A completed load remains in OOB until all old stores have generated physical addresses and checked dependencies. Similarly, the LOQ CAM detects memory order violations between load instructions (of the same or different threads) by monitoring cache events. Cache events include cache probes, such as a level 1 data cache probe, and cache evictions, such as a level 1 data cache eviction.

[0015] The ordering violation memory structure filtering table 208 is a mechanism for filtering out, from the ordering violation memory structure 210, certain ordering check triggering transactions (e.g., load instructions, store instructions, and cache events) for which there is an ordering violation, including a dependency violation. The filtering table 208 contains entries that represent the target addresses (i.e., physical addresses or logical addresses) or ranges of target addresses of the ordering check triggering transactions. For example, in some embodiments, the filtering table may include entries that represent 2 Nentries, where N is a subset of the bits in the target address of the order check triggering transaction. In some embodiments, a filtering table (208) is implemented for each or any of the order violation memory structures (210) in the LSU (200).

[0016] In some embodiments, the order violation memory structure filtering table (208) is implemented as two or more separate filtering tables. In some embodiments, each of the filtering tables is assigned to a different set of ranges of target addresses. In some embodiments, the control logic (204) makes an initial determination of which filtering table to query based on a portion of the target address.

[0017] 3 is a flow chart illustrating a non-limiting exemplary method for address-based filtering for load / store speculation, according to some embodiments, the method including maintaining (302) a filtering table including table entries associated with a range of addresses. In some embodiments, maintaining (302) the filtering table including table entries associated with a range of addresses is performed by the control logic (204) placing an indication of a potential ordering violation in the filtering table. In some embodiments, maintaining (302) the filtering table including table entries associated with a range of addresses is performed by the control logic (204) shifting the table entries based on a condition of a filtering table shift trigger.

[0018] The method of FIG. 3 includes, in response to receiving an order check trigger transaction (320), querying (304) a filtering table (208) using a target address of the order check trigger transaction (320) to determine if an instruction dependent on the order check trigger transaction (320) previously generated a physical address. In some embodiments, receiving the order check trigger transaction (320) is accomplished by the control logic (204) detecting that an address generation unit provided a physical address for the order check trigger transaction (320) (e.g., a load instruction, a store instruction, a cache event). In some embodiments, the control logic (204) receives the physical address from the address generation unit and extracts a subset of the physical address for use as a key into the filtering table (208). Alternatively, in some embodiments, the control logic (204) uses a portion of the logical address as a key into the filtering table (208).

[0019] In some embodiments, querying (304) the filtering table (208) using the target address of the order check trigger transaction (320) to determine if an instruction dependent on the order check trigger transaction (320) previously generated the physical address is performed by the control logic (204) generating a query entry identifier using a portion of the target address (i.e., a physical address or a logical address) and accessing an entry identified by the entry identifier. In some embodiments, for example, the entry identifier is generated from the physical address using [M:M+N-1], where M is the starting address of the memory window and N is a subset of the physical address bits for the filtering table (208).

[0020] The method of FIG. 3 includes, in response to determining that the filtering table (208) does not have an indication that an instruction dependent on the order check trigger transaction (320) previously generated a physical address, bypassing (306) a lookup operation in an out-of-order memory structure to determine whether an instruction dependent on the order check trigger transaction (320) is currently in-flight. "In-flight" refers to an instruction that has completed but not yet been retired. In some embodiments, determining that the filtering table (208) does not have an indication that an instruction dependent on the order check trigger transaction (320) previously generated a physical address is performed by the control logic (204) accessing an entry in the filtering table and determining that the contents of the entry are zero. Because there is no indication of a previous instruction dependent on the order check trigger transaction (320), the control logic (204) is guaranteed that the dependent previous instruction is not currently in-flight (i.e., data is not being loaded from or stored to the target physical address by any in-flight instruction in the pipeline).

[0021] In some embodiments, bypassing (306) the lookup operation in the out-of-order memory structure to determine whether an instruction dependent on the order check trigger transaction (320) is currently in-flight is implemented by the control logic (204) operating as if a lookup operation in the out-of-order memory structure had been performed and a response is returned indicating that an instruction dependent on the order check trigger transaction (320) is not currently in-flight (i.e., data is not being loaded from or stored to a target physical address by any in-flight instruction in the pipeline).

[0022] The above features improve the operation of a computer system by avoiding expensive lookup operations in memory structures by maintaining a filtering table for incoming order-check trigger transactions (e.g., load instructions, store instructions, cache events) that can, in some circumstances, identify the absence of dependent instructions using inexpensive access of the filtering table. Additionally, applications that perform a large number of load / store micro-operations within a processor core are more efficiently executed by reducing dynamic power consumption without degrading performance.

[0023] For further explanation, FIG. 4 is a flowchart illustrating a further exemplary method for address-based filtering for load / store speculation, according to an embodiment, the method including maintaining (302) a filtering table including table entries associated with a range of addresses; in response to receiving an order check trigger transaction (320), querying (304) a filtering table (208) using a target address of the order check trigger transaction (320) to determine whether an instruction dependent on the order check trigger transaction (320) previously generated a physical address; and in response to determining that the filtering table (208) does not have an indication that the instruction dependent on the order check trigger transaction (320) previously generated a physical address, bypassing (306) a lookup operation in an order violation memory structure to determine whether an instruction dependent on the order check trigger transaction (320) is currently in-flight.

[0024] However, the method of FIG. 4 differs from the method of FIG. 3 in that, in response to determining that the filtering table (208) includes an indication that an instruction dependent on the order check trigger transaction (320) previously generated a physical address, the method of FIG. 4 further includes performing (402) a lookup operation in the order violation memory structure (210) to determine whether an instruction dependent on the order check trigger transaction (320) is currently in-flight.

[0025] In some embodiments, determining that the filtering table (208) includes an indication that an instruction dependent on the order check trigger transaction (320) previously generated a physical address is performed by the control logic (204) accessing an entry in the filtering table and determining that the entry is non-zero (i.e., the entry is marked to indicate that a previous dependent instruction is potentially in-flight (i.e., data has not been loaded from or stored to the target physical address by any in-flight instruction). If each entry represents a range of addresses, the marking of the entry does not necessarily indicate the presence of an order violation. Instead, the mark indicates that the dependent instruction has a generated physical address that targets the same range. Because there is an indication of a previous instruction that potentially depends on the order check trigger transaction (320), the control logic (204) has no guarantee that the dependent previous instruction is not currently in-flight (i.e., data has not been loaded from or stored to the target physical address by any in-flight instruction). In such a case, a relatively expensive lookup operation is performed in the out-of-order memory structure (210) to determine whether an instruction dependent on the order-check trigger transaction (320) is currently in-flight.

[0026] For further explanation, FIG. 5 is a flowchart illustrating a further exemplary method for address-based filtering for load / store speculation, according to an embodiment, the method including maintaining (302) a filtering table including table entries associated with a range of addresses; in response to receiving an order check trigger transaction (320), querying (304) a filtering table (208) using a target address of the order check trigger transaction (320) to determine whether an instruction dependent on the order check trigger transaction (320) previously generated a physical address; and in response to determining that the filtering table (208) does not have an indication that the instruction dependent on the order check trigger transaction (320) previously generated a physical address, bypassing (306) a lookup operation in an order violation memory structure to determine whether an instruction dependent on the order check trigger transaction (320) is currently in-flight.

[0027] However, the method of FIG. 5 differs from the method of FIG. 3 in that maintaining a filtering table (302) including table entries associated with a range of addresses includes detecting that a dependent instruction generated a physical address (502), indicating that the dependent instruction generated the physical address in an entry in the filtering table (208) associated with the target address of the dependent instruction (504), and shifting the table entry in the filtering table (208) in response to detecting that a particular slot has been reused in the in-program-order deallocated queue (506).

[0028] In some embodiments, detecting that a dependent instruction has generated a physical address (502) is accomplished by the control logic (204) being notified by the address generation unit (202) that a physical address has been generated for a particular type of dependent instruction (e.g., a load instruction or a store instruction). In some embodiments, the control logic (204) receives a physical address for the instruction, a logical address for the instruction, or a portion of either.

[0029] In some embodiments, indicating (504) that the dependent instruction generated the physical address in an entry of the filtering table (208) associated with the target address of the dependent instruction is performed by the control logic (204) marking the entry for the target address in the filtering table (208). In some embodiments, the control logic (204) marks the entry in a manner that uses a minimal amount of power. In some embodiments, for example, the control logic (204) writes a value of “0x03” to indicate a non-zero entry.

[0030] In some embodiments, detecting that a particular slot has been reused in a program-order deallocated queue is performed by the control logic (204) monitoring a filtering table shift trigger (206) for a condition that causes the filtering table (208) to be shifted. In some embodiments, the condition is reuse of a particular slot in the queue. In some embodiments, shifting (506) a table entry in the filtering table (208) in response to detecting that a particular slot has been reused in a program-order deallocated queue is performed by the control logic (204) advancing each table entry by one to ensure that if the entry is zero, there is no in-flight load / store with the same physical address bits as the address indexing. In some embodiments, the program-order deallocated queue is a store queue or a load tracking queue, depending on the out-of-order memory structure in which filtering is performed. Alternatively, in some embodiments, the filtering table shift trigger (206) is detection of reuse of a preselected reorder buffer ID within the instruction window.

[0031] For further explanation, Figures 6, 7, and 8 are flow charts illustrating example contexts of the methods described in Figures 3, 4, and 5. Specifically, Figures 6, 7, and 8 are flow charts illustrating examples in the context of a Store-to-Load Forward (STLF) CAM, an Out-of-Order Buffer (OOB) CAM, and a Load-Order Queue (LOQ) CAM, respectively. Figure 6 is a flow chart illustrating an exemplary method for address-based filtering for load / store speculation according to an embodiment in the context of a STLF CAM. Similar to the combination of Figures 3, 4 and 5, Figure 6 includes maintaining (302) a filtering table including table entries associated with a range of addresses, including detecting (502) that a dependent (store) instruction generated a physical address, indicating (504) that the dependent (store) instruction generated a physical address in an entry in the filtering table (208A) associated with the target address of the dependent (store) instruction, and shifting (506) the table entry in the filtering table (208A) in response to detecting that a particular slot has been reused in the out-of-program-order deallocated queue.FIG. 6 further illustrates the process of querying (304) a filtering table (208A) in response to receiving an order check trigger transaction (load instruction) (320) using a target address of the order check trigger transaction (load instruction) to determine whether a (store) instruction that is dependent on the order check trigger transaction (load instruction) has previously generated a physical address, and in response to determining that the filtering table (208A) does not have an indication that a (store) instruction that is dependent on the order check trigger transaction (load instruction) (320) has previously generated a physical address, querying (304) a filtering table (208A) using a target address of the order check trigger transaction (load instruction) (320) to determine whether a (store) instruction that is dependent on the order check trigger transaction (load instruction) has previously generated a physical address. and, in response to determining that the filtering table (208A) includes an indication that the (store) instruction dependent on the order check trigger transaction (load instruction) (320) previously generated a physical address, performing a lookup operation (402) in the out-of-order memory structure (210A) to determine whether the (store) instruction dependent on the order check trigger transaction (load instruction) (320) is currently in-flight.

[0032] In the exemplary method of FIG. 6, detecting (502) that the dependent instruction generated a physical address is accomplished by the control logic (204) detecting that the store instruction generated a physical address via the address generation unit (202A). The control logic (204) updates the filtering table (208A) of the STLF CAM (210A) each time the control logic (204) is notified that the address generation unit (202A) has generated a physical address for a store instruction. Specifically, in the exemplary method of FIG. 6, indicating (504) that the dependent instruction generated a physical address in an entry in the filtering table (208A) associated with the target address of the dependent instruction is accomplished by the control logic (204) using a subset of bits of the target address (i.e., a portion of the physical address or logical address) of the store instruction as an identification of an entry in the filtering table (208A) for the STLF CAM (210A). This entry represents a range of target addresses and is marked with 0x03. This action indicates that there is an in-flight store instruction that targets an address within the indicated entry range.

[0033] In the exemplary method of Figure 6, shifting (506) table entries in the filtering table (208A) in response to detecting that a particular slot has been reused in a queue that has been deallocated in program order is accomplished by the control logic (204) detecting that a pre-programmed slot in the store queue (206A) has been reused. In the case of a partial or full flush of the pipeline, the table is not modified. Because the store queue is allocated and deallocated in program order, it behaves similarly to a first-in-first-out queue, and therefore no table flush is required.

[0034] In the exemplary method of Figure 6, receiving an order check trigger transaction (320) is implemented by the control logic (204) detecting that a load instruction has generated a physical address by the address generation unit (202A). Each time the control logic (204) is notified that the address generation unit (202A) has generated a physical address for a load instruction, the control logic (204) queries a filtering table (208A) of the STLF CAM (210A). In the exemplary method of Figure 6, querying (304) the filtering table (208A) using a target address of the order check trigger transaction (320) to determine whether an instruction dependent on the order check trigger transaction (320) has previously generated a physical address is implemented by the control logic (204) querying the filtering table (208A) using a target address of the load instruction to determine whether an in-flight store instruction has previously generated a physical address in the same range of the target address of the load instruction.

[0035] 6, determining that the filtering table (208A) does not have an indication that an instruction dependent on the order check trigger transaction (320) previously generated a physical address is performed by the control logic (204) accessing the STLF CAM filtering table (208A) using a portion of the target address of the load instruction and reading a zero entry (e.g., “0x0”). As a result, the control logic (204) determines that the associated entry in the filtering table (208A) does not have an indication that an in-flight store instruction to the same target address range previously generated a physical address by the address generation unit (202A).

[0036] In the example method of FIG. 6 , bypassing (306) a lookup operation in an out-of-order memory structure to determine whether an instruction dependent on an order-check trigger transaction (320) is currently in-flight is implemented by the control logic (204) bypassing a lookup operation in the STLF CAM (210A) to determine whether a store instruction is currently in-flight (i.e., whether data was stored to a target physical address by an in-flight store instruction).

[0037] 6, determining that the filtering table (208A) contains an indication that an instruction dependent on the order check trigger transaction (320) previously generated a physical address is performed by the control logic (204) accessing the STLF CAM filtering table (208A) using a portion of the target address of the load instruction and reading a non-zero entry, such that the control logic (204) determines that the associated entry in the filtering table (208A) contains an indication that an in-flight store instruction to the same target address range previously generated a physical address by the address generation unit (202A).

[0038] In the example method of FIG. 6, performing (402) a lookup operation in the order-violating memory structure (210A) to determine whether an instruction dependent on the order-check trigger transaction (320) is currently in-flight is accomplished by the control logic (204) performing a CAM lookup operation on the STLF CAM (210A) to determine whether the load instruction has a dependency on an in-flight store instruction.

[0039] Figure 7 is a flow chart illustrating an exemplary method for address-based filtering for load / store speculation, according to an embodiment in the context of an OOB CAM. Similar to a combination of Figures 3, 4, and 5, Figure 7 includes maintaining (302) a filtering table including table entries associated with a range of addresses, including detecting (502) that a dependent (load) instruction generated a physical address, indicating (504) that the dependent (load) instruction generated a physical address in an entry of the filtering table (208B) associated with a target address of the dependent (load) instruction, and shifting (506) the table entry in the filtering table (208B) in response to detecting that a particular slot has been reused in the program order deallocated queue. FIG. 7 further illustrates a method for querying (304) a filtering table (208B) in response to receiving an order check trigger transaction (store instruction) (320) to determine whether a (load) instruction that is dependent on the order check trigger transaction (store instruction) (320) previously generated a physical address, using the target address of the order check trigger transaction (store instruction) (320) to determine whether a (load) instruction that is dependent on the order check trigger transaction (store instruction) (320) previously generated a physical address, and in response to determining that the filtering table (208B) does not have an indication that a (load) instruction that is dependent on the order check trigger transaction (store instruction) (320) previously generated a physical address, and bypassing (306) a lookup operation in the out-of-order memory structure to determine whether a (load) instruction that depends on the order check trigger transaction (store instruction) (320) is currently in-flight; and, in response to determining that the filtering table (208B) includes an indication that the (load) instruction that depends on the order check trigger transaction (store instruction) (320) previously generated a physical address, performing (402) a lookup operation in the out-of-order memory structure (210B) to determine whether the (load) instruction that depends on the order check trigger transaction (store instruction) (320) is currently in-flight.

[0040] In the exemplary method of FIG. 7, determining that the dependent instruction generated a physical address (502) is performed by the control logic (204) detecting that a load instruction generated a physical address by the address generation unit (202B). Each time the control logic (204) is notified that the address generation unit (202B) has generated a physical address for a load instruction, the filtering table (208B) of the OOB CAM (210B) is updated. Specifically, in the exemplary method of FIG. 7, indicating that the dependent instruction generated a physical address (504) in an entry in the filtering table (208B) associated with the target address of the dependent instruction is performed by the control logic (204) using a subset of bits of the target address (i.e., a portion of the physical address or logical address) of the load instruction as an identification of an entry in the filtering table (208B) of the OOB CAM (210B). The entry represents a range of target addresses and is marked with 0x03. This action indicates that there is an in-flight load instruction that targets an address within the indicated entry range.

[0041] In the exemplary method of FIG. 7, shifting (506) table entries in the filtering table (208B) in response to detecting that a particular slot has been reused in the program-order deallocated queue is accomplished by the control logic (204) detecting that a pre-programmed slot in the load tracking queue (206B) has been reused. The load tracking queue (206B) is a bit vector indexed by load ID that is allocated (in program order) at dispatch time and deallocated (again in program order) at retirement time. The load tracking queue (206B) sets a bit if the corresponding load ID is reserved by an in-flight load. The load tracking queue (206B) is managed as a first-in-first-out queue, and upon a pipeline flush, the load tracking queue (206B) is cleared with the load ID of the violating load or the load ID of the oldest load closest to the violating instruction or micro-op that triggered the pipeline flush.

[0042] In the exemplary method of Figure 7, receiving an order check trigger transaction (320) is implemented by the control logic (204) detecting that a store instruction has generated a physical address by the address generation unit (202B). The control logic (204) queries a filtering table (208B) of the OOB CAM (210B) each time it is notified that the address generation unit (202B) has generated a physical address for a store instruction. In the exemplary method of Figure 7, querying (304) the filtering table (208B) using a target address of the order check trigger transaction (320) to determine whether an instruction dependent on the order check trigger transaction (320) has previously generated a physical address is implemented by the control logic (204) querying the filtering table (208B) using a target address of the store instruction to determine whether a load instruction has previously generated a physical address in the same range of the target address of the store instruction.

[0043] 7, determining that the filtering table (208B) does not have an indication that an instruction dependent on the order check trigger transaction (320) previously generated a physical address is performed by the control logic (204) accessing the OOB CAM filtering table (208B) with a portion of the target address of the store instruction and reading a zero entry. As a result, the control logic (204) determines that the associated entry in the filtering table (208B) does not have an indication that a load instruction for the same target address range previously generated a physical address by the address generation unit (202B).

[0044] In the example method of FIG. 7 , bypassing (306) a lookup operation in an out-of-order memory structure to determine whether an instruction dependent on an order-check trigger transaction (320) is currently in-flight is implemented by the control logic (204) bypassing a lookup operation in the OOB CAM (210B) to determine whether a load instruction is currently in-flight (i.e., whether data has been loaded from a physical address targeted by an in-flight load).

[0045] 7, determining that the filtering table (208B) includes an indication that an instruction dependent on the order check trigger transaction (320) previously generated a physical address is performed by the control logic (204) accessing the OOB CAM filtering table (208B) using a portion of the target address of the store instruction and reading a non-zero entry, such that the control logic (204) determines that the associated entry in the filtering table (208B) includes an indication that a load instruction for the same target address range previously generated a physical address by the address generation unit (202B).

[0046] In the example method of FIG. 7, performing (402) a lookup operation in an order violation memory structure (210B) to determine whether an instruction dependent on an order check trigger transaction (320) is currently in-flight is accomplished by the control logic (204) performing a CAM lookup operation on the OOB CAM (210B) to determine whether a store instruction is subject to an order violation.

[0047] Figure 8 is a flow chart illustrating an exemplary method for address-based filtering for load / store speculation according to an embodiment in the context of a LOQ CAM. Similar to a combination of Figures 3, 4, and 5, Figure 8 includes maintaining (302) a filtering table including table entries associated with a range of addresses, including detecting (502) that a dependent (first load) instruction generated a physical address, indicating (504) that the dependent (first load) instruction generated a physical address in an entry of the filtering table (208C) associated with a target address of the dependent (first load) instruction, and shifting (506) the table entry in the filtering table (208C) in response to detecting that a particular slot has been reused in the program order deallocated queue.FIG. 8 further illustrates the process of, in response to receiving an order check trigger transaction (second load instruction) (320), querying (304) a filtering table (208C) using a target address of the order check trigger transaction (second load instruction) (320) to determine whether a (first load) instruction dependent on the order check trigger transaction (second load instruction) (320) previously generated a physical address, and, in response to determining that the filtering table (208C) does not have an indication that a (first load) instruction dependent on the order check trigger transaction (second load instruction) (320) previously generated a physical address, querying (304) a filtering table (208C) using a target address of the order check trigger transaction (second load instruction) (320) to determine whether a (first load) instruction dependent on the order check trigger transaction (second load instruction) (320) previously generated a physical address. and bypassing (306) a lookup operation in the out-of-order memory structure to determine whether a (first load) instruction dependent on the order check trigger transaction (second load instruction) (320) is currently in-flight; and performing (402) a lookup operation in the out-of-order memory structure (210C) to determine whether a (first load) instruction dependent on the order check trigger transaction (second load instruction) (320) is currently in-flight in response to determining that the filtering table (208C) includes an indication that the (first load) instruction dependent on the order check trigger transaction (second load instruction) (320) previously generated a physical address.

[0048] In the exemplary method of FIG. 8, detecting (502) that the dependent instruction generated a physical address is performed by the control logic (204) detecting that the load instruction generated a physical address by the address generation unit (202C). The control logic (204) updates the filtering table (208C) of the LOQ CAM (210C) each time the control logic (204) is notified that the address generation unit (202C) has generated a physical address for a load instruction. Specifically, in the exemplary method of FIG. 8, indicating (504) that the dependent instruction generated a physical address in an entry of the filtering table (208C) associated with the target address of the dependent instruction is performed by the control logic (204) using a subset of bits of the target address (i.e., a portion of the physical address or logical address) of the load instruction as an identification of an entry in the filtering table (208C) of the LOQ CAM (210C). This entry represents a range of target addresses and is marked with 0x03. This action indicates that there is an in-flight load instruction that targets an address within the indicated entry range.

[0049] 8, shifting (506) a table entry in the filtering table (208C) in response to detecting that a particular slot has been reused in the program order deallocated queue is accomplished by the control logic (204) detecting that a pre-programmed slot in the load tracking queue (206C) has been reused. In some embodiments, the load tracking queue (206C) is used as a filtering table shift trigger in both the OOB CAM context and the LOQ CAM context.

[0050] In the exemplary method of Figure 8, receiving an order check trigger transaction (320) is performed by the control logic (204) detecting that a cache probe or cache eviction has occurred. Each time the control logic (204) is notified that a cache probe or cache eviction has occurred, the control logic (204) queries a filtering table (208C) of the LOQ CAM (210B). In the exemplary method of Figure 8, querying (304) a filtering table (208C) using a target address of the order check trigger transaction (320) to determine whether an instruction dependent on the order check trigger transaction (320) previously generated a physical address is performed by the control logic (204) querying the filtering table (208C) using a target address of the cache probe victim or cache eviction victim to determine whether a load instruction previously generated a physical address in the same range of target addresses of the cache probe victim or cache eviction victim.

[0051] 8, determining that the filtering table (208C) does not have an indication that an instruction dependent on the order check trigger transaction (320) previously generated a physical address is performed by the control logic (204) accessing the LOQ CAM filtering table (208C) using a portion of the target address of the cache probe and reading a zero entry. As a result, the control logic (204) determines that the associated entry in the filtering table (208B) does not have an indication that a load instruction for the same target address range previously generated a physical address by the address generation unit (202C).

[0052] In the example method of FIG. 8 , bypassing (306) a lookup operation in an out-of-order memory structure to determine whether an instruction dependent on an order-check trigger transaction (320) is currently in-flight is implemented by the control logic (204) bypassing a lookup operation in the LOQ CAM (210C) to determine whether a load instruction is currently in-flight (i.e., whether data has been loaded from a physical address targeted by an in-flight load).

[0053] 8, determining that the filtering table (208C) contains an indication that an instruction dependent on the order check trigger transaction (320) previously generated a physical address is performed by the control logic (204) accessing the LOQ CAM filtering table (208C) using a portion of the target address of the cache probe and reading a non-zero entry, such that the control logic (204) determines that the associated entry in the filtering table (208C) contains an indication that a load instruction for the same target address range previously generated a physical address by the address generation unit (202C).

[0054] In the example method of FIG. 8, performing (402) a lookup operation in an order violation memory structure (210C) to determine whether an instruction dependent on an order check trigger transaction (320) is currently in-flight is accomplished by the control logic (204) performing a CAM lookup operation on the LOQ CAM (210C) to determine whether a cache probe victim or a cache eviction victim is subject to a memory order violation.

[0055] In light of the above discussion, the reader will appreciate that advantages of address-based filtering for load / store speculation according to embodiments include the following: Improve the operation of a computing system by maintaining a filtering table for incoming order check trigger transactions (e.g., load instructions, store instructions, cache probes, cache evictions) and in some circumstances being able to use inexpensive filtering table accesses to identify when dependent instructions are not present, thereby improving the power efficiency of the computing system. Improving computing system operation by reducing dynamic power consumption without performance degradation and improving power efficiency of load / store micro-operations in processor cores.

[0056] Exemplary embodiments are described primarily in the context of a computer system that is fully functional with respect to address-based filtering for load / store speculation. Aspects of the present disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the present disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, may be implemented by computer readable program instructions.

[0057] The flowcharts and block diagrams in the drawings represent the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or part of instructions that includes one or more executable instructions for performing a particular logical function(s). In some alternative implementations, the functions described in the blocks may be performed out of the order described in the drawings. For example, two blocks shown in succession may in fact be executed substantially simultaneously or may sometimes be executed in the reverse order, depending on the functionality involved. It should also be noted that each block in the block diagrams and / or flowchart illustrations, as well as combinations of blocks in the block diagrams and / or flowchart illustrations, may be implemented by a system based on special purpose hardware that performs a particular function or operation, or may be implemented by a combination of special purpose hardware and computer instructions.

[0058] The above describes a method of address-based filtering for load / store speculation, the method including maintaining a filtering table including table entries associated with a range of addresses; in response to receiving an order check trigger transaction, querying the filtering table using a target address of the order check trigger transaction to determine whether an instruction dependent on the order check trigger transaction has previously generated the physical address; and in response to determining that the filtering table does not have an indication that an instruction dependent on the order check trigger transaction has previously generated the physical address, bypassing a lookup operation in an order violation memory structure to determine whether an instruction dependent on the order check trigger transaction is currently in-flight.

[0059] The method includes, in response to determining that the filtering table includes an indication that an instruction dependent on the order check triggering transaction previously generated a physical address, performing a lookup operation in an order violation memory structure to determine whether an instruction dependent on the order check triggering transaction is currently in-flight.

[0060] The above also describes a load store unit of a processor, a processor and an apparatus using address-based filtering for load / store speculation, the load store unit includes a filtering table including table entries associated with a range of addresses, the control logic of the load store unit maintains the filtering table, in response to receiving an order check trigger transaction, queries the filtering table using a target address of the order check trigger transaction to determine whether an instruction dependent on the order check trigger transaction has previously generated the physical address, and in response to determining that the filtering table does not have an indication that the instruction dependent on the order check trigger transaction has previously generated the physical address, bypasses a lookup operation in an out-of-order memory structure to determine whether an instruction dependent on the order check trigger transaction is currently in-flight.

[0061] In response to determining that the filtering table contains an indication that an instruction prior to the order check triggering transaction previously generated a physical address, the control logic performs a lookup operation in the order violation memory structure to determine whether an instruction dependent on the order check triggering transaction is currently in-flight.

[0062] Maintaining a filtering table with table entries associated with a range of addresses may include detecting that a dependent instruction generated the physical address and indicating that the dependent instruction generated the physical address in an entry of the filtering table associated with a target address of the dependent instruction. Maintaining a filtering table with table entries associated with a range of addresses may also include shifting a table entry in the filtering table in response to detecting that a particular slot has been reused in a program-order deallocated queue. The program-order deallocated queue may be a store queue or a load tracking queue. Maintaining a filtering table with table entries associated with a range of addresses may also include shifting a table entry in the filtering table in response to detecting a reuse of a preselected reorder buffer ID. The filtering table may include a plurality of separate tables.

[0063] The order check trigger transaction may be a load instruction. Thus, receiving the order check trigger transaction may include detecting that a load instruction generated the physical address, querying a filtering table using a target address of the order check trigger transaction to determine whether an instruction dependent on the order check trigger transaction previously generated the physical address may include querying a filtering table using a target address of the load instruction to determine whether a store instruction previously generated the physical address, determining that the filtering table does not have an indication that an instruction dependent on the order check trigger transaction previously generated the physical address may include determining that the filtering table does not have an indication that a store instruction previously generated the physical address, and bypassing a lookup operation in an order violation memory structure to determine whether an instruction dependent on the order check trigger transaction is currently in-flight may include bypassing a lookup operation in a store-to-load forwarding memory structure to determine whether a store is currently in-flight.

[0064] The order check trigger transaction may be a store instruction. Thus, receiving the order check trigger transaction may include detecting that a store instruction generated the physical address, querying a filtering table using a target address of the order check trigger transaction to determine whether an instruction dependent on the order check trigger transaction previously generated the physical address may include querying a filtering table using a target address of the store instruction to determine whether a load instruction previously generated the physical address, determining that the filtering table does not have an indication that an instruction dependent on the order check trigger transaction previously generated the physical address may include determining that the filtering table does not have an indication that a load instruction previously generated the physical address, and bypassing a lookup operation in an out-of-order memory structure to determine whether an instruction dependent on the order check trigger transaction is currently in-flight may include bypassing a lookup operation in an out-of-order buffer memory structure to determine whether a load is currently in-flight.

[0065] The reader will appreciate that the steps described herein may be performed in a variety of ways, and that no particular order is required. It will be further appreciated from the above description that modifications and changes can be made in various embodiments of the present disclosure. The description herein is for illustrative purposes only and is not to be construed in a limiting sense. The scope of the present disclosure is limited only by the language of the following claims.

Claims

1. 1. A load-store unit of a processor with address-based filtering for load / store speculation, comprising: The load store unit includes: a filtering table including table entries associated with ranges of addresses; The control logic of the load store unit includes: maintaining said filtering table; in response to receiving an order check trigger transaction, querying the filtering table using a target address of the order check trigger transaction to determine whether an instruction dependent on the order check trigger transaction previously generated a physical address; in response to determining that the filtering table does not have an indication that an instruction dependent on the order check triggering transaction previously generated a physical address, bypassing a lookup operation in an order violation memory structure to determine whether an instruction dependent on the order check triggering transaction is currently in-flight; [0023] Load store unit.

2. The control logic is further configured to, in response to determining that the filtering table includes an indication that an instruction dependent on the order check triggering transaction previously generated a physical address, perform a lookup operation in an order violation memory structure to determine whether an instruction dependent on the order check triggering transaction is currently in-flight. The load store unit of claim 1 .

3. The control logic includes: Detecting that a dependent instruction generated a physical address; indicating in an entry in a filtering table associated with the target address of the dependent instruction that the dependent instruction generated a physical address; and further configured to: The load store unit of claim 1 .

4. the control logic is further configured to shift the table entries in the filtering table in response to detecting that a particular slot has been reused in a queue that has been deallocated in program order. The load store unit of claim 1 .

5. the queues deallocated in program order are queues selected from the group consisting of store queues and load tracking queues. The load store unit of claim 4.

6. the control logic is further configured to shift the table entries in the filtering table in response to detecting a reuse of a preselected reorder buffer ID. The load store unit of claim 1 .

7. the filtering table includes a plurality of individual tables; The load store unit of claim 1 .

8. the order-check trigger transaction is a load instruction; receiving the order check trigger transaction includes detecting that the load instruction generated a physical address; Querying the filtering table using a target address of the order check triggering transaction to determine whether an instruction dependent on the order check triggering transaction previously generated a physical address includes querying the filtering table using the target address of the load instruction to determine whether a store instruction previously generated a physical address; determining that the filtering table does not have an indication that an instruction dependent on the order check trigger transaction previously generated a physical address includes determining that the filtering table does not have an indication that the store instruction previously generated a physical address; bypassing a lookup operation in an order-violating memory structure to determine whether an instruction dependent on the order-check trigger transaction is currently in-flight includes bypassing the lookup operation in a store-to-load forwarding memory structure to determine whether the store instruction is currently in-flight. The load store unit of claim 1 .

9. the order-check trigger transaction is a store instruction; receiving the order check trigger transaction includes detecting that the store instruction generated a physical address; Querying the filtering table using a target address of the order check triggering transaction to determine whether an instruction dependent on the order check triggering transaction previously generated a physical address includes querying the filtering table using the target address of the store instruction to determine whether a load instruction previously generated a physical address; determining that the filtering table does not have an indication that an instruction dependent on the order check trigger transaction previously generated a physical address includes determining that the filtering table does not have an indication that the load instruction previously generated a physical address; bypassing a lookup operation in an out-of-order memory structure to determine whether an instruction dependent on the order-check trigger transaction is currently in-flight includes bypassing the lookup operation in an out-of-order buffer memory structure to determine whether the load instruction is currently in-flight. The load store unit of claim 1 .

10. the order check trigger transaction is a cache event; receiving the order check trigger transaction includes detecting that the cache event generated a physical address; Querying the filtering table using a target address of the order check trigger transaction to determine whether an instruction dependent on the order check trigger transaction previously generated a physical address includes querying the filtering table using the target address of the cache event to determine whether a load instruction previously generated a physical address; determining that the filtering table does not have an indication that an instruction dependent on the order check trigger transaction previously generated a physical address includes determining that the filtering table does not have an indication that the load instruction previously generated a physical address; bypassing a lookup operation in an order violation memory structure to determine whether an instruction dependent on the order check trigger transaction is currently in flight includes bypassing the lookup operation in a load order queue memory structure to determine whether the load instruction is currently in flight. The load store unit of claim 1 .

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