System Direct Memory Access Engine Offload

Abstract

A system, device, and method for direct memory access are provided. A system direct memory access (SDMA) device located on a processor die sends a message including the physical addresses of a source buffer and a destination buffer and the size of the data transfer to a data fabric device. The data fabric device sends an instruction including the physical addresses of the source and destination buffers and the size of the data transfer to a first agent device. Each of the first agent devices reads a portion of the source buffer from a memory device at the physical address of the source buffer. Each of the first agent devices sends a portion of the source buffer to any of the second agent devices. Each of the second agent devices writes a portion of the source buffer to a destination buffer.

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims the benefit of U.S. Patent Application No. 16 / 723,709, filed December 20, 2019, the contents of which are incorporated herein by reference. [Background technology]

[0002] A system direct memory access (SDMA) engine is a device that coordinates direct memory access (DMA) transfers of data between devices and memory or between different locations in memory in a computer system. The SDMA engine is typically located on a processor, such as a graphics processor (GPU), and receives commands from an application running on the processor. Based on the commands, the SDMA engine reads data from an SDMA source (e.g., a first memory buffer defined in main memory) and writes data to an SDMA destination (e.g., a second buffer defined in main memory).

[0003] The SDMA source and the SDMA destination are sometimes located on different physical devices. In a multiprocessor system, the SDMA source and the SDMA destination are sometimes located on different devices associated with different processors. In such cases, the SDMA engine resolves the virtual address to obtain the physical address and issues remote read and / or write commands to perform the DMA transfer.

[0004] A more detailed understanding may be had from the following description, given by way of example in conjunction with the accompanying drawings, in which: [Brief description of the drawings]

[0005] [Figure 1] FIG. 1 is a block diagram of an example device capable of implementing one or more features of the present disclosure. [Diagram 2]FIG. 1 is a block diagram illustrating a portion of an exemplary computing system. [Diagram 3] FIG. 1 is a block diagram illustrating a portion of an exemplary multi-processor computing system. [Figure 4] 4 is a message sequence chart illustrating exemplary direct memory access messaging. [Diagram 5] 4 is a flowchart illustrating an exemplary method of direct memory access. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0006] In some embodiments, a computing system configured for direct memory access is provided. The system includes an SDMA device on a processor die. The SDMA device sends a message to a data fabric device. The message includes a physical address of a source buffer, a physical address of a destination buffer, and a size of a data transfer from the source buffer to the destination buffer. The data fabric device sends one or more instructions to a first agent device. The instructions include a physical address of the source buffer, a physical address of the destination buffer, and a size of the data transfer. Each of the first agent devices reads a portion of the source buffer from a memory device at the physical address of the source buffer. Each of the first agent devices also sends the portion of the source buffer to one of the second agent devices. Each of the second agent devices operates a memory controller to write the portion of the source buffer to the destination buffer.

[0007] In some embodiments, the SDMA device receives one or more instructions from a processor on the processor die. The one or more instructions indicate a virtual address of a source buffer and a virtual address of a destination buffer. The SDMA device translates the virtual address of the source buffer to a physical address of the source buffer. The SDMA device translates the virtual address of the destination buffer to a physical address of the destination buffer. In some embodiments, the data fabric device includes a miscellaneous (MISC) functional block of the data fabric. In some embodiments, the agent device includes a coherent slave device of the data fabric. In some embodiments, the first agent device is on the processor die and the second agent device is on a remote processor die. In some embodiments, the second agent device is on the processor die and the first agent device is on a remote processor die. In some embodiments, each of the first agent devices stores a portion of the source buffer in a local buffer before sending the portion of the source buffer to one of the second agent devices. In some embodiments, a coherent link is included between the processor die and the remote processor die, and the first agent device communicates with the second agent device over the coherent link. In some embodiments, each of the first agent devices operates a memory controller to read a portion of the source buffer from a memory device at a physical address of the source buffer. In some embodiments, the data fabric device broadcasts one or more instructions to the first agent devices.

[0008] Some embodiments provide a method for direct memory access. The method includes sending a message from a system direct memory access (SDMA) device located on a processor die to a data fabric device. The message includes a physical address of a source buffer, a physical address of a destination buffer, and a size of a data transfer from the source buffer to the destination buffer. The method also includes sending one or more instructions by the data fabric device to a first agent device. The one or more instructions include a physical address of the source buffer, a physical address of the destination buffer, and a size of the data transfer. The method also includes each of the first agent devices reading a portion of the source buffer from a memory device at the physical address of the source buffer. The method also includes each of the first agent devices sending a portion of the source buffer to a second agent device. The method also includes each of the second agent devices writing a portion of the source buffer to the destination buffer.

[0009] Some embodiments include an SDMA device receiving one or more instructions from a processor on the processor die. The instructions indicate a virtual address of a source buffer and a virtual address of a destination buffer. Some embodiments include an SDMA device translating the virtual address of the source buffer to a physical address of the source buffer. Some embodiments include an SDMA device translating the virtual address of the destination buffer to a physical address of the destination buffer. In some embodiments, the data fabric device includes a miscellaneous (MISC) functional block of the data fabric. In some embodiments, the agent device includes a coherent slave device of the data fabric. In some embodiments, a first agent device is on the processor die and a second agent device is on a remote processor die. In some embodiments, a second agent device is on the processor die and a first agent device is on a remote processor die. Some embodiments include each of the first agent devices storing a portion of the source buffer in a local buffer before transmitting the portion of the source buffer to one of the second agent devices. Some embodiments include a first agent device communicating with a second agent device over a coherent link between the processor die and the remote processor die. In some embodiments, each of the first agent devices includes a data fabric device that operates a memory controller to read a portion of the source buffer from a memory device at a physical address of the source buffer, and broadcasts one or more instructions to the first agent devices.

[0010] 1 is a block diagram of an example device 100 capable of implementing one or more features of the disclosure. Device 100 may include, for example, a computer, a gaming device, a handheld device, a set-top box, a television, a mobile phone, or a tablet computer. Device 100 includes a processor 102, a memory 104, a storage 106, one or more input devices 108, and one or more output devices 110. Device 100 may also include optional input drivers 112 and output drivers 114. It should be understood that device 100 may include additional components not shown in FIG. 1.

[0011] In various alternatives, the processor 102 may include a central processing unit (CPU), a graphics processing unit (GPU), a CPU and a GPU located on the same die, or one or more processor cores, each of which may be a CPU or a GPU. In various alternatives, the memory 104 may be located on the same die as the processor 102 or may be separate from the processor 102. The memory 104 may include volatile or non-volatile memory (e.g., random access memory (RAM), dynamic RAM, cache).

[0012] Storage 106 includes fixed or removable storage (e.g., hard disk drive, solid state drive, optical disk, flash drive). Input devices 108 include, but are not limited to, a keyboard, a keypad, a touch screen, a touch pad, a detector, a microphone, an accelerometer, a gyroscope, a biometric scanner, or a network connection (e.g., a wireless local area network card for transmitting and / or receiving wireless IEEE 802 signals). Output devices 110 include, but are not limited to, a display, a speaker, a printer, a haptic feedback device, one or more lights, an antenna, or a network connection (e.g., a wireless local area network card for transmitting and / or receiving wireless IEEE 802 signals).

[0013] The input driver 112 communicates with the processor 102 and the input device 108, allowing the processor 102 to receive input from the input device 108. The output driver 114 communicates with the processor 102 and the output device 110, allowing the processor 102 to send output to the output device 110. It should be noted that the input driver 112 and the output driver 114 are optional components, and that the device 100 operates similarly when the input driver 112 and the output driver 114 are not present. The output driver 114 includes an accelerated processing device (APD) 116 coupled to a display device 118. The APD accepts computational and graphics rendering commands from the processor 102, processes the computational and graphics rendering commands, and provides pixel output to the display device 118 for display. As described in more detail below, the APD 116 includes one or more parallel processing units that perform computations according to a single instruction, multiple data (SIMD) paradigm. As follows, although various functions are described herein as being performed by or in cooperation with APD 116, in various alternatives, the functions described as being performed by APD 116 are additionally or alternatively performed by other computing devices having similar capabilities that are not driven by a host processor (e.g., processor 102) and that provide graphical output to display device 118. For example, it is contemplated that any processing system that performs processing tasks according to the SIMD paradigm may perform the functions described herein. Alternatively, it is contemplated that computing systems that do not perform processing tasks according to the SIMD paradigm may perform the functions described herein.

[0014] 2 is a block diagram illustrating a portion of an exemplary computing system 200. In some examples, computing system 200 is implemented using some or all of device 100 as shown and described with respect to FIG. 1. Computing system 200 includes a first semiconductor die 205. Semiconductor die 205 includes one or more processors 210A-210N, an input / output (I / O) interface 220, an interconnect 230, a memory controller(s) 240, and a network interface 250. In other examples, computing system 200 includes additional components, different components, and / or is configured in a different manner.

[0015] In some embodiments, each of the processors 210A-210N includes one or more processing devices. In this example, at least one of the processors 210A-210N includes one or more general-purpose processing devices, such as a CPU. In some embodiments, such processing devices are implemented using the processor 102 as shown and described with respect to FIG. 1. In this example, at least one of the processors 210A-210N includes one or more data parallel processors. Examples of data parallel processors include GPUs, digital signal processors (DSPs), field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), etc. In some embodiments, such processing devices are implemented using the APD 116 as shown and described with respect to FIG. 1.

[0016] In some embodiments, each processor includes a cache subsystem with one or more levels of cache. In some embodiments, each core complex 210A-210N includes a cache (e.g., a level 3 (L3) cache) that is shared among multiple processor cores.

[0017] Memory controller 240 includes at least one memory controller accessible by core complexes 210A-210N, for example, via interconnect 230. Memory controller 240 includes one or more of any suitable type of memory controller. Each of the memory controllers is coupled to (or otherwise in communication with) and controls access to any number and type of memory devices (not shown). In some embodiments, such memory devices include dynamic random access memory (DRAM), static random access memory (SRAM), NAND flash memory, NOR flash memory, ferroelectric random access memory (FeRAM), and / or other suitable memory devices. Interconnect 230 includes any computer communication medium suitable for communication between the devices shown in FIG. 2, such as a bus, a data fabric, or the like.

[0018] I / O interface 220 includes one or more I / O interfaces (e.g., Peripheral Component Interconnect (PCI) bus, PCI Extended (PCI-X), PCI Express (PCIe) bus, Gigabit Ethernet (GBE) bus, Universal Serial Bus (USB), etc.). In some embodiments, I / O interface 220 is implemented using input drivers 112 and / or output drivers 114 as shown and described with respect to FIG. 1. Various types of peripheral devices may be coupled to I / O interface 220. Such peripheral devices include, but are not limited to, displays, keyboards, mice, printers, scanners, joysticks or other types of game controllers, media recording devices, external storage devices, network interface cards, etc. In some embodiments, such peripheral devices are implemented using input devices 108 and / or output devices 110 as shown and described with respect to FIG. 1.

[0019] 3 is a block diagram illustrating a portion of an exemplary multiprocessor computing system 300. System 300, or portions thereof, can be implemented using some or all of semiconductor die 205 (as shown and described with respect to FIG. 2) and / or device 100 (as shown and described with respect to FIGS. 1 and 2).

[0020] System 300 includes one or more processors 310A-310N and one or more memory controllers 340A-340N that communicate with processors 310A-310N (e.g., via other components) via an interconnect 330. In some examples, processors 310A-310N are coupled to interconnect 330 via coherent masters 315A-315N, and memory controllers 340A-340N are coupled to interconnect 330 via coherent slaves 345A-345N. Interconnect 330, coherent masters 315A-315N, and coherent slaves 345A-345N form part of a data fabric that facilitates communication between components of system 300.

[0021] System 300 includes, in this example, semiconductor die 0 and semiconductor die 1, and coherent link 350 extends a data fabric across both dies via interconnect 330 and I / O interfaces 360A-360B (which also form part of the data fabric). Interconnect 330 includes any computer communication medium suitable for communication between the devices shown in FIG. 3, such as a bus, a data fabric, etc. Each of processors 310A-310N includes one or more processor cores (e.g., a CPU and / or GPU, as described with respect to FIG. 2). Each of processors 310A-310N also includes a corresponding SDMA engine 370A-370N.

[0022] Each processor 310A-310N communicates with a corresponding coherent master 315A-315N. In some embodiments, a coherent master is an agent that handles traffic flowing on an interconnect (e.g., interconnect 330) and manages coherency for a connected CPU or core complex. In some embodiments, to manage coherency, a coherent master receives and processes coherency-related messages and probes and generates and sends coherency-related requests and probes.

[0023] Each processor 310A-310N communicates with one or more coherent slaves 345A-345N via a corresponding coherent master 315A-315N and via interconnect 330. A coherent slave is an agent device that manages coherency for a memory controller (e.g., a memory controller connected to the coherent slave). In some embodiments, to manage coherency, a coherent slave receives and processes requests and probes targeted to a corresponding memory controller.

[0024] 3, the processor 310A communicates with a coherent master 315A and a coherent slave 345A via interconnect 330. The coherent slave (CS) 345A communicates with a memory controller (MC) 340A, which controls a memory device (e.g., a main memory DRAM device). In some embodiments, each processor 310A-310N communicates with any suitable number of memory controllers 340A-340N via a corresponding coherent master 315A-315N and a corresponding coherent slave 340A-340N.

[0025] A probe includes a message passed from a coherency point (e.g., a coherent slave) to one or more caches in a computer system, requesting a response indicating whether the cache has a copy of the data block, and in some embodiments indicating the cache state in which the cache places the block of data. In some embodiments, when a coherent slave receives a memory request targeted to its corresponding memory controller (e.g., a memory request for data stored at an address or region of addresses in memory controlled by a memory controller for which the coherent slave manages coherency), the coherent slave performs a lookup (e.g., a tag-based lookup) into its corresponding cache directory to determine whether the request targets a memory address or region cached in at least one cache line of any cache subsystem.

[0026] SDMA engines 370A-370N coordinate DMA transfers of data between devices and memory in system 300 or between different locations in memory. SDMA engines 370A-370N can receive instructions from their corresponding processors 310A-310N. Based on the received instructions, in some cases, SDMA engines 370A-370N read and buffer data from any memory via the data fabric and write buffered data to any memory via the data fabric. In some embodiments, based on the received instructions, SDMA engines 370A-370N send messages to data fabric devices, such as miscellaneous (MISC) blocks of the data fabric, with instructions to perform DMA.

[0027] MISC blocks 380A-380B are data fabric devices that handle other functions. In some cases, MISC blocks 380A-380B host power management and interrupt functions. In some cases, MISC blocks 380A-380B host SDMA functions as described herein. For example, MISC block 380A receives a message from SDMA engine 370A (e.g., via an agent device such as coherent master 315A) with instructions to perform a DMA transfer of a specified size from a source buffer of physical addresses to a destination buffer of physical addresses. In this example, MISC block 380A broadcasts a corresponding command to agent devices (e.g., coherent slaves 345A-345D) on the same die to perform the DMA transfer, for example, as described further herein.

[0028] In some embodiments, interconnect 330 is connected to and / or communicates with other components not shown in Figure 3 for ease of illustration. For example, in some embodiments, interconnect 330 includes a connection to one or more network interfaces 250 as shown and described with respect to Figure 2.

[0029] FIG. 4 is a message sequence chart illustrating exemplary direct memory access messaging 400 that can be implemented between devices of system 300, for example, as shown and described with respect to FIG.

[0030] SDMA 370A coordinates DMA from a source memory buffer physically located in the local memory of processor 310A (i.e., accessible via on-die memory controllers 340A-440B) to a destination buffer physically located in the local memory of processor 310N (i.e., accessible via on-die memory controllers 340E-340N). This is referred to herein as a "local read, remote write" DMA. The corresponding "remote read, local write" operation is performed by rearranging messaging accordingly. Similarly, the corresponding "local read, local write" or "remote read, remote write" operation is performed by rearranging messaging accordingly.

[0031] Processor 310A sends an SDMA command, including the virtual address of the source buffer, the virtual address of the destination buffer, and the size of the data transfer, to SDMA 370A in instruction 405. Note that instruction 405, in some embodiments, includes multiple commands and / or messages.

[0032] SDMA 370A performs virtual to physical address translation of the source and destination buffers in step 410 to obtain the physical address of the source buffer and the physical address of the destination buffer, respectively.

[0033] SDMA 370A sends the physical address of the source buffer, the physical address of the destination buffer, and the size of the data transfer in an SDMA message 415 to MISC block 380A.

[0034] MISC block 380A sends an SDMA command broadcast 420, which includes the physical address of the source buffer, the physical address of the destination buffer, and the size of the data transfer, to all coherent slave devices on die 0. In this example, CS 345A-D are on die 0.

[0035] Each of the CSs 345A-345D sends a read command 425 to its associated local MC 340A-340D. Each MC 340A-340D reads the corresponding portion of the source buffer in step 430 and returns the source buffer data to the CS 340A-340D in step 435. Each CS 340A-340D buffers the source buffer data in its local buffer 440 for transmission (and / or as needed).

[0036] Each of the CSs 345A-345D sends a remote write command 445 to a remote CS 345E-345N, which in turn sends a write command 450 to its associated MC 340E-340N. Each MC 340E-340N writes a corresponding portion of the destination buffer in step 455 and returns an acknowledgement 460 to each of the CSs 345E-345N. In some embodiments, an acknowledgement is only required for the last transfer (i.e., the last write command 450), and thus only one acknowledgement 460 is returned for every write command 450.

[0037] After the destination buffer is completely written, i.e., after the final MC 340E-340N has returned an acknowledgement to each of the CSs 345E-345N, the CS 445E-445N that receives the final acknowledgement (or the only acknowledgement if an acknowledgement is requested only for the last write command 450) returns a cumulative acknowledgement 465 to the CSs 445A-445D. After receiving the cumulative acknowledgement 465, each CS 345A-345D issues a command 470 to the MISC block 380A to indicate completion of the transfer. In some embodiments, the command 470 includes an identification of the transfer (e.g., a transfer ID). Based on the command 470, the MISC block 380A sends an indicator 475 to the SDMA 370A indicating completion of the transfer.

[0038] 5 is a flow chart illustrating an example method for direct memory access. Method 500 can be implemented, for example, in system 300 (shown and described with respect to FIG. 3) and / or in some examples can be implemented using signaling 400 (shown and described with respect to FIG. 4).

[0039] At block 505, SDMA 370A receives an instruction from processor 310A. The instruction may be, for example, an SDMA command that includes a virtual address of a source buffer, a virtual address of a destination buffer, and a size of the data transfer, such as instruction 405 (as shown and described with respect to FIG. 4).

[0040] In block 510, SDMA 370A performs a virtual-to-physical address translation of the source buffer and the destination buffer to obtain a physical address of the source buffer and a physical address of the destination buffer, respectively (e.g., as shown and described with respect to 410 shown and described with respect to FIG. 4).

[0041] At block 515, the SDMA 370A sends the physical address of the source buffer, the physical address of the destination buffer, and the size of the data transfer to the MISC block 380A in block 515 (eg, message 415 shown and described with respect to FIG. 4).

[0042] At block 520, MISC block 380A receives the message and at block 525 sends an SDMA command broadcast (e.g., broadcast 420 shown and described with respect to FIG. 4) including the physical address of the source buffer, the physical address of the destination buffer, and the size of the data transfer to all coherent slave devices on die 0. In this example, CSs 345A-345D are on die 0. In some embodiments, broadcast 420 includes an identification of the transfer (e.g., a transfer ID) to identify the transfer job.

[0043] With the condition 530 that the source buffer is local and the destination buffer is remote, in block 535, each of the local CSs 345A-345D sends a read command (e.g., command 425 shown and described with respect to FIG. 4) to the associated MC 340A-340D such that each MC 340A-340D reads the corresponding portion of the source buffer (if present) and returns the source buffer data to the CS 340A-340D. Each CS 340A-340D buffers the source buffer data in a local buffer for transmission (and / or as needed).

[0044] At block 540, each of the local CSs 345A-345D sends a remote write command to the remote CSs 345E-345N to write the buffer to the remote memory. At block 545, each of the remote CSs 345E-345N sends a write command to the associated MC 340E-340N to cause each MC 340E-340N to write the corresponding portion of the source buffer data to the destination buffer in the associated memory. After writing the corresponding portion of the destination buffer, each MC 340E-340N returns an acknowledgement to each of the CSs 345E-345N.

[0045] At block 550, after the destination buffer is completely written, i.e., after the final MC 340E-340N returns an acknowledgement to each of the CSs 345E-345N, the CS 345E-345N receiving the final acknowledgement returns a cumulative acknowledgement 465 to the local CS 345A-345D. After receiving the cumulative acknowledgement 465, each CS 345A-345D issues a command to the MISC block 380A to indicate completion of the transfer. In some embodiments, the command includes an identification of the transfer (e.g., a transfer ID). Based on the command, the MISC block 380A sends an indication to the SDMA 370A indicating completion of the transfer.

[0046] With condition 530 that the source buffer is remote and the destination buffer is local, each of the local CSs 345A-345D sends a remote read command to the remote CSs 345E-345N in block 555. Based on the remote read command, each of the remote CSs 345E-345N sends a read command to the associated MC 340E-340N in block 560 so that the MC 340E-340N returns the source buffer data to the CSs 345E-345N. The CSs 345E-345N buffer the source buffer data in local buffers for transmission (and / or as needed).

[0047] The remote CSs 345E-345N transmit the buffered data to the local CSs 345A-345D over the coherent link in block 565. The local CSs 345A-345D write the data to the destination buffers at the physical memory addresses via the associated MCs 340A-340D in block 570. After the destination buffers are completely written, i.e., after the last MC 340A-340D returns an acknowledgement to each of the CSs 345A-345D, the CS 345A-345D that receives the last acknowledgement issues a command to the MISC block 380A in block 575 to indicate completion of the transfer. In some embodiments, the command includes an identification of the transfer (e.g., a transfer ID). Based on the command, the MISC block 380A transmits an indication indicating completion of the transfer to the SDMA 370A.

[0048] It should be understood that many variations are possible based on the disclosure herein, and although features and elements have been described above in particular combinations, each feature or element can be used alone without the other features and elements, or in various combinations with or without the other features and elements.

[0049] The various functional units shown in the figures and / or described herein (including, but not limited to, the processor 102, the input driver 112, the input device 108, the output driver 114, the output device 110, and the accelerated processing device 116) may be implemented as a general purpose computer, processor, or processor core, or as a program, software, or firmware stored in a non-transitory computer-readable storage medium or another medium and executable by a general purpose computer, processor, or processor core. The provided methods may be implemented in a general purpose computer, processor, or processor core. Suitable processors include, by way of example, a general purpose processor, a special purpose processor, a conventional processor, a digital signal processor (DSP), multiple microprocessors, one or more microprocessors associated with a DSP core, a controller, a microcontroller, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) circuit, other types of integrated circuits (ICs), and / or state machines. Such processors may be manufactured by configuring a manufacturing process with the results of processing hardware description language (HDL) instructions and other intermediate data, including a netlist (such as instructions that may be stored in a computer-readable medium). The result of such processing may be a maskwork used in a semiconductor manufacturing process to produce a processor implementing features of the present disclosure.

[0050] The methods or flow charts provided herein may be implemented in a computer program, software, or firmware embodied in a non-transitory computer-readable storage medium for execution by a general purpose computer or processor. Examples of non-transitory computer-readable storage media include read-only memory (ROM), random access memory (RAM), registers, cache memory, semiconductor memory devices, magnetic media such as internal hard disks and removable disks, magneto-optical media, and optical media such as CD-ROM disks and digital versatile disks (DVDs).

Claims

1. 1. A computing system configured for direct memory access, comprising: a system direct memory access (SDMA) device disposed on the processor die and configured to send a message to a data fabric device, the message including a physical address of a source buffer, a physical address of a destination buffer, and a size of a data transfer from the source buffer to the destination buffer; a data fabric device configured to send at least one instruction to a first plurality of agent devices, the instruction including a physical address of the source buffer, a physical address of the destination buffer, and a size of the data transfer; a first plurality of agent devices, each configured to read a portion of the source buffer from a memory device at a physical address of the source buffer, and to transmit the portion of the source buffer to one of a second plurality of agent devices; a second plurality of agent devices, each configured to operate a memory controller to write a portion of the source buffer to the destination buffer; system.

2. The SDMA device is receiving at least one instruction from a processor on the processor die indicating a virtual address of the source buffer and a virtual address of the destination buffer; translating a virtual address of the source buffer to a physical address of the source buffer; translating a virtual address of the destination buffer to a physical address of the destination buffer; 4. The method of claim 3, further comprising: The system of claim 1.

3. the data fabric device includes a data fabric miscellaneous (MISC) function block; The system of claim 1.

4. the agent device comprises a coherent slave device of a data fabric; The system of claim 1.

5. the first plurality of agent devices are disposed on the processor die; the second plurality of agent devices are disposed on a remote processor die; The system of claim 1.

6. the second plurality of agent devices are disposed on the processor die; the first plurality of agent devices are disposed on a remote processor die; The system of claim 1.

7. each of the first plurality of agent devices is further configured to store a portion of the source buffer in a local buffer before transmitting the portion of the source buffer to any of the second plurality of agent devices; The system of claim 1.

8. a coherent link between the processor die and a remote processor die; the first plurality of agent devices being further configured to communicate with the second plurality of agent devices via the coherent link. The system of claim 1.

9. each of the first plurality of agent devices is further configured to operate a memory controller to read a portion of the source buffer from the memory device at a physical address of the source buffer; The system of claim 1.

10. the data fabric device is further configured to broadcast the at least one instruction to the first plurality of agent devices. The system of claim 1.

11. 1. A method for direct memory access, comprising: sending a message from a System Direct Memory Access (SDMA) device located on the processor die to a data fabric device, the message including a physical address of a source buffer, a physical address of a destination buffer, and a size of the data transfer from the source buffer to the destination buffer; the data fabric device sending at least one instruction to a first plurality of agent devices, the instruction including a physical address of the source buffer, a physical address of the destination buffer, and a size of the data transfer; each of the first plurality of agent devices reading a portion of the source buffer from a memory device at a physical address of the source buffer; each of the first plurality of agent devices transmitting a portion of the source buffer to one of a second plurality of agent devices; each of the second plurality of agent devices writing a portion of the source buffer to the destination buffer; method.

12. receiving, by the SDMA device, at least one instruction from a processor on the processor die, the instruction indicating a virtual address of the source buffer and a virtual address of the destination buffer; the SDMA device converting a virtual address of the source buffer to a physical address of the source buffer; the SDMA device translating a virtual address of the destination buffer to a physical address of the destination buffer.

12. The method of claim 11.

13. the data fabric device includes a data fabric miscellaneous (MISC) function block; 12. The method of claim 11.

14. the agent device comprises a coherent slave device of a data fabric; 12. The method of claim 11.

15. the first plurality of agent devices are disposed on the processor die; the second plurality of agent devices are disposed on a remote processor die; 12. The method of claim 11.

16. the second plurality of agent devices are disposed on the processor die; the first plurality of agent devices are disposed on a remote processor die; 12. The method of claim 11.

17. and each of the first plurality of agent devices storing a portion of the source buffer in a local buffer before transmitting the portion of the source buffer to any of the second plurality of agent devices.

12. The method of claim 11.

18. the first plurality of agent devices communicating with the second plurality of agent devices via a coherent link between the processor die and a remote processor die.

12. The method of claim 11.

19. each of the first plurality of agent devices further comprising: operating a memory controller to read a portion of the source buffer from a memory device at a physical address of the source buffer; 12. The method of claim 11.

20. the data fabric device broadcasting the at least one instruction to the first plurality of agent devices.

12. The method of claim 11.

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