Semiconductor device, semiconductor device manufacturing method, and power conversion device

Abstract

The present invention provides a technology capable of improving the insulation reliability of a semiconductor device. The semiconductor device includes a termination well region surrounding an active region in a plan view, and an FLR region surrounding the termination well region in a plan view. The FLR region surrounds the termination well region in a plan view, and includes a plurality of floating wells having a floating potential that are spaced apart from each other and nested, and the number of the plurality of floating wells is equal to or greater than VR / 100 for a rated voltage VR [V] of the semiconductor device.

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device, a method for manufacturing a semiconductor device, and a power conversion device. [Background technology]

[0002] Various techniques have been proposed for ensuring the breakdown voltage performance of vertical semiconductor devices such as Schottky Barrier Diodes (SBDs) used in power semiconductor devices, etc. For example, Patent Document 1 proposes a technique for providing a guard ring region (also called a termination well region) made of multiple p-type semiconductor layers in a termination region that is the outer periphery of an n-type semiconductor layer. With this configuration, the electric field generated inside the semiconductor layer when a reverse voltage is applied to the main electrode of the semiconductor device is alleviated by a depletion layer formed by a pn junction between the n-type semiconductor layer and the p-type guard ring region.

[0003] On the other hand, even if the electric field generated inside the semiconductor layer is effectively alleviated in the guard ring region, a high electric field may occur outside the semiconductor layer. Therefore, for example, in Patent Document 2, the guard ring region is covered with a surface protection film such as polyimide or sealed with a sealant such as gel. Such surface protection films and sealants can be applied not only to SBDs but also to other semiconductor devices such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2009-94433 A [Patent Document 2] JP 2013-211503 A Summary of the Invention [Problem to be solved by the invention]

[0005] Surface protection films such as polyimide and sealing materials such as gels are prone to contain moisture that may adversely affect semiconductor devices under high humidity conditions. Specifically, when the semiconductor layer and its surrounding materials react with moisture in a high electric field, insulating materials such as oxides are generated, causing peeling of the surface protection film or moisture to accumulate at the interface between the surface protection film and the sealing material. As a result, a leak path different from normal is formed in the semiconductor device, which may impair the insulation reliability of the semiconductor device.

[0006] Therefore, the present disclosure has been made in consideration of the above-mentioned problems, and has an object to provide a technique capable of improving the insulation reliability of a semiconductor device. [Means for solving the problem]

[0007] The semiconductor device according to the present disclosure is a semiconductor device having an active region and a termination region surrounding the active region in a plan view, the semiconductor device including a first conductivity type semiconductor substrate made of silicon carbide and a termination region selectively provided on an upper portion of the semiconductor substrate in the termination region and surrounding the active region in a plan view. nothing a second conductive type termination well region, an FLR region selectively provided on the upper portion of the semiconductor substrate in the termination region and surrounding the termination well region in a plan view; On the board a field insulating film provided on the semiconductor substrate, the field insulating film covering a part of the termination well region and the FLR region; a surface electrode provided on the semiconductor substrate on the active region side of the field insulating film; an upper surface film provided on the field insulating film, the upper surface film covering an end of the surface electrode on the termination region side; back and a back surface electrode provided on a surface of the FLR region, the FLR region includes a plurality of floating wells of a second conductivity type that surround the termination well region in a plan view, are spaced apart from each other and are nested and have a floating potential, the FLR region includes a region in which the distance between adjacent floating wells increases toward the outer periphery of the FLR region, When a voltage of 0.8 times the rated voltage VR [V] of the semiconductor device is applied to the back electrode with respect to the front electrode, the electric field strength on the top surface of the semiconductor substrate outside the outer periphery of the termination well region is 1 MV / cm or less. It is. Effect of the Invention

[0008] According to the present disclosure, where rated voltage VR [V] of the semiconductor device, the number of the plurality of floating wells is equal to or greater than VR / 100. With such a configuration, it is possible to improve the insulation reliability of the semiconductor device.

[0009] The objects, features, aspects and advantages of the present disclosure will become more apparent from the following detailed description and the accompanying drawings. [Brief description of the drawings]

[0010] [Figure 1] 1 is a partial cross-sectional view showing a configuration of a semiconductor device according to a first embodiment. [Diagram 2] 1 is a plan view showing a configuration of a semiconductor device according to a first embodiment. [Diagram 3] 1 is a partial cross-sectional view showing a configuration of a semiconductor device according to a first embodiment. [Figure 4] 1 is a partial cross-sectional view showing a configuration of a semiconductor device according to a first embodiment. [Diagram 5] FIG. 4 is a diagram showing the lifetime of samples of the semiconductor device according to the first embodiment. [Figure 6] FIG. 4 is a diagram showing the lifetime of samples of the semiconductor device according to the first embodiment. [Figure 7] 1(a) to 1(c) are diagrams showing the appearance of the top surface of a semiconductor device sample. [Figure 8] FIG. 4 is a diagram showing a simulation result for the semiconductor device according to the first embodiment. [Figure 9] FIG. 4 is a diagram showing a simulation result for the semiconductor device according to the first embodiment. [Figure 10] 1 is a partial cross-sectional view showing a configuration of a semiconductor device according to a first embodiment. [Figure 11] 5 is a diagram showing calculation results of the electric field strength in the semiconductor device according to the first embodiment. FIG. [Figure 12] 5 is a diagram showing calculation results of the electric field strength in the semiconductor device according to the first embodiment. FIG. [Figure 13] FIG. 11 is a partial cross-sectional view showing the configuration of a semiconductor device according to a second embodiment. [Figure 14] FIG. 11 is a plan view showing a configuration of a semiconductor device according to a second embodiment. [Figure 15] FIG. 11 is a partial cross-sectional view showing the configuration of a semiconductor device according to a second embodiment. [Figure 16] FIG. 11 is a block diagram illustrating a schematic configuration of a power conversion system according to a third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, the embodiments will be described with reference to the attached drawings. In this specification, the "active region" of a semiconductor device is a region through which a main current flows when the semiconductor device is in an on-state, and the "termination region" of the semiconductor device is defined as a region surrounding the active region in a plan view. In addition, the "outside" of the semiconductor device means a direction from the center to the outer periphery of the semiconductor device in a plan view, and the "inside" of the semiconductor device means a direction opposite to the "outside". In addition, the conductivity types of the impurities are described assuming that the "first conductivity type" is n-type and the "second conductivity type" is p-type, but conversely, the "first conductivity type" may be p-type and the "second conductivity type" may be n-type.

[0012] Here, the term "MOS" has traditionally been used to represent a laminated structure of metal-oxide-semiconductor, and is considered to be an acronym for Metal-Oxide-Semiconductor. However, in particular in field effect transistors having a MOS structure (hereinafter simply referred to as "MOS transistors"), materials other than metals and oxides may be used for the gate electrode and gate insulating film from the viewpoint of recent integration and improvements in manufacturing processes. For example, polycrystalline silicon may be used instead of metals for the gate electrode, mainly from the viewpoint of forming the source and drain of a MOS transistor in a self-aligned manner. Also, from the viewpoint of improving electrical characteristics, materials with high dielectric constants other than oxides may be used for the gate insulating film.

[0013] For this reason, the term "MOS" is not necessarily limited to a metal-oxide-semiconductor laminated structure. In other words, in light of common technical knowledge, "MOS" is often defined to include not only the laminated structure indicated by the abbreviation Metal-Oxide-Semiconductor, but also a broader conductor-insulator-semiconductor laminated structure, and this is also true in this specification.

[0014] In addition, even if the following description uses the terms "on" and "covering", it does not prevent the presence of an intervening element between the components. For example, even if the description uses "B provided on A" or "B covering A", other components may be provided between A and B. In addition, in the following description, terms that indicate specific positions or directions, such as "top", "bottom", "side", "bottom", "front" or "back", may be used, but these terms are used for convenience of explanation and do not relate to the directions in actual use.

[0015] In addition, the drawings used in the following description are schematic. Therefore, the size, position and relationship between elements shown in the drawings may not be accurate and may be changed as appropriate. In addition, the size and relationship between elements shown in different drawings may not be accurate and may be changed as appropriate.

[0016] In each drawing, components having the same names and functions as components shown in other drawings are given the same reference numerals, and therefore, in order to avoid redundant explanations, explanations of components similar to those previously explained using other drawings may be omitted.

[0017] <Embodiment 1> <Device configuration> Fig. 1 is a partial cross-sectional view showing the configuration of a Schottky barrier diode (SBD) 100 which is a semiconductor device according to the first embodiment. Fig. 2 is a plan view of the SBD 100, and Fig. 1 corresponds to a cross-sectional view taken along line AA in Fig. 2. The left side of Fig. 1 is an active region through which a main current flows when the SBD 100 is in an on-state, and the right side of Fig. 1 is a termination region which is a region outside the SBD 100's active region. Hereinafter, the region corresponding to the active region may be referred to as an "inner region RI", and the region corresponding to the termination region may be referred to as an "outer region RO".

[0018] 1, SBD 100 according to the first embodiment is configured with epitaxial substrate 30 including single crystal substrate 31 and epitaxial layer 32 provided thereon. Single crystal substrate 31 is a substrate having n-type (first conductivity type) and is made of, for example, silicon carbide (SiC). Epitaxial layer 32 is made of n-type SiC and includes a semiconductor layer epitaxially grown on single crystal substrate 31. When configured in this manner, SBD 100 according to the first embodiment is a SiC-SBD.

[0019] The semiconductor substrate according to the first embodiment is an epitaxial substrate 30 including a single crystal substrate 31 and an epitaxial layer 32, but is not limited thereto, and may be, for example, either one of the single crystal substrate 31 and the epitaxial layer 32. In the first embodiment, the epitaxial substrate 30 is a substrate having a 4H polytype. The upper and lower sides of the epitaxial substrate 30 in FIG. 1 are defined as the "front side" and the "rear side", respectively, and hereinafter, the lower surface which is the main surface of the rear side of the epitaxial substrate 30 may be referred to as the "rear side S1", and the upper surface which is the main surface of the front side may be referred to as the "front surface S2".

[0020] A p-type (second conductivity type) termination well region 2 is selectively provided on the epitaxial layer 32 in the outer region RO, which is the termination region. The n-type epitaxial layer 32 in the inner region RI, which is the active region, includes an n-type drift layer 1 in which a current flows due to drift. The impurity concentration of the drift layer 1 is lower than the impurity concentration of the single crystal substrate 31. Therefore, the single crystal substrate 31 has a lower resistivity than the drift layer 1. The impurity concentration of the drift layer 1 is, for example, 1×10 14 / cm 3 More than 1×10 17 / cm 3 The following is the result.

[0021] The termination well region 2 is a frame-shaped (ring-shaped) region that surrounds the active region in a plan view and has an outer periphery, and functions as a so-called guard ring. In FIG. 2, the outer periphery of the termination well region 2 is indicated by a dotted line. Note that the "outer periphery" refers to the end of the outer periphery of a ring-shaped component such as the termination well region 2 that is located outside the SBD 100. Conversely, the "inner periphery" refers to the end of the inner periphery of a ring-shaped component such as the termination well region 2 that is located inside the SBD 100.

[0022] 1, in the first embodiment, the inner portion of the SBD 100 relative to the inner circumferential edge of the termination well region 2 is the active region (i.e., the inner region RI), and the outer portion of the SBD 100 relative to the boundary is the termination region (i.e., the outer region RO). In the first embodiment, the outer region RO is a frame-like region surrounding the inner region RI in a plan view, and has straight portions that are linear regions along each side of the semiconductor chip, and corner portions that are curved regions connecting two straight portions that extend in different directions.

[0023] 1, an FLR (Field Limiting Ring) region 3 is selectively provided on the upper portion of the epitaxial layer 32 in the outer region RO, which is the termination region, surrounding the termination well region 2 in a planar view. The FLR region 3 includes a plurality of p-type floating wells 3a having a floating potential. The plurality of floating wells 3a are provided on the outer periphery of the termination well region 2 at intervals, surrounding the termination well region 2 in a planar view, and are provided in a nested manner at intervals from each other.

[0024] In the FLR region 3, regions in which floating wells 3a are provided and regions of the epitaxial layer 32 in which no floating wells 3a are provided are alternately provided from the inside to the outside of the SBD 100. The inner periphery of the FLR region 3 corresponds to the inner periphery of the innermost floating well 3a among the multiple floating wells 3a, and the outer periphery of the FLR region 3 corresponds to the outer periphery of the outermost floating well 3a among the multiple floating wells 3a.

[0025] In the FLR region 3, it is desirable that the distance between the floating wells 3a increases from the inside to the outside of the SBD 100, as shown in Fig. 3. For example, as shown in Fig. 4, the distance between the xth (x=1, 2, ..., n) floating well 3a and the x-1th floating well 3a counting from the inner circumference is set to S x As the value of x increases, S x In FIG. 4, the 0th floating well 3a corresponds to the termination well region 2. Note that not all S x does not have to be monotonically increasing with x.

[0026] As shown in FIG. 3, the width of the x-th floating well 3a counted from the inside of the SBD 100 is L x As the value of x increases, L x The value of may be small, may be partially large, or may be the same regardless of the value of x. However, from the viewpoint of reducing costs, S x +Lx The value of is preferably as small as possible so long as the required avalanche voltage is obtained, and is desirably set to, for example, a value between 3 μm and 10 μm.

[0027] A field insulating film 4, a surface electrode 5, and a surface protective film 6 are provided on the surface S2 of the epitaxial substrate 30. Note that in the plan view of Fig. 2, the field insulating film 4 and the like are omitted, and the position of the end of the surface protective film 6, i.e., the contour line of the surface protective film 6, is shown by a solid line.

[0028] The field insulating film 4 covers a part of the termination well region 2 and the FLR region 3, and extends beyond the outer periphery of the FLR region 3. The field insulating film 4 is preferably made of an insulating material such as SiO2 or SiN, and has a thickness of, for example, 10 nm or more. For example, the field insulating film 4 may be a SiO2 film having a thickness of 1 μm.

[0029] The front surface electrode 5 is provided on the front surface S2 of the epitaxial substrate 30 closer to the active region than the field insulating film 4, and is provided on at least a part of the front surface S2 of the epitaxial substrate 30 in the inner region RI. In the first embodiment, the front surface electrode 5 includes a Schottky electrode 5a provided on the front surface S2 of the epitaxial substrate 30, and an electrode pad 5b provided on the Schottky electrode 5a. The outer peripheral ends of the Schottky electrode 5a and the electrode pad 5b ride on the field insulating film 4.

[0030] In this manner, the front surface electrode 5 rides up onto the field insulating film 4. The outer circumferential edge of the front surface electrode 5 is located inside the SBD 100 relative to the outer circumferential edge of the termination well region 2 in a plan view, and is not provided above the FLR region 3 beyond the outer circumferential edge of the termination well region 2.

[0031] The Schottky electrode 5a contacts the drift layer 1 in the inner region RI and the remaining part of the termination well region 2 in the outer region RO that is exposed from the field insulating film 4. This electrically connects the surface electrode 5 to the termination well region 2. The material of the Schottky electrode 5a may be any metal that forms a Schottky junction with the drift layer 1, which is an n-type SiC semiconductor, and may be, for example, Ti (titanium), Mo (molybdenum), Ni (nickel), Au (gold), or W (tungsten). The thickness of the Schottky electrode 5a is preferably, for example, 30 nm or more and 300 nm or less. For example, a Ti film having a thickness of 100 nm may be used as the Schottky electrode 5a.

[0032] The material of the electrode pad 5b may be, for example, a metal containing one or more of Al (aluminum), Cu (copper), Mo, and Ni, or an Al alloy such as Al-Si (silicon). The thickness of the electrode pad 5b is preferably, for example, 300 nm or more and 10 μm or less. For example, an Al film having a thickness of 3 μm may be used as the electrode pad 5b.

[0033] The surface protective film 6 is provided on the field insulating film 4 and is an upper surface film that covers the end of the surface electrode 5 on the outer region RO side. Specifically, the surface protective film 6 covers the end and end face (side face) of the upper surface of the electrode pad 5b and the end face (side face) of the Schottky electrode 5a. Therefore, the outer peripheral edge of the upper surface of the electrode pad 5b is covered by the surface protective film 6.

[0034] However, the center of the electrode pad 5b is exposed from the surface protective film 6 so that it can function as an external connection terminal. That is, the surface protective film 6 has an opening in the inner region RI that exposes the upper surface of the electrode pad 5b as shown in Fig. 1. The surface protective film 6 in Fig. 1 completely covers the outer peripheral edge of the field insulating film 4 and also covers at least a part of the surface S2 of the epitaxial substrate 30 in the outer region RO. However, the surface protective film 6 does not need to expose the outer peripheral edge of the field insulating film 4 and not need to be in contact with the surface S2 of the epitaxial substrate 30 as long as it is in contact with the field insulating film 4 above the FLR region 3.

[0035] The material of the surface protection film 6 may be, for example, polyimide, which is a resin insulating material that relieves external stress, or silicon nitride (SiN) with high resistance that can discharge external charges generated in the gel of the sealing resin 41 to the outside of the gel by an electrode. Alternatively, the surface protection film 6 may be a multilayer film in which a polyimide film and a SiN film are laminated.

[0036] A back surface electrode 8 is provided on the back surface S1 of the epitaxial substrate 30. The material of the back surface electrode 8 is, for example, a metal containing one or more of Ti, Ni, Al, Cu, and Au. The sealing resin 41 covers the surface protection film 6 and the like. The sealing resin 41 may be a gel sealing resin or a thermosetting sealing resin.

[0037] In the above configuration, the overall length of the FLR region 3 and the number of the floating wells 3a are changed depending on the withstand voltage required for the SBD 100. Usually, the withstand voltage of the SBD 100 varies depending on the applied product and application conditions, and rated voltages such as 1.2 kV class, 1.7 kV class, 3.3 kV class, 6.5 kV class, etc. are set. From the viewpoint of increasing the rated voltage, i.e., withstand voltage, of the SBD 100, it is preferable to increase the overall length of the FLR region 3 and increase the number of the floating wells 3a. On the other hand, from the viewpoint of reducing costs, it is preferable to shorten the overall length of the FLR region 3 as much as possible and reduce the number of the floating wells 3a.

[0038] Now, when the SBD 100 is used under high temperature and high humidity conditions, a high voltage may be applied to the SBD 100 while it contains some moisture. The inventors' research has revealed that in order to improve the insulation reliability under such conditions, it is necessary to increase the overall length of the FLR region 3 and / or to increase the number of floating wells 3a, compared to the configuration of the SBD 100 under normal usage conditions.

[0039] Reflecting the survey results, in the SBD 100 according to the first embodiment, the number of the floating wells 3a is VR÷100 or more, preferably VR÷85 or more, and more preferably VR÷65 or more, relative to the rated voltage VR [V] of the SBD 100. With this configuration, an SBD 100 with high insulation reliability can be obtained. Also, in the first embodiment, the length from the outer circumferential end of the termination well region 2 to the outer circumferential end of the FLR region 3 is VR×0.08 μm or more, preferably VR×0.09 μm or more, and more preferably VR×0.1 μm or more. With this configuration, an SBD 100 with even higher insulation reliability can be obtained. Note that by appropriately changing the combination of the number of the floating wells 3a and the length from the outer circumferential end of the termination well region 2 to the outer circumferential end of the FLR region 3, a desired SBD 100 can be obtained in terms of withstand voltage and cost.

[0040] In the first embodiment, the outer circumferential edge of the front surface electrode 5 is provided on the field insulating film 4 and is located inside the SBD 100 relative to the outer circumferential edge of the termination well region 2 in a plan view. With this configuration, it is possible to prevent a high electric field from being generated on the upper surface of the epitaxial layer 32 and the upper surface of the surface protective film 6.

[0041] In the first embodiment, SiC is used as the material of the epitaxial substrate 30. SiC has a wider band gap than Si, and a SiC semiconductor device has a higher withstand voltage, a higher allowable current density, and a higher heat resistance than a Si semiconductor device, and therefore can operate at high temperatures. However, the material of the epitaxial substrate 30 is not limited to SiC, and may be other wide band gap semiconductors such as gallium nitride (GaN) or gallium oxide (Ga2O3), particularly when a high electric field is likely to occur in the termination region. The semiconductor device according to the first embodiment may be a diode other than an SBD, such as a pn junction diode or a junction barrier Schottky (JBS) diode.

[0042] <Manufacturing method> Next, a method for manufacturing the SBD 100 according to the first embodiment will be described.

[0043] First, n-type impurities are added at a relatively high concentration (i.e., n + ) is prepared. In the present embodiment, a SiC substrate having a 4H polytype and an off-angle of 4 degrees or 8 degrees is used as the single crystal substrate 31.

[0044] Subsequently, an n-type epitaxial layer 32 is formed on the single crystal substrate 31 by epitaxially growing SiC on the single crystal substrate 31. The n-type impurity concentration of the epitaxial layer 32 is lower than the n-type impurity concentration of the single crystal substrate 31, and is, for example, 1×10 14 / cm 3 More than 1×10 17 / cm 3 As a result, epitaxial substrate 30 including single crystal substrate 31 and epitaxial layer 32 is formed.

[0045] Next, a resist mask having a pattern with openings for the formation regions of the termination well region 2 and the FLR region 3 is formed on the epitaxial layer 32 by a photolithography process. Then, using the resist mask as an implantation mask, p-type impurities (acceptors) such as Al or B (boron) are ion-implanted into the epitaxial layer 32 to form the p-type termination well region 2 on the upper part of the epitaxial layer 32. The termination well region 2 and the FLR region 3 can be formed simultaneously, and the dose of the p-type impurities is 1.0×10 13 / cm 2 Above 3.0×10 13 / cm 2 It is preferable that the value is equal to or less than 2.0×10 13 / cm 2 Alternatively, the formation of an implantation mask (patterning of a resist mask) and ion implantation may be repeated multiple times to form the termination well region 2 and the FLR region 3 in separate steps.

[0046] The implantation energy of the ion implantation in the FLR region 3 is, for example, 100 keV or more and 700 keV or less when the p-type impurity is Al. -2 The peak impurity concentration of the floating well 3a calculated from 17 / cm 3 More than 1×10 19 / cm 3 In addition, when implantation is performed with high energy of 300 keV or more, even if the upper surface of the epitaxial layer 32 is etched in various manufacturing processes, the p-type impurity concentration in the upper surface of the plurality of floating wells 3a is 1.0×10 17 cm -3 It can be the following:

[0047] After the formation of the termination well region 2 and the FLR region 3, annealing is performed in an inert gas atmosphere such as argon (Ar) gas at a temperature of 1300° C. to 1900° C. for 30 seconds to 1 hour using a heat treatment device. This annealing activates the impurities added to the epitaxial layer 32 by ion implantation.

[0048] Next, for example, by a CVD (Chemical Vapor Deposition) method, a SiO2 film or the like having a thickness of 1 μm is formed as a material layer for the field insulating film 4 on the surface S2 of the epitaxial substrate 30. Then, the material layer for the field insulating film 4 is patterned by a photolithography process and an etching process to form the field insulating film 4. At this time, the field insulating film 4 is patterned so as to cover at least a part of the termination well region 2 and the FLR region 3, and to extend beyond the outer circumferential edge of the FLR region 3.

[0049] Thereafter, a material layer for the Schottky electrode 5a and a material layer for the electrode pad 5b are laminated in this order by, for example, a sputtering method on the epitaxial layer 32 and the field insulating film 4. As the material layer for the Schottky electrode 5a, for example, a Ti film having a thickness of 100 nm is used, and as the material layer for the electrode pad 5b, for example, an Al film having a thickness of 3 μm is used.

[0050] Next, a resist mask having a pattern of the front electrode 5 is formed on the material layer of the electrode pad 5b by a photolithography process. Then, the material layer of the electrode pad 5b and the material layer of the Schottky electrode 5a are patterned using the resist mask as an etching mask to form the front electrode 5 including the Schottky electrode 5a and the electrode pad 5b. At this time, the outer periphery of the front electrode 5 is patterned so as to be located inside the SBD 100 with respect to the outer periphery of the termination well region 2 connected to the front electrode 5, and is not provided above the FLR region 3.

[0051] The material layer of the electrode pad 5b and the material layer of the Schottky electrode 5a can be etched by dry etching or wet etching. In the case of wet etching, an etching solution such as hydrofluoric acid (HF) or phosphoric acid can be used.

[0052] The patterning of the Schottky electrode 5a and the patterning of the electrode pad 5b may be performed separately. In this case, the position of the end of the Schottky electrode 5a and the position of the end of the electrode pad 5b may be shifted from each other in the left-right direction (also called the planar direction) of FIG. 1. For example, the electrode pad 5b may completely cover the Schottky electrode 5a by making the end of the electrode pad 5b protrude beyond the end of the Schottky electrode 5a. Alternatively, the end of the Schottky electrode 5a may not be covered by the electrode pad 5b by making the end of the Schottky electrode 5a protrude beyond the end of the electrode pad 5b.

[0053] Next, a material layer of the surface protection film 6, such as a resin layer, is formed on the surface S2 of the epitaxial substrate 30 so as to cover the field insulating film 4 and the end of the surface electrode 5 on the outer region RO side. This resin layer is formed by applying, for example, photosensitive polyimide. Then, the resin layer is patterned by a photolithography process to form the surface protection film 6. At this time, the surface protection film 6 on the central portion of the surface electrode 5 that becomes the external connection terminal is removed. In the first embodiment, the resin layer of the surface protection film 6 is patterned so that in the outer region RO, the surface protection film 6 covers the end of the surface electrode 5 on the outer region RO side and covers at least a part of the epitaxial substrate 30 in the outer region RO.

[0054] In the outer region RO, the resin layer of the surface protective film 6 may be patterned so that the outer peripheral end is exposed on the field insulating film 4 and does not come into contact with the surface S2 of the epitaxial substrate 30. However, the resin layer of the surface protective film 6 is patterned so that the surface protective film 6 and the field insulating film 4 come into contact with each other above the FLR region 3.

[0055] Finally, the back electrode 8 is formed on the back surface S1 of the epitaxial substrate 30 by, for example, a sputtering method, thereby forming the SBD 100 shown in FIG. 1. The back electrode 8 may be formed before or after the process of forming the material layer of the Schottky electrode 5a and the material layer of the electrode pad 5b. The material of the back electrode 8 may be, for example, a metal containing one or more of Ti, Ni, Al, Cu, and Au. The thickness of the back electrode 8 is preferably, for example, 50 nm or more and 2 μm or less. For example, a 1 μm-thick double-layered film of Ti / Au may be used as the back electrode 8.

[0056] <Operation> Next, a description will be given of the operation of the SBD 100 according to the first embodiment. In the following description, the region functioning as a p-type region, which is the combination of the termination well region 2 and the FLR region 3, may be referred to as "p-type functional regions 2, 3."

[0057] When a negative voltage is applied to the rear electrode 8 with respect to the potential of the front electrode 5, the SBD 100 enters a state in which a current flows from the front electrode 5 to the rear electrode 8, i.e., the SBD 100 enters a conductive state (ON state). Conversely, when a positive voltage is applied to the rear electrode 8 with respect to the potential of the front electrode 5, the SBD 100 enters a non-conductive state (OFF state).

[0058] When the SBD 100 is in the off state, a large electric field is applied near the top surface of the drift layer 1 in the inner region RI (active region) and near the interface of the pn junction between the drift layer 1 and the p-type functional regions 2, 3. The voltage applied to the back electrode 8 when this electric field reaches a critical electric field and avalanche breakdown occurs is defined as the maximum voltage (avalanche voltage) of the SBD 100. Typically, the rated voltage VR [V] of the SBD 100 is determined so that the SBD 100 is used within a voltage range in which avalanche breakdown does not occur.

[0059] When the SBD 100 is in the off state, a depletion layer spreads from the top surface of the drift layer 1 in the active region and the pn junction interface between the drift layer 1 and the p-type functional regions 2, 3 in the active region toward the single crystal substrate 31 (downward in FIG. 1) and from the drift layer 1 toward the periphery (rightward in FIG. 1). The depletion layer also spreads from the pn junction interface between the drift layer 1 and the p-type functional regions 2, 3 into the p-type functional regions 2, 3, and the extent of the spread is largely dependent on the impurity concentrations of the termination well region 2 and the floating well 3a. In other words, increasing the impurity concentrations of the termination well region 2 and the floating well 3a suppresses the spread of the depletion layer in the p-type functional regions 2, 3, and the tip position of the depletion layer is located near the boundary between the termination well region 2 and the drift layer 1.

[0060] For example, the dose of the terminal well region 2 and the floating well 3a is set to 1.0×10 13 / cm 2In the above cases, the depletion layer does not spread widely in the p-type functional regions 2, 3, and a potential gradient occurs mainly between the floating wells 3a in the FLR region 3. On the upper surface of the epitaxial layer 32 between the floating wells 3a, a potential gradient occurs in a direction perpendicular to the upper surface (planar direction), and the potential increases from the inner periphery to the outer periphery of the FLR region 3. On the upper surface of the epitaxial layer 32, the portion where the potential gradient is greatest between the floating wells 3a is the peripheral portion of the pn junction on the outer periphery of each floating well 3a, and a high electric field occurs in this peripheral portion.

[0061] However, depending on the process for fabricating the SBD 100 or the electric field generated when a high voltage is applied, the fixed charges trapped in the portion near the top surface of the epitaxial layer 32 in the FLR region 3 may affect the spread of the depletion layer in that portion. Taking this into consideration, the dose of the termination well region 2 is set to 1.5×10 13 / cm 2 More than this is desirable.

[0062] Here, consider a case where the SBD 100 is in an off state under high humidity. The sealing resin 41 provided to cover the surface protection film 6 may contain moisture. For example, if the surface protection film 6 is made of a resin material having high hygroscopicity such as polyimide, the surface protection film 6 may contain a lot of moisture under high humidity, and the moisture may reach the upper surface of the epitaxial layer 32. Also, for example, if the surface protection film 6 is made of a material having high resistance such as SiN, the surface protection film 6 may easily crack due to stress generated during the process, and the upper surface of the epitaxial layer 32 may be exposed to moisture through the crack. In such a case, when the epitaxial layer 32 in the FLR region 3 acts as an anode due to a voltage applied to the SBD 100 in the off state, a reaction of Si atoms and moisture to generate SiO2 occurs, especially around the p-type termination well region 2. The following formula (1) is a chemical formula representing the reaction of generating SiO2.

[0063] Si+2H2O+4h +→SiO2+4H + (1) When this SiO2 generation reaction occurs on the upper surface of the epitaxial layer 32 in the FLR region 3, the field insulating film 4 and the surface protective film 6, which are located above the region where SiO2 is generated, may be pushed up and peeled off. In this case, a leak path different from normal may be formed in the SBD 100, and the insulation reliability of the SBD 100 may be impaired.

[0064] The inventors found that this SiO2 generation reaction depends on the electric field around the pn junction on the outer periphery between the floating wells 3a. For example, AQG324, which is a reliability guideline for power semiconductor devices defined by ECPE (European Center for Power Electronics), specifies a test in which a voltage 0.8 times the rated voltage of the SBD 100 is applied for a long time at 85°C and 85%rh. In consideration of this, in the first embodiment, when a voltage 0.8 times the rated voltage VR [V] of the SBD 100 is applied to the back electrode 8 with the front electrode 5 as a reference, the electric field intensity at the upper surface of the epitaxial layer 32 in the FLR region 3 is configured to be 1MV / cm or less. In other words, the electric field intensity at the upper surface of the epitaxial substrate 30 outside the SBD 100 from the outer periphery of the terminal well region 2 is configured to be 1MV / cm or less. The inventors found that with this configuration, the SiO2 generation reaction can be significantly suppressed even in the high temperature and high humidity environment as described above.

[0065] The dose of each floating well 3a is 3.0×10 13 / cm 2 When the ionization current (H + ) may be supplied in a large amount, accelerating the reaction of generating SiO2 expressed by the above formula (1). Therefore, even if the electric field strength on the upper surface of the epitaxial layer 32 in the FLR region 3 is suppressed to 1 MV / cm or less, the dose of each floating well 3a may be increased to 3.0×10 13 / cm 2Furthermore, the hole (h + In order to reduce the supply amount of ions, it is preferable that the ion implantation energy when forming the termination well region 2 and the FLR region 3 is 300 keV or more.

[0066] In particular, in a high voltage rating class where the n-type impurity concentration in the upper surface of the epitaxial layer 32 is low, for example, in a rating class where the avalanche voltage is 1.7 kV or more, it is desirable to use ion implantation energy of 500 keV or more when forming the termination well region 2 and the FLR region 3. By forming the termination well region 2 and the FLR region 3 with high energy, the p-type impurity concentration in the upper surface of the multiple floating wells 3a can be reduced to 1.0×10 17 cm -3 Since the above reaction can be suppressed, the reaction for producing SiO2 represented by the above formula (1) can be suppressed.

[0067] Furthermore, when the SBD 100 is exposed to a high-humidity environment, moisture may remain at the interface between the semiconductor chip that has peeled off due to stress or the like and the sealing resin 41, or moisture may be captured and remain at the interface between the semiconductor chip and the sealing resin 41. For example, when the sealing resin 41 is made of a thermosetting material such as epoxy, the sealing resin 41 expands when it absorbs moisture, and minute peeling occurs at the interface between the semiconductor chip and the sealing resin 41, which makes it easy for moisture to remain at the interface between the surface protection film 6 and the sealing resin 41. Furthermore, when the sealing resin 41 is made of a gel-like material such as silicone, moisture that has permeated the sealing resin 41 is easy to remain at the interface between the surface protection film 6 and the sealing resin 41.

[0068] When the SBD 100 is in the off state, ionization of the accumulated moisture is accelerated on the upper surface of the surface protection film 6 above the FLR region 3, which is particularly subject to a high electric field, and a leak path different from the normal leak path is likely to be formed. The central portion of the electrode pad 5b, where the surface protection film 6 is open, acts as a cathode due to this leak path, and corrosion of the electrode pad 5b progresses at the inner peripheral edge of the surface protection film 6. For this reason, when the electrode pad 5b expands, the Schottky electrode 5a may crack or the surface protection film 6 may peel off from the surface electrode 5, which may impair the insulation reliability of the SBD 100.

[0069] The inventors found that the corrosion of the electrode pad 5b depends on the electric field on the upper surface of the surface protective film 6 above the FLR region 3. Therefore, in the first embodiment, when a voltage 0.8 times the rated voltage VR [V] of the SBD 100 is applied to the back electrode 8 with the surface electrode 5 as a reference, the electric field strength on the surface protective film 6 on the FLR region 3, that is, on the upper surface of the surface protective film 6 on the outer side of the SBD 100 from the outer periphery of the termination well region 2, is set to 0.1 MV / cm or less. The inventors found that this configuration can suppress the formation of a leak path at the interface between the surface protective film 6 and the sealing resin 41 even in a high-temperature and high-humidity environment specified in the reliability guideline, and can suppress the corrosion of the electrode pad 5b exposed from the surface protective film 6. In other words, the inventors found that the insulation reliability of the SBD 100 can be improved.

[0070] The electric field strength on the top surface of the epitaxial layer 32 in the FLR region 3 or the electric field strength on the top surface of the surface protective film 6 above the FLR region 3 depends on at least one of the number of floating wells 3a and the overall width of the FLR region 3. In this specification, for example, at least one of A, B, C, ..., and Z means any one of all combinations of one or more types extracted from the group of A, B, C, ..., and Z.

[0071] Here, we will explain how the insulation reliability of SBD 100 can be improved by having the electric field strength at the top surface of epitaxial substrate 30 outside SBD 100 from the outer circumferential end of termination well region 2 be 1 MV / cm or less, and the electric field strength at the top surface of surface protective film 6 outside SBD 100 from the outer circumferential end of termination well region 2 be 0.1 MV / cm or less.

[0072] Fig. 5 shows the results of applying a voltage to five SBD 100 samples under different electric field conditions A to C under high temperature and high humidity, and applying a Weibull distribution to the measurement results obtained, to determine the time at which the failure probability reaches 50%. Fig. 6 shows a graph of the time at which the failure probability reaches 50% under conditions A to C.

[0073] As shown in Figure 5, differences in the lifetime (i.e., the time when the failure probability becomes 50%) are observed depending on the difference in the SiC surface electric field (i.e., the electric field strength at the top surface of the epitaxial substrate 30) and the difference in the protective film surface electric field (i.e., the electric field strength at the top surface of the surface protective film 6).

[0074] For example, in Figure 5, comparing the lifespan under conditions A and B, where the SiC surface electric field is greater than 1MV / cm, with the lifespan under condition C, where the SiC surface electric field is less than 1MV / cm, it can be seen that the lifespan extends when the SiC surface electric field is 1.0MV / cm or less. The curves in Figure 6 also provide an indication of the data. As shown in Figure 6, keeping the SiC surface electric field below 1.0MV / cm significantly lengthens the time to 50% failure, which is thought to extend the lifespan. Extending this, it can be seen that the lifespan extends as the SiC surface electric field increases to 1MV / cm, 0.9MV / cm, and 0.8MV / cm.

[0075] 5, for example, comparing the lifetime under conditions A and B, where the protective film surface electric field is greater than 0.1 MV / cm, with the lifetime under condition C, where the protective film surface electric field is less than 0.1 MV / cm, it can be seen that the lifetime is extended when the protective film surface electric field is 0.1 MV / cm or less. Extending this, it can be considered that the lifetime is extended as the protective film surface electric field becomes 0.1 MV / cm, 0.09 MV / cm, and 0.08 MV / cm.

[0076] FIG. 7(a) is a diagram showing the appearance of the upper surface of a sample applied with an electric field of condition B, in which the SiC surface electric field is 1.1 MV / cm, for 753 hours. FIG. 7(b) is a diagram showing the appearance of the upper surface of a sample applied with an electric field of condition C, in which the SiC surface electric field is 0.9 MV / cm, for 2166 hours. FIG. 7(c) is a diagram showing the appearance of the upper surface of a sample applied with an electric field of 0.8 MV / cm, in which the SiC surface electric field is 939 hours. Comparing the appearance of FIG. 7(a) with the appearances of FIG. 7(b) and (c), it can be seen that when the SiC surface electric field is 1.0 MV / cm or less, the deterioration of the FLR region 3 due to the reaction of generating SiO2 on the upper surface of the epitaxial layer 32 is suppressed. It is believed that the life is extended by suppressing the deterioration of the FLR region 3 in this way.

[0077] In the first embodiment, in order to keep the electric field strength on the surface of the epitaxial layer 32 in the FLR region 3 at 1 MV / cm or less, the number of floating wells 3a is configured to be increased within a range in which an avalanche voltage higher than the rated voltage is realized. This configuration does not substantially contribute to reducing the electric field strength inside the epitaxial layer 32 in the FLR region 3, i.e., to increasing the avalanche voltage, but it can reduce the electric field strength on the upper surface of the epitaxial layer 32 in the FLR region 3. From the viewpoint of reducing costs, it is desirable to reduce the number of floating wells 3a within a range in which an avalanche voltage higher than the rated voltage of the SBD 100 is realized.

[0078] In the first embodiment, the number of floating wells 3a is relatively large, and the p-type impurity concentration per unit area of ​​the floating wells 3a, that is, the dose amount, is 1.0×1013 cm -2 More than 1.5×10 13 cm -2 According to this configuration, the peak value of the electric field strength on the upper surface of the epitaxial layer 32 in the FLR region 3 is equal to the distance S between the floating wells 3a. x and width L x The peak position of the electric field intensity hardly changes depending on the distance S between the floating wells 3a, and only the peak position of the electric field intensity changes. Specifically, when the dose is increased, the peak position of the electric field intensity moves toward the outer periphery of the FLR region 3, and when the dose is decreased, the peak position of the electric field intensity moves toward the inner periphery of the FLR region 3. x When the distance S x When the distance is large, the FLR region 3 moves toward the inner periphery.

[0079] FIG. 8 is a diagram showing the results of a TCAD simulation of a 3.3 kV class semiconductor chip for an SBD 100 of a high voltage rating class (for example, an avalanche voltage of 1.7 kV or more) where the above-mentioned various problems are particularly likely to occur. As shown in FIG. 8, if the number of floating wells 3a is 33 (=3.3 kV (rated voltage VR)÷100) or more, the electric field strength on the upper surface of the epitaxial layer 32 in the FLR region 3 when a voltage 0.8 times the rated voltage VR is applied can be suppressed to 1 MV / cm or less. Similarly, if the number of floating wells is 39 (=3.3 kV (rated voltage VR)÷85) or more, the electric field strength can be suppressed to 0.9 MV / cm or less. If the number of floating wells is 51 (=3.3 kV (rated voltage VR)÷65) or more, the electric field strength can be suppressed to 0.8 MV / cm or less.

[0080] 9 is a diagram showing the results of a TCAD simulation of a 6.5 kV class semiconductor chip. As shown in FIG. 9, if the number of floating wells 3a is 65 (=6.5 kV (rated voltage VR)÷100) or more, the electric field strength on the upper surface of the epitaxial layer 32 in the FLR region 3 when a voltage 0.8 times the rated voltage VR is applied can be suppressed to 1 MV / cm or less. Although not shown, if the number of floating wells is 77 (=6.5 kV (rated voltage VR)÷85) or more, the electric field strength can be suppressed to 0.9 MV / cm or less, and if the number is 100 (=6.5 kV (rated voltage VR)÷65) or more, the electric field strength can be suppressed to 0.8 MV / cm or less.

[0081] Considering the above, by setting the floating well 3a to VR÷100 or more for the rated voltage VR [V], the electric field strength on the top surface of the epitaxial layer 32 in the FLR region 3 when a voltage 0.8 times the rated voltage VR is applied can be suppressed to 1 MV / cm or less. As a result, an SBD 100 with high insulation reliability can be obtained.

[0082] In actual use, a voltage of rated voltage VR [V] × 0.8 or more may be applied to back electrode 8 with respect to front electrode 5. Even in this case, the number of floating wells 3a is preferably VR÷80 or more, and more preferably VR÷65 or more, so as to suppress the SiO2 generation reaction on the upper surface of epitaxial layer 32 in FLR region 3.

[0083] On the other hand, the width of the FLR region 3 is important in order to keep the electric field strength on the upper surface of the surface protective film 6 above the FLR region 3 at 0.1 MV / cm or less. The upper surface of the surface protective film 6 has an electric field strength distribution similar to the electric field strength distribution on the upper surface of the epitaxial layer 32 in the FLR region 3. In particular, when the upper surface of the surface protective film 6 has a rectangular electric field strength distribution as shown in FIG. 10, the electric field strength can be minimized.

[0084] The theoretical minimum value E of the electric field strength on the surface of the surface protective film 6 is the length W from the outer edge of the termination well region 2 to the outer edge of the FLR region 3 when the electric field applied to the back electrode 8 with respect to the front electrode 5 is V. FLR For E=V / W FLR The length W FLR corresponds to the width of the FLR region 3.

[0085] 11 is a diagram showing the calculation results of the electric field strength when a voltage of rated voltage VR [V] × 0.8 (2640 V) is applied to a 3.3 kV class SBD 100. As shown in FIG. 11, in order to suppress the electric field strength on the upper surface of the surface protection film 6 above the FLR region 3 to 0.1 MV / cm or less, theoretically, the length W FLR should be set to 264 μm, or rated voltage VR [V] × 0.08 μm or more.

[0086] 12 is a diagram showing the calculation results of the electric field strength when a voltage of rated voltage VR [V] × 0.8 (5200 V) is applied to a 6.5 kV class SBD 100. As shown in FIG. 12, in order to suppress the electric field strength on the upper surface of the surface protection film 6 above the FLR region 3 to 0.1 MV / cm or less, theoretically, the length W FLR should be set to 520 μm, or rated voltage VR [V] × 0.08 μm or more.

[0087] Considering the above, in order to suppress the electric field strength on the upper surface of the surface protection film 6 above the FLR region 3 to 0.1 MV / cm or less, the length W from the outer edge of the termination well region 2 to the outer edge of the FLR region 3 must be FLR Here, from the plotted parts of Figs. 11 and 12, the length W FLR When the rated voltage VR×0.09μm or more, the electric field strength can be reduced to 0.09MV / cm or less, and the length W FLR It can be seen that when the rated voltage VR × 0.1 μm or more, the electric field strength can be reduced to 0.08 MV / cm or less.

[0088] On the upper surface of the surface protective film 6 above the FLR region 3, the number of floating wells 3a is increased, and the width L of the floating wells 3a is increased. x It is possible to reduce the electric field strength by increasing the value of . On the other hand, on the upper surface of the surface protective film 6 above the FLR region 3, the electric field strength distribution on the upper surface of the epitaxial layer 32 of the FLR region 3 becomes a distribution that is smoothed, so that the electric field strength distribution has a peak at a certain position on the upper surface of the surface protective film 6 above the FLR region 3.

[0089] Therefore, the length W FLR The length W may be longer than the distance theoretically required to suppress the electric field intensity on the upper surface of the surface protection film 6 above the FLR region 3 to 0.1 MV / cm or less. FLR may be VR[V]×0.08 μm, preferably VR×0.09 μm or more, and more preferably VR×0.1 μm or more. With this configuration, the corrosion reaction of the electrode pad 5b in the region where the surface protective film 6 in the center of the electrode pad 5b is open can be suppressed even in a high-temperature and high-humidity environment.

[0090] Furthermore, in a configuration in which the front electrode 5 protrudes to the periphery beyond the termination well region 2, a location with a low potential is generated above the FLR region 3. This may result in an increase in the electric field strength at the top surface of the epitaxial layer 32 in the FLR region 3 and at the top surface of the surface protective film 6 above the FLR region 3. In contrast, in the first embodiment, the outer periphery of the front electrode 5 is located inside the SBD 100 relative to the outer periphery of the termination well region 2 in a plan view, and therefore the increase in electric field strength can be suppressed.

[0091] <Summary of the First Embodiment> As described above, the SBD 100 according to the first embodiment can suppress the formation of leakage paths that are different from normal when a high voltage is applied in a high-temperature, high-humidity environment, thereby improving the insulation reliability of the SBD 100.

[0092] <Embodiment 2> <Device configuration> FIG. 13 is a partial cross-sectional view showing the configuration of a MOSFET 200 which is a semiconductor device according to the second embodiment. FIG. 14 is a plan view of the MOSFET 200, and FIG. 13 is a cross-sectional view taken along the line BB in FIG. 14. FIG. 15 is a cross-sectional view showing the configuration of a unit cell UC which is a minimum unit structure of the MOSFET 200 provided in the inner region RI which is an active region. A plurality of unit cells UC shown in FIG. 15 are arranged in the inner region RI of the MOSFET 200, and the outermost unit cell UC is shown in the left end portion of FIG. 13. In FIGS. 13 to 15, elements having the same functions as those of the SBD 100 according to the first embodiment shown in FIGS. 1 and 2 are denoted by the same reference numerals, and description of those elements will be omitted below.

[0093] The semiconductor substrate constituting MOSFET 200 according to the second embodiment of FIG. 13 is epitaxial substrate 30 including single crystal substrate 31 and epitaxial layer 32, similarly to the first embodiment.

[0094] A p-type (second conductivity type) element well region 9 is selectively provided on the epitaxial layer 32 of the inner region RI, which is an active region. An n-type source region 11 and a p-type contact region 19 having a higher p-type impurity concentration than the element well region 9 are selectively provided on the upper portion of the element well region 9.

[0095] A p-type boundary region 20 is selectively provided in the upper part of the epitaxial layer 32 in the outer region RO, which is the termination region, surrounding the active region in a plan view. The inner peripheral end of the boundary region 20 corresponds to the boundary between the inner region RI and the outer region RO. The boundary region 20 includes a low concentration portion 20a having a relatively low concentration of p-type impurities, and a high concentration portion 20b selectively provided above the low concentration portion 20a and having a relatively high concentration of p-type impurities. The conductivity type of the high concentration portion 20b is not limited to p-type, and may be n-type.

[0096] A p-type (second conductivity type) termination well region 2 is selectively provided in an upper portion of the epitaxial layer 32 in the outer region RO, which is the termination region, surrounding the boundary region 20 in a plan view. The p-type impurity concentration of the termination well region 2 is lower than the p-type impurity concentration of the boundary region 20.

[0097] The n-type epitaxial layer 32 in the inner region RI, which is the active region, except for the element well region 9, the source region 11, and the contact region 19, includes a drift layer 1 through which a current flows due to drift. This drift layer 1 is similar to the drift layer 1 described in the first embodiment.

[0098] The termination well region 2 is a frame-shaped (ring-shaped) region that surrounds the active region in a plan view and has an outer peripheral edge, and functions as a so-called guard ring, as in the first embodiment. In FIG. 14, the outer periphery of the termination well region 2 is indicated by a dotted line.

[0099] 13, in the upper portion of the epitaxial layer 32 in the outer region RO, which is the termination region, the FLR region 3 is selectively provided so as to surround the termination well region 2 in a plan view, as in the first embodiment. The FLR region 3 includes a plurality of p-type floating wells 3a having a floating potential, as in the first embodiment. The spacing and width of the floating wells 3a are set to the spacing S described in the first embodiment. x and width L x It may be similar to:

[0100] A gate insulating film 12 is provided on the surface S2 of the epitaxial substrate 30 in the active region, that is, on the epitaxial substrate 30 closer to the active region than the field insulating film 4, and extends over the source region 11, the element well region 9, and the drift layer 1. A gate electrode 13 is provided on the gate insulating film 12. Of the upper part of the element well region 9 covered with the gate insulating film 12 and the gate electrode 13, the portion between the source region 11 and the drift layer 1 is a channel region in which an inversion channel is formed when the MOSFET 200 is turned on.

[0101] The interlayer insulating film 14 covers the gate electrode 13, and a source electrode 51 is provided on the interlayer insulating film 14. The source electrode 51 and the gate electrode 13 are electrically insulated by the interlayer insulating film 14. The source electrode 51 is electrically connected to the source region 11 and the contact region 19 through a contact hole provided in the interlayer insulating film 14. The source electrode 51 and the contact region 19 form an ohmic contact. A back surface electrode 8 functioning as a drain electrode is formed on the back surface S1 of the epitaxial substrate 30.

[0102] 13, the gate insulating film 12, the gate electrode 13, the interlayer insulating film 14, and a part of the source electrode 51 extend beyond the boundary between the inner region RI and the outer region RO to the outer region RO, and are provided across the inner region RI and the outer region RO. The source electrode 51 provided in the outer region RO is electrically connected to the high concentration portion 20b of the boundary region 20 through a contact hole provided in the interlayer insulating film 14 so as to form an ohmic contact or a Schottky contact. The gate electrode 13 provided in the outer region RO is disposed on the high concentration portion 20b of the boundary region 20 via the gate insulating film 12, and extends in a frame shape in a plan view similar to the high concentration portion 20b.

[0103] In addition to the above-mentioned components provided across the inner region RI and the outer region RO, a field insulating film 4, a gate wiring electrode 52, and a surface protective film 6 are provided on the surface S2 of the epitaxial substrate 30 in the termination region. Note that in the plan view of Fig. 14, the field insulating film 4 and the like are omitted, and the position of the end of the surface protective film 6, i.e., the contour line of the surface protective film 6, is shown by a solid line.

[0104] The field insulating film 4 covers a part of the termination well region 2 and the FLR region 3, and extends beyond the outer peripheral edge of the FLR region 3, as in the first embodiment. The gate wiring electrode 52 is provided on the interlayer insulating film 14 that covers the gate electrode 13 provided in the outer region RO. The gate wiring electrode 52 is electrically connected to the gate electrode 13 through a contact hole provided in the interlayer insulating film 14. The gate wiring electrode 52 functions as an electrode that receives a gate signal (control signal) for controlling an electrical path between the source electrode 51 and the back electrode 8. The gate wiring electrode 52 is separated from the source electrode 51 and is electrically insulated from the source electrode 51.

[0105] The gate wiring electrode 52 extends in a frame shape in plan view, similar to the gate electrode 13 provided in the outer region RO. In the second embodiment, the gate wiring electrode 52 includes a gate wiring 52w surrounding the source electrode 51 and a gate pad 52p provided so as to enter a recess provided in a straight portion that is one side of the substantially rectangular source electrode 51, as shown in FIG. 14. The gate wiring 52w and the gate pad 52p are connected to each other. The gate wiring electrode 52 shown in FIG. 13 corresponds to the gate wiring 52w in FIG. 14. The gate pad 52p functions as an external connection terminal for inputting a gate signal. Note that, in FIG. 14, the gate pad 52p is provided on the straight portion of the substantially rectangular source electrode 51, but may be provided on a corner portion.

[0106] The surface electrode 5 according to the second embodiment includes a source electrode 51 and a gate wiring electrode 52. The source electrode 51 and the gate wiring electrode 52 are provided on the epitaxial substrate 30 via the interlayer insulating film 14, and are divided on the interlayer insulating film 14. The surface electrode 5 is provided on the surface S2 of the epitaxial substrate 30 closer to the active region than the field insulating film 4, and is provided on at least a part of the surface S2 of the epitaxial substrate 30 in the inner region RI. The surface electrode 5 is provided over the entire inner region RI, and a part of it extends beyond the boundary between the inner region RI and the outer region RO to the outer region RO. A part of the surface electrode 5 is provided so as to ride on the interlayer insulating film 14.

[0107] 13, the inner peripheral edge of the field insulating film 4 is in contact with the outer peripheral edge of the interlayer insulating film 14, and the gate electrode 13 and the surface electrode 5 are provided inside the MOSFET 200 from the inner peripheral edge of the field insulating film 4. However, the interlayer insulating film 14, the gate electrode 13, and the surface electrode 5 may be provided so as to run onto the field insulating film 4. The source electrode 51 may be connected to the high concentration portion 20b of the boundary region 20 through a contact hole penetrating both the interlayer insulating film 14 and the field insulating film 4. However, the outer peripheral edges of the surface electrode 5 and the gate electrode 13 are located inside the MOSFET 200 from the outer peripheral edge of the terminal well region 2 in a plan view, and are not provided above the FLR region 3 beyond the outer peripheral edge of the terminal well region 2.

[0108] The surface protective film 6 is provided on the field insulating film 4, and is an upper surface film covering the end of the surface electrode 5 on the outer region RO side. In the second embodiment, the surface protective film 6 covers the source electrode 51 and the gate wiring electrode 52, and also covers at least a part of the surface S2 of the epitaxial substrate 30 in the outer region RO. As shown in FIG. 14, the surface protective film 6 has openings on the center of the source electrode 51 and on the center of the gate pad 52p. As a result, the source electrode 51 and the gate pad 52p each function as an external connection terminal.

[0109] In the above configuration, the total length of the FLR region 3 and the number of the plurality of floating wells 3a are changed depending on the withstand voltage required for the semiconductor device, as in the first embodiment. That is, in the MOSFET 200 according to the second embodiment, the number of the plurality of floating wells 3a is equal to or greater than VR÷100, preferably equal to or greater than VR÷85, and more preferably equal to or greater than VR÷65, where VR [V] is the rated voltage of the MOSFET 200. With such a configuration, a MOSFET 200 with high insulation reliability can be obtained.

[0110] In the second embodiment, the length from the outer circumferential edge of the termination well region 2 to the outer circumferential edge of the FLR region 3 is VR×0.08 μm or more, preferably VR×0.09 μm or more, and more preferably VR×0.1 μm or more. With this configuration, a MOSFET 200 with even higher insulation reliability can be obtained.

[0111] In the second embodiment, as in the first embodiment, for example, SiC is used as the material of the epitaxial substrate 30. The semiconductor device according to the second embodiment may be a transistor other than a MOSFET, for example, a JFET (Junction FET) or an IGBT (Insulated Gate Bipolar Transistor). Furthermore, the semiconductor device according to the second embodiment is a planar type transistor, but may be a trench type transistor.

[0112] <Manufacturing method> Next, a description will be given of a method for manufacturing MOSFET 200 according to the second embodiment. First, similarly to the first embodiment, epitaxial substrate 30 including single crystal substrate 31 and epitaxial layer 32 is formed.

[0113] Then, a photolithography process for forming a resist mask and an ion implantation process for forming an impurity region in the upper part of the epitaxial layer 32 by ion implantation using the resist mask as an implantation mask are repeated. As a result, the terminal well region 2, the FLR region 3, the element well region 9, the source region 11, the contact region 19, and the boundary region 20 are formed in the epitaxial layer 32. For example, N (nitrogen) is used as the n-type impurity, and for example, Al or B is used as the p-type impurity. The terminal well region 2 and the FLR region 3 may be formed together in the same ion implantation process. The element well region 9 and the low concentration portion 20a of the boundary region 20 may be formed together in the same ion implantation process. Also, the contact region 19 and the high concentration portion 20b of the boundary region 20 may be formed together in the same ion implantation process.

[0114] The impurity concentration of the element well region 9 and the low concentration portion 20a of the boundary region 20 is, for example, 1.0×10 18 / cm 3 Above 1.0×10 20 / cm 3 The impurity concentrations of the source region 11, the contact region 19, and the high concentration portion 20b of the boundary region 20 are higher than the impurity concentration of the element well region 9, and are preferably 1.0×10 19 / cm 3 Above 1.0×10 21 / cm 3 It is preferable that:

[0115] The dose amount of p-type impurity and the formation conditions of the FLR region 3 are the same as those of the FLR region 3 according to the first embodiment. When N impurities are implanted as n-type impurities, the implantation energy of the ion implantation is preferably, for example, 20 keV to 300 keV. Then, annealing is performed at a temperature of, for example, 1500° C. or higher using a heat treatment device. This activates the impurities added to the epitaxial layer 32 by ion implantation.

[0116] Next, for example, by a CVD method, a SiO2 film or the like having a thickness of 0.5 μm or more and 2 μm or less is formed as a material layer for the field insulating film 4 on the surface S2 of the epitaxial substrate 30, and the material layer is patterned to form the field insulating film 4. The field insulating film 4 is patterned to cover at least a part of the termination well region 2 and the FLR region 3, and to extend beyond the outer circumferential edge of the FLR region 3.

[0117] Next, the surface of the epitaxial layer 32 that is not covered with the field insulating film 4 is thermally oxidized to form, for example, a SiO2 film as the gate insulating film 12. Then, for example, a conductive polycrystalline silicon film is formed on the gate insulating film 12 by a low-pressure CVD method, and the polycrystalline silicon film is patterned by a photolithography process and an etching process to form a gate electrode 13. At this time, the gate electrode 13 may be formed so as to run onto the field insulating film 4.

[0118] Thereafter, for example, a SiO2 film is formed as the interlayer insulating film 14 by the CVD method. Then, contact holes are formed by photolithography and etching processes, penetrating the gate insulating film 12 and the interlayer insulating film 14 and reaching the contact region 19, the source region 11, and the high concentration portion 20b of the boundary region 20. Also, in the termination region, contact holes are formed penetrating the interlayer insulating film 14 and reaching the gate electrode 13, and the interlayer insulating film 14 on the field insulating film 4 and the interlayer insulating film 14 on the outer periphery of the field insulating film 4 are removed.

[0119] Next, a material layer of the front electrode 5 is formed on the front surface S2 of the epitaxial substrate 30 by a sputtering method, a deposition method, or the like. Similarly to the front electrode 5, a material layer of the back electrode 8 is formed on the back surface S1 of the epitaxial substrate 30. The material of the front electrode 5 is, for example, a metal containing at least one of Ti, Ni, Al, Cu, and Au, or an Al alloy such as Al-Si. The material of the back electrode 8 is, for example, a metal containing one or more of Ti, Ni, Al, Cu, and Au. A silicide film may be formed in advance by heat treatment on the part of the epitaxial substrate 30 that contacts the front electrode 5 or the back electrode 8. The formation of the back electrode 8 may be performed at the end of all the steps.

[0120] Next, the material layer of the surface electrode 5 is patterned by photolithography and etching processes to form the separated source electrode 51 and gate wiring electrode 52.

[0121] Finally, a surface protective film 6 is formed to cover the field insulating film 4 and the end of the surface electrode 5 on the outer region RO side. The surface protective film 6 is formed in a desired shape, for example, by applying and exposing a photosensitive polyimide. In the second embodiment, the surface protective film 6 is formed in the outer region RO so as to cover the end of the surface electrode 5 on the outer region RO side and to cover at least a part of the epitaxial substrate 30 in the outer region RO. In this manner, the MOSFET 200 shown in FIG. 13 is formed.

[0122] <Operation> Next, the operation of the MOSFET 200 according to the second embodiment will be described in two states. In the following description, the region functioning as a p-type region, which is the combination of the termination well region 2 and the FLR region 3, will be referred to as p-type functional regions 2 and 3.

[0123] The first state is a state in which a positive voltage equal to or higher than the threshold voltage is applied to the gate electrode 13, and this state will be referred to as the "on state" hereinafter. When the MOSFET 200 is in the on state, an inversion channel is formed in the channel region. The inversion channel becomes a path for electrons, which are carriers, to flow between the source region 11 and the drift layer 1. When a high voltage is applied to the back electrode 8 with respect to the potential of the source electrode 51 as a reference, the MOSFET is in the on state, and a current flows through the single crystal substrate 31 and the drift layer 1. At this time, the voltage between the source electrode 51 and the back electrode 8 is called the "on voltage", and the current flowing between the source electrode 51 and the back electrode 8 is called the "on current". The on current flows only through the active region where the channel exists, and does not flow through the termination region.

[0124] The second state is a state in which a voltage less than the threshold voltage is applied to the gate electrode 13, and hereinafter, this state will be referred to as the "off state." When the MOSFET 200 is in the off state, an inversion channel is not formed in the channel region, and therefore no on-current flows. Therefore, when a high voltage is applied between the source electrode 51 and the rear electrode 8, this high voltage is maintained. At this time, the voltage between the gate electrode 13 and the source electrode 51 is much smaller than the voltage between the source electrode 51 and the rear electrode 8, so that a high voltage is applied between the gate electrode 13 and the rear electrode 8.

[0125] In the off state, a high voltage is also applied in the termination region between the gate wiring electrode 52 and the gate electrode 13 and the back surface electrode 8. However, just as an electrical contact is formed between the element well region 9 and the source electrode 51 in the active region, an electrical contact is also formed between the boundary region 20 and the source electrode 51 in the termination region. Therefore, application of a high electric field to the gate insulating film 12 and the interlayer insulating film 14 is suppressed.

[0126] The termination region of MOSFET 200 functions in the same manner as in the off-state of SBD 100 described in the first embodiment. That is, a large electric field is applied near the interface of the pn junction between drift layer 1 and p-type functional regions 2, 3. The voltage applied to back electrode 8 when this electric field reaches a critical electric field and avalanche breakdown occurs is defined as the maximum voltage (avalanche voltage) of MOSFET 200. Usually, the rated voltage VR [V] of MOSFET 200 is determined so that MOSFET 200 is used within a voltage range in which avalanche breakdown does not occur.

[0127] When the MOSFET 200 is in an off state, a depletion layer spreads from the pn junction interface between the drift layer 1 in the active region and the element well region 9, the boundary region 20, and the p-type functional regions 2 and 3 in a direction toward the single crystal substrate 31 (downward in FIG. 13) and toward the outer periphery of the drift layer 1 (rightward in FIG. 13). Thus, when the MOSFET 200 is in an off state, the depletion layer spreads in the same manner as in the off state of the SBD 100 described in the first embodiment, and a high electric field is generated in the peripheral portion of the pn junction on the outer periphery side of each floating well 3a. Then, a reaction of SiO2 is generated by the Si atoms represented by the above chemical formula (1) and moisture, particularly around the p-type termination well region 2.

[0128] Therefore, in the second embodiment as well, similarly to the first embodiment, when a voltage 0.8 times the rated voltage VR [V] of the MOSFET 200 is applied to the back electrode 8 with respect to the front electrode 5, the electric field intensity at the top surface of the epitaxial layer 32 in the FLR region 3 is set to 1 MV / cm or less. In other words, the electric field intensity at the top surface of the epitaxial substrate 30 on the outer side of the MOSFET 200 than the outer periphery of the termination well region 2 is set to 1 MV / cm or less. The inventors have found that with this configuration, the SiO2 production reaction can be significantly suppressed even in a high-temperature and high-humidity environment as in the first embodiment.

[0129] In addition, the holes (h +In order to reduce the supply amount of ions, it is preferable that the ion implantation energy when forming the termination well region 2 and the FLR region 3 is 300 keV or more.

[0130] In particular, in a high voltage rating class where the n-type impurity concentration in the upper surface of the epitaxial layer 32 is low, for example, in a rating class where the avalanche voltage is 1.7 kV or more, it is desirable to use ion implantation energy of 500 keV or more when forming the termination well region 2 and the FLR region 3. By forming the termination well region 2 and the FLR region 3 with high energy, the p-type impurity concentration in the upper surface of the multiple floating wells 3a can be reduced to 1.0×10 17 cm -3 Since the above reaction can be suppressed, the reaction for producing SiO2 represented by the above formula (1) can be suppressed.

[0131] Furthermore, when the MOSFET 200 is exposed to a high-humidity environment, ionization of the moisture remaining on the upper surface of the surface protective film 6 above the FLR region 3 is accelerated, and a leak path different from the normal one is likely to be formed. This may cause corrosion of the surface electrode 5 to progress at the inner peripheral edge of the surface protective film 6, resulting in a loss of insulation reliability of the MOSFET 200.

[0132] Therefore, in the second embodiment, when a voltage 0.8 times the rated voltage VR [V] of the MOSFET 200 is applied to the back electrode 8 with respect to the front electrode 5, the electric field intensity on the front protective film 6 on the FLR region 3, that is, on the top surface of the front protective film 6 on the outer side of the MOSFET 200 from the outer periphery of the termination well region 2, is set to 0.1 MV / cm or less. The inventors have found that this configuration can suppress the formation of a leak path at the interface between the front protective film 6 and the sealing resin 41 and the corrosion of the electrode pad 5b even in a high-temperature and high-humidity environment specified in the reliability guidelines, thereby improving the insulation reliability of the MOSFET 200.

[0133] In the second embodiment, similarly to the first embodiment, the number of floating wells 3a is relatively large, and the p-type impurity concentration per unit area of ​​the floating wells 3a, that is, the dose amount, is 1.0×10 13 cm-2 More than 1.5×10 13 cm -2 That's all.

[0134] 8 and 9 are obtained for the MOSFET 200 according to the second embodiment, as in the SBD 100 according to the first embodiment. Therefore, if the number of floating wells 3a is equal to or greater than the rated voltage VR [V]÷100, the electric field strength on the upper surface of the epitaxial layer 32 in the FLR region 3 when a voltage 0.8 times the rated voltage VR is applied can be suppressed to 1 MV / cm or less. Similarly, if the number of floating wells is equal to or greater than the rated voltage VR [V]÷85, the electric field strength can be suppressed to 0.9 MV / cm or less, and if the number is equal to or greater than the rated voltage VR [V]÷65, the electric field strength can be suppressed to 0.8 MV / cm or less.

[0135] 11 and 12 are obtained for the MOSFET 200 according to the second embodiment, as in the SBD 100 according to the first embodiment. FLR If the length W is equal to or greater than the rated voltage VR [V] × 0.08 μm, the electric field strength on the upper surface of the surface protection film 6 above the FLR region 3 can be suppressed to 0.1 MV / cm or less. FLR However, if the rated voltage VR [V] × 0.09 μm or more, the electric field strength can be kept to 0.09 MV / cm or less, and if the rated voltage VR [V] × 0.1 μm or more, the electric field strength can be kept to 0.08 MV / cm or less.

[0136] The gate electrode 13 may extend onto the field insulating film 4. However, if the gate electrode 13 protrudes to the periphery beyond the termination well region 2, a location with a low potential will be generated above the FLR region 3. This may increase the electric field strength on the upper surface of the epitaxial layer 32 in the FLR region 3 and on the upper surface of the surface protective film 6 above the FLR region 3. In contrast, in the second embodiment, the outer periphery edge of the gate electrode 13 is located inside the MOSFET 200 relative to the outer periphery edge of the termination well region 2 in a plan view, and therefore the increase in the electric field strength can be suppressed.

[0137] <Summary of the Second Embodiment> As described above, according to the MOSFET 200 of the second embodiment, the formation of a leakage path different from the normal state when a high voltage is applied in a high-temperature and high-humidity environment can be suppressed, thereby improving the insulation reliability of the MOSFET 200.

[0138] <Embodiment 3> A power conversion device and a method for manufacturing the power conversion device according to the third embodiment will be described. In the third embodiment, the semiconductor device according to the first and second embodiments described above is applied to the power conversion device. Therefore, in the following description, components similar to those described in the first and second embodiments are illustrated with the same reference numerals, and detailed description thereof will be omitted as appropriate.

[0139] <Configuration> The power conversion device according to the third embodiment is not limited to a specific application, but the following description will be given of a case where it is applied to a three-phase inverter.

[0140] FIG. 16 is a block diagram illustrating a schematic configuration of a power conversion system including a power conversion device 2200 according to the third embodiment.

[0141] The power conversion system shown in Fig. 16 includes a power supply 2100, a power conversion device 2200, and a load 2300. The power supply 2100 is a DC power supply and supplies DC power to the power conversion device 2200. The power supply 2100 can be configured with various power supplies, and may be configured with, for example, a DC system, a solar cell, or a storage battery. The power supply 2100 may also be configured with a rectifier circuit or an AC-DC converter connected to an AC system. The power supply 2100 may also be configured with a DC-DC converter that converts DC power output from a DC system into predetermined power.

[0142] The power conversion device 2200 is a three-phase inverter connected between the power source 2100 and the load 2300. The power conversion device 2200 converts DC power supplied from the power source 2100 into AC power, and supplies the AC power to the load 2300.

[0143] As shown in FIG. 16 , the power conversion device 2200 includes a conversion circuit 2201 that converts DC power into AC power and outputs it, a drive circuit 2202 that outputs drive signals for driving each switching element of the conversion circuit 2201, and a control circuit 2203 that outputs a control signal to the drive circuit 2202 for controlling the drive circuit 2202.

[0144] The load 2300 is a three-phase motor driven by AC power supplied from the power conversion device 2200. The load 2300 is not limited to a specific application, but is a motor mounted on various electric devices, and is used as a motor for, for example, a hybrid vehicle, an electric vehicle, a railroad car, an elevator, or an air conditioner.

[0145] The power conversion device 2200 will be described in detail below. The conversion circuit 2201 includes a switching element and a free wheel diode (not shown). The switching element performs a switching operation, so that the conversion circuit 2201 converts DC power supplied from the power source 2100 into AC power and supplies the AC power to the load 2300.

[0146] Various specific circuit configurations are assumed for the conversion circuit 2201, and the conversion circuit 2201 according to the third embodiment is a two-level three-phase full-bridge circuit, and can be composed of six switching elements and six freewheeling diodes connected in inverse parallel to each switching element.

[0147] The semiconductor device according to any one of the above-mentioned first and second embodiments is applied as at least one of the switching elements and the free wheel diodes in the conversion circuit 2201. The six switching elements are connected in series in groups of two to form upper and lower arms, and each of the upper and lower arms forms each phase (U phase, V phase, and W phase) of the full bridge circuit. The output terminals of each of the upper and lower arms, i.e., the three output terminals of the conversion circuit 2201, are connected to the load 2300.

[0148] The drive circuit 2202 generates drive signals for driving the switching elements of the conversion circuit 2201, and supplies the drive signals to control electrodes of the switching elements of the conversion circuit 2201. Specifically, based on control signals output from a control circuit 2203 (described later), the drive circuit 2202 outputs drive signals for turning the switching elements on and off to the control electrodes of the respective switching elements.

[0149] When the switching element is maintained in the on state, the drive signal is a voltage signal (on signal) that is equal to or greater than the threshold voltage of the switching element, and when the switching element is maintained in the off state, the drive signal is a voltage signal (off signal) that is less than the threshold voltage of the switching element.

[0150] The control circuit 2203 controls the switching elements of the conversion circuit 2201 so that a desired power is supplied to the load 2300. Specifically, the control circuit 2203 calculates the time (on time) during which each switching element of the conversion circuit 2201 should be in an on state based on the power to be supplied to the load 2300. For example, the conversion circuit 2201 can be controlled by pulse width modulation (PWM) control that modulates the on time of the switching element according to the voltage to be output.

[0151] Then, the control circuit 2203 outputs a control command (control signal) to the drive circuit 2202 so that an ON signal is output to the switching element that should be in the ON state at each point in time, and an OFF signal is output to the switching element that should be in the OFF state. Based on the control signal, the drive circuit 2202 outputs an ON signal or an OFF signal as a drive signal to the control electrode of each switching element.

[0152] Usually, semiconductor devices are embedded in gel or epoxy resin when used, but these materials cannot completely block moisture, and therefore the insulation reliability of the semiconductor device is impaired. In contrast, in the power conversion device 2200 according to the third embodiment, the semiconductor device according to either the first or second embodiment, which has improved insulation reliability, is used as at least one of the switching element and the free wheel diode of the conversion circuit 2201. This makes it possible to improve the reliability of the power conversion device 2200.

[0153] In the third embodiment, an example has been described in which the semiconductor device of the first and second embodiments is applied to a two-level three-phase inverter, but the semiconductor device of the first and second embodiments can be applied to various power conversion devices.

[0154] In addition, in the third embodiment, a two-level power conversion device has been described, but the semiconductor devices of the first and second embodiments can be applied to a three-level or multilevel power conversion device. When power is supplied to a single-phase load, the semiconductor devices of the first and second embodiments can be applied to a single-phase inverter. When power is supplied to a DC load or the like, the semiconductor devices of the first and second embodiments can be applied to a DC-DC converter or an AC-DC converter.

[0155] The power conversion device according to the third embodiment is not limited to the above-mentioned load being an electric motor, and can be used as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a non-contact power supply system, for example. The power conversion device according to the third embodiment can also be used as a power conditioner in a solar power generation system, a power storage system, or the like.

[0156] <Manufacturing method> Next, a method for manufacturing a power conversion device according to the present embodiment 3 will be described. First, a semiconductor device is manufactured by the manufacturing methods described in the embodiments 1 and 2. Then, a conversion circuit 2201 having the semiconductor device is incorporated into a power conversion device 2200. The conversion circuit 2201 is a circuit for converting input power and outputting it.

[0157] A drive circuit 2202 is then incorporated into the power conversion device 2200. The drive circuit 2202 is a circuit for outputting a drive signal for driving the semiconductor device to the semiconductor device. A control circuit 2203 is then incorporated into the power conversion device 2200. The control circuit 2203 is a circuit for outputting a control signal for controlling the drive circuit 2202 to the drive circuit 2202.

[0158] Although the semiconductor device described in the first and second embodiments is an example configured with a SiC semiconductor, it is also possible to use a switching element configured with other wide band gap semiconductors such as gallium nitride (GaN) or gallium oxide (Ga2O3). A switching element configured with a wide band gap semiconductor can be used in a high voltage region where unipolar operation is difficult with a Si switching element, and can greatly reduce switching loss occurring during switching operation. Therefore, it is possible to greatly reduce power loss.

[0159] In addition, switching elements made of wide band gap semiconductors have low power loss and high heat resistance, so when configuring a power module equipped with a cooling unit, it is possible to reduce the size of the heat dissipation fins of the heat sink, making it possible to further reduce the size of the semiconductor module.

[0160] In addition, switching elements made of wide band gap semiconductors are suitable for high frequency switching operations, so when they are applied to converter circuits that require higher frequencies, the increased switching frequency can reduce the size of reactors or capacitors connected to the converter circuits.

[0161] In each of the above embodiments, the physical properties, materials, dimensions, shapes, relative positional relationships, or implementation conditions of each component may be described, but these are merely examples in all respects, and the present disclosure is not limited to those described. Therefore, countless modified examples not illustrated are assumed within the scope of the present disclosure.

[0162] For example, this includes cases in which any component is modified, added, or omitted, and cases in which at least one component in at least one embodiment is extracted and combined with a component of another embodiment.

[0163] Additionally, unless a contradiction arises, a component described in each of the above embodiments as being provided with "one" may be provided with "one or more." Furthermore, the components constituting the present disclosure are conceptual units, and one component may include multiple structures, or one component may correspond to a part of a structure. Furthermore, each component of the present disclosure includes structures having other structures or shapes as long as they perform the same function.

[0164] It should be noted that the embodiments and modifications may be freely combined, and the embodiments and modifications may be modified or omitted as appropriate.

[0165] The above description is illustrative in all respects and is not restrictive. It is understood that countless variations not illustrated can be envisioned. [Explanation of symbols]

[0166] 2 termination well region, 3 FLR region, 3a floating well, 4 field insulating film, 5 surface electrode, 6 surface protective film, 8 back electrode, 12 gate insulating film, 13 gate electrode, 14 interlayer insulating film, 30 epitaxial substrate, 41 sealing resin, 51 source electrode, 52 gate wiring electrode, 100 SBD, 200 MOSFET, 2201 conversion circuit, 2202 drive circuit, 2203 control circuit, W FLR length.

Claims

1. A semiconductor device having an active region and a termination region surrounding the active region in a plan view, a semiconductor substrate of a first conductivity type made of silicon carbide; a second conductivity type termination well region selectively provided on an upper portion of the semiconductor substrate in the termination region and surrounding the active region in a plan view; an FLR region selectively provided on an upper portion of the semiconductor substrate in the termination region and surrounding the termination well region in a plan view; a field insulating film provided on the semiconductor substrate and covering a part of the termination well region and the FLR region; a surface electrode provided on the semiconductor substrate on the side of the active region relative to the field insulating film; an upper surface film provided on the field insulating film and covering an end portion of the surface electrode on the termination region side; a back surface electrode provided on a back surface of the semiconductor substrate; Equipped with the FLR region includes a plurality of floating wells of a second conductivity type having a floating potential, the floating wells being spaced apart from one another and nested in a manner that surrounds the termination well region in a plan view, the FLR region includes a region in which the distance between adjacent floating wells increases toward the outer periphery of the FLR region, A semiconductor device, wherein when a voltage 0.8 times the rated voltage VR [V] of the semiconductor device is applied to the back electrode with respect to the front electrode, the electric field strength on the top surface of the semiconductor substrate outside the outer periphery of the termination well region is 1 MV / cm or less.

2. The semiconductor device according to claim 1, A semiconductor device, wherein the number of the plurality of floating wells is equal to or greater than VR / 100, where VR [V] is a rated voltage of the semiconductor device.

3. 3. The semiconductor device according to claim 2, A semiconductor device, wherein the distance from the outer circumferential edge of the termination well region to the outer circumferential edge of the FLR region is VR×0.08 μm or more.

4. 4. The semiconductor device according to claim 3, A semiconductor device, wherein when a voltage 0.8 times the rated voltage VR [V] of the semiconductor device is applied to the back electrode with respect to the front electrode, the electric field strength at the top surface of the top film outside the outer circumferential end of the termination well region is 0.1 MV / cm or less.

5. 5. The semiconductor device according to claim 1, a peripheral edge of the surface electrode is provided on the field insulating film and is located inside the peripheral edge of the termination well region in a plan view of the semiconductor device.

6. 5. The semiconductor device according to claim 1, a gate insulating film provided on the semiconductor substrate on the active region side of the field insulating film; a gate electrode provided on the gate insulating film; an interlayer insulating film covering the gate electrode; Further equipped with The surface electrode is a source electrode and a gate wiring electrode provided on the semiconductor substrate via the interlayer insulating film and divided on the interlayer insulating film; a gate wiring electrode and a gate electrode, each of which has an outer circumferential edge located inside the outer circumferential edge of the termination well region in a plan view;

7. 5. The semiconductor device according to claim 1, The second conductivity type impurity concentration per unit area of ​​the plurality of floating wells is 1.5×10 １３ cm －２ That is the semiconductor device.

8. 5. The semiconductor device according to claim 1, The second conductivity type impurity concentration in the upper surface of the plurality of floating wells is 1.0×10 １７ cm －３ The semiconductor device is as follows:

9. 5. The semiconductor device according to claim 1, The semiconductor device has an avalanche voltage of 1.7 kV or more.

10. 5. The semiconductor device according to claim 1, The semiconductor device further comprises a gel-like sealing resin covering the upper surface film.

11. 5. The semiconductor device according to claim 1, The semiconductor device further comprises a thermosetting sealing resin covering the upper surface film.

12. 5. The semiconductor device according to claim 1, a field insulating film covering the FLR region, the field insulating film being made of silicon oxide;

13. 13. The semiconductor device according to claim 12, The field insulating film is in contact with the upper surface film.

14. 9. The method of manufacturing a semiconductor device according to claim 8, The method for manufacturing a semiconductor device, wherein the FLR region is formed with ion implantation energy of 300 keV or more.

15. A conversion circuit having the semiconductor device according to any one of claims 1 to 4, which converts input power and outputs the converted power; a drive circuit that outputs a drive signal for driving the semiconductor device to the semiconductor device; a control circuit that outputs a control signal to the drive circuit; A power conversion device comprising:

Images