METHOD FOR STORING MEMORY FAILURE DATA, APPARATUS FOR STORING THE SAME, AND COMPUTER PROGRAM - Patent application

Abstract

To provide a method of storing memory failure data, a device using the same, and a computer program.SOLUTION: A method of the present invention includes: selectively storing one part of memory failure data in a failure buffer based on an address of a selected first line of row lines or column lines of memory failure data detected from a plurality of failure cells in which failures occurred; storing an address of a second line and the number of failures in a defect filter based on the address of the remaining second line; and storing one part of memory failure data in a defect storing portion in the memory using information stored in the failure buffer and the defect filter. According to the present invention, it becomes possible to reduce the structure and device hardware overhead for storing memory failure data and reduce the time required to read memory failure data.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a method, an apparatus, and a computer program for storing memory failure data, and more particularly to a method, an apparatus, and a computer program for storing memory failure data resulting from a memory test.

[0002] This invention is the result of a research project on "Ultra-high-speed memory system (CK 8GHz DQ 16Gbps) equipment structure", the organization in charge of this project is Korea Institute for Industrial Technology Assessment and Management, and the name of the research project is "Industrial Technology Innovation Project". The project ID number is 1415181114, and the project ID number is 20019363. [Background technology]

[0003] FIG. 1 is a diagram for explaining an example of a conventional method for storing memory failure data based on a fault bitmap.

[0004] 1, after memory test and repair was introduced for memory yield, a fault bitmap was adopted as a memory fault data storage structure and is widely used to store memory fault data. This is because, when a memory test is performed, the same memory fault is not detected within one memory test pattern, but the same memory fault is repeatedly detected while all memory test patterns are applied to the memory in sequence.

[0005] If a fault bitmap were not used, a newly detected fault would have to be compared with all previously detected faults to prevent storing the same memory fault in the memory fault data storage structure and to preserve available space for another fault.

[0006] On the other hand, in the case of a fault bitmap, since it is possible to simply write 1 to the corresponding location without making a comparison, the use of fault bitmaps has become commonplace.

[0007] However, in order to classify memory failure data from the fault bitmap, all data must be read from the fault bitmap. Since the size of the fault bitmap is the same as the memory capacity, the time required to read all data from the fault bitmap increases significantly at a time when memory capacity has increased exponentially. Summary of the Invention [Problem to be solved by the invention]

[0008] It is an object of the present invention to provide a method for storing memory fault data, an apparatus for doing so, and a computer program product, which reduce the hardware overhead of a structure and apparatus for storing memory fault data and reduce the time it takes to read the memory fault data.

[0009] Other objects of the present invention that are not explicitly stated can be considered within the scope that can be easily inferred from the following detailed description and its effects. [Means for solving the problem]

[0010] According to an embodiment of the present invention, there is provided a method for storing memory fault data, the method comprising: A processor selectively stores a portion of the memory failure data in a failure buffer of the memory based on an address of a first line selected from row lines or column lines of memory failure data detected from a plurality of failed cells in the test memory where a failure has occurred; storing the address of a second line, which is another one of the row line or column line of the memory failure data, and the number of failures in a defect filter of the memory; The method includes storing a portion of the selectively stored memory fault data in a fault store of the memory, taking into consideration the address of the second line and the number of faults stored in the fault filter.

[0011] In the present invention, the detected memory failure data is sequentially detected while a failure test is performed on the test memory, and the first line is a row line and the second line is a column line. The row lines of the failure buffer correspond to the row lines of the memory failure data, and the column lines of the failure buffer include a counter indicating the number of failures occurring for each row line, and the number of the column lines of the failure buffer depends on the number of spare resources for the column lines of the failure buffer, and the number of spare resources for the column lines may be less than the number of the column lines of the memory failure data.

[0012] The memory failure data selectively stored in the failure buffer includes a row line address and a column line address corresponding to a position of a failure cell where a failure has occurred, and a processor selectively stores a portion of the detected memory failure data in the failure buffer based on the row line address.

[0013] The processor of the present invention selectively stores a portion of the detected memory failure data in the failure buffer includes storing the detected memory failure data for a selected portion of the cells in which the failure occurs, taking into consideration the information stored in the counter and a first reference value predetermined according to the number of column lines of the failure buffer.

[0014] The processor of the present invention selectively storing a portion of the detected memory failure data in a failure buffer may include the processor sequentially storing address information of column lines for failures occurring in each row line in the failure buffer, and when the number of failures occurring in an Nth row line is greater than the number of spare resources in the column direction, determining the Nth row line as a target for failure repair and not storing any more address information of column lines for the Nth row line.

[0015] In the present invention, storing the address of the second line and the number of faults in the defect filter of the memory may include the processor storing the address of the column line and the number of faults corresponding to the column line in the defect filter of the memory based on the address of the column line.

[0016] In the present invention, the step of storing the column line addresses and the number of faults in the defect filter of the memory may include storing in the defect buffer the column line addresses for each of the faulty cells stored sequentially by row line in the fault buffer, and updating the number of faults associated with the stored column line addresses.

[0017] In the present invention, the processor may store memory failure data for selected cells among the faulty cells corresponding to the column line in the defect storage, taking into consideration the number of faults updated in association with the address of the column line and a second predetermined reference value. The processor may store row line address information and column line address information for the faulty cells stored in the fault buffer in the defect storage, and may determine the M column line as a target for fault repair when the number of updated faults stored in the defect buffer exceeds a second predetermined reference value, and may not store memory failure data for the faulty cells in the M column line in the defect storage any more.

[0018] In the present invention, the processor may sequentially store memory failure data including address information of row line and address information of column line for a faulty cell in row line of the fault buffer corresponding to the row line, and when the number of faults occurring in the Nth row line is greater than the number of spare resources in the column direction, the processor may temporarily store the address information of column line for the faulty cell associated with the Nth row line in an additional row line. In this case, the processor may selectively store the memory failure data for the faulty cell temporarily stored in the additional row line in the fault storage, taking into consideration the number of faults for the column line stored in the defect buffer.

[0019] In order to achieve another object of the present invention, a memory failure data storage device according to the present invention includes a processor and a memory for storing instructions for executing a method for storing memory failure data obtained through a failure test on a test memory to be tested, the method being performed by the processor, The method of storing memory failure data performed by the processor is as follows: The method may further include the steps of: selectively storing a portion of the memory failure data in a failure buffer of the memory based on an address of a first line selected from row lines or column lines of memory failure data detected from a plurality of failure cells in which failures have occurred in a test memory; based on an address of a second line, which is another one of the row lines or column lines of the memory failure data, storing an address of the second line and a number of failures in a defect filter of the memory; and storing the selectively stored portion of the memory failure data in a defect storage of the memory based on the address of the second line and the number of failures stored in the defect filter.

[0020] In order to achieve the above technical objectives, a method for storing memory failure data according to a preferred embodiment of the present invention includes the steps of obtaining first memory failure data for a memory, obtaining only failure data that needs to be stored from the first memory failure data based on a row direction of the memory to obtain second memory failure data, obtaining only failure data that needs to be stored from the second memory failure data based on a column direction of the memory to obtain third memory failure data, and storing the third memory failure data as final memory failure data required for repairing the memory.

[0021] Here, the first memory failure data acquiring step may be implemented by acquiring the first memory failure data including first failure data detected while a test of the memory is in progress.

[0022] Here, the second memory fault data acquiring step may be realized by acquiring the second memory fault data from the first memory fault data using a fault buffer having a number of rows equal to the number of rows of the memory and a number of columns set based on a number of spare resources in the column direction.

[0023] In this case, the second memory failure data acquiring step can be realized by: when the first failure data, consisting of a first row address and a first column address according to the first memory failure data, is input to the failure buffer, storing an address of the first column of the first failure data in an empty column of a row of the failure buffer corresponding to the address of the first row of the first failure data; incrementing a value of a count column corresponding to the row of the failure buffer by 1; if the value of the count column corresponding to the row of the failure buffer is greater than a number of spare resources in the column direction, setting the address of the row corresponding to the row of the failure buffer as a row-wise row needing repair; if there is no empty column in the row of the failure buffer corresponding to the address of the first row of the first failure data, the address of the row corresponding to the row of the defect buffer is the row-wise row needing repair, and not storing the first failure data in the defect buffer.

[0024] Here, the second memory failure data acquisition step can be realized by acquiring the second memory failure data including the first failure data as second failure data when the first failure data is stored in the defect buffer.

[0025] Here, the third memory failure data acquisition step can be realized by acquiring the third memory failure data from the second memory failure data using a fault filter having a number of rows equal to the number of columns of the memory, and two columns in which column addresses and count values ​​are stored.

[0026] In the third memory failure data acquiring step, when the second failure data, which is composed of a second row address and a second column address according to the second memory failure data, is input to the defect filter, if the second column address of the second failure data has already been stored in a column address column of the defect filter, and if the value of the count column corresponding to the stored column address column is equal to or less than the number of spare resources in the row direction, the value of the count column corresponding to the stored column address column is incremented by 1, and the value of the count column corresponding to the stored column address column is incremented by 1. If the number is greater than the number of spare resources, the column address corresponding to the address of the second column of the second failure data is set as a column-wise row needing repair, and since the column address corresponding to the address of the second column of the second failure data is the column-wise row needing repair, the second failure data is not stored in the defect filter; if the address of the second column of the second failure data is not stored in the column address column of the defect filter, the address of the second column of the second failure data is stored in an empty row of the column address column, and the value of the count column corresponding to the column address column is increased by 1.

[0027] Here, the third memory failure data acquisition step can be realized by acquiring the third memory failure data including the second failure data as third failure data when the second failure data is stored in the defect filter.

[0028] Here, the final memory failure data storing step can be realized by storing the third failure data consisting of a third row address and a third column address according to the third memory failure data in a fault storage as final failure data, and storing the final memory failure data necessary for repairing the memory.

[0029] In order to achieve the above technical objectives, a computer program according to a preferred embodiment of the present invention is stored in a computer-readable storage medium and causes a computer to execute any one of the above memory failure data storage methods.

[0030] In order to achieve the above technical objectives, a memory failure data storage device according to a preferred embodiment of the present invention includes: a memory storing one or more programs for storing memory failure data; and one or more processors performing an operation for storing memory failure data in accordance with the one or more programs stored in the memory; wherein the processor acquires first memory failure data for a memory, acquires only failure data that needs to be stored from the first memory failure data based on a row direction of the memory to acquire second memory failure data, acquires only failure data that needs to be stored from the second memory failure data based on a column direction of the memory to acquire third memory failure data, and stores the third memory failure data as final memory failure data required for repairing the memory.

[0031] Here, the processor may obtain the first memory failure data including first failure data detected while testing of the memory is in progress.

[0032] Here, the processor may obtain the second memory failure data from the first memory failure data using a fault buffer having a number of rows equal to the number of rows of the memory and a number of columns set based on the number of spare resources in the column direction. Effect of the Invention

[0033] According to the method, apparatus, and computer program for storing memory fault data according to preferred embodiments of the present invention, the hardware overhead of structures and apparatus for storing memory fault data can be reduced, and the time required to read memory fault data can be shortened, thereby significantly reducing overall memory testing and repair costs. The effects of the present invention are not limited to those described above, and other effects not described will be clearly understood by those skilled in the art from the following description. [Brief description of the drawings]

[0034] [Figure 1] 1 is a diagram illustrating an example of a conventional method for storing memory failure data based on a fault bitmap; [Diagram 2] 1 is a block diagram illustrating a memory failure data storage device according to a preferred embodiment of the present invention; [Diagram 3] 4 is a flowchart illustrating a method for storing memory failure data according to a preferred embodiment of the present invention. [Figure 4] 1 is a diagram illustrating an example of a method for storing memory failure data according to a preferred embodiment of the present invention; [Diagram 5] FIG. 1 illustrates an example of an unnecessary failure according to a preferred embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0035] Hereinafter, the embodiments of the present invention will be described in detail with reference to the attached drawings. Advantages and features of the present invention, as well as methods for achieving the same, will become apparent from the following detailed embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments shown below, and may be embodied in various different forms, and the present embodiments are provided to complete the disclosure of the present invention and to fully explain the scope of the invention to those skilled in the art to which the present invention pertains, and the present invention is defined by the scope of the claims. The same reference numerals refer to the same elements throughout the specification.

[0036] Unless otherwise defined, all terms (including technical and scientific terms) used in this specification are used in the sense commonly understood by those having ordinary skill in the art to which the present invention belongs. In addition, terms defined in commonly used dictionaries are not interpreted ideally and excessively unless clearly and specifically defined.

[0037] In this specification, the terms "first", "second", etc. are used to distinguish one component from another component, and should not be used to limit the scope of the rights. For example, the first component can be named as the second component, and similarly, the second component can be named as the first component.

[0038] In this specification, identification numbers (e.g., a, b, c, etc.) are used in each step for convenience of explanation, and the identification numbers do not describe the order of each step, and each step may be performed in a different order than specified unless a specific order is clearly stated in the context. That is, each step may be performed in the same order as specified, substantially simultaneously, or in the reverse order.

[0039] In this specification, terms such as "have," "may have," "include," or "may include" indicate the presence of a given feature (e.g., a value, function, operation, or component such as a part) and do not exclude the presence of additional features.

[0040] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of a method for storing memory fault data, an apparatus for performing the same, and a computer program according to the present invention will be described in detail with reference to the accompanying drawings.

[0041] First, a memory failure data storage device according to a preferred embodiment of the present invention will be described with reference to FIG.

[0042] 2 is a block diagram illustrating a memory fault data storage device according to a preferred embodiment of the present invention. Referring to FIG. 2, the memory fault data storage device 100 according to a preferred embodiment of the present invention can reduce the hardware overhead of the structure and device for storing memory fault data and shorten the time required to read memory fault data. As a result, the present invention can significantly reduce the overall memory test and repair costs.

[0043] The memory fault data storage device 100 shown in Fig. 2 includes a processor 110, a memory 120, a test logic generator 130, an input / output interface 140, and a communication interface 150. In Fig. 2, the memory under test is a target of a fault test.

[0044] The memory failure data storage device 100 according to the present invention is, for example, an automated test equipment (ATE) for diagnosing a failure in a memory. The test logic generator 130 generates a test logic or a pre-designed algorithmic pattern for diagnosing a test memory. The test logic generator may be, for example, an algorithmic pattern generator (APG). The test logic generator 130 generates a signal associated with a test logic and transmits the test logic to an external test memory via an input / output interface 140 or a communication interface 150. The test logic generator 130 may be embodied as the test logic generator 130 in the form of hardware or software. A source code for generating a test logic signal may be stored in the memory 120, and the processor 110 may be embodied to perform an operation for generating the test logic signal.

[0045] Existing memory failure data storage devices store and manage memory failure data in the form of a fault bitmap, but the memory failure data storage device of the present embodiment removes unnecessary failure data from the memory failure data obtained as a result of memory testing and selects and stores necessary failure data.

[0046] The processor 110 may control the operation of the memory fault data storage device 100. For example, the processor 110 may execute one or more programs stored in the memory 120 or a computer-readable storage medium. The one or more programs may include one or more computer-executable instructions that, when executed by the processor 110, may be configured to cause the memory fault data storage device 100 to perform an operation to store the memory fault data.

[0047] The input / output interface 140 is connected to the processor 110 and the test logic generator 130 via a data bus, and enables data transfer with an external device. The input / output interface 140 provides a test pattern signal including a test logic to an external memory to be tested (a test memory). The test pattern signal can also be transmitted to the test memory via a communication interface 150.

[0048] When a faulty cell is included in the test memory, the response of the test memory to the test pattern signal includes fault information (memory fault data) detected from the faulty cell. The memory fault data includes location information (address information of row line, address information of column line) of the faulty cell.

[0049] The memory 120 (which may also include a computer-readable storage medium) is configured to store computer-executable instructions or program code, program data, and / or other suitable forms of information for storing memory fault data. The memory may be a volatile memory, such as a random access memory (RAM), a non-volatile memory, or a suitable combination thereof. The memory may also be one or more magnetic disk storage devices, optical disk storage devices, flash memory devices, or other forms of storage media that can be accessed by the memory fault data storage apparatus 100 to store the desired information, or a suitable combination thereof.

[0050] Preferably, in this embodiment, the memory 120 may include a fault buffer (122), a fault filter (124), and a fault storage (126). The fault buffer, fault filter, and fault storage refer to memory areas in which data is stored. The fault buffer, fault filter, and fault storage may be implemented as separate memories, or may be implemented in a single memory with different storage areas allocated to each of them.

[0051] The processor 110 selectively stores a portion of memory failure data detected from the test memory in the failure buffer 122. The processor 110 selectively stores a portion of the memory failure data in the failure buffer of the memory based on an address of a first line selected from row lines or column lines of memory failure data detected from a plurality of failed cells in which failures have occurred in the test memory. Here, the first line may be a row line and the second line may be a column line, or vice versa.

[0052] 4, "Fault Detection Order" refers to the order in which fault information for faulty cells is detected sequentially. Memory fault data is a concept of a collection of such fault information. The processor 110 of the present embodiment does not store all acquired memory fault data in a defect storage, but stores them selectively.

[0053] First, the processor 110 selectively stores a portion of the memory failure data in the failure buffer 122. Referring to FIG. 4, assuming that the row line is the first line and the column line is the second line, it is preferable that the row line of the failure buffer 122 corresponds to the row line of the failure memory data. The number (size) of column lines of the failure buffer depends on the number of spare resources of the column line (e.g., spare column in FIG. 5). It is preferable that the number of column lines of the failure buffer is less than the number of column lines of the area where data exists in the test memory and more than the number of spare resources of the column line. The column lines of the failure buffer may include a column line address area for storing the address of the column line of the failure cell where a failure occurs, and a counter. The counter is the number of column lines where a failure occurs in the corresponding row line, and the counter value is increased as the column line address information is stored.

[0054] For example, when there are four faulty cells in the second column, the processor 110 sequentially stores address information of the column lines of the faulty cells in the fault buffer. The counter value indicates the number of stored address information of the column lines. In this embodiment, the processor 110 compares the information stored in the counter with a first reference value that is predetermined according to the number of column lines in the fault buffer. The processor 110 determines whether or not to set the corresponding row line as a row line to be repaired according to the comparison result. In relation to the row line determined as the row line to be repaired, the processor does not store address information of the column lines for the additional faulty cells in the fault buffer even if an additional faulty cell exists. Here, the first reference value is the maximum number of faulty cells to be recorded in the fault buffer, and in the case of FIG. 4, the first reference value is 3. If the counter value is 3, the #5(2,7) information is not recorded in the fault buffer. The processor 110 also determines the corresponding row line as a row line to be repaired according to the comparison result.

[0055] The processor 110 of the present embodiment sequentially stores address information of column lines for failures occurring in each row line in the failure buffer, and selectively stores some memory failure data for row lines that satisfy a specific condition. For example, if the number of failures occurring in the Nth row line is greater than the number of spare resources in the column direction, the processor 110 may determine the Nth row line as a target for failure repair and may perform an operation of not storing any more address information of column lines for the Nth row line.

[0056] A method for storing memory failure data, comprising selectively storing memory failure data for faulty cells temporarily stored in the additional row line in the defect storage location, taking into consideration the number of faults for the column line stored in the defect buffer.

[0057] Next, the processor 110 stores in the defect filter 124 the address of the second line, which is the other one of the row lines or column lines of the memory failure data, and the number of failures based on the address of the second line.

[0058] When the first line is a row line and the second line is a column line, the processor 110 stores address information of the column line and the number of faults occurring in the corresponding column line in the defect filter 124 based on the address of the column line. The processor counts the number of faults for each column line from the memory fault information selectively stored in the fault buffer. For example, referring to FIG. 4, the processor does not store the initially acquired information of #5(2,7) in the fault buffer, so the presence of a faulty cell in the 7th column of #5(2,7) is not counted by the defect filter.

[0059] The defect filter includes an area for storing address information of a column line, and a counter, which stores information on the number of defective cells on a column line basis.

[0060] Referring to FIG. 4, in “5,3” which is the first row of the defect filter, “5” means column line information of the first faulty cell #1(1,5). “3” means “the number of faulty cells in which a fault has occurred in the fifth column line”. However, referring to FIG. 4, “in the case of the fifth column line, the number of faulty cells is indicated as 4”. In this embodiment, a second predetermined reference value, which will be described later, is the maximum value of the counter value of the defect filter 124. Referring to FIG. 4, the second reference value is “3”, and the counter value increases according to the number of faulty cells recognized, but does not exceed 3. When the counter value corresponds to the second reference value, the processor 110 does not count the number of faulty cells in the corresponding column line any more, and determines the corresponding cell line as a column line to be repaired.

[0061] More specifically, the processor 110 of the present embodiment stores row address information and column address information for the faulty cells stored in the fault buffer in the defect storage, and if the number of updated faults stored in the fault buffer exceeds a second predetermined reference value, determines the Mth column line as a target for fault repair, and does not store any more memory fault data for the faulty cells in the Mth column line in the defect storage.

[0062] Next, the processor 110 stores a portion of the selectively stored memory failure data in the memory failure storage 126, taking into consideration the address of the second line and the number of failures stored in the defect filter 124. The processor 110 selects a portion of the memory failure data stored in the fixed buffer 122 and stores it in the defect storage 126, referring to the information stored in the defect filter 124. The defect filter 124 stores the address of the column line and information on the number of failures occurring at the address of the column line. When the counter value of the defect filter corresponds to a second reference value, the processor 110 deletes the memory failure information for the failed cell occurring in the corresponding column line (corresponding to #10(7,5) with reference to FIG. 4), and finally stores the memory failure data stored in the failure buffer that has not been deleted in the defect storage 126.

[0063] According to another embodiment of the present invention, when the number of faults occurring in the Nth row line is greater than the number of spare resources in the column direction, the processor 110 may temporarily store fault information for additional faulty cells in additional row lines rather than deleting the fault information.

[0064] The additional row line may be, for example, an additional fault buffer (not shown) separate from the fault buffer or may be located in a region below the fault buffer, but is not limited thereto. The additional row line stores information on faulty cells that do not need to be stored any more because the row line currently being processed has already been classified as a repair target. The processor temporarily stores faulty cell information (row line address and column line address) that does not need to be stored any more or is to be deleted in the additional fault buffer. In this case, the processor generates and inputs information to the defect filter, taking into consideration not only the information stored in the fault buffer but also the information temporarily stored in the defect filter.

[0065] The processor counts the number of faulty cells generated at the column line address of the faulty cell temporarily stored in the additional row line, taking into consideration the additional faulty cells. For example, if the number of faulty cells is less than the second reference value, the processor deletes the fault information of the additional faulty cells temporarily stored in the additional row line. Conversely, if the number of faulty cells is equal to or exceeds the second reference value, the processor does not delete the fault information of the additional faulty cells. As a result, the deletion process is performed at the fault buffer 122 stage, and thus errors that are dropped from the column line to be repaired can be reduced.

[0066] A method for storing memory fault data according to a preferred embodiment of the present invention will now be described with reference to FIG.

[0067] 3 is a flow chart illustrating a method for storing memory fault data according to a preferred embodiment of the present invention. Each step illustrated in FIG. 3 includes the following steps, which are performed in time sequence in the memory fault data storage device 100. The same points as those described above with reference to FIG. 2 will be omitted.

[0068] 3, the processor 110 of the memory failure data storage device 100 acquires memory failure data for identifying the location of a failed cell where a failure has occurred from the test memory (S110). The memory failure data is a response obtained by applying a test pattern to the test memory, and may include cell location information of the test memory and information stored in each cell. There is no particular limit to the method of determining whether a failure has occurred in the test memory, and the processor 110 can easily acquire information on the failed cell where a failure has occurred (memory failure data) using various known methods, as shown in the upper left part of FIG.

[0069] Next, the processor 110 selectively stores a portion of the acquired memory failure data in a failure buffer based on the row line of the memory failure data (S120). The row lines of the failure buffer correspond to the row lines of the test memory, and the column lines sequentially store column line information of the failure cells present in the corresponding row lines. The column lines include an area for storing column line information and a count.

[0070] Next, the processor 110 stores the number of failures and the address of the column line in the defect filter 124 based on the column line of the memory failure data (S130). Referring to FIG. 4, column line address information and a counter value are stored in the column line of the defect filter. The processor sequentially records information of the failed cells stored in the failure buffer in the defect filter. The counter value does not exceed a second reference value, for example, if the second reference value is 3 as shown in FIG. 4, the processor can determine a cell with a counter value of 3 as a cell line to be repaired. For a cell determined as a cell line to be repaired, the processor does not store any more information on the failed cell as final memory failure data.

[0071] The processor 110 then uses the information stored in the defect filter to store a portion of the memory failure data stored in the fault buffer in the defect storage 126 as final memory failure data.

[0072] According to another embodiment of the present invention, the processor 110 of the memory failure data storage device 100 may acquire first memory failure data for a memory. That is, the processor 110 may acquire first memory failure data including first failure data detected while a test of the memory is in progress.

[0073] Next, the processor 110 may obtain only the fault data that needs to be stored from the first memory fault data based on the row direction of the memory, and obtain the second memory fault data. In this case, the processor 110 may obtain the second memory fault data from the first memory fault data using a fault buffer. Here, the fault buffer may have the same number of rows as the number of rows of the memory, and a number of columns (a column address column in which the address of the column is stored and a count column in which the count value is stored) set based on the number of spare resources in the column direction. That is, when the first failure data consisting of a first row address and a first column address according to the first memory failure data is input to the failure buffer, the processor 110 stores the address of the first column of the first failure data in an empty column of the row of the failure buffer corresponding to the address of the first row of the first failure data, increments the value of the count column corresponding to the row of the failure buffer by 1, and if the value of the count column corresponding to the row of the failure buffer is greater than the number of spare resources in the column direction, sets the address of the row corresponding to the row of the failure buffer as a row-wise repair-needed row. On the other hand, if there is no empty column in the row of the failure buffer corresponding to the address of the first row of the first failure data, the processor 110 does not need to store the first failure data in the failure buffer because the address of the row corresponding to the row of the failure buffer is a row-wise repair-needed row.

[0074] Additionally, the processor 110 may obtain second memory failure data including the first failure data as second failure data when the first failure data is stored in the defect buffer.

[0075] Next, the processor 110 may obtain only the fault data that needs to be stored from the second memory fault data based on the column direction of the memory, and obtain the third memory fault data. In this case, the processor 110 may obtain the third memory fault data from the second memory fault data using a fault filter. Here, the fault filter may have rows equal in number to the number of columns of the memory, and two columns (a column address column and a count column) in which column addresses and count values ​​are stored.

[0076] That is, when second failure data consisting of a second row address and a second column address according to the second memory failure data is input to the defect filter, if the address of the second column of the second failure data has already been stored in the column address column of the defect filter, and if the value of the count column corresponding to the stored column address column is less than or equal to the number of spare resources in the row direction, the processor 110 can increment the value of the count column corresponding to the stored column address column by 1. On the other hand, if the value of the count column corresponding to the stored column address column is greater than the number of spare resources in the row direction, the processor 110 sets the column address corresponding to the second column address of the second failure data as a column-wise repair-needed row, and since the column address corresponding to the second column address of the second failure data is a column-wise repair-needed row, the second failure data does not need to be stored in the defect filter. On the other hand, if the address of the second column of the second failure data is not stored in the column address column of the defect filter, the processor 110 can store the address of the second column of the second failure data in an empty row of the column address column and increment the value of the count column corresponding to the column address column by 1.

[0077] Additionally, the processor 110 may obtain third memory failure data including the second failure data as third failure data when the second failure data is stored in the defect filter. The processor 110 may then store the third memory failure data as the final memory failure data required for repair of the memory.

[0078] That is, the processor 110 can store the third failure data consisting of the third row address and the third column address based on the third memory failure data in the fault storage as final failure data, thereby storing the final memory failure data required for repairing the memory.

[0079] Also, with reference to FIG. 4 and FIG. 5, an example of a method for storing memory failure data according to a preferred embodiment of the present invention will be described.

[0080] FIG. 4 is a diagram for explaining an example of a memory failure data storage method according to a preferred embodiment of the present invention.

[0081] Referring to FIG. 4, failures detected during the progress of the memory test may be sent to a defect buffer in order, and the column address of the detected failure may be stored at a specific row address location.

[0082] In this case, for a row such as memory row address “2” where the number of faults occurring in the row is greater than the number of spare resources in the column direction and where row-wise repair has already been confirmed, there is no need to store any more fault data. This, unlike existing methods, reduces the amount of failure data that needs to be read.

[0083] In addition, in a test cycle in which no faults are detected, the fault data in the defect buffer is transferred to the defect filter, which checks for column-wise faults based on the addresses of memory columns, thereby identifying columns for which column-wise repairs have already been determined, and eliminating unnecessary column-wise faults.

[0084] Finally, the remaining faults, excluding the faults identified by the fault filter, are stored in the fault storage, and after the test is completed, the memory fault data can be read only from the fault storage for memory repair.

[0085] FIG. 5 illustrates an example of an unnecessary failure according to a preferred embodiment of the present invention.

[0086] "Row must repair" means that the number of faults in one memory row is greater than the number of spare resources in the column direction. In the case of "row must repair" shown in Figure 5, the number of faults in the memory row is "4", but the number of spare resources in the column direction is "2", so the fault in the row cannot be repaired even if all the spare resources in the column direction are used.

[0087] This means that the row must be repaired using row-wise spare resources, so "row must repair" may be specified.

[0088] In addition, even if the failure data shown in red for the corresponding "row must repair" does not exist at the time of failure analysis for repair, it can be determined that the corresponding "row must repair" occurs because the corresponding memory row already has three failures.

[0089] Thus, in the present invention, if the three faults indicated by "row must repair" have already been stored in the defect buffer, the additional unnecessary faults indicated in red do not need to be additionally stored in the defect buffer.

[0090] Similarly, in the case of "column must repair," the defect filter takes into account unnecessary failures, such as those shown in red in the "column must repair" section of the defect filter, and the corresponding failure data may not be stored.

[0091] The operations according to the present embodiment may be embodied in the form of program instructions that can be executed by various computer means and may be recorded in a computer-readable storage medium. A computer-readable storage medium refers to any medium that participates in providing instructions to a processor for execution. A computer-readable storage medium may include program instructions, data files, data structures, or combinations thereof. For example, there may be a magnetic medium, an optical storage medium, a memory, etc. A computer program may be distributed on computer systems connected by a network, and computer-readable code may be stored and executed in a distributed manner. Functional programs, codes, and code segments for implementing the present embodiment may be easily construed by a programmer or the like in the technical field to which the present embodiment pertains.

[0092] The present embodiment is intended to explain the technical idea of ​​the present embodiment, and the scope of the technical idea of ​​the present embodiment is not limited by these embodiments. The scope of protection of the present embodiment should be interpreted according to the following claims, and all technical ideas within the scope equivalent thereto should be interpreted as being included in the scope of rights of the present embodiment. [Explanation of symbols]

[0093] 100: Memory failure data storage device 110 Processor 120 Memory 122 Fault Buffer 124 Defect Filter 126 Defective Storage 130 Test logic generator 140 Input / Output Interface 150 Communication Interface

Claims

1. In a method for storing memory failure data performed by a memory failure data storage device, the memory failure data storage device includes a processor and a memory for storing instructions for executing a method for storing memory failure data obtained through a failure test on a test memory to be tested, the method for storing memory failure data performed by the processor includes: A processor selectively stores a portion of the memory failure data in a failure buffer of the memory based on an address of a first line selected from row lines or column lines of memory failure data detected from a plurality of failed cells in the test memory where a failure has occurred; storing an address of a second line, which is the other of the row line or column line of the memory failure data, and the number of failures in a defect filter of the memory; storing a portion of the selectively stored memory fault data in a fault storage of the memory, taking into consideration the address of the second line and the number of faults stored in the fault filter; 4. A method for storing memory failure data, comprising:

2. 2. The method of claim 1, wherein the detected memory failure data is detected sequentially as a failure test is performed on the test memory, the first line being a row line, and the second line being a column line.

3. 3. The method of claim 2, wherein the row lines of the fault buffer correspond to the row lines of the memory fault data, and the row lines of the fault buffer include an address of a cell line in which a fault has occurred in the row line and a counter indicating the number of faults that have occurred in the row line.

4. The memory fault data selectively stored in the fault buffer includes a row address and a column address corresponding to a location of a faulty cell where a fault occurs, the number of column lines of the fault buffer depends on the number of spare resources of the column lines of the fault buffer, and the number of spare resources of the column lines is less than the number of column lines of the memory fault data; 3. The method of claim 2, wherein the processor selectively stores a portion of the detected memory failure data in the failure buffer based on an address of the row line.

5. Selectively storing a portion of the detected memory fault data in the fault buffer includes: The processor further comprises: information stored in the counter; 4. The method of claim 3, further comprising storing memory failure data detected for a selected portion of the cells in which the failure occurs, taking into consideration a first reference value that is predetermined according to the number of column lines of the failure buffer.

6. The processor selectively storing a portion of the detected memory fault data in a fault buffer, The processor sequentially stores in the fault buffer the addresses of the column lines for the faults occurring in each row line; 3. The method of claim 2, further comprising: when the number of faults occurring in the Nth row line of the test memory is greater than the number of spare resources in the column direction, the processor determines the Nth row line as a target for fault repair, and does not store any more column line addresses for the Nth row line.

7. the first lines are row lines and the second lines are column lines; storing the address of the second line and the number of faults in a defect filter in the memory; 2. The method of claim 1, wherein the processor stores in a defect filter of the memory an address of a column line contained in the memory failure data stored in the failure buffer and a number of failures corresponding to the column line.

8. the first lines are row lines and the second lines are column lines; storing the address of the column line and the number of failures in a defect filter of the memory based on the address of the column line of the memory failure data, 2. The method of claim 1, further comprising: storing in a defect filter a column line address for each faulty cell stored in the fault buffer in sequence, while updating a number of faults associated with the stored column line address.

9. The processor storing a portion of the memory fault data stored in the fault buffer in the fault store, 9. The method of claim 8, further comprising storing memory failure data for a selected portion of the failure cells corresponding to the column line in the defect storage, taking into consideration the number of failures updated in association with the address of the column line and a second predetermined reference value.

10. The processor storing a portion of the memory fault data stored in the fault buffer in the fault store, storing row line address information and column line address information for the faulty cell stored in the fault buffer in the defect storage; 3. The method of claim 2, further comprising: determining that an Mth column line is to be repaired if the number of updated faults stored in the fault filter exceeds a predetermined second reference value; and not storing any more memory fault data for faulty cells in the fault storage for the Mth column line.

11. The processor selectively storing a portion of the detected memory fault data in a fault buffer, The processor sequentially stores memory fault data including row address information and column address information for a faulty cell in a row line of the fault buffer corresponding to the row line, and when the number of faults occurring in the Nth row line is greater than the number of spare resources in the column direction, 3. The method of claim 2, wherein the processor temporarily stores address information of column lines for faulty cells associated with the N row lines in an additional row line, and the processor selectively stores memory fault data for the faulty cells temporarily stored in the additional row line in the defect storage location, taking into account the number of faults for the column lines stored in a defect filter.

12. A computer program stored on a computer-readable storage medium for causing a computer to execute the method for storing memory failure data according to any one of claims 1 to 11.

13. A memory failure data storage device, comprising: The method includes: a processor; and a memory for storing instructions for executing a method for storing memory failure data obtained through a failure test on a test memory to be tested, the method being performed by the processor, the method comprising: The processor selectively stores a portion of the memory failure data in a failure buffer of the memory based on an address of a first line selected from row lines or column lines of memory failure data detected from a plurality of failed cells in a test memory where a failure has occurred; storing an address of a second line, which is the other of the row line or column line of the memory failure data, and the number of failures in a defect filter of the memory; storing a portion of the selectively stored memory fault data in a fault storage location of the memory, taking into consideration the address of the second line and the number of faults stored in the fault filter.

14. The detected memory failure data is sequentially detected while a failure test is performed on the test memory, the first line being a row line, and the second line being a column line, 14. The memory fault data storage device of claim 13, wherein the row lines of the fault buffer correspond to the row lines of the memory fault data, and the row lines of the fault buffer include an address of a cell line in which a fault has occurred in the row line and a counter indicating the number of faults that have occurred in the row line.

15. The memory fault data selectively stored in the fault buffer includes a row address and a column address corresponding to a location of a faulty cell where a fault occurs, the number of column lines of the fault buffer depends on the number of spare resources of the column lines of the fault buffer, and the number of spare resources of the column lines is less than the number of column lines of the memory fault data; 15. The memory fault data storage device of claim 14, wherein the processor selectively stores a portion of the detected memory fault data in the fault buffer based on an address of the row line.

16. The processor selectively storing a portion of the detected memory fault data in the fault buffer, the processor stores memory failure data detected for selected cells among the cells in which the failure occurs, taking into consideration the information stored in the counter and a first reference value that is predetermined according to the number of column lines of the failure buffer; 16. The memory fault data storage device of claim 15, wherein the processor stores the address and number of faults of the second line in the fault filter of the memory by storing the address of a column line included in the memory fault data stored in the fault buffer and the number of faults corresponding to the column line in the fault filter of the memory.

17. The processor storing a portion of the memory fault data stored in the fault buffer in the fault store, 16. The memory failure data storage device of claim 15, further comprising: storing memory failure data for selected cells among the faulty cells corresponding to the column line in the defect storage, taking into consideration the number of faults updated in association with the address of the column line and a second predetermined reference value.

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